sys/dev/nvme/nvme_sim.c

   1 /*-
   2  * Copyright (c) 2016 Netflix, Inc
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer,
   9  *    without modification, immediately at the beginning of the file.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  15  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  16  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  17  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  18  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  19  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  20  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  21  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  22  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  23  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  24  */
  25
  26 #include <sys/cdefs.h>
  27 __FBSDID("$FreeBSD$");
  28
  29 #include <sys/param.h>
  30 #include <sys/systm.h>
  31 #include <sys/buf.h>
  32 #include <sys/bus.h>
  33 #include <sys/conf.h>
  34 #include <sys/ioccom.h>
  35 #include <sys/malloc.h>
  36 #include <sys/proc.h>
  37 #include <sys/smp.h>
  38
  39 #include <cam/cam.h>
  40 #include <cam/cam_ccb.h>
  41 #include <cam/cam_sim.h>
  42 #include <cam/cam_xpt_sim.h>
  43 #include <cam/cam_debug.h>
  44
  45 #include <dev/pci/pcivar.h>
  46 #include <dev/pci/pcireg.h>
  47
  48 #include "nvme_private.h"
  49
  50 #define ccb_accb_ptr spriv_ptr0
  51 #define ccb_ctrlr_ptr spriv_ptr1
  52 static void     nvme_sim_action(struct cam_sim *sim, union ccb *ccb);
  53 static void     nvme_sim_poll(struct cam_sim *sim);
  54
  55 #define sim2softc(sim)  ((struct nvme_sim_softc *)cam_sim_softc(sim))
  56 #define sim2ctrlr(sim)  (sim2softc(sim)->s_ctrlr)
  57
  58 struct nvme_sim_softc
  59 {
  60         struct nvme_controller  *s_ctrlr;
  61         struct cam_sim          *s_sim;
  62         struct cam_path         *s_path;
  63 };
  64
  65 static void
  66 nvme_sim_nvmeio_done(void *ccb_arg, const struct nvme_completion *cpl)
  67 {
  68         union ccb *ccb = (union ccb *)ccb_arg;
  69
  70         /*
  71          * Let the periph know the completion, and let it sort out what
  72          * it means. Make our best guess, though for the status code.
  73          */
  74         memcpy(&ccb->nvmeio.cpl, cpl, sizeof(*cpl));
  75         ccb->ccb_h.status &= ~CAM_SIM_QUEUED;
  76         if (nvme_completion_is_error(cpl)) {
  77                 ccb->ccb_h.status = CAM_REQ_CMP_ERR;
  78                 xpt_done(ccb);
  79         } else {
  80                 ccb->ccb_h.status = CAM_REQ_CMP;
  81                 xpt_done_direct(ccb);
  82         }
  83 }
  84
  85 static void
  86 nvme_sim_nvmeio(struct cam_sim *sim, union ccb *ccb)
  87 {
  88         struct ccb_nvmeio       *nvmeio = &ccb->nvmeio;
  89         struct nvme_request     *req;
  90         void                    *payload;
  91         uint32_t                size;
  92         struct nvme_controller *ctrlr;
  93
  94         ctrlr = sim2ctrlr(sim);
  95         payload = nvmeio->data_ptr;
  96         size = nvmeio->dxfer_len;
  97         /* SG LIST ??? */
  98         if ((nvmeio->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_BIO)
  99                 req = nvme_allocate_request_bio((struct bio *)payload,
 100                     nvme_sim_nvmeio_done, ccb);
 101         else if ((nvmeio->ccb_h.flags & CAM_DATA_SG) == CAM_DATA_SG)
 102                 req = nvme_allocate_request_ccb(ccb, nvme_sim_nvmeio_done, ccb);
 103         else if (payload == NULL)
 104                 req = nvme_allocate_request_null(nvme_sim_nvmeio_done, ccb);
 105         else
 106                 req = nvme_allocate_request_vaddr(payload, size,
 107                     nvme_sim_nvmeio_done, ccb);
 108
 109         if (req == NULL) {
 110                 nvmeio->ccb_h.status = CAM_RESRC_UNAVAIL;
 111                 xpt_done(ccb);
 112                 return;
 113         }
 114         ccb->ccb_h.status |= CAM_SIM_QUEUED;
 115
 116         memcpy(&req->cmd, &ccb->nvmeio.cmd, sizeof(ccb->nvmeio.cmd));
 117
 118         if (ccb->ccb_h.func_code == XPT_NVME_IO)
 119                 nvme_ctrlr_submit_io_request(ctrlr, req);
 120         else
 121                 nvme_ctrlr_submit_admin_request(ctrlr, req);
 122 }
 123
 124 static uint32_t
 125 nvme_link_kBps(struct nvme_controller *ctrlr)
 126 {
 127         uint32_t speed, lanes, link[] = { 1, 250000, 500000, 985000, 1970000 };
 128         uint32_t status;
 129
 130         status = pcie_read_config(ctrlr->dev, PCIER_LINK_STA, 2);
 131         speed = status & PCIEM_LINK_STA_SPEED;
 132         lanes = (status & PCIEM_LINK_STA_WIDTH) >> 4;
 133         /*
 134          * Failsafe on link speed indicator. If it is insane report the number of
 135          * lanes as the speed. Not 100% accurate, but may be diagnostic.
 136          */
 137         if (speed >= nitems(link))
 138                 speed = 0;
 139         return link[speed] * lanes;
 140 }
 141
 142 static void
 143 nvme_sim_action(struct cam_sim *sim, union ccb *ccb)
 144 {
 145         struct nvme_controller *ctrlr;
 146
 147         CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE,
 148             ("nvme_sim_action: func= %#x\n",
 149                 ccb->ccb_h.func_code));
 150
 151         ctrlr = sim2ctrlr(sim);
 152
 153         mtx_assert(&ctrlr->lock, MA_OWNED);
 154
 155         switch (ccb->ccb_h.func_code) {
 156         case XPT_CALC_GEOMETRY:         /* Calculate Geometry Totally nuts ? XXX */
 157                 /*
 158                  * Only meaningful for old-school SCSI disks since only the SCSI
 159                  * da driver generates them. Reject all these that slip through.
 160                  */
 161                 /*FALLTHROUGH*/
 162         case XPT_ABORT:                 /* Abort the specified CCB */
 163                 ccb->ccb_h.status = CAM_REQ_INVALID;
 164                 break;
 165         case XPT_SET_TRAN_SETTINGS:
 166                 /*
 167                  * NVMe doesn't really have different transfer settings, but
 168                  * other parts of CAM think failure here is a big deal.
 169                  */
 170                 ccb->ccb_h.status = CAM_REQ_CMP;
 171                 break;
 172         case XPT_PATH_INQ:              /* Path routing inquiry */
 173         {
 174                 struct ccb_pathinq      *cpi = &ccb->cpi;
 175                 device_t                dev = ctrlr->dev;
 176
 177                 /*
 178                  * NVMe may have multiple LUNs on the same path. Current generation
 179                  * of NVMe devives support only a single name space. Multiple name
 180                  * space drives are coming, but it's unclear how we should report
 181                  * them up the stack.
 182                  */
 183                 cpi->version_num = 1;
 184                 cpi->hba_inquiry = 0;
 185                 cpi->target_sprt = 0;
 186                 cpi->hba_misc =  PIM_UNMAPPED | PIM_NOSCAN;
 187                 cpi->hba_eng_cnt = 0;
 188                 cpi->max_target = 0;
 189                 cpi->max_lun = ctrlr->cdata.nn;
 190                 cpi->maxio = ctrlr->max_xfer_size;
 191                 cpi->initiator_id = 0;
 192                 cpi->bus_id = cam_sim_bus(sim);
 193                 cpi->base_transfer_speed = nvme_link_kBps(ctrlr);
 194                 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
 195                 strlcpy(cpi->hba_vid, "NVMe", HBA_IDLEN);
 196                 strlcpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
 197                 cpi->unit_number = cam_sim_unit(sim);
 198                 cpi->transport = XPORT_NVME;            /* XXX XPORT_PCIE ? */
 199                 cpi->transport_version = nvme_mmio_read_4(ctrlr, vs);
 200                 cpi->protocol = PROTO_NVME;
 201                 cpi->protocol_version = nvme_mmio_read_4(ctrlr, vs);
 202                 cpi->xport_specific.nvme.nsid = xpt_path_lun_id(ccb->ccb_h.path);
 203                 cpi->xport_specific.nvme.domain = pci_get_domain(dev);
 204                 cpi->xport_specific.nvme.bus = pci_get_bus(dev);
 205                 cpi->xport_specific.nvme.slot = pci_get_slot(dev);
 206                 cpi->xport_specific.nvme.function = pci_get_function(dev);
 207                 cpi->xport_specific.nvme.extra = 0;
 208                 cpi->ccb_h.status = CAM_REQ_CMP;
 209                 break;
 210         }
 211         case XPT_GET_TRAN_SETTINGS:     /* Get transport settings */
 212         {
 213                 struct ccb_trans_settings       *cts;
 214                 struct ccb_trans_settings_nvme  *nvmep;
 215                 struct ccb_trans_settings_nvme  *nvmex;
 216                 device_t dev;
 217                 uint32_t status, caps;
 218
 219                 dev = ctrlr->dev;
 220                 cts = &ccb->cts;
 221                 nvmex = &cts->xport_specific.nvme;
 222                 nvmep = &cts->proto_specific.nvme;
 223
 224                 status = pcie_read_config(dev, PCIER_LINK_STA, 2);
 225                 caps = pcie_read_config(dev, PCIER_LINK_CAP, 2);
 226                 nvmex->valid = CTS_NVME_VALID_SPEC | CTS_NVME_VALID_LINK;
 227                 nvmex->spec = nvme_mmio_read_4(ctrlr, vs);
 228                 nvmex->speed = status & PCIEM_LINK_STA_SPEED;
 229                 nvmex->lanes = (status & PCIEM_LINK_STA_WIDTH) >> 4;
 230                 nvmex->max_speed = caps & PCIEM_LINK_CAP_MAX_SPEED;
 231                 nvmex->max_lanes = (caps & PCIEM_LINK_CAP_MAX_WIDTH) >> 4;
 232
 233                 /* XXX these should be something else maybe ? */
 234                 nvmep->valid = 1;
 235                 nvmep->spec = nvmex->spec;
 236
 237                 cts->transport = XPORT_NVME;
 238                 cts->protocol = PROTO_NVME;
 239                 cts->ccb_h.status = CAM_REQ_CMP;
 240                 break;
 241         }
 242         case XPT_TERM_IO:               /* Terminate the I/O process */
 243                 /*
 244                  * every driver handles this, but nothing generates it. Assume
 245                  * it's OK to just say 'that worked'.
 246                  */
 247                 /*FALLTHROUGH*/
 248         case XPT_RESET_DEV:             /* Bus Device Reset the specified device */
 249         case XPT_RESET_BUS:             /* Reset the specified bus */
 250                 /*
 251                  * NVMe doesn't really support physically resetting the bus. It's part
 252                  * of the bus scanning dance, so return sucess to tell the process to
 253                  * proceed.
 254                  */
 255                 ccb->ccb_h.status = CAM_REQ_CMP;
 256                 break;
 257         case XPT_NVME_IO:               /* Execute the requested I/O operation */
 258         case XPT_NVME_ADMIN:            /* or Admin operation */
 259                 nvme_sim_nvmeio(sim, ccb);
 260                 return;                 /* no done */
 261         default:
 262                 ccb->ccb_h.status = CAM_REQ_INVALID;
 263                 break;
 264         }
 265         xpt_done(ccb);
 266 }
 267
 268 static void
 269 nvme_sim_poll(struct cam_sim *sim)
 270 {
 271
 272         nvme_ctrlr_poll(sim2ctrlr(sim));
 273 }
 274
 275 static void *
 276 nvme_sim_new_controller(struct nvme_controller *ctrlr)
 277 {
 278         struct nvme_sim_softc *sc;
 279         struct cam_devq *devq;
 280         int max_trans;
 281
 282         max_trans = ctrlr->max_hw_pend_io;
 283         devq = cam_simq_alloc(max_trans);
 284         if (devq == NULL)
 285                 return (NULL);
 286
 287         sc = malloc(sizeof(*sc), M_NVME, M_ZERO | M_WAITOK);
 288         sc->s_ctrlr = ctrlr;
 289
 290         sc->s_sim = cam_sim_alloc(nvme_sim_action, nvme_sim_poll,
 291             "nvme", sc, device_get_unit(ctrlr->dev),
 292             &ctrlr->lock, max_trans, max_trans, devq);
 293         if (sc->s_sim == NULL) {
 294                 printf("Failed to allocate a sim\n");
 295                 cam_simq_free(devq);
 296                 goto err1;
 297         }
 298         if (xpt_bus_register(sc->s_sim, ctrlr->dev, 0) != CAM_SUCCESS) {
 299                 printf("Failed to create a bus\n");
 300                 goto err2;
 301         }
 302         if (xpt_create_path(&sc->s_path, /*periph*/NULL, cam_sim_path(sc->s_sim),
 303             CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
 304                 printf("Failed to create a path\n");
 305                 goto err3;
 306         }
 307
 308         return (sc);
 309
 310 err3:
 311         xpt_bus_deregister(cam_sim_path(sc->s_sim));
 312 err2:
 313         cam_sim_free(sc->s_sim, /*free_devq*/TRUE);
 314 err1:
 315         free(sc, M_NVME);
 316         return (NULL);
 317 }
 318
 319 static void *
 320 nvme_sim_new_ns(struct nvme_namespace *ns, void *sc_arg)
 321 {
 322         struct nvme_sim_softc *sc = sc_arg;
 323         struct nvme_controller *ctrlr = sc->s_ctrlr;
 324         union ccb *ccb;
 325
 326         mtx_lock(&ctrlr->lock);
 327
 328         ccb = xpt_alloc_ccb_nowait();
 329         if (ccb == NULL) {
 330                 printf("unable to alloc CCB for rescan\n");
 331                 return (NULL);
 332         }
 333
 334         if (xpt_create_path(&ccb->ccb_h.path, /*periph*/NULL,
 335             cam_sim_path(sc->s_sim), 0, ns->id) != CAM_REQ_CMP) {
 336                 printf("unable to create path for rescan\n");
 337                 xpt_free_ccb(ccb);
 338                 return (NULL);
 339         }
 340
 341         xpt_rescan(ccb);
 342
 343         mtx_unlock(&ctrlr->lock);
 344
 345         return (ns);
 346 }
 347
 348 static void
 349 nvme_sim_controller_fail(void *ctrlr_arg)
 350 {
 351         struct nvme_sim_softc *sc = ctrlr_arg;
 352         struct nvme_controller *ctrlr = sc->s_ctrlr;
 353
 354         mtx_lock(&ctrlr->lock);
 355         xpt_async(AC_LOST_DEVICE, sc->s_path, NULL);
 356         xpt_free_path(sc->s_path);
 357         xpt_bus_deregister(cam_sim_path(sc->s_sim));
 358         cam_sim_free(sc->s_sim, /*free_devq*/TRUE);
 359         mtx_unlock(&ctrlr->lock);
 360         free(sc, M_NVME);
 361 }
 362
 363 struct nvme_consumer *consumer_cookie;
 364
 365 static void
 366 nvme_sim_init(void)
 367 {
 368         if (nvme_use_nvd)
 369                 return;
 370
 371         consumer_cookie = nvme_register_consumer(nvme_sim_new_ns,
 372             nvme_sim_new_controller, NULL, nvme_sim_controller_fail);
 373 }
 374
 375 SYSINIT(nvme_sim_register, SI_SUB_DRIVERS, SI_ORDER_ANY,
 376     nvme_sim_init, NULL);
 377
 378 static void
 379 nvme_sim_uninit(void)
 380 {
 381         if (nvme_use_nvd)
 382                 return;
 383         /* XXX Cleanup */
 384
 385         nvme_unregister_consumer(consumer_cookie);
 386 }
 387
 388 SYSUNINIT(nvme_sim_unregister, SI_SUB_DRIVERS, SI_ORDER_ANY,
 389     nvme_sim_uninit, NULL);