sys/dev/nvme/nvme_sim.c

   1 /*-
   2  * Copyright (c) 2016 Netflix, Inc
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer,
   9  *    without modification, immediately at the beginning of the file.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  15  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  16  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  17  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  18  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  19  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  20  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  21  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  22  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  23  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  24  */
  25
  26 #include <sys/cdefs.h>
  27 __FBSDID("$FreeBSD$");
  28
  29 #include <sys/param.h>
  30 #include <sys/systm.h>
  31 #include <sys/buf.h>
  32 #include <sys/bus.h>
  33 #include <sys/conf.h>
  34 #include <sys/ioccom.h>
  35 #include <sys/malloc.h>
  36 #include <sys/proc.h>
  37 #include <sys/smp.h>
  38
  39 #include <cam/cam.h>
  40 #include <cam/cam_ccb.h>
  41 #include <cam/cam_sim.h>
  42 #include <cam/cam_xpt_sim.h>
  43 #include <cam/cam_xpt_internal.h>       // Yes, this is wrong.
  44 #include <cam/cam_debug.h>
  45
  46 #include <dev/pci/pcivar.h>
  47 #include <dev/pci/pcireg.h>
  48
  49 #include "nvme_private.h"
  50
  51 #define ccb_accb_ptr spriv_ptr0
  52 #define ccb_ctrlr_ptr spriv_ptr1
  53 static void     nvme_sim_action(struct cam_sim *sim, union ccb *ccb);
  54 static void     nvme_sim_poll(struct cam_sim *sim);
  55
  56 #define sim2softc(sim)  ((struct nvme_sim_softc *)cam_sim_softc(sim))
  57 #define sim2ns(sim)     (sim2softc(sim)->s_ns)
  58 #define sim2ctrlr(sim)  (sim2softc(sim)->s_ctrlr)
  59
  60 struct nvme_sim_softc
  61 {
  62         struct nvme_controller  *s_ctrlr;
  63         struct nvme_namespace   *s_ns;
  64         struct cam_sim          *s_sim;
  65         struct cam_path         *s_path;
  66 };
  67
  68 static void
  69 nvme_sim_nvmeio_done(void *ccb_arg, const struct nvme_completion *cpl)
  70 {
  71         union ccb *ccb = (union ccb *)ccb_arg;
  72
  73         /*
  74          * Let the periph know the completion, and let it sort out what
  75          * it means. Make our best guess, though for the status code.
  76          */
  77         memcpy(&ccb->nvmeio.cpl, cpl, sizeof(*cpl));
  78         ccb->ccb_h.status &= ~CAM_SIM_QUEUED;
  79         if (nvme_completion_is_error(cpl)) {
  80                 ccb->ccb_h.status = CAM_REQ_CMP_ERR;
  81                 xpt_done(ccb);
  82         } else {
  83                 ccb->ccb_h.status = CAM_REQ_CMP;
  84                 xpt_done_direct(ccb);
  85         }
  86 }
  87
  88 static void
  89 nvme_sim_nvmeio(struct cam_sim *sim, union ccb *ccb)
  90 {
  91         struct ccb_nvmeio       *nvmeio = &ccb->nvmeio;
  92         struct nvme_request     *req;
  93         void                    *payload;
  94         uint32_t                size;
  95         struct nvme_controller *ctrlr;
  96
  97         ctrlr = sim2ctrlr(sim);
  98         payload = nvmeio->data_ptr;
  99         size = nvmeio->dxfer_len;
 100         /* SG LIST ??? */
 101         if ((nvmeio->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_BIO)
 102                 req = nvme_allocate_request_bio((struct bio *)payload,
 103                     nvme_sim_nvmeio_done, ccb);
 104         else if ((nvmeio->ccb_h.flags & CAM_DATA_SG) == CAM_DATA_SG)
 105                 req = nvme_allocate_request_ccb(ccb, nvme_sim_nvmeio_done, ccb);
 106         else if (payload == NULL)
 107                 req = nvme_allocate_request_null(nvme_sim_nvmeio_done, ccb);
 108         else
 109                 req = nvme_allocate_request_vaddr(payload, size,
 110                     nvme_sim_nvmeio_done, ccb);
 111
 112         if (req == NULL) {
 113                 nvmeio->ccb_h.status = CAM_RESRC_UNAVAIL;
 114                 xpt_done(ccb);
 115                 return;
 116         }
 117         ccb->ccb_h.status |= CAM_SIM_QUEUED;
 118
 119         memcpy(&req->cmd, &ccb->nvmeio.cmd, sizeof(ccb->nvmeio.cmd));
 120
 121         if (ccb->ccb_h.func_code == XPT_NVME_IO)
 122                 nvme_ctrlr_submit_io_request(ctrlr, req);
 123         else
 124                 nvme_ctrlr_submit_admin_request(ctrlr, req);
 125 }
 126
 127 static uint32_t
 128 nvme_link_kBps(struct nvme_controller *ctrlr)
 129 {
 130         uint32_t speed, lanes, link[] = { 1, 250000, 500000, 985000, 1970000 };
 131         uint32_t status;
 132
 133         status = pcie_read_config(ctrlr->dev, PCIER_LINK_STA, 2);
 134         speed = status & PCIEM_LINK_STA_SPEED;
 135         lanes = (status & PCIEM_LINK_STA_WIDTH) >> 4;
 136         /*
 137          * Failsafe on link speed indicator. If it is insane report the number of
 138          * lanes as the speed. Not 100% accurate, but may be diagnostic.
 139          */
 140         if (speed >= nitems(link))
 141                 speed = 0;
 142         return link[speed] * lanes;
 143 }
 144
 145 static void
 146 nvme_sim_action(struct cam_sim *sim, union ccb *ccb)
 147 {
 148         struct nvme_controller *ctrlr;
 149         struct nvme_namespace *ns;
 150
 151         CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE,
 152             ("nvme_sim_action: func= %#x\n",
 153                 ccb->ccb_h.func_code));
 154
 155         /*
 156          * XXX when we support multiple namespaces in the base driver we'll need
 157          * to revisit how all this gets stored and saved in the periph driver's
 158          * reserved areas. Right now we store all three in the softc of the sim.
 159          */
 160         ns = sim2ns(sim);
 161         ctrlr = sim2ctrlr(sim);
 162
 163         mtx_assert(&ctrlr->lock, MA_OWNED);
 164
 165         switch (ccb->ccb_h.func_code) {
 166         case XPT_CALC_GEOMETRY:         /* Calculate Geometry Totally nuts ? XXX */
 167                 /*
 168                  * Only meaningful for old-school SCSI disks since only the SCSI
 169                  * da driver generates them. Reject all these that slip through.
 170                  */
 171                 /*FALLTHROUGH*/
 172         case XPT_ABORT:                 /* Abort the specified CCB */
 173                 ccb->ccb_h.status = CAM_REQ_INVALID;
 174                 break;
 175         case XPT_SET_TRAN_SETTINGS:
 176                 /*
 177                  * NVMe doesn't really have different transfer settings, but
 178                  * other parts of CAM think failure here is a big deal.
 179                  */
 180                 ccb->ccb_h.status = CAM_REQ_CMP;
 181                 break;
 182         case XPT_PATH_INQ:              /* Path routing inquiry */
 183         {
 184                 struct ccb_pathinq      *cpi = &ccb->cpi;
 185                 device_t                dev = ctrlr->dev;
 186
 187                 /*
 188                  * NVMe may have multiple LUNs on the same path. Current generation
 189                  * of NVMe devives support only a single name space. Multiple name
 190                  * space drives are coming, but it's unclear how we should report
 191                  * them up the stack.
 192                  */
 193                 cpi->version_num = 1;
 194                 cpi->hba_inquiry = 0;
 195                 cpi->target_sprt = 0;
 196                 cpi->hba_misc =  PIM_UNMAPPED /* | PIM_NOSCAN */;
 197                 cpi->hba_eng_cnt = 0;
 198                 cpi->max_target = 0;
 199                 cpi->max_lun = ctrlr->cdata.nn;
 200                 cpi->maxio = nvme_ns_get_max_io_xfer_size(ns);
 201                 cpi->initiator_id = 0;
 202                 cpi->bus_id = cam_sim_bus(sim);
 203                 cpi->base_transfer_speed = nvme_link_kBps(ctrlr);
 204                 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
 205                 strlcpy(cpi->hba_vid, "NVMe", HBA_IDLEN);
 206                 strlcpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
 207                 cpi->unit_number = cam_sim_unit(sim);
 208                 cpi->transport = XPORT_NVME;            /* XXX XPORT_PCIE ? */
 209                 cpi->transport_version = nvme_mmio_read_4(ctrlr, vs);
 210                 cpi->protocol = PROTO_NVME;
 211                 cpi->protocol_version = nvme_mmio_read_4(ctrlr, vs);
 212                 cpi->xport_specific.nvme.nsid = ns->id;
 213                 cpi->xport_specific.nvme.domain = pci_get_domain(dev);
 214                 cpi->xport_specific.nvme.bus = pci_get_bus(dev);
 215                 cpi->xport_specific.nvme.slot = pci_get_slot(dev);
 216                 cpi->xport_specific.nvme.function = pci_get_function(dev);
 217                 cpi->xport_specific.nvme.extra = 0;
 218                 cpi->ccb_h.status = CAM_REQ_CMP;
 219                 break;
 220         }
 221         case XPT_GET_TRAN_SETTINGS:     /* Get transport settings */
 222         {
 223                 struct ccb_trans_settings       *cts;
 224                 struct ccb_trans_settings_nvme  *nvmep;
 225                 struct ccb_trans_settings_nvme  *nvmex;
 226                 device_t dev;
 227                 uint32_t status, caps;
 228
 229                 dev = ctrlr->dev;
 230                 cts = &ccb->cts;
 231                 nvmex = &cts->xport_specific.nvme;
 232                 nvmep = &cts->proto_specific.nvme;
 233
 234                 status = pcie_read_config(dev, PCIER_LINK_STA, 2);
 235                 caps = pcie_read_config(dev, PCIER_LINK_CAP, 2);
 236                 nvmex->valid = CTS_NVME_VALID_SPEC | CTS_NVME_VALID_LINK;
 237                 nvmex->spec = nvme_mmio_read_4(ctrlr, vs);
 238                 nvmex->speed = status & PCIEM_LINK_STA_SPEED;
 239                 nvmex->lanes = (status & PCIEM_LINK_STA_WIDTH) >> 4;
 240                 nvmex->max_speed = caps & PCIEM_LINK_CAP_MAX_SPEED;
 241                 nvmex->max_lanes = (caps & PCIEM_LINK_CAP_MAX_WIDTH) >> 4;
 242
 243                 /* XXX these should be something else maybe ? */
 244                 nvmep->valid = 1;
 245                 nvmep->spec = nvmex->spec;
 246
 247                 cts->transport = XPORT_NVME;
 248                 cts->protocol = PROTO_NVME;
 249                 cts->ccb_h.status = CAM_REQ_CMP;
 250                 break;
 251         }
 252         case XPT_TERM_IO:               /* Terminate the I/O process */
 253                 /*
 254                  * every driver handles this, but nothing generates it. Assume
 255                  * it's OK to just say 'that worked'.
 256                  */
 257                 /*FALLTHROUGH*/
 258         case XPT_RESET_DEV:             /* Bus Device Reset the specified device */
 259         case XPT_RESET_BUS:             /* Reset the specified bus */
 260                 /*
 261                  * NVMe doesn't really support physically resetting the bus. It's part
 262                  * of the bus scanning dance, so return sucess to tell the process to
 263                  * proceed.
 264                  */
 265                 ccb->ccb_h.status = CAM_REQ_CMP;
 266                 break;
 267         case XPT_NVME_IO:               /* Execute the requested I/O operation */
 268         case XPT_NVME_ADMIN:            /* or Admin operation */
 269                 nvme_sim_nvmeio(sim, ccb);
 270                 return;                 /* no done */
 271         default:
 272                 ccb->ccb_h.status = CAM_REQ_INVALID;
 273                 break;
 274         }
 275         xpt_done(ccb);
 276 }
 277
 278 static void
 279 nvme_sim_poll(struct cam_sim *sim)
 280 {
 281
 282         nvme_ctrlr_poll(sim2ctrlr(sim));
 283 }
 284
 285 static void *
 286 nvme_sim_new_controller(struct nvme_controller *ctrlr)
 287 {
 288         struct cam_devq *devq;
 289         int max_trans;
 290         int unit;
 291         struct nvme_sim_softc *sc = NULL;
 292
 293         max_trans = ctrlr->max_hw_pend_io;
 294         unit = device_get_unit(ctrlr->dev);
 295         devq = cam_simq_alloc(max_trans);
 296         if (devq == NULL)
 297                 return NULL;
 298
 299         sc = malloc(sizeof(*sc), M_NVME, M_ZERO | M_WAITOK);
 300
 301         sc->s_ctrlr = ctrlr;
 302
 303         sc->s_sim = cam_sim_alloc(nvme_sim_action, nvme_sim_poll,
 304             "nvme", sc, unit, &ctrlr->lock, max_trans, max_trans, devq);
 305         if (sc->s_sim == NULL) {
 306                 printf("Failed to allocate a sim\n");
 307                 cam_simq_free(devq);
 308                 free(sc, M_NVME);
 309                 return NULL;
 310         }
 311
 312         return sc;
 313 }
 314
 315 static void
 316 nvme_sim_rescan_target(struct nvme_controller *ctrlr, struct cam_path *path)
 317 {
 318         union ccb *ccb;
 319
 320         ccb = xpt_alloc_ccb_nowait();
 321         if (ccb == NULL) {
 322                 printf("unable to alloc CCB for rescan\n");
 323                 return;
 324         }
 325
 326         if (xpt_clone_path(&ccb->ccb_h.path, path) != CAM_REQ_CMP) {
 327                 printf("unable to copy path for rescan\n");
 328                 xpt_free_ccb(ccb);
 329                 return;
 330         }
 331
 332         xpt_rescan(ccb);
 333 }
 334
 335 static void *
 336 nvme_sim_new_ns(struct nvme_namespace *ns, void *sc_arg)
 337 {
 338         struct nvme_sim_softc *sc = sc_arg;
 339         struct nvme_controller *ctrlr = sc->s_ctrlr;
 340         int i;
 341
 342         sc->s_ns = ns;
 343
 344         /*
 345          * XXX this is creating one bus per ns, but it should be one
 346          * XXX target per controller, and one LUN per namespace.
 347          * XXX Current drives only support one NS, so there's time
 348          * XXX to fix it later when new drives arrive.
 349          *
 350          * XXX I'm pretty sure the xpt_bus_register() call below is
 351          * XXX like super lame and it really belongs in the sim_new_ctrlr
 352          * XXX callback. Then the create_path below would be pretty close
 353          * XXX to being right. Except we should be per-ns not per-ctrlr
 354          * XXX data.
 355          */
 356
 357         mtx_lock(&ctrlr->lock);
 358 /* Create bus */
 359
 360         /*
 361          * XXX do I need to lock ctrlr->lock ?
 362          * XXX do I need to lock the path?
 363          * ata and scsi seem to in their code, but their discovery is
 364          * somewhat more asynchronous. We're only every called one at a
 365          * time, and nothing is in parallel.
 366          */
 367
 368         i = 0;
 369         if (xpt_bus_register(sc->s_sim, ctrlr->dev, 0) != CAM_SUCCESS)
 370                 goto error;
 371         i++;
 372         if (xpt_create_path(&sc->s_path, /*periph*/NULL, cam_sim_path(sc->s_sim),
 373             1, ns->id) != CAM_REQ_CMP)
 374                 goto error;
 375         i++;
 376
 377         sc->s_path->device->nvme_data = nvme_ns_get_data(ns);
 378         sc->s_path->device->nvme_cdata = nvme_ctrlr_get_data(ns->ctrlr);
 379
 380 /* Scan bus */
 381         nvme_sim_rescan_target(ctrlr, sc->s_path);
 382
 383         mtx_unlock(&ctrlr->lock);
 384
 385         return ns;
 386
 387 error:
 388         switch (i) {
 389         case 2:
 390                 xpt_free_path(sc->s_path);
 391         case 1:
 392                 xpt_bus_deregister(cam_sim_path(sc->s_sim));
 393         case 0:
 394                 cam_sim_free(sc->s_sim, /*free_devq*/TRUE);
 395         }
 396         mtx_unlock(&ctrlr->lock);
 397         return NULL;
 398 }
 399
 400 static void
 401 nvme_sim_controller_fail(void *ctrlr_arg)
 402 {
 403         /* XXX cleanup XXX */
 404 }
 405
 406 struct nvme_consumer *consumer_cookie;
 407
 408 static void
 409 nvme_sim_init(void)
 410 {
 411         if (nvme_use_nvd)
 412                 return;
 413
 414         consumer_cookie = nvme_register_consumer(nvme_sim_new_ns,
 415             nvme_sim_new_controller, NULL, nvme_sim_controller_fail);
 416 }
 417
 418 SYSINIT(nvme_sim_register, SI_SUB_DRIVERS, SI_ORDER_ANY,
 419     nvme_sim_init, NULL);
 420
 421 static void
 422 nvme_sim_uninit(void)
 423 {
 424         if (nvme_use_nvd)
 425                 return;
 426         /* XXX Cleanup */
 427
 428         nvme_unregister_consumer(consumer_cookie);
 429 }
 430
 431 SYSUNINIT(nvme_sim_unregister, SI_SUB_DRIVERS, SI_ORDER_ANY,
 432     nvme_sim_uninit, NULL);