2 * Copyright (c) 2002-2007 Neterion, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <dev/nxge/include/xgehal.h>
33 #include <dev/nxge/xge-osdep.h>
35 /* Printing description, Copyright */
36 #define XGE_DRIVER_VERSION \
37 XGELL_VERSION_MAJOR"."XGELL_VERSION_MINOR"." \
38 XGELL_VERSION_FIX"."XGELL_VERSION_BUILD
39 #define XGE_COPYRIGHT "Copyright(c) 2002-2007 Neterion Inc."
42 #define xge_trace(trace, fmt, args...) xge_debug_ll(trace, fmt, ## args);
44 #define XGE_ALIGN_TO(buffer_length, to) { \
45 if((buffer_length % to) != 0) { \
46 buffer_length += (to - (buffer_length % to)); \
50 #define XGE_EXIT_ON_ERR(text, label, return_value) { \
51 xge_trace(XGE_ERR, "%s (Status: %d)", text, return_value); \
52 status = return_value; \
56 #define XGE_SET_BUFFER_MODE_IN_RINGS(mode) { \
57 for(index = 0; index < XGE_RING_COUNT; index++) \
58 ring_config->queue[index].buffer_mode = mode; \
61 #define XGE_DEFAULT_USER_HARDCODED -1
62 #define XGE_MAX_SEGS 100 /* Maximum number of segments */
63 #define XGE_TX_LEVEL_LOW 16
64 #define XGE_FIFO_COUNT XGE_HAL_MIN_FIFO_NUM
65 #define XGE_RING_COUNT XGE_HAL_MIN_RING_NUM
66 #define XGE_BUFFER_SIZE 20
67 #define XGE_LRO_DEFAULT_ENTRIES 12
68 #define XGE_BAUDRATE 1000000000
70 /* Default values to configuration parameters */
71 #define XGE_DEFAULT_ENABLED_TSO 1
72 #define XGE_DEFAULT_ENABLED_LRO 1
73 #define XGE_DEFAULT_ENABLED_MSI 1
74 #define XGE_DEFAULT_BUFFER_MODE 1
75 #define XGE_DEFAULT_INITIAL_MTU 1500
76 #define XGE_DEFAULT_LATENCY_TIMER -1
77 #define XGE_DEFAULT_MAX_SPLITS_TRANS -1
78 #define XGE_DEFAULT_MMRB_COUNT -1
79 #define XGE_DEFAULT_SHARED_SPLITS 0
80 #define XGE_DEFAULT_ISR_POLLING_CNT 8
81 #define XGE_DEFAULT_STATS_REFRESH_TIME_SEC 4
82 #define XGE_DEFAULT_MAC_RMAC_BCAST_EN 1
83 #define XGE_DEFAULT_MAC_TMAC_UTIL_PERIOD 5
84 #define XGE_DEFAULT_MAC_RMAC_UTIL_PERIOD 5
85 #define XGE_DEFAULT_MAC_RMAC_PAUSE_GEN_EN 1
86 #define XGE_DEFAULT_MAC_RMAC_PAUSE_RCV_EN 1
87 #define XGE_DEFAULT_MAC_RMAC_PAUSE_TIME 65535
88 #define XGE_DEFAULT_MAC_MC_PAUSE_THRESHOLD_Q0Q3 187
89 #define XGE_DEFAULT_MAC_MC_PAUSE_THRESHOLD_Q4Q7 187
90 #define XGE_DEFAULT_FIFO_MEMBLOCK_SIZE PAGE_SIZE
91 #define XGE_DEFAULT_FIFO_RESERVE_THRESHOLD 0
92 #define XGE_DEFAULT_FIFO_MAX_FRAGS 64
93 #define XGE_DEFAULT_FIFO_QUEUE_INTR 0
94 #define XGE_DEFAULT_FIFO_QUEUE_MAX 2048
95 #define XGE_DEFAULT_FIFO_QUEUE_INITIAL 2048
96 #define XGE_DEFAULT_FIFO_QUEUE_TTI_URANGE_A 5
97 #define XGE_DEFAULT_FIFO_QUEUE_TTI_URANGE_B 10
98 #define XGE_DEFAULT_FIFO_QUEUE_TTI_URANGE_C 20
99 #define XGE_DEFAULT_FIFO_QUEUE_TTI_UFC_A 15
100 #define XGE_DEFAULT_FIFO_QUEUE_TTI_UFC_B 30
101 #define XGE_DEFAULT_FIFO_QUEUE_TTI_UFC_C 45
102 #define XGE_DEFAULT_FIFO_QUEUE_TTI_UFC_D 60
103 #define XGE_DEFAULT_FIFO_QUEUE_TTI_TIMER_CI_EN 1
104 #define XGE_DEFAULT_FIFO_QUEUE_TTI_TIMER_AC_EN 1
105 #define XGE_DEFAULT_FIFO_QUEUE_TTI_TIMER_VAL_US 8000
106 #define XGE_DEFAULT_FIFO_ALIGNMENT_SIZE sizeof(u64)
107 #define XGE_DEFAULT_RING_MEMBLOCK_SIZE PAGE_SIZE
108 #define XGE_DEFAULT_RING_STRIP_VLAN_TAG 1
109 #define XGE_DEFAULT_RING_QUEUE_MAX 16
110 #define XGE_DEFAULT_RING_QUEUE_INITIAL 16
111 #define XGE_DEFAULT_RING_QUEUE_DRAM_SIZE_MB 32
112 #define XGE_DEFAULT_RING_QUEUE_INDICATE_MAX_PKTS 16
113 #define XGE_DEFAULT_RING_QUEUE_BACKOFF_INTERVAL_US 1000
114 #define XGE_DEFAULT_RING_QUEUE_RTI_URANGE_A 5
115 #define XGE_DEFAULT_RING_QUEUE_RTI_URANGE_B 10
116 #define XGE_DEFAULT_RING_QUEUE_RTI_URANGE_C 50
117 #define XGE_DEFAULT_RING_QUEUE_RTI_UFC_A 1
118 #define XGE_DEFAULT_RING_QUEUE_RTI_UFC_B 8
119 #define XGE_DEFAULT_RING_QUEUE_RTI_UFC_C 16
120 #define XGE_DEFAULT_RING_QUEUE_RTI_UFC_D 32
121 #define XGE_DEFAULT_RING_QUEUE_RTI_TIMER_AC_EN 1
122 #define XGE_DEFAULT_RING_QUEUE_RTI_TIMER_VAL_US 250
124 #define XGE_DRV_STATS(param) (lldev->driver_stats.param++)
126 #define XGE_SAVE_PARAM(to, what, value) to.what = value;
128 #define XGE_GET_PARAM(str_kenv, to, param, hardcode) { \
129 static int param##__LINE__; \
130 if(testenv(str_kenv) == 1) { \
131 getenv_int(str_kenv, ¶m##__LINE__); \
134 param##__LINE__ = hardcode; \
136 XGE_SAVE_PARAM(to, param, param##__LINE__); \
139 #define XGE_GET_PARAM_MAC(str_kenv, param, hardcode) \
140 XGE_GET_PARAM(str_kenv, ((*dconfig).mac), param, hardcode);
142 #define XGE_GET_PARAM_FIFO(str_kenv, param, hardcode) \
143 XGE_GET_PARAM(str_kenv, ((*dconfig).fifo), param, hardcode);
145 #define XGE_GET_PARAM_FIFO_QUEUE(str_kenv, param, qindex, hardcode) \
146 XGE_GET_PARAM(str_kenv, ((*dconfig).fifo.queue[qindex]), param, \
149 #define XGE_GET_PARAM_FIFO_QUEUE_TTI(str_kenv, param, qindex, tindex, hardcode)\
150 XGE_GET_PARAM(str_kenv, ((*dconfig).fifo.queue[qindex].tti[tindex]), \
153 #define XGE_GET_PARAM_RING(str_kenv, param, hardcode) \
154 XGE_GET_PARAM(str_kenv, ((*dconfig).ring), param, hardcode);
156 #define XGE_GET_PARAM_RING_QUEUE(str_kenv, param, qindex, hardcode) \
157 XGE_GET_PARAM(str_kenv, ((*dconfig).ring.queue[qindex]), param, \
160 #define XGE_GET_PARAM_RING_QUEUE_RTI(str_kenv, param, qindex, hardcode) \
161 XGE_GET_PARAM(str_kenv, ((*dconfig).ring.queue[qindex].rti), param, \
164 /* Values to identify the requests from getinfo tool in ioctl */
165 #define XGE_QUERY_STATS 1
166 #define XGE_QUERY_PCICONF 2
167 #define XGE_QUERY_DEVSTATS 3
168 #define XGE_QUERY_DEVCONF 4
169 #define XGE_READ_VERSION 5
170 #define XGE_QUERY_SWSTATS 6
171 #define XGE_QUERY_DRIVERSTATS 7
172 #define XGE_SET_BUFFER_MODE_1 8
173 #define XGE_SET_BUFFER_MODE_2 9
174 #define XGE_SET_BUFFER_MODE_5 10
175 #define XGE_QUERY_BUFFER_MODE 11
177 #define XGE_OFFSET_OF_LAST_REG 0x3180
179 #define VENDOR_ID_AMD 0x1022
180 #define DEVICE_ID_8131_PCI_BRIDGE 0x7450
182 typedef struct mbuf *mbuf_t;
184 typedef enum xge_lables {
187 xge_free_terminate_hal_driver = 2,
188 xge_free_hal_device = 3,
189 xge_free_pci_info = 4,
191 xge_free_bar0_resource = 6,
193 xge_free_bar1_resource = 8,
194 xge_free_irq_resource = 9,
195 xge_free_terminate_hal_device = 10,
196 xge_free_media_interface = 11,
199 typedef enum xge_option {
204 typedef enum xge_event_e {
205 XGE_LL_EVENT_TRY_XMIT_AGAIN = XGE_LL_EVENT_BASE + 1,
206 XGE_LL_EVENT_DEVICE_RESETTING = XGE_LL_EVENT_BASE + 2
209 typedef struct xge_msi_info {
210 u16 msi_control; /* MSI control 0x42 */
211 u32 msi_lower_address; /* MSI lower address 0x44 */
212 u32 msi_higher_address; /* MSI higher address 0x48 */
213 u16 msi_data; /* MSI data */
216 typedef struct xge_driver_stats_t {
250 u64 lro_session_exceeded;
252 } xge_driver_stats_t;
254 typedef struct xge_lro_entry_t {
255 SLIST_ENTRY(xge_lro_entry_t) next;
258 struct ip *lro_header_ip;
275 SLIST_HEAD(lro_head, xge_lro_entry_t);
277 /* Adapter structure */
278 typedef struct xge_lldev_t {
279 device_t device; /* Device */
280 struct ifnet *ifnetp; /* Interface ifnet structure */
281 struct resource *irq; /* Resource structure for IRQ */
282 void *irqhandle; /* IRQ handle */
283 xge_pci_info_t *pdev; /* PCI info */
284 xge_hal_device_t *devh; /* HAL: Device Handle */
285 struct mtx mtx_drv; /* Mutex - Driver */
286 struct mtx mtx_tx[XGE_FIFO_COUNT];
288 char mtx_name_drv[16];/*Mutex Name - Driver */
289 char mtx_name_tx[16][XGE_FIFO_COUNT];
290 /* Mutex Name - Tx */
291 struct callout timer; /* Timer for polling */
292 struct ifmedia media; /* In-kernel representation of a */
293 /* single supported media type */
294 xge_hal_channel_h fifo_channel[XGE_FIFO_COUNT];
296 xge_hal_channel_h ring_channel[XGE_RING_COUNT];
298 bus_dma_tag_t dma_tag_tx; /* Tag for dtr dma mapping (Tx) */
299 bus_dma_tag_t dma_tag_rx; /* Tag for dtr dma mapping (Rx) */
300 bus_dmamap_t extra_dma_map; /* Extra DMA map for Rx */
301 xge_msi_info_t msi_info; /* MSI info */
302 xge_driver_stats_t driver_stats; /* Driver statistics */
303 int initialized; /* Flag: Initialized or not */
304 int all_multicast; /* All multicast flag */
305 int macaddr_count; /* Multicast address count */
306 int in_detach; /* To avoid ioctl during detach */
307 int buffer_mode; /* Buffer Mode */
308 int rxd_mbuf_cnt; /* Number of buffers used */
309 int rxd_mbuf_len[5];/* Buffer lengths */
310 int enabled_tso; /* Flag: TSO Enabled */
311 int enabled_lro; /* Flag: LRO Enabled */
312 int enabled_msi; /* Flag: MSI Enabled */
313 int mtu; /* Interface MTU */
314 int lro_num; /* Number of LRO sessions */
315 struct lro_head lro_active; /* Active LRO sessions */
316 struct lro_head lro_free; /* Free LRO sessions */
319 /* Rx descriptor private structure */
320 typedef struct xge_rx_priv_t {
322 xge_dma_mbuf_t dmainfo[5];
325 /* Tx descriptor private structure */
326 typedef struct xge_tx_priv_t {
328 bus_dmamap_t dma_map;
332 typedef struct xge_register_t {
338 void xge_init_params(xge_hal_device_config_t *, device_t);
339 void xge_init(void *);
340 void xge_device_init(xge_lldev_t *, xge_hal_channel_reopen_e);
341 void xge_device_stop(xge_lldev_t *, xge_hal_channel_reopen_e);
342 void xge_stop(xge_lldev_t *);
343 void xge_resources_free(device_t, xge_lables_e);
344 void xge_callback_link_up(void *);
345 void xge_callback_link_down(void *);
346 void xge_callback_crit_err(void *, xge_hal_event_e, u64);
347 void xge_callback_event(xge_queue_item_t *);
348 int xge_ifmedia_change(struct ifnet *);
349 void xge_ifmedia_status(struct ifnet *, struct ifmediareq *);
350 int xge_ioctl(struct ifnet *, unsigned long, caddr_t);
351 int xge_ioctl_stats(xge_lldev_t *, struct ifreq *);
352 int xge_ioctl_registers(xge_lldev_t *, struct ifreq *);
353 void xge_timer(void *);
354 int xge_isr_filter(void *);
355 void xge_isr_line(void *);
356 void xge_isr_msi(void *);
357 void xge_enable_msi(xge_lldev_t *);
358 int xge_rx_open(int, xge_lldev_t *, xge_hal_channel_reopen_e);
359 int xge_tx_open(xge_lldev_t *, xge_hal_channel_reopen_e);
360 void xge_channel_close(xge_lldev_t *, xge_hal_channel_reopen_e);
361 int xge_channel_open(xge_lldev_t *, xge_hal_channel_reopen_e);
362 xge_hal_status_e xge_rx_compl(xge_hal_channel_h, xge_hal_dtr_h, u8, void *);
363 xge_hal_status_e xge_tx_compl(xge_hal_channel_h, xge_hal_dtr_h, u8, void *);
364 xge_hal_status_e xge_tx_initial_replenish(xge_hal_channel_h, xge_hal_dtr_h,
365 int, void *, xge_hal_channel_reopen_e);
366 xge_hal_status_e xge_rx_initial_replenish(xge_hal_channel_h, xge_hal_dtr_h,
367 int, void *, xge_hal_channel_reopen_e);
368 void xge_rx_term(xge_hal_channel_h, xge_hal_dtr_h, xge_hal_dtr_state_e,
369 void *, xge_hal_channel_reopen_e);
370 void xge_tx_term(xge_hal_channel_h, xge_hal_dtr_h, xge_hal_dtr_state_e,
371 void *, xge_hal_channel_reopen_e);
372 void xge_set_mbuf_cflags(mbuf_t);
373 void xge_send(struct ifnet *);
374 static void inline xge_send_locked(struct ifnet *, int);
375 int xge_get_buf(xge_hal_dtr_h, xge_rx_priv_t *, xge_lldev_t *, int);
376 int xge_ring_dtr_get(mbuf_t, xge_hal_channel_h, xge_hal_dtr_h, xge_lldev_t *,
378 int xge_get_buf_3b_5b(xge_hal_dtr_h, xge_rx_priv_t *, xge_lldev_t *);
379 void dmamap_cb(void *, bus_dma_segment_t *, int, int);
380 void xge_reset(xge_lldev_t *);
381 void xge_setmulti(xge_lldev_t *);
382 void xge_enable_promisc(xge_lldev_t *);
383 void xge_disable_promisc(xge_lldev_t *);
384 int xge_change_mtu(xge_lldev_t *, int);
385 void xge_buffer_mode_init(xge_lldev_t *, int);
386 void xge_initialize(device_t, xge_hal_channel_reopen_e);
387 void xge_terminate(device_t, xge_hal_channel_reopen_e);
388 int xge_probe(device_t);
389 int xge_driver_initialize(void);
390 void xge_media_init(device_t);
391 void xge_pci_space_save(device_t);
392 void xge_pci_space_restore(device_t);
393 void xge_msi_info_save(xge_lldev_t *);
394 void xge_msi_info_restore(xge_lldev_t *);
395 int xge_attach(device_t);
396 int xge_interface_setup(device_t);
397 int xge_detach(device_t);
398 int xge_shutdown(device_t);
399 void xge_mutex_init(xge_lldev_t *);
400 void xge_mutex_destroy(xge_lldev_t *);
401 void xge_print_info(xge_lldev_t *);
402 void xge_lro_flush_sessions(xge_lldev_t *);
403 void xge_rx_buffer_sizes_set(xge_lldev_t *, int, int);
404 void xge_accumulate_large_rx(xge_lldev_t *, struct mbuf *, int,
406 xge_hal_status_e xge_create_dma_tags(device_t);
407 void xge_add_sysctl_handlers(xge_lldev_t *);
408 void xge_confirm_changes(xge_lldev_t *, xge_option_e);
409 static int xge_lro_accumulate(xge_lldev_t *, struct mbuf *);
410 static void xge_lro_flush(xge_lldev_t *, xge_lro_entry_t *);