2 * Copyright (c) 2002-2007 Neterion, Inc.
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6 * modification, are permitted provided that the following conditions
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30 * FileName : xgehal-device.h
32 * Description: HAL device object functionality
34 * Created: 14 May 2004
37 #ifndef XGE_HAL_DEVICE_H
38 #define XGE_HAL_DEVICE_H
40 #include <dev/nxge/include/xge-os-pal.h>
41 #include <dev/nxge/include/xge-queue.h>
42 #include <dev/nxge/include/xgehal-event.h>
43 #include <dev/nxge/include/xgehal-config.h>
44 #include <dev/nxge/include/xgehal-regs.h>
45 #include <dev/nxge/include/xgehal-channel.h>
46 #include <dev/nxge/include/xgehal-stats.h>
47 #include <dev/nxge/include/xgehal-ring.h>
49 #include "xgehal-common-regs.h"
50 #include "xgehal-pcicfg-mgmt-regs.h"
51 #include "xgehal-mrpcim-regs.h"
52 #include "xgehal-srpcim-regs.h"
53 #include "xgehal-vpath-regs.h"
54 #include "xgehal-bitmap.h"
55 #include "xgehal-virtualpath.h"
56 #include "xgehal-lbwrapper.h"
57 #include "xgehal-blockpool.h"
58 #include "xgehal-regpool.h"
63 #define XGE_HAL_VPD_LENGTH 80
64 #define XGE_HAL_CARD_XENA_VPD_ADDR 0x50
65 #define XGE_HAL_CARD_HERC_VPD_ADDR 0x80
66 #define XGE_HAL_VPD_READ_COMPLETE 0x80
67 #define XGE_HAL_VPD_BUFFER_SIZE 128
68 #define XGE_HAL_DEVICE_XMSI_WAIT_MAX_MILLIS 500
69 #define XGE_HAL_DEVICE_CMDMEM_WAIT_MAX_MILLIS 500
70 #define XGE_HAL_DEVICE_QUIESCENT_WAIT_MAX_MILLIS 500
71 #define XGE_HAL_DEVICE_FAULT_WAIT_MAX_MILLIS 50
72 #define XGE_HAL_DEVICE_RESET_WAIT_MAX_MILLIS 250
73 #define XGE_HAL_DEVICE_SPDM_READY_WAIT_MAX_MILLIS 250 /* TODO */
75 #define XGE_HAL_MAGIC 0x12345678
76 #define XGE_HAL_DEAD 0xDEADDEAD
77 #define XGE_HAL_DUMP_BUF_SIZE 0x4000
79 #define XGE_HAL_LRO_MAX_BUCKETS 32
82 * enum xge_hal_card_e - Xframe adapter type.
83 * @XGE_HAL_CARD_UNKNOWN: Unknown device.
84 * @XGE_HAL_CARD_XENA: Xframe I device.
85 * @XGE_HAL_CARD_HERC: Xframe II (PCI-266Mhz) device.
86 * @XGE_HAL_CARD_TITAN: Xframe ER (PCI-266Mhz) device.
88 * Enumerates Xframe adapter types. The corresponding PCI device
89 * IDs are listed in the file xgehal-defs.h.
90 * (See XGE_PCI_DEVICE_ID_XENA_1, etc.)
92 * See also: xge_hal_device_check_id().
94 typedef enum xge_hal_card_e {
95 XGE_HAL_CARD_UNKNOWN = 0,
96 XGE_HAL_CARD_XENA = 1,
97 XGE_HAL_CARD_HERC = 2,
98 XGE_HAL_CARD_TITAN = 3,
102 * struct xge_hal_device_attr_t - Device memory spaces.
103 * @regh0: BAR0 mapped memory handle (Solaris), or simply PCI device @pdev
104 * (Linux and the rest.)
105 * @regh1: BAR1 mapped memory handle. Same comment as above.
106 * @bar0: BAR0 virtual address.
107 * @bar1: BAR1 virtual address.
108 * @irqh: IRQ handle (Solaris).
109 * @cfgh: Configuration space handle (Solaris), or PCI device @pdev (Linux).
110 * @pdev: PCI device object.
112 * Device memory spaces. Includes configuration, BAR0, BAR1, etc. per device
113 * mapped memories. Also, includes a pointer to OS-specific PCI device object.
115 typedef struct xge_hal_device_attr_t {
125 } xge_hal_device_attr_t;
128 * enum xge_hal_device_link_state_e - Link state enumeration.
129 * @XGE_HAL_LINK_NONE: Invalid link state.
130 * @XGE_HAL_LINK_DOWN: Link is down.
131 * @XGE_HAL_LINK_UP: Link is up.
134 typedef enum xge_hal_device_link_state_e {
138 } xge_hal_device_link_state_e;
142 * enum xge_hal_pci_mode_e - PIC bus speed and mode specific enumeration.
143 * @XGE_HAL_PCI_33MHZ_MODE: 33 MHZ pci mode.
144 * @XGE_HAL_PCI_66MHZ_MODE: 66 MHZ pci mode.
145 * @XGE_HAL_PCIX_M1_66MHZ_MODE: PCIX M1 66MHZ mode.
146 * @XGE_HAL_PCIX_M1_100MHZ_MODE: PCIX M1 100MHZ mode.
147 * @XGE_HAL_PCIX_M1_133MHZ_MODE: PCIX M1 133MHZ mode.
148 * @XGE_HAL_PCIX_M2_66MHZ_MODE: PCIX M2 66MHZ mode.
149 * @XGE_HAL_PCIX_M2_100MHZ_MODE: PCIX M2 100MHZ mode.
150 * @XGE_HAL_PCIX_M2_133MHZ_MODE: PCIX M3 133MHZ mode.
151 * @XGE_HAL_PCIX_M1_RESERVED: PCIX M1 reserved mode.
152 * @XGE_HAL_PCIX_M1_66MHZ_NS: PCIX M1 66MHZ mode not supported.
153 * @XGE_HAL_PCIX_M1_100MHZ_NS: PCIX M1 100MHZ mode not supported.
154 * @XGE_HAL_PCIX_M1_133MHZ_NS: PCIX M1 133MHZ not supported.
155 * @XGE_HAL_PCIX_M2_RESERVED: PCIX M2 reserved.
156 * @XGE_HAL_PCIX_533_RESERVED: PCIX 533 reserved.
157 * @XGE_HAL_PCI_BASIC_MODE: PCI basic mode, XENA specific value.
158 * @XGE_HAL_PCIX_BASIC_MODE: PCIX basic mode, XENA specific value.
159 * @XGE_HAL_PCI_INVALID_MODE: Invalid PCI or PCIX mode.
162 typedef enum xge_hal_pci_mode_e {
163 XGE_HAL_PCI_33MHZ_MODE = 0x0,
164 XGE_HAL_PCI_66MHZ_MODE = 0x1,
165 XGE_HAL_PCIX_M1_66MHZ_MODE = 0x2,
166 XGE_HAL_PCIX_M1_100MHZ_MODE = 0x3,
167 XGE_HAL_PCIX_M1_133MHZ_MODE = 0x4,
168 XGE_HAL_PCIX_M2_66MHZ_MODE = 0x5,
169 XGE_HAL_PCIX_M2_100MHZ_MODE = 0x6,
170 XGE_HAL_PCIX_M2_133MHZ_MODE = 0x7,
171 XGE_HAL_PCIX_M1_RESERVED = 0x8,
172 XGE_HAL_PCIX_M1_66MHZ_NS = 0xA,
173 XGE_HAL_PCIX_M1_100MHZ_NS = 0xB,
174 XGE_HAL_PCIX_M1_133MHZ_NS = 0xC,
175 XGE_HAL_PCIX_M2_RESERVED = 0xD,
176 XGE_HAL_PCIX_533_RESERVED = 0xE,
177 XGE_HAL_PCI_BASIC_MODE = 0x10,
178 XGE_HAL_PCIX_BASIC_MODE = 0x11,
179 XGE_HAL_PCI_INVALID_MODE = 0x12,
180 } xge_hal_pci_mode_e;
183 * enum xge_hal_pci_bus_frequency_e - PCI bus frequency enumeration.
184 * @XGE_HAL_PCI_BUS_FREQUENCY_33MHZ: PCI bus frequency 33MHZ
185 * @XGE_HAL_PCI_BUS_FREQUENCY_66MHZ: PCI bus frequency 66MHZ
186 * @XGE_HAL_PCI_BUS_FREQUENCY_100MHZ: PCI bus frequency 100MHZ
187 * @XGE_HAL_PCI_BUS_FREQUENCY_133MHZ: PCI bus frequency 133MHZ
188 * @XGE_HAL_PCI_BUS_FREQUENCY_200MHZ: PCI bus frequency 200MHZ
189 * @XGE_HAL_PCI_BUS_FREQUENCY_250MHZ: PCI bus frequency 250MHZ
190 * @XGE_HAL_PCI_BUS_FREQUENCY_266MHZ: PCI bus frequency 266MHZ
191 * @XGE_HAL_PCI_BUS_FREQUENCY_UNKNOWN: Unrecognized PCI bus frequency value.
194 typedef enum xge_hal_pci_bus_frequency_e {
195 XGE_HAL_PCI_BUS_FREQUENCY_33MHZ = 33,
196 XGE_HAL_PCI_BUS_FREQUENCY_66MHZ = 66,
197 XGE_HAL_PCI_BUS_FREQUENCY_100MHZ = 100,
198 XGE_HAL_PCI_BUS_FREQUENCY_133MHZ = 133,
199 XGE_HAL_PCI_BUS_FREQUENCY_200MHZ = 200,
200 XGE_HAL_PCI_BUS_FREQUENCY_250MHZ = 250,
201 XGE_HAL_PCI_BUS_FREQUENCY_266MHZ = 266,
202 XGE_HAL_PCI_BUS_FREQUENCY_UNKNOWN = 0
203 } xge_hal_pci_bus_frequency_e;
206 * enum xge_hal_pci_bus_width_e - PCI bus width enumeration.
207 * @XGE_HAL_PCI_BUS_WIDTH_64BIT: 64 bit bus width.
208 * @XGE_HAL_PCI_BUS_WIDTH_32BIT: 32 bit bus width.
209 * @XGE_HAL_PCI_BUS_WIDTH_UNKNOWN: unknown bus width.
212 typedef enum xge_hal_pci_bus_width_e {
213 XGE_HAL_PCI_BUS_WIDTH_64BIT = 0,
214 XGE_HAL_PCI_BUS_WIDTH_32BIT = 1,
215 XGE_HAL_PCI_BUS_WIDTH_UNKNOWN = 2,
216 } xge_hal_pci_bus_width_e;
218 #if defined (XGE_HAL_CONFIG_LRO)
220 #define IP_TOTAL_LENGTH_OFFSET 2
221 #define IP_FAST_PATH_HDR_MASK 0x45
222 #define TCP_FAST_PATH_HDR_MASK1 0x50
223 #define TCP_FAST_PATH_HDR_MASK2 0x10
224 #define TCP_FAST_PATH_HDR_MASK3 0x18
225 #define IP_SOURCE_ADDRESS_OFFSET 12
226 #define IP_DESTINATION_ADDRESS_OFFSET 16
227 #define TCP_DESTINATION_PORT_OFFSET 2
228 #define TCP_SOURCE_PORT_OFFSET 0
229 #define TCP_DATA_OFFSET_OFFSET 12
230 #define TCP_WINDOW_OFFSET 14
231 #define TCP_SEQUENCE_NUMBER_OFFSET 4
232 #define TCP_ACKNOWLEDGEMENT_NUMBER_OFFSET 8
234 typedef struct tcplro {
246 typedef struct iplro {
257 /*The options start here. */
261 * LRO object, one per each LRO session.
264 /* non-linear: contains scatter-gather list of
265 xframe-mapped received buffers */
266 OS_NETSTACK_BUF os_buf;
267 OS_NETSTACK_BUF os_buf_end;
269 /* link layer header of the first frame;
270 remains intack throughout the processing */
273 /* IP header - gets _collapsed_ */
276 /* transport header - gets _collapsed_ */
279 /* Next tcp sequence number */
280 u32 tcp_next_seq_num;
281 /* Current tcp seq & ack */
285 /* total number of accumulated (so far) frames */
288 /* total data length */
291 /* receive side hash value, available from Hercules */
297 /* Total length of the fragments clubbed with the inital frame */
300 /* LRO frame contains time stamp, if (ts_off != -1) */
307 * xge_hal_spdm_entry_t
309 * Represents a single spdm entry in the SPDM table.
311 typedef struct xge_hal_spdm_entry_t {
312 xge_hal_ipaddr_t src_ip;
313 xge_hal_ipaddr_t dst_ip;
322 } xge_hal_spdm_entry_t;
324 #if defined(XGE_HAL_CONFIG_LRO)
326 lro_t lro_pool[XGE_HAL_LRO_MAX_BUCKETS];
329 } xge_hal_lro_desc_t;
334 * Represents vpd capabilty structure
336 typedef struct xge_hal_vpd_data_t {
337 u8 product_name[XGE_HAL_VPD_LENGTH];
338 u8 serial_num[XGE_HAL_VPD_LENGTH];
339 } xge_hal_vpd_data_t;
344 * HAL device object. Represents Xframe.
358 xge_hal_pci_config_t pci_config_space;
359 xge_hal_pci_config_t pci_config_space_bios;
360 xge_hal_device_config_t config;
361 xge_list_t free_channels;
362 xge_list_t fifo_channels;
363 xge_list_t ring_channels;
365 __hal_bitmap_entry_t bitmap_table[XGE_HAL_MAX_BITMAP_BITS];
366 __hal_virtualpath_t virtual_paths[XGE_HAL_MAX_VIRTUAL_PATHS];
367 __hal_blockpool_t block_pool;
368 __hal_regpool_t reg_pool;
370 volatile int is_initialized;
371 volatile int terminating;
372 xge_hal_stats_t stats;
373 macaddr_t macaddr[1];
375 volatile int mcast_refcnt;
377 volatile xge_hal_device_link_state_e link_state;
378 void *upper_layer_info;
379 xge_hal_device_attr_t orig_attr;
383 int hw_is_initialized;
387 int inject_bad_tcode_for_chan_type;
388 int reset_needed_after_close;
390 xge_hal_tti_config_t bimodal_tti[XGE_HAL_MAX_RING_NUM];
391 int bimodal_timer_val_us;
392 int bimodal_urange_a_en;
393 int bimodal_intr_cnt;
395 u16 spdm_max_entries;
396 xge_hal_spdm_entry_t **spdm_table;
397 spinlock_t spdm_lock;
399 #if defined(XGE_HAL_CONFIG_LRO)
400 xge_hal_lro_desc_t lro_desc[XGE_HAL_MAX_RING_NUM];
402 spinlock_t xena_post_lock;
404 /* bimodal workload stats */
405 int irq_workload_rxd[XGE_HAL_MAX_RING_NUM];
406 int irq_workload_rxcnt[XGE_HAL_MAX_RING_NUM];
407 int irq_workload_rxlen[XGE_HAL_MAX_RING_NUM];
408 int irq_workload_txd[XGE_HAL_MAX_FIFO_NUM];
409 int irq_workload_txcnt[XGE_HAL_MAX_FIFO_NUM];
410 int irq_workload_txlen[XGE_HAL_MAX_FIFO_NUM];
412 int mtu_first_time_set;
414 u64 rxufca_lbolt_time;
415 u64 rxufca_intr_thres;
417 xge_hal_pci_mode_e pci_mode;
418 xge_hal_pci_bus_frequency_e bus_frequency;
419 xge_hal_pci_bus_width_e bus_width;
420 xge_hal_vpd_data_t vpd_data;
421 volatile int in_poll;
422 u64 msix_vector_table[XGE_HAL_MAX_MSIX_MESSAGES_WITH_ADDR];
426 /* ========================== PRIVATE API ================================= */
429 __hal_device_event_queued(void *data, int event_type);
432 __hal_device_set_swapper(xge_hal_device_t *hldev);
435 __hal_device_rth_it_configure(xge_hal_device_t *hldev);
438 __hal_device_rth_spdm_configure(xge_hal_device_t *hldev);
441 __hal_verify_pcc_idle(xge_hal_device_t *hldev, u64 adp_status);
444 __hal_device_handle_pic(xge_hal_device_t *hldev, u64 reason);
447 __hal_read_spdm_entry_line(xge_hal_device_t *hldev, u8 spdm_line,
448 u16 spdm_entry, u64 *spdm_line_val);
450 void __hal_pio_mem_write32_upper(pci_dev_h pdev, pci_reg_h regh, u32 val,
453 void __hal_pio_mem_write32_lower(pci_dev_h pdev, pci_reg_h regh, u32 val,
455 void __hal_device_get_vpd_data(xge_hal_device_t *hldev);
458 __hal_device_handle_txpic(xge_hal_device_t *hldev, u64 reason);
461 __hal_device_handle_txdma(xge_hal_device_t *hldev, u64 reason);
464 __hal_device_handle_txmac(xge_hal_device_t *hldev, u64 reason);
467 __hal_device_handle_txxgxs(xge_hal_device_t *hldev, u64 reason);
470 __hal_device_handle_rxpic(xge_hal_device_t *hldev, u64 reason);
473 __hal_device_handle_rxdma(xge_hal_device_t *hldev, u64 reason);
476 __hal_device_handle_rxmac(xge_hal_device_t *hldev, u64 reason);
479 __hal_device_handle_rxxgxs(xge_hal_device_t *hldev, u64 reason);
482 __hal_device_handle_mc(xge_hal_device_t *hldev, u64 reason);
485 __hal_device_register_poll(xge_hal_device_t *hldev, u64 *reg, int op, u64 mask,
488 __hal_device_rts_mac_configure(xge_hal_device_t *hldev);
491 __hal_device_rts_qos_configure(xge_hal_device_t *hldev);
494 __hal_device_rts_port_configure(xge_hal_device_t *hldev);
497 __hal_device_rti_configure(xge_hal_device_t *hldev, int runtime);
500 __hal_device_msi_intr_endis(xge_hal_device_t *hldev, int flag);
503 __hal_device_msix_intr_endis(xge_hal_device_t *hldev,
504 xge_hal_channel_t *channel, int flag);
506 /* =========================== PUBLIC API ================================= */
509 __hal_fix_time_ival_herc(xge_hal_device_t *hldev,
510 unsigned int time_ival);
512 xge_hal_rts_rth_itable_set(xge_hal_device_t *hldev, u8 *itable,
516 xge_hal_rts_rth_set(xge_hal_device_t *hldev, u8 def_q, u64 hash_type,
520 xge_hal_rts_rth_init(xge_hal_device_t *hldev);
523 xge_hal_rts_rth_clr(xge_hal_device_t *hldev);
526 xge_hal_rts_rth_start(xge_hal_device_t *hldev);
529 xge_hal_rts_rth_stop(xge_hal_device_t *hldev);
532 xge_hal_device_rts_rth_key_set(xge_hal_device_t *hldev, u8 KeySize, u8 *Key);
535 xge_hal_device_rts_mac_enable(xge_hal_device_h devh, int index, macaddr_t macaddr);
538 xge_hal_device_rts_mac_disable(xge_hal_device_h devh, int index);
540 int xge_hal_reinitialize_hw(xge_hal_device_t * hldev);
543 * xge_hal_device_rti_reconfigure
546 static inline xge_hal_status_e
547 xge_hal_device_rti_reconfigure(xge_hal_device_t *hldev)
549 return __hal_device_rti_configure(hldev, 1);
553 * xge_hal_device_rts_port_reconfigure
556 static inline xge_hal_status_e
557 xge_hal_device_rts_port_reconfigure(xge_hal_device_t *hldev)
559 return __hal_device_rts_port_configure(hldev);
563 * xge_hal_device_is_initialized - Returns 0 if device is not
564 * initialized, non-zero otherwise.
565 * @devh: HAL device handle.
567 * Returns 0 if device is not initialized, non-zero otherwise.
570 xge_hal_device_is_initialized(xge_hal_device_h devh)
572 return ((xge_hal_device_t*)devh)->is_initialized;
577 * xge_hal_device_in_poll - non-zero, if xge_hal_device_poll() is executing.
578 * @devh: HAL device handle.
580 * Returns non-zero if xge_hal_device_poll() is executing, and 0 - otherwise.
583 xge_hal_device_in_poll(xge_hal_device_h devh)
585 return ((xge_hal_device_t*)devh)->in_poll;
590 * xge_hal_device_inject_ecc - Inject ECC error.
591 * @devh: HAL device, pointer to xge_hal_device_t structure.
592 * @err_reg: Contains the error register.
594 * This function is used to inject ECC error into the driver flow.
595 * This facility can be used to test the driver flow in the
596 * case of ECC error is reported by the firmware.
599 * See also: xge_hal_device_inject_serr(),
600 * xge_hal_device_inject_bad_tcode()
603 xge_hal_device_inject_ecc(xge_hal_device_h devh, u64 err_reg)
605 ((xge_hal_device_t*)devh)->inject_ecc = err_reg;
610 * xge_hal_device_inject_serr - Inject SERR error.
611 * @devh: HAL device, pointer to xge_hal_device_t structure.
612 * @err_reg: Contains the error register.
614 * This function is used to inject SERR error into the driver flow.
615 * This facility can be used to test the driver flow in the
616 * case of SERR error is reported by firmware.
619 * See also: xge_hal_device_inject_ecc(),
620 * xge_hal_device_inject_bad_tcode()
623 xge_hal_device_inject_serr(xge_hal_device_h devh, u64 err_reg)
625 ((xge_hal_device_t*)devh)->inject_serr = err_reg;
630 * xge_hal_device_inject_bad_tcode - Inject Bad transfer code.
631 * @devh: HAL device, pointer to xge_hal_device_t structure.
632 * @chan_type: Channel type (fifo/ring).
633 * @t_code: Transfer code.
635 * This function is used to inject bad (Tx/Rx Data)transfer code
636 * into the driver flow.
638 * This facility can be used to test the driver flow in the
639 * case of bad transfer code reported by firmware for a Tx/Rx data
643 * See also: xge_hal_device_inject_ecc(), xge_hal_device_inject_serr()
646 xge_hal_device_inject_bad_tcode(xge_hal_device_h devh, int chan_type, u8 t_code)
648 ((xge_hal_device_t*)devh)->inject_bad_tcode_for_chan_type = chan_type;
649 ((xge_hal_device_t*)devh)->inject_bad_tcode = t_code;
652 void xge_hal_device_msi_enable(xge_hal_device_h devh);
655 * xge_hal_device_msi_mode - Is MSI enabled?
656 * @devh: HAL device handle.
658 * Returns 0 if MSI is enabled for the specified device,
659 * non-zero otherwise.
662 xge_hal_device_msi_mode(xge_hal_device_h devh)
664 return ((xge_hal_device_t*)devh)->msi_enabled;
668 * xge_hal_device_queue - Get per-device event queue.
669 * @devh: HAL device handle.
671 * Returns: event queue associated with the specified HAL device.
673 static inline xge_queue_h
674 xge_hal_device_queue (xge_hal_device_h devh)
676 return ((xge_hal_device_t*)devh)->queueh;
680 * xge_hal_device_attr - Get original (user-specified) device
682 * @devh: HAL device handle.
684 * Returns: original (user-specified) device attributes.
686 static inline xge_hal_device_attr_t*
687 xge_hal_device_attr(xge_hal_device_h devh)
689 return &((xge_hal_device_t*)devh)->orig_attr;
693 * xge_hal_device_private_set - Set ULD context.
694 * @devh: HAL device handle.
695 * @data: pointer to ULD context
697 * Use HAL device to set upper-layer driver (ULD) context.
699 * See also: xge_hal_device_from_private(), xge_hal_device_private()
702 xge_hal_device_private_set(xge_hal_device_h devh, void *data)
704 ((xge_hal_device_t*)devh)->upper_layer_info = data;
708 * xge_hal_device_private - Get ULD context.
709 * @devh: HAL device handle.
711 * Use HAL device to get upper-layer driver (ULD) context.
713 * Returns: ULD context.
715 * See also: xge_hal_device_from_private(), xge_hal_device_private_set()
718 xge_hal_device_private(xge_hal_device_h devh)
720 return ((xge_hal_device_t*)devh)->upper_layer_info;
724 * xge_hal_device_from_private - Get HAL device object from private.
725 * @info_ptr: ULD context.
727 * Use ULD context to get HAL device.
729 * Returns: Device handle.
731 * See also: xge_hal_device_private(), xge_hal_device_private_set()
733 static inline xge_hal_device_h
734 xge_hal_device_from_private(void *info_ptr)
736 return xge_container_of((void ** ) info_ptr, xge_hal_device_t,
741 * xge_hal_device_mtu_check - check MTU value for ranges
743 * @new_mtu: new MTU value to check
745 * Will do sanity check for new MTU value.
747 * Returns: XGE_HAL_OK - success.
748 * XGE_HAL_ERR_INVALID_MTU_SIZE - MTU is invalid.
750 * See also: xge_hal_device_mtu_set()
752 static inline xge_hal_status_e
753 xge_hal_device_mtu_check(xge_hal_device_t *hldev, int new_mtu)
755 if ((new_mtu < XGE_HAL_MIN_MTU) || (new_mtu > XGE_HAL_MAX_MTU)) {
756 return XGE_HAL_ERR_INVALID_MTU_SIZE;
762 void xge_hal_device_bcast_enable(xge_hal_device_h devh);
764 void xge_hal_device_bcast_disable(xge_hal_device_h devh);
766 void xge_hal_device_terminating(xge_hal_device_h devh);
768 xge_hal_status_e xge_hal_device_initialize(xge_hal_device_t *hldev,
769 xge_hal_device_attr_t *attr, xge_hal_device_config_t *config);
771 void xge_hal_device_terminate(xge_hal_device_t *hldev);
773 xge_hal_status_e xge_hal_device_reset(xge_hal_device_t *hldev);
775 xge_hal_status_e xge_hal_device_macaddr_get(xge_hal_device_t *hldev,
776 int index, macaddr_t *macaddr);
778 xge_hal_status_e xge_hal_device_macaddr_set(xge_hal_device_t *hldev,
779 int index, macaddr_t macaddr);
781 xge_hal_status_e xge_hal_device_macaddr_clear(xge_hal_device_t *hldev,
784 int xge_hal_device_macaddr_find(xge_hal_device_t *hldev, macaddr_t wanted);
786 xge_hal_status_e xge_hal_device_mtu_set(xge_hal_device_t *hldev, int new_mtu);
788 xge_hal_status_e xge_hal_device_status(xge_hal_device_t *hldev, u64 *hw_status);
790 void xge_hal_device_intr_enable(xge_hal_device_t *hldev);
792 void xge_hal_device_intr_disable(xge_hal_device_t *hldev);
794 xge_hal_status_e xge_hal_device_mcast_enable(xge_hal_device_t *hldev);
796 xge_hal_status_e xge_hal_device_mcast_disable(xge_hal_device_t *hldev);
798 void xge_hal_device_promisc_enable(xge_hal_device_t *hldev);
800 void xge_hal_device_promisc_disable(xge_hal_device_t *hldev);
802 xge_hal_status_e xge_hal_device_disable(xge_hal_device_t *hldev);
804 xge_hal_status_e xge_hal_device_enable(xge_hal_device_t *hldev);
806 xge_hal_status_e xge_hal_device_handle_tcode(xge_hal_channel_h channelh,
810 xge_hal_status_e xge_hal_device_link_state(xge_hal_device_h devh,
811 xge_hal_device_link_state_e *ls);
813 void xge_hal_device_sched_timer(xge_hal_device_h devh, int interval_us,
816 void xge_hal_device_poll(xge_hal_device_h devh);
818 xge_hal_card_e xge_hal_device_check_id(xge_hal_device_h devh);
820 int xge_hal_device_is_slot_freeze(xge_hal_device_h devh);
823 xge_hal_device_pci_info_get(xge_hal_device_h devh, xge_hal_pci_mode_e *pci_mode,
824 xge_hal_pci_bus_frequency_e *bus_frequency,
825 xge_hal_pci_bus_width_e *bus_width);
828 xge_hal_spdm_entry_add(xge_hal_device_h devh, xge_hal_ipaddr_t *src_ip,
829 xge_hal_ipaddr_t *dst_ip, u16 l4_sp, u16 l4_dp,
830 u8 is_tcp, u8 is_ipv4, u8 tgt_queue);
833 xge_hal_spdm_entry_remove(xge_hal_device_h devh, xge_hal_ipaddr_t *src_ip,
834 xge_hal_ipaddr_t *dst_ip, u16 l4_sp, u16 l4_dp,
835 u8 is_tcp, u8 is_ipv4);
838 xge_hal_device_rts_section_enable(xge_hal_device_h devh, int index);
841 xge_hal_device_is_closed (xge_hal_device_h devh);
843 /* private functions, don't use them in ULD */
845 void __hal_serial_mem_write64(xge_hal_device_t *hldev, u64 value, u64 *reg);
847 u64 __hal_serial_mem_read64(xge_hal_device_t *hldev, u64 *reg);
850 /* Some function protoypes for MSI implementation. */
852 xge_hal_channel_msi_set (xge_hal_channel_h channelh, int msi,
855 xge_hal_mask_msi(xge_hal_device_t *hldev);
858 xge_hal_unmask_msi(xge_hal_channel_h channelh);
861 xge_hal_channel_msix_set(xge_hal_channel_h channelh, int msix_idx);
864 xge_hal_mask_msix(xge_hal_device_h devh, int msi_id);
867 xge_hal_unmask_msix(xge_hal_device_h devh, int msi_id);
869 #if defined(XGE_HAL_CONFIG_LRO)
871 xge_hal_lro_init(u32 lro_scale, xge_hal_device_t *hldev);
874 #if defined(XGE_DEBUG_FP) && (XGE_DEBUG_FP & XGE_DEBUG_FP_DEVICE)
875 #define __HAL_STATIC_DEVICE
876 #define __HAL_INLINE_DEVICE
878 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE int
879 xge_hal_device_rev(xge_hal_device_t *hldev);
881 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
882 xge_hal_device_begin_irq(xge_hal_device_t *hldev, u64 *reason);
884 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
885 xge_hal_device_clear_rx(xge_hal_device_t *hldev);
887 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
888 xge_hal_device_clear_tx(xge_hal_device_t *hldev);
890 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
891 xge_hal_device_continue_irq(xge_hal_device_t *hldev);
893 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
894 xge_hal_device_handle_irq(xge_hal_device_t *hldev);
896 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char *
897 xge_hal_device_bar0(xge_hal_device_t *hldev);
899 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char *
900 xge_hal_device_isrbar0(xge_hal_device_t *hldev);
902 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char *
903 xge_hal_device_bar1(xge_hal_device_t *hldev);
905 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
906 xge_hal_device_bar0_set(xge_hal_device_t *hldev, char *bar0);
908 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
909 xge_hal_device_isrbar0_set(xge_hal_device_t *hldev, char *isrbar0);
911 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
912 xge_hal_device_bar1_set(xge_hal_device_t *hldev, xge_hal_channel_h channelh,
915 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
916 xge_hal_device_mask_tx(xge_hal_device_t *hldev);
918 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
919 xge_hal_device_mask_rx(xge_hal_device_t *hldev);
921 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
922 xge_hal_device_mask_all(xge_hal_device_t *hldev);
924 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
925 xge_hal_device_unmask_tx(xge_hal_device_t *hldev);
927 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
928 xge_hal_device_unmask_rx(xge_hal_device_t *hldev);
930 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
931 xge_hal_device_unmask_all(xge_hal_device_t *hldev);
933 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
934 xge_hal_device_poll_tx_channels(xge_hal_device_t *hldev, int *got_tx);
936 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
937 xge_hal_device_poll_rx_channels(xge_hal_device_t *hldev, int *got_rx);
939 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
940 xge_hal_device_poll_rx_channel(xge_hal_channel_t *channel, int *got_rx);
942 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
943 xge_hal_device_poll_tx_channel(xge_hal_channel_t *channel, int *got_tx);
945 #if defined (XGE_HAL_CONFIG_LRO)
946 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u8
947 __hal_header_parse_token_u8(u8 *string,u16 offset);
949 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u16
950 __hal_header_parse_token_u16(u8 *string,u16 offset);
952 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u32
953 __hal_header_parse_token_u32(u8 *string,u16 offset);
955 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
956 __hal_header_update_u8(u8 *string, u16 offset, u8 val);
958 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
959 __hal_header_update_u16(u8 *string, u16 offset, u16 val);
961 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
962 __hal_header_update_u32(u8 *string, u16 offset, u32 val);
964 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u16
965 __hal_tcp_seg_len(iplro_t *ip, tcplro_t *tcp);
967 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
968 __hal_ip_lro_capable(iplro_t *ip, xge_hal_dtr_info_t *ext_info);
970 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
971 __hal_tcp_lro_capable(iplro_t *ip, tcplro_t *tcp, lro_t *lro, int *ts_off);
973 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
974 __hal_lro_capable(u8 *buffer, iplro_t **ip, tcplro_t **tcp,
975 xge_hal_dtr_info_t *ext_info);
977 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
978 __hal_get_lro_session(u8 *eth_hdr, iplro_t *ip, tcplro_t *tcp, lro_t **lro,
979 xge_hal_dtr_info_t *ext_info, xge_hal_device_t *hldev,
980 xge_hal_lro_desc_t *ring_lro, lro_t **lro_end3);
982 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
983 __hal_lro_under_optimal_thresh(iplro_t *ip, tcplro_t *tcp, lro_t *lro,
984 xge_hal_device_t *hldev);
986 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
987 __hal_collapse_ip_hdr(iplro_t *ip, tcplro_t *tcp, lro_t *lro,
988 xge_hal_device_t *hldev);
990 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
991 __hal_collapse_tcp_hdr(iplro_t *ip, tcplro_t *tcp, lro_t *lro,
992 xge_hal_device_t *hldev);
994 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
995 __hal_append_lro(iplro_t *ip, tcplro_t **tcp, u32 *seg_len, lro_t *lro,
996 xge_hal_device_t *hldev);
998 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
999 xge_hal_lro_process_rx(int ring, u8 *eth_hdr, u8 *ip_hdr, tcplro_t **tcp,
1000 u32 *seglen, lro_t **p_lro,
1001 xge_hal_dtr_info_t *ext_info, xge_hal_device_t *hldev,
1004 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
1005 xge_hal_accumulate_large_rx(u8 *buffer, tcplro_t **tcp, u32 *seglen,
1006 lro_t **lro, xge_hal_dtr_info_t *ext_info,
1007 xge_hal_device_t *hldev, lro_t **lro_end3);
1010 xge_hal_lro_terminate(u32 lro_scale, xge_hal_device_t *hldev);
1012 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL lro_t *
1013 xge_hal_lro_next_session (xge_hal_device_t *hldev, int ring);
1015 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL lro_t *
1016 xge_hal_lro_get_next_session(xge_hal_device_t *hldev);
1018 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
1019 __hal_open_lro_session (u8 *buffer, iplro_t *ip, tcplro_t *tcp, lro_t **lro,
1020 xge_hal_device_t *hldev, xge_hal_lro_desc_t *ring_lro,
1021 int slot, u32 tcp_seg_len, int ts_off);
1023 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL int
1024 __hal_lro_get_free_slot (xge_hal_lro_desc_t *ring_lro);
1027 #else /* XGE_FASTPATH_EXTERN */
1028 #define __HAL_STATIC_DEVICE static
1029 #define __HAL_INLINE_DEVICE inline
1030 #include <dev/nxge/xgehal/xgehal-device-fp.c>
1031 #endif /* XGE_FASTPATH_INLINE */
1036 #endif /* XGE_HAL_DEVICE_H */