2 * Copyright (C) 2012 Emulex
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of the Emulex Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
31 * Contact Information:
32 * freebsd-drivers@emulex.com
36 * Costa Mesa, CA 92626
43 static int oce_POST(POCE_SOFTC sc);
46 * @brief Function to post status
47 * @param sc software handle to the device
50 oce_POST(POCE_SOFTC sc)
52 mpu_ep_semaphore_t post_status;
55 /* read semaphore CSR */
56 post_status.dw0 = OCE_READ_REG32(sc, csr, MPU_EP_SEMAPHORE(sc));
58 /* if host is ready then wait for fw ready else send POST */
59 if (post_status.bits.stage <= POST_STAGE_AWAITING_HOST_RDY) {
60 post_status.bits.stage = POST_STAGE_CHIP_RESET;
61 OCE_WRITE_REG32(sc, csr, MPU_EP_SEMAPHORE(sc), post_status.dw0);
64 /* wait for FW ready */
71 post_status.dw0 = OCE_READ_REG32(sc, csr, MPU_EP_SEMAPHORE(sc));
72 if (post_status.bits.error) {
73 device_printf(sc->dev,
74 "POST failed: %x\n", post_status.dw0);
77 if (post_status.bits.stage == POST_STAGE_ARMFW_READY)
81 device_printf(sc->dev, "POST timed out: %x\n", post_status.dw0);
87 * @brief Function for hardware initialization
88 * @param sc software handle to the device
91 oce_hw_init(POCE_SOFTC sc)
99 /* create the bootstrap mailbox */
100 rc = oce_dma_alloc(sc, sizeof(struct oce_bmbx), &sc->bsmbx, 0);
102 device_printf(sc->dev, "Mailbox alloc failed\n");
106 rc = oce_reset_fun(sc);
111 rc = oce_mbox_init(sc);
116 rc = oce_get_fw_version(sc);
121 rc = oce_get_fw_config(sc);
126 sc->macaddr.size_of_struct = 6;
127 rc = oce_read_mac_addr(sc, 0, 1, MAC_ADDRESS_TYPE_NETWORK,
132 if (IS_BE(sc) && (sc->flags & OCE_FLAGS_BE3)) {
133 rc = oce_mbox_check_native_mode(sc);
142 oce_dma_free(sc, &sc->bsmbx);
143 device_printf(sc->dev, "Hardware initialisation failed\n");
150 * @brief Releases the obtained pci resources
151 * @param sc software handle to the device
154 oce_hw_pci_free(POCE_SOFTC sc)
156 int pci_cfg_barnum = 0;
158 if (IS_BE(sc) && (sc->flags & OCE_FLAGS_BE2))
159 pci_cfg_barnum = OCE_DEV_BE2_CFG_BAR;
161 pci_cfg_barnum = OCE_DEV_CFG_BAR;
163 if (sc->devcfg_res != NULL) {
164 bus_release_resource(sc->dev,
166 PCIR_BAR(pci_cfg_barnum), sc->devcfg_res);
167 sc->devcfg_res = (struct resource *)NULL;
168 sc->devcfg_btag = (bus_space_tag_t) 0;
169 sc->devcfg_bhandle = (bus_space_handle_t)0;
170 sc->devcfg_vhandle = (void *)NULL;
173 if (sc->csr_res != NULL) {
174 bus_release_resource(sc->dev,
176 PCIR_BAR(OCE_PCI_CSR_BAR), sc->csr_res);
177 sc->csr_res = (struct resource *)NULL;
178 sc->csr_btag = (bus_space_tag_t)0;
179 sc->csr_bhandle = (bus_space_handle_t)0;
180 sc->csr_vhandle = (void *)NULL;
183 if (sc->db_res != NULL) {
184 bus_release_resource(sc->dev,
186 PCIR_BAR(OCE_PCI_DB_BAR), sc->db_res);
187 sc->db_res = (struct resource *)NULL;
188 sc->db_btag = (bus_space_tag_t)0;
189 sc->db_bhandle = (bus_space_handle_t)0;
190 sc->db_vhandle = (void *)NULL;
198 * @brief Function to get the PCI capabilities
199 * @param sc software handle to the device
202 void oce_get_pci_capabilities(POCE_SOFTC sc)
206 if (pci_find_cap(sc->dev, PCIY_PCIX, &val) == 0) {
208 sc->flags |= OCE_FLAGS_PCIX;
211 if (pci_find_cap(sc->dev, PCIY_EXPRESS, &val) == 0) {
213 uint16_t link_status =
214 pci_read_config(sc->dev, val + 0x12, 2);
216 sc->flags |= OCE_FLAGS_PCIE;
217 sc->pcie_link_speed = link_status & 0xf;
218 sc->pcie_link_width = (link_status >> 4) & 0x3f;
222 if (pci_find_cap(sc->dev, PCIY_MSI, &val) == 0) {
224 sc->flags |= OCE_FLAGS_MSI_CAPABLE;
227 if (pci_find_cap(sc->dev, PCIY_MSIX, &val) == 0) {
229 val = pci_msix_count(sc->dev);
230 sc->flags |= OCE_FLAGS_MSIX_CAPABLE;
236 * @brief Allocate PCI resources.
238 * @param sc software handle to the device
239 * @returns 0 if successful, or error
242 oce_hw_pci_alloc(POCE_SOFTC sc)
244 int rr, pci_cfg_barnum = 0;
247 pci_enable_busmaster(sc->dev);
249 oce_get_pci_capabilities(sc);
251 sc->fn = pci_get_function(sc->dev);
253 /* setup the device config region */
254 if (IS_BE(sc) && (sc->flags & OCE_FLAGS_BE2))
255 pci_cfg_barnum = OCE_DEV_BE2_CFG_BAR;
257 pci_cfg_barnum = OCE_DEV_CFG_BAR;
259 rr = PCIR_BAR(pci_cfg_barnum);
262 sc->devcfg_res = bus_alloc_resource_any(sc->dev,
264 RF_ACTIVE|RF_SHAREABLE);
266 sc->devcfg_res = bus_alloc_resource(sc->dev,
269 RF_ACTIVE|RF_SHAREABLE);
274 sc->devcfg_btag = rman_get_bustag(sc->devcfg_res);
275 sc->devcfg_bhandle = rman_get_bushandle(sc->devcfg_res);
276 sc->devcfg_vhandle = rman_get_virtual(sc->devcfg_res);
278 /* Read the SLI_INTF register and determine whether we
279 * can use this port and its features
281 intf.dw0 = pci_read_config((sc)->dev,OCE_INTF_REG_OFFSET,4);
283 if (intf.bits.sli_valid != OCE_INTF_VALID_SIG)
286 if (intf.bits.sli_rev != OCE_INTF_SLI_REV4) {
287 device_printf(sc->dev, "Adapter doesnt support SLI4\n");
291 if (intf.bits.sli_if_type == OCE_INTF_IF_TYPE_1)
292 sc->flags |= OCE_FLAGS_MBOX_ENDIAN_RQD;
294 if (intf.bits.sli_hint1 == OCE_INTF_FUNC_RESET_REQD)
295 sc->flags |= OCE_FLAGS_FUNCRESET_RQD;
297 if (intf.bits.sli_func_type == OCE_INTF_VIRT_FUNC)
298 sc->flags |= OCE_FLAGS_VIRTUAL_PORT;
300 /* Lancer has one BAR (CFG) but BE3 has three (CFG, CSR, DB) */
302 /* set up CSR region */
303 rr = PCIR_BAR(OCE_PCI_CSR_BAR);
304 sc->csr_res = bus_alloc_resource_any(sc->dev,
305 SYS_RES_MEMORY, &rr, RF_ACTIVE|RF_SHAREABLE);
308 sc->csr_btag = rman_get_bustag(sc->csr_res);
309 sc->csr_bhandle = rman_get_bushandle(sc->csr_res);
310 sc->csr_vhandle = rman_get_virtual(sc->csr_res);
312 /* set up DB doorbell region */
313 rr = PCIR_BAR(OCE_PCI_DB_BAR);
314 sc->db_res = bus_alloc_resource_any(sc->dev,
315 SYS_RES_MEMORY, &rr, RF_ACTIVE|RF_SHAREABLE);
318 sc->db_btag = rman_get_bustag(sc->db_res);
319 sc->db_bhandle = rman_get_bushandle(sc->db_res);
320 sc->db_vhandle = rman_get_virtual(sc->db_res);
332 * @brief Function for device shutdown
333 * @param sc software handle to the device
334 * @returns 0 on success, error otherwise
337 oce_hw_shutdown(POCE_SOFTC sc)
341 /* disable hardware interrupts */
342 oce_hw_intr_disable(sc);
343 #if defined(INET6) || defined(INET)
344 /* Free LRO resources */
348 oce_queue_release_all(sc);
349 /*Delete Network Interface*/
350 oce_delete_nw_interface(sc);
351 /* After fw clean we dont send any cmds to fw.*/
353 /* release intr resources */
355 /* release PCI resources */
357 /* free mbox specific resources */
358 LOCK_DESTROY(&sc->bmbx_lock);
359 LOCK_DESTROY(&sc->dev_lock);
361 oce_dma_free(sc, &sc->bsmbx);
366 * @brief Function for creating nw interface.
367 * @param sc software handle to the device
368 * @returns 0 on success, error otherwise
371 oce_create_nw_interface(POCE_SOFTC sc)
374 uint32_t capab_flags;
375 uint32_t capab_en_flags;
377 /* interface capabilities to give device when creating interface */
378 capab_flags = OCE_CAPAB_FLAGS;
380 /* capabilities to enable by default (others set dynamically) */
381 capab_en_flags = OCE_CAPAB_ENABLE;
384 /* LANCER A0 workaround */
385 capab_en_flags &= ~MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR;
386 capab_flags &= ~MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR;
389 /* enable capabilities controlled via driver startup parameters */
391 capab_en_flags |= MBX_RX_IFACE_FLAGS_RSS;
393 capab_en_flags &= ~MBX_RX_IFACE_FLAGS_RSS;
394 capab_flags &= ~MBX_RX_IFACE_FLAGS_RSS;
397 rc = oce_if_create(sc,
400 0, &sc->macaddr.mac_addr[0], &sc->if_id);
404 atomic_inc_32(&sc->nifs);
406 sc->if_cap_flags = capab_en_flags;
408 /* Enable VLAN Promisc on HW */
409 rc = oce_config_vlan(sc, (uint8_t) sc->if_id, NULL, 0, 1, 1);
413 /* set default flow control */
414 rc = oce_set_flow_control(sc, sc->flow_control);
418 rc = oce_rxf_set_promiscuous(sc, sc->promisc);
425 oce_delete_nw_interface(sc);
431 * @brief Function to delete a nw interface.
432 * @param sc software handle to the device
435 oce_delete_nw_interface(POCE_SOFTC sc)
437 /* currently only single interface is implmeneted */
439 oce_if_del(sc, sc->if_id);
440 atomic_dec_32(&sc->nifs);
446 * @param sc software handle to the device
447 * @returns 0 on success, error otherwise
450 oce_pci_soft_reset(POCE_SOFTC sc)
453 mpu_ep_control_t ctrl;
455 ctrl.dw0 = OCE_READ_REG32(sc, csr, MPU_EP_CONTROL);
456 ctrl.bits.cpu_reset = 1;
457 OCE_WRITE_REG32(sc, csr, MPU_EP_CONTROL, ctrl.dw0);
465 * @brief Function for hardware start
466 * @param sc software handle to the device
467 * @returns 0 on success, error otherwise
470 oce_hw_start(POCE_SOFTC sc)
472 struct link_status link = { 0 };
475 rc = oce_get_link_status(sc, &link);
479 if (link.logical_link_status == NTWK_LOGICAL_LINK_UP) {
480 sc->ifp->if_drv_flags |= IFF_DRV_RUNNING;
481 sc->link_status = NTWK_LOGICAL_LINK_UP;
482 if_link_state_change(sc->ifp, LINK_STATE_UP);
484 sc->ifp->if_drv_flags &=
485 ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
486 sc->link_status = NTWK_LOGICAL_LINK_DOWN;
487 if_link_state_change(sc->ifp, LINK_STATE_DOWN);
490 if (link.mac_speed > 0 && link.mac_speed < 5)
491 sc->link_speed = link.mac_speed;
495 sc->qos_link_speed = (uint32_t )link.qos_link_speed * 10;
497 rc = oce_start_mq(sc->mq);
499 /* we need to get MCC aync events. So enable intrs and arm
500 first EQ, Other EQs will be armed after interface is UP
502 oce_hw_intr_enable(sc);
503 oce_arm_eq(sc, sc->eq[0]->eq_id, 0, TRUE, FALSE);
505 /* Send first mcc cmd and after that we get gracious
506 MCC notifications from FW
508 oce_first_mcc_cmd(sc);
515 * @brief Function for hardware enable interupts.
516 * @param sc software handle to the device
519 oce_hw_intr_enable(POCE_SOFTC sc)
523 reg = OCE_READ_REG32(sc, devcfg, PCICFG_INTR_CTRL);
524 reg |= HOSTINTR_MASK;
525 OCE_WRITE_REG32(sc, devcfg, PCICFG_INTR_CTRL, reg);
531 * @brief Function for hardware disable interupts
532 * @param sc software handle to the device
535 oce_hw_intr_disable(POCE_SOFTC sc)
539 reg = OCE_READ_REG32(sc, devcfg, PCICFG_INTR_CTRL);
540 reg &= ~HOSTINTR_MASK;
541 OCE_WRITE_REG32(sc, devcfg, PCICFG_INTR_CTRL, reg);
547 * @brief Function for hardware update multicast filter
548 * @param sc software handle to the device
551 oce_hw_update_multicast(POCE_SOFTC sc)
553 struct ifnet *ifp = sc->ifp;
554 struct ifmultiaddr *ifma;
555 struct mbx_set_common_iface_multicast *req = NULL;
559 /* Allocate DMA mem*/
560 if (oce_dma_alloc(sc, sizeof(struct mbx_set_common_iface_multicast),
564 req = OCE_DMAPTR(&dma, struct mbx_set_common_iface_multicast);
565 bzero(req, sizeof(struct mbx_set_common_iface_multicast));
567 #if __FreeBSD_version > 800000
570 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
571 if (ifma->ifma_addr->sa_family != AF_LINK)
574 if (req->params.req.num_mac == OCE_MAX_MC_FILTER_SIZE) {
575 /*More multicast addresses than our hardware table
576 So Enable multicast promiscus in our hardware to
577 accept all multicat packets
579 req->params.req.promiscuous = 1;
582 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
583 &req->params.req.mac[req->params.req.num_mac],
585 req->params.req.num_mac = req->params.req.num_mac + 1;
587 #if __FreeBSD_version > 800000
588 if_maddr_runlock(ifp);
590 req->params.req.if_id = sc->if_id;
591 rc = oce_update_multicast(sc, &dma);
592 oce_dma_free(sc, &dma);