sys/dev/oce/oce_hw.h

   1 /*-
   2  * Copyright (C) 2012 Emulex
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright notice,
   9  *    this list of conditions and the following disclaimer.
  10  *
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * 3. Neither the name of the Emulex Corporation nor the names of its
  16  *    contributors may be used to endorse or promote products derived from
  17  *    this software without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  *
  31  * Contact Information:
  32  * freebsd-drivers@emulex.com
  33  *
  34  * Emulex
  35  * 3333 Susan Street
  36  * Costa Mesa, CA 92626
  37  */
  38
  39 /* $FreeBSD$ */
  40
  41 #include <sys/types.h>
  42
  43 #undef _BIG_ENDIAN /* TODO */
  44 #pragma pack(1)
  45
  46 #define OC_CNA_GEN2                     0x2
  47 #define OC_CNA_GEN3                     0x3
  48 #define DEVID_TIGERSHARK                0x700
  49 #define DEVID_TOMCAT                    0x710
  50
  51 /* PCI CSR offsets */
  52 #define PCICFG_F1_CSR                   0x0     /* F1 for NIC */
  53 #define PCICFG_SEMAPHORE                0xbc
  54 #define PCICFG_SOFT_RESET               0x5c
  55 #define PCICFG_UE_STATUS_HI_MASK        0xac
  56 #define PCICFG_UE_STATUS_LO_MASK        0xa8
  57 #define PCICFG_ONLINE0                  0xb0
  58 #define PCICFG_ONLINE1                  0xb4
  59 #define INTR_EN                         0x20000000
  60 #define IMAGE_TRANSFER_SIZE             (32 * 1024)     /* 32K at a time */
  61
  62 /* CSR register offsets */
  63 #define MPU_EP_CONTROL                  0
  64 #define MPU_EP_SEMAPHORE_BE3            0xac
  65 #define MPU_EP_SEMAPHORE_XE201          0x400
  66 #define MPU_EP_SEMAPHORE(sc) \
  67         ((IS_BE(sc)) ? MPU_EP_SEMAPHORE_BE3 : MPU_EP_SEMAPHORE_XE201)
  68 #define PCICFG_INTR_CTRL                0xfc
  69 #define HOSTINTR_MASK                   (1 << 29)
  70 #define HOSTINTR_PFUNC_SHIFT            26
  71 #define HOSTINTR_PFUNC_MASK             7
  72
  73 /* POST status reg struct */
  74 #define POST_STAGE_POWER_ON_RESET       0x00
  75 #define POST_STAGE_AWAITING_HOST_RDY    0x01
  76 #define POST_STAGE_HOST_RDY             0x02
  77 #define POST_STAGE_CHIP_RESET           0x03
  78 #define POST_STAGE_ARMFW_READY          0xc000
  79 #define POST_STAGE_ARMFW_UE             0xf000
  80
  81 /* DOORBELL registers */
  82 #define PD_RXULP_DB                     0x0100
  83 #define PD_TXULP_DB                     0x0060
  84 #define DB_RQ_ID_MASK                   0x3FF
  85
  86 #define PD_CQ_DB                        0x0120
  87 #define PD_EQ_DB                        PD_CQ_DB
  88 #define PD_MPU_MBOX_DB                  0x0160
  89 #define PD_MQ_DB                        0x0140
  90
  91 /* EQE completion types */
  92 #define EQ_MINOR_CODE_COMPLETION        0x00
  93 #define EQ_MINOR_CODE_OTHER             0x01
  94 #define EQ_MAJOR_CODE_COMPLETION        0x00
  95
  96 /* Link Status field values */
  97 #define PHY_LINK_FAULT_NONE             0x0
  98 #define PHY_LINK_FAULT_LOCAL            0x01
  99 #define PHY_LINK_FAULT_REMOTE           0x02
 100
 101 #define PHY_LINK_SPEED_ZERO             0x0     /* No link */
 102 #define PHY_LINK_SPEED_10MBPS           0x1     /* (10 Mbps) */
 103 #define PHY_LINK_SPEED_100MBPS          0x2     /* (100 Mbps) */
 104 #define PHY_LINK_SPEED_1GBPS            0x3     /* (1 Gbps) */
 105 #define PHY_LINK_SPEED_10GBPS           0x4     /* (10 Gbps) */
 106
 107 #define PHY_LINK_DUPLEX_NONE            0x0
 108 #define PHY_LINK_DUPLEX_HALF            0x1
 109 #define PHY_LINK_DUPLEX_FULL            0x2
 110
 111 #define NTWK_PORT_A                     0x0     /* (Port A) */
 112 #define NTWK_PORT_B                     0x1     /* (Port B) */
 113
 114 #define PHY_LINK_SPEED_ZERO                     0x0     /* (No link.) */
 115 #define PHY_LINK_SPEED_10MBPS           0x1     /* (10 Mbps) */
 116 #define PHY_LINK_SPEED_100MBPS          0x2     /* (100 Mbps) */
 117 #define PHY_LINK_SPEED_1GBPS            0x3     /* (1 Gbps) */
 118 #define PHY_LINK_SPEED_10GBPS           0x4     /* (10 Gbps) */
 119
 120 /* Hardware Address types */
 121 #define MAC_ADDRESS_TYPE_STORAGE        0x0     /* (Storage MAC Address) */
 122 #define MAC_ADDRESS_TYPE_NETWORK        0x1     /* (Network MAC Address) */
 123 #define MAC_ADDRESS_TYPE_PD             0x2     /* (Protection Domain MAC Addr) */
 124 #define MAC_ADDRESS_TYPE_MANAGEMENT     0x3     /* (Management MAC Address) */
 125 #define MAC_ADDRESS_TYPE_FCOE           0x4     /* (FCoE MAC Address) */
 126
 127 /* CREATE_IFACE capability and cap_en flags */
 128 #define MBX_RX_IFACE_FLAGS_RSS          0x4
 129 #define MBX_RX_IFACE_FLAGS_PROMISCUOUS  0x8
 130 #define MBX_RX_IFACE_FLAGS_BROADCAST    0x10
 131 #define MBX_RX_IFACE_FLAGS_UNTAGGED     0x20
 132 #define MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS     0x80
 133 #define MBX_RX_IFACE_FLAGS_VLAN         0x100
 134 #define MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS    0x200
 135 #define MBX_RX_IFACE_FLAGS_PASS_L2_ERR  0x400
 136 #define MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR        0x800
 137 #define MBX_RX_IFACE_FLAGS_MULTICAST    0x1000
 138 #define MBX_RX_IFACE_RX_FILTER_IF_MULTICAST_HASH 0x2000
 139 #define MBX_RX_IFACE_FLAGS_HDS          0x4000
 140 #define MBX_RX_IFACE_FLAGS_DIRECTED     0x8000
 141 #define MBX_RX_IFACE_FLAGS_VMQ          0x10000
 142 #define MBX_RX_IFACE_FLAGS_NETQ         0x20000
 143 #define MBX_RX_IFACE_FLAGS_QGROUPS      0x40000
 144 #define MBX_RX_IFACE_FLAGS_LSO          0x80000
 145 #define MBX_RX_IFACE_FLAGS_LRO          0x100000
 146
 147 #define MQ_RING_CONTEXT_SIZE_16         0x5     /* (16 entries) */
 148 #define MQ_RING_CONTEXT_SIZE_32         0x6     /* (32 entries) */
 149 #define MQ_RING_CONTEXT_SIZE_64         0x7     /* (64 entries) */
 150 #define MQ_RING_CONTEXT_SIZE_128        0x8     /* (128 entries) */
 151
 152 #define MBX_DB_READY_BIT                0x1
 153 #define MBX_DB_HI_BIT                   0x2
 154 #define ASYNC_EVENT_CODE_LINK_STATE     0x1
 155 #define ASYNC_EVENT_LINK_UP             0x1
 156 #define ASYNC_EVENT_LINK_DOWN           0x0
 157
 158 /* port link_status */
 159 #define ASYNC_EVENT_LOGICAL             0x02
 160
 161 /* Logical Link Status */
 162 #define NTWK_LOGICAL_LINK_DOWN          0
 163 #define NTWK_LOGICAL_LINK_UP            1
 164
 165 /* Rx filter bits */
 166 #define NTWK_RX_FILTER_IP_CKSUM         0x1
 167 #define NTWK_RX_FILTER_TCP_CKSUM        0x2
 168 #define NTWK_RX_FILTER_UDP_CKSUM        0x4
 169 #define NTWK_RX_FILTER_STRIP_CRC        0x8
 170
 171 /* max SGE per mbx */
 172 #define MAX_MBX_SGE                     19
 173
 174 /* Max multicast filter size*/
 175 #define OCE_MAX_MC_FILTER_SIZE          64
 176
 177 /* PCI SLI (Service Level Interface) capabilities register */
 178 #define OCE_INTF_REG_OFFSET             0x58
 179 #define OCE_INTF_VALID_SIG              6       /* register's signature */
 180 #define OCE_INTF_FUNC_RESET_REQD        1
 181 #define OCE_INTF_HINT1_NOHINT           0
 182 #define OCE_INTF_HINT1_SEMAINIT         1
 183 #define OCE_INTF_HINT1_STATCTRL         2
 184 #define OCE_INTF_IF_TYPE_0              0
 185 #define OCE_INTF_IF_TYPE_1              1
 186 #define OCE_INTF_IF_TYPE_2              2
 187 #define OCE_INTF_IF_TYPE_3              3
 188 #define OCE_INTF_SLI_REV3               3       /* not supported by driver */
 189 #define OCE_INTF_SLI_REV4               4       /* driver supports SLI-4 */
 190 #define OCE_INTF_PHYS_FUNC              0
 191 #define OCE_INTF_VIRT_FUNC              1
 192 #define OCE_INTF_FAMILY_BE2             0       /* not supported by driver */
 193 #define OCE_INTF_FAMILY_BE3             1       /* driver supports BE3 */
 194 #define OCE_INTF_FAMILY_A0_CHIP         0xA     /* Lancer A0 chip (supported) */
 195 #define OCE_INTF_FAMILY_B0_CHIP         0xB     /* Lancer B0 chip (future) */
 196
 197 #define NIC_WQE_SIZE    16
 198 #define NIC_UNICAST     0x00
 199 #define NIC_MULTICAST   0x01
 200 #define NIC_BROADCAST   0x02
 201
 202 #define NIC_HDS_NO_SPLIT        0x00
 203 #define NIC_HDS_SPLIT_L3PL      0x01
 204 #define NIC_HDS_SPLIT_L4PL      0x02
 205
 206 #define NIC_WQ_TYPE_FORWARDING          0x01
 207 #define NIC_WQ_TYPE_STANDARD            0x02
 208 #define NIC_WQ_TYPE_LOW_LATENCY         0x04
 209
 210 #define OCE_RESET_STATS         1
 211 #define OCE_RETAIN_STATS        0
 212 #define OCE_TXP_SW_SZ           48
 213
 214 typedef union pci_sli_intf_u {
 215         uint32_t dw0;
 216         struct {
 217 #ifdef _BIG_ENDIAN
 218                 uint32_t sli_valid:3;
 219                 uint32_t sli_hint2:5;
 220                 uint32_t sli_hint1:8;
 221                 uint32_t sli_if_type:4;
 222                 uint32_t sli_family:4;
 223                 uint32_t sli_rev:4;
 224                 uint32_t rsv0:3;
 225                 uint32_t sli_func_type:1;
 226 #else
 227                 uint32_t sli_func_type:1;
 228                 uint32_t rsv0:3;
 229                 uint32_t sli_rev:4;
 230                 uint32_t sli_family:4;
 231                 uint32_t sli_if_type:4;
 232                 uint32_t sli_hint1:8;
 233                 uint32_t sli_hint2:5;
 234                 uint32_t sli_valid:3;
 235 #endif
 236         } bits;
 237 } pci_sli_intf_t;
 238
 239
 240
 241 /* physical address structure to be used in MBX */
 242 struct phys_addr {
 243         /* dw0 */
 244         uint32_t lo;
 245         /* dw1 */
 246         uint32_t hi;
 247 };
 248
 249
 250
 251 typedef union pcicfg_intr_ctl_u {
 252         uint32_t dw0;
 253         struct {
 254 #ifdef _BIG_ENDIAN
 255                 uint32_t winselect:2;
 256                 uint32_t hostintr:1;
 257                 uint32_t pfnum:3;
 258                 uint32_t vf_cev_int_line_en:1;
 259                 uint32_t winaddr:23;
 260                 uint32_t membarwinen:1;
 261 #else
 262                 uint32_t membarwinen:1;
 263                 uint32_t winaddr:23;
 264                 uint32_t vf_cev_int_line_en:1;
 265                 uint32_t pfnum:3;
 266                 uint32_t hostintr:1;
 267                 uint32_t winselect:2;
 268 #endif
 269         } bits;
 270 } pcicfg_intr_ctl_t;
 271
 272
 273
 274
 275 typedef union pcicfg_semaphore_u {
 276         uint32_t dw0;
 277         struct {
 278 #ifdef _BIG_ENDIAN
 279                 uint32_t rsvd:31;
 280                 uint32_t lock:1;
 281 #else
 282                 uint32_t lock:1;
 283                 uint32_t rsvd:31;
 284 #endif
 285         } bits;
 286 } pcicfg_semaphore_t;
 287
 288
 289
 290
 291 typedef union pcicfg_soft_reset_u {
 292         uint32_t dw0;
 293         struct {
 294 #ifdef _BIG_ENDIAN
 295                 uint32_t nec_ll_rcvdetect:8;
 296                 uint32_t dbg_all_reqs_62_49:14;
 297                 uint32_t scratchpad0:1;
 298                 uint32_t exception_oe:1;
 299                 uint32_t soft_reset:1;
 300                 uint32_t rsvd0:7;
 301 #else
 302                 uint32_t rsvd0:7;
 303                 uint32_t soft_reset:1;
 304                 uint32_t exception_oe:1;
 305                 uint32_t scratchpad0:1;
 306                 uint32_t dbg_all_reqs_62_49:14;
 307                 uint32_t nec_ll_rcvdetect:8;
 308 #endif
 309         } bits;
 310 } pcicfg_soft_reset_t;
 311
 312
 313
 314
 315 typedef union pcicfg_online1_u {
 316         uint32_t dw0;
 317         struct {
 318 #ifdef _BIG_ENDIAN
 319                 uint32_t host8_online:1;
 320                 uint32_t host7_online:1;
 321                 uint32_t host6_online:1;
 322                 uint32_t host5_online:1;
 323                 uint32_t host4_online:1;
 324                 uint32_t host3_online:1;
 325                 uint32_t host2_online:1;
 326                 uint32_t ipc_online:1;
 327                 uint32_t arm_online:1;
 328                 uint32_t txp_online:1;
 329                 uint32_t xaui_online:1;
 330                 uint32_t rxpp_online:1;
 331                 uint32_t txpb_online:1;
 332                 uint32_t rr_online:1;
 333                 uint32_t pmem_online:1;
 334                 uint32_t pctl1_online:1;
 335                 uint32_t pctl0_online:1;
 336                 uint32_t pcs1online_online:1;
 337                 uint32_t mpu_iram_online:1;
 338                 uint32_t pcs0online_online:1;
 339                 uint32_t mgmt_mac_online:1;
 340                 uint32_t lpcmemhost_online:1;
 341 #else
 342                 uint32_t lpcmemhost_online:1;
 343                 uint32_t mgmt_mac_online:1;
 344                 uint32_t pcs0online_online:1;
 345                 uint32_t mpu_iram_online:1;
 346                 uint32_t pcs1online_online:1;
 347                 uint32_t pctl0_online:1;
 348                 uint32_t pctl1_online:1;
 349                 uint32_t pmem_online:1;
 350                 uint32_t rr_online:1;
 351                 uint32_t txpb_online:1;
 352                 uint32_t rxpp_online:1;
 353                 uint32_t xaui_online:1;
 354                 uint32_t txp_online:1;
 355                 uint32_t arm_online:1;
 356                 uint32_t ipc_online:1;
 357                 uint32_t host2_online:1;
 358                 uint32_t host3_online:1;
 359                 uint32_t host4_online:1;
 360                 uint32_t host5_online:1;
 361                 uint32_t host6_online:1;
 362                 uint32_t host7_online:1;
 363                 uint32_t host8_online:1;
 364 #endif
 365         } bits;
 366 } pcicfg_online1_t;
 367
 368
 369
 370 typedef union mpu_ep_semaphore_u {
 371         uint32_t dw0;
 372         struct {
 373 #ifdef _BIG_ENDIAN
 374                 uint32_t error:1;
 375                 uint32_t backup_fw:1;
 376                 uint32_t iscsi_no_ip:1;
 377                 uint32_t iscsi_ip_conflict:1;
 378                 uint32_t option_rom_installed:1;
 379                 uint32_t iscsi_drv_loaded:1;
 380                 uint32_t rsvd0:10;
 381                 uint32_t stage:16;
 382 #else
 383                 uint32_t stage:16;
 384                 uint32_t rsvd0:10;
 385                 uint32_t iscsi_drv_loaded:1;
 386                 uint32_t option_rom_installed:1;
 387                 uint32_t iscsi_ip_conflict:1;
 388                 uint32_t iscsi_no_ip:1;
 389                 uint32_t backup_fw:1;
 390                 uint32_t error:1;
 391 #endif
 392         } bits;
 393 } mpu_ep_semaphore_t;
 394
 395
 396
 397
 398 typedef union mpu_ep_control_u {
 399         uint32_t dw0;
 400         struct {
 401 #ifdef _BIG_ENDIAN
 402                 uint32_t cpu_reset:1;
 403                 uint32_t rsvd1:15;
 404                 uint32_t ep_ram_init_status:1;
 405                 uint32_t rsvd0:12;
 406                 uint32_t m2_rxpbuf:1;
 407                 uint32_t m1_rxpbuf:1;
 408                 uint32_t m0_rxpbuf:1;
 409 #else
 410                 uint32_t m0_rxpbuf:1;
 411                 uint32_t m1_rxpbuf:1;
 412                 uint32_t m2_rxpbuf:1;
 413                 uint32_t rsvd0:12;
 414                 uint32_t ep_ram_init_status:1;
 415                 uint32_t rsvd1:15;
 416                 uint32_t cpu_reset:1;
 417 #endif
 418         } bits;
 419 } mpu_ep_control_t;
 420
 421
 422
 423
 424 /* RX doorbell */
 425 typedef union pd_rxulp_db_u {
 426         uint32_t dw0;
 427         struct {
 428 #ifdef _BIG_ENDIAN
 429                 uint32_t num_posted:8;
 430                 uint32_t invalidate:1;
 431                 uint32_t rsvd1:13;
 432                 uint32_t qid:10;
 433 #else
 434                 uint32_t qid:10;
 435                 uint32_t rsvd1:13;
 436                 uint32_t invalidate:1;
 437                 uint32_t num_posted:8;
 438 #endif
 439         } bits;
 440 } pd_rxulp_db_t;
 441
 442
 443 /* TX doorbell */
 444 typedef union pd_txulp_db_u {
 445         uint32_t dw0;
 446         struct {
 447 #ifdef _BIG_ENDIAN
 448                 uint32_t rsvd1:2;
 449                 uint32_t num_posted:14;
 450                 uint32_t rsvd0:6;
 451                 uint32_t qid:10;
 452 #else
 453                 uint32_t qid:10;
 454                 uint32_t rsvd0:6;
 455                 uint32_t num_posted:14;
 456                 uint32_t rsvd1:2;
 457 #endif
 458         } bits;
 459 } pd_txulp_db_t;
 460
 461 /* CQ doorbell */
 462 typedef union cq_db_u {
 463         uint32_t dw0;
 464         struct {
 465 #ifdef _BIG_ENDIAN
 466                 uint32_t rsvd1:2;
 467                 uint32_t rearm:1;
 468                 uint32_t num_popped:13;
 469                 uint32_t rsvd0:5;
 470                 uint32_t event:1;
 471                 uint32_t qid:10;
 472 #else
 473                 uint32_t qid:10;
 474                 uint32_t event:1;
 475                 uint32_t rsvd0:5;
 476                 uint32_t num_popped:13;
 477                 uint32_t rearm:1;
 478                 uint32_t rsvd1:2;
 479 #endif
 480         } bits;
 481 } cq_db_t;
 482
 483 /* EQ doorbell */
 484 typedef union eq_db_u {
 485         uint32_t dw0;
 486         struct {
 487 #ifdef _BIG_ENDIAN
 488                 uint32_t rsvd1:2;
 489                 uint32_t rearm:1;
 490                 uint32_t num_popped:13;
 491                 uint32_t rsvd0:5;
 492                 uint32_t event:1;
 493                 uint32_t clrint:1;
 494                 uint32_t qid:9;
 495 #else
 496                 uint32_t qid:9;
 497                 uint32_t clrint:1;
 498                 uint32_t event:1;
 499                 uint32_t rsvd0:5;
 500                 uint32_t num_popped:13;
 501                 uint32_t rearm:1;
 502                 uint32_t rsvd1:2;
 503 #endif
 504         } bits;
 505 } eq_db_t;
 506
 507 /* bootstrap mbox doorbell */
 508 typedef union pd_mpu_mbox_db_u {
 509         uint32_t dw0;
 510         struct {
 511 #ifdef _BIG_ENDIAN
 512                 uint32_t address:30;
 513                 uint32_t hi:1;
 514                 uint32_t ready:1;
 515 #else
 516                 uint32_t ready:1;
 517                 uint32_t hi:1;
 518                 uint32_t address:30;
 519 #endif
 520         } bits;
 521 } pd_mpu_mbox_db_t;
 522
 523 /* MQ ring doorbell */
 524 typedef union pd_mq_db_u {
 525         uint32_t dw0;
 526         struct {
 527 #ifdef _BIG_ENDIAN
 528                 uint32_t rsvd1:2;
 529                 uint32_t num_posted:14;
 530                 uint32_t rsvd0:5;
 531                 uint32_t mq_id:11;
 532 #else
 533                 uint32_t mq_id:11;
 534                 uint32_t rsvd0:5;
 535                 uint32_t num_posted:14;
 536                 uint32_t rsvd1:2;
 537 #endif
 538         } bits;
 539 } pd_mq_db_t;
 540
 541 /*
 542  * Event Queue Entry
 543  */
 544 struct oce_eqe {
 545         uint32_t evnt;
 546 };
 547
 548 /* MQ scatter gather entry. Array of these make an SGL */
 549 struct oce_mq_sge {
 550         uint32_t pa_lo;
 551         uint32_t pa_hi;
 552         uint32_t length;
 553 };
 554
 555 /*
 556  * payload can contain an SGL or an embedded array of upto 59 dwords
 557  */
 558 struct oce_mbx_payload {
 559         union {
 560                 union {
 561                         struct oce_mq_sge sgl[MAX_MBX_SGE];
 562                         uint32_t embedded[59];
 563                 } u1;
 564                 uint32_t dw[59];
 565         } u0;
 566 };
 567
 568 /*
 569  * MQ MBX structure
 570  */
 571 struct oce_mbx {
 572         union {
 573                 struct {
 574 #ifdef _BIG_ENDIAN
 575                         uint32_t special:8;
 576                         uint32_t rsvd1:16;
 577                         uint32_t sge_count:5;
 578                         uint32_t rsvd0:2;
 579                         uint32_t embedded:1;
 580 #else
 581                         uint32_t embedded:1;
 582                         uint32_t rsvd0:2;
 583                         uint32_t sge_count:5;
 584                         uint32_t rsvd1:16;
 585                         uint32_t special:8;
 586 #endif
 587                 } s;
 588                 uint32_t dw0;
 589         } u0;
 590
 591         uint32_t payload_length;
 592         uint32_t tag[2];
 593         uint32_t rsvd2[1];
 594         struct oce_mbx_payload payload;
 595 };
 596
 597 /* completion queue entry for MQ */
 598 struct oce_mq_cqe {
 599         union {
 600                 struct {
 601 #ifdef _BIG_ENDIAN
 602                         /* dw0 */
 603                         uint32_t extended_status:16;
 604                         uint32_t completion_status:16;
 605                         /* dw1 dw2 */
 606                         uint32_t mq_tag[2];
 607                         /* dw3 */
 608                         uint32_t valid:1;
 609                         uint32_t async_event:1;
 610                         uint32_t hpi_buffer_cmpl:1;
 611                         uint32_t completed:1;
 612                         uint32_t consumed:1;
 613                         uint32_t rsvd0:27;
 614 #else
 615                         /* dw0 */
 616                         uint32_t completion_status:16;
 617                         uint32_t extended_status:16;
 618                         /* dw1 dw2 */
 619                         uint32_t mq_tag[2];
 620                         /* dw3 */
 621                         uint32_t rsvd0:27;
 622                         uint32_t consumed:1;
 623                         uint32_t completed:1;
 624                         uint32_t hpi_buffer_cmpl:1;
 625                         uint32_t async_event:1;
 626                         uint32_t valid:1;
 627 #endif
 628                 } s;
 629                 uint32_t dw[4];
 630         } u0;
 631 };
 632
 633 /* Mailbox Completion Status Codes */
 634 enum MBX_COMPLETION_STATUS {
 635         MBX_CQE_STATUS_SUCCESS = 0x00,
 636         MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES = 0x01,
 637         MBX_CQE_STATUS_INVALID_PARAMETER = 0x02,
 638         MBX_CQE_STATUS_INSUFFICIENT_RESOURCES = 0x03,
 639         MBX_CQE_STATUS_QUEUE_FLUSHING = 0x04,
 640         MBX_CQE_STATUS_DMA_FAILED = 0x05
 641 };
 642
 643 struct oce_async_cqe_link_state {
 644         union {
 645                 struct {
 646 #ifdef _BIG_ENDIAN
 647                         /* dw0 */
 648                         uint8_t speed;
 649                         uint8_t duplex;
 650                         uint8_t link_status;
 651                         uint8_t phy_port;
 652                         /* dw1 */
 653                         uint16_t qos_link_speed;
 654                         uint8_t rsvd0;
 655                         uint8_t fault;
 656                         /* dw2 */
 657                         uint32_t event_tag;
 658                         /* dw3 */
 659                         uint32_t valid:1;
 660                         uint32_t async_event:1;
 661                         uint32_t rsvd2:6;
 662                         uint32_t event_type:8;
 663                         uint32_t event_code:8;
 664                         uint32_t rsvd1:8;
 665 #else
 666                         /* dw0 */
 667                         uint8_t phy_port;
 668                         uint8_t link_status;
 669                         uint8_t duplex;
 670                         uint8_t speed;
 671                         /* dw1 */
 672                         uint8_t fault;
 673                         uint8_t rsvd0;
 674                         uint16_t qos_link_speed;
 675                         /* dw2 */
 676                         uint32_t event_tag;
 677                         /* dw3 */
 678                         uint32_t rsvd1:8;
 679                         uint32_t event_code:8;
 680                         uint32_t event_type:8;
 681                         uint32_t rsvd2:6;
 682                         uint32_t async_event:1;
 683                         uint32_t valid:1;
 684 #endif
 685                 } s;
 686                 uint32_t dw[4];
 687         } u0;
 688 };
 689
 690 /* MQ mailbox structure */
 691 struct oce_bmbx {
 692         struct oce_mbx mbx;
 693         struct oce_mq_cqe cqe;
 694 };
 695
 696 /* ---[ MBXs start here ]---------------------------------------------- */
 697 /* MBXs sub system codes */
 698 enum MBX_SUBSYSTEM_CODES {
 699         MBX_SUBSYSTEM_RSVD = 0,
 700         MBX_SUBSYSTEM_COMMON = 1,
 701         MBX_SUBSYSTEM_COMMON_ISCSI = 2,
 702         MBX_SUBSYSTEM_NIC = 3,
 703         MBX_SUBSYSTEM_TOE = 4,
 704         MBX_SUBSYSTEM_PXE_UNDI = 5,
 705         MBX_SUBSYSTEM_ISCSI_INI = 6,
 706         MBX_SUBSYSTEM_ISCSI_TGT = 7,
 707         MBX_SUBSYSTEM_MILI_PTL = 8,
 708         MBX_SUBSYSTEM_MILI_TMD = 9,
 709         MBX_SUBSYSTEM_RDMA = 10,
 710         MBX_SUBSYSTEM_LOWLEVEL = 11,
 711         MBX_SUBSYSTEM_LRO = 13,
 712         IOCBMBX_SUBSYSTEM_DCBX = 15,
 713         IOCBMBX_SUBSYSTEM_DIAG = 16,
 714         IOCBMBX_SUBSYSTEM_VENDOR = 17
 715 };
 716
 717 /* common ioctl opcodes */
 718 enum COMMON_SUBSYSTEM_OPCODES {
 719 /* These opcodes are common to both networking and storage PCI functions
 720  * They are used to reserve resources and configure CNA. These opcodes
 721  * all use the MBX_SUBSYSTEM_COMMON subsystem code.
 722  */
 723         OPCODE_COMMON_QUERY_IFACE_MAC = 1,
 724         OPCODE_COMMON_SET_IFACE_MAC = 2,
 725         OPCODE_COMMON_SET_IFACE_MULTICAST = 3,
 726         OPCODE_COMMON_CONFIG_IFACE_VLAN = 4,
 727         OPCODE_COMMON_QUERY_LINK_CONFIG = 5,
 728         OPCODE_COMMON_READ_FLASHROM = 6,
 729         OPCODE_COMMON_WRITE_FLASHROM = 7,
 730         OPCODE_COMMON_QUERY_MAX_MBX_BUFFER_SIZE = 8,
 731         OPCODE_COMMON_CREATE_CQ = 12,
 732         OPCODE_COMMON_CREATE_EQ = 13,
 733         OPCODE_COMMON_CREATE_MQ = 21,
 734         OPCODE_COMMON_GET_QOS = 27,
 735         OPCODE_COMMON_SET_QOS = 28,
 736         OPCODE_COMMON_READ_EPROM = 30,
 737         OPCODE_COMMON_GET_CNTL_ATTRIBUTES = 32,
 738         OPCODE_COMMON_NOP = 33,
 739         OPCODE_COMMON_SET_IFACE_RX_FILTER = 34,
 740         OPCODE_COMMON_GET_FW_VERSION = 35,
 741         OPCODE_COMMON_SET_FLOW_CONTROL = 36,
 742         OPCODE_COMMON_GET_FLOW_CONTROL = 37,
 743         OPCODE_COMMON_SET_FRAME_SIZE = 39,
 744         OPCODE_COMMON_MODIFY_EQ_DELAY = 41,
 745         OPCODE_COMMON_CREATE_IFACE = 50,
 746         OPCODE_COMMON_DESTROY_IFACE = 51,
 747         OPCODE_COMMON_MODIFY_MSI_MESSAGES = 52,
 748         OPCODE_COMMON_DESTROY_MQ = 53,
 749         OPCODE_COMMON_DESTROY_CQ = 54,
 750         OPCODE_COMMON_DESTROY_EQ = 55,
 751         OPCODE_COMMON_UPLOAD_TCP = 56,
 752         OPCODE_COMMON_SET_NTWK_LINK_SPEED = 57,
 753         OPCODE_COMMON_QUERY_FIRMWARE_CONFIG = 58,
 754         OPCODE_COMMON_ADD_IFACE_MAC = 59,
 755         OPCODE_COMMON_DEL_IFACE_MAC = 60,
 756         OPCODE_COMMON_FUNCTION_RESET = 61,
 757         OPCODE_COMMON_SET_PHYSICAL_LINK_CONFIG = 62,
 758         OPCODE_COMMON_GET_BOOT_CONFIG = 66,
 759         OPCPDE_COMMON_SET_BOOT_CONFIG = 67,
 760         OPCODE_COMMON_SET_BEACON_CONFIG = 69,
 761         OPCODE_COMMON_GET_BEACON_CONFIG = 70,
 762         OPCODE_COMMON_GET_PHYSICAL_LINK_CONFIG = 71,
 763         OPCODE_COMMON_GET_OEM_ATTRIBUTES = 76,
 764         OPCODE_COMMON_GET_PORT_NAME = 77,
 765         OPCODE_COMMON_GET_CONFIG_SIGNATURE = 78,
 766         OPCODE_COMMON_SET_CONFIG_SIGNATURE = 79,
 767         OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG = 80,
 768         OPCODE_COMMON_GET_BE_CONFIGURATION_RESOURCES = 81,
 769         OPCODE_COMMON_SET_BE_CONFIGURATION_RESOURCES = 82,
 770         OPCODE_COMMON_GET_RESET_NEEDED = 84,
 771         OPCODE_COMMON_GET_SERIAL_NUMBER = 85,
 772         OPCODE_COMMON_GET_NCSI_CONFIG = 86,
 773         OPCODE_COMMON_SET_NCSI_CONFIG = 87,
 774         OPCODE_COMMON_CREATE_MQ_EXT = 90,
 775         OPCODE_COMMON_SET_FUNCTION_PRIVILEGES = 100,
 776         OPCODE_COMMON_SET_VF_PORT_TYPE = 101,
 777         OPCODE_COMMON_GET_PHY_CONFIG = 102,
 778         OPCODE_COMMON_SET_FUNCTIONAL_CAPS = 103,
 779         OPCODE_COMMON_GET_ADAPTER_ID = 110,
 780         OPCODE_COMMON_GET_UPGRADE_FEATURES = 111,
 781         OPCODE_COMMON_GET_INSTALLED_FEATURES = 112,
 782         OPCODE_COMMON_GET_AVAIL_PERSONALITIES = 113,
 783         OPCODE_COMMON_GET_CONFIG_PERSONALITIES = 114,
 784         OPCODE_COMMON_SEND_ACTIVATION = 115,
 785         OPCODE_COMMON_RESET_LICENSES = 116,
 786         OPCODE_COMMON_GET_CNTL_ADDL_ATTRIBUTES = 121,
 787         OPCODE_COMMON_QUERY_TCB = 144,
 788         OPCODE_COMMON_ADD_IFACE_QUEUE_FILTER = 145,
 789         OPCODE_COMMON_DEL_IFACE_QUEUE_FILTER = 146,
 790         OPCODE_COMMON_GET_IFACE_MAC_LIST = 147,
 791         OPCODE_COMMON_SET_IFACE_MAC_LIST = 148,
 792         OPCODE_COMMON_MODIFY_CQ = 149,
 793         OPCODE_COMMON_GET_IFACE_VLAN_LIST = 150,
 794         OPCODE_COMMON_SET_IFACE_VLAN_LIST = 151,
 795         OPCODE_COMMON_GET_HSW_CONFIG = 152,
 796         OPCODE_COMMON_SET_HSW_CONFIG = 153,
 797         OPCODE_COMMON_GET_RESOURCE_EXTENT_INFO = 154,
 798         OPCODE_COMMON_GET_ALLOCATED_RESOURCE_EXTENTS = 155,
 799         OPCODE_COMMON_ALLOC_RESOURCE_EXTENTS = 156,
 800         OPCODE_COMMON_DEALLOC_RESOURCE_EXTENTS = 157,
 801         OPCODE_COMMON_SET_DIAG_REGISTERS = 158,
 802         OPCODE_COMMON_GET_FUNCTION_CONFIG = 160,
 803         OPCODE_COMMON_GET_PROFILE_CAPACITIES = 161,
 804         OPCODE_COMMON_GET_MR_PROFILE_CAPACITIES = 162,
 805         OPCODE_COMMON_SET_MR_PROFILE_CAPACITIES = 163,
 806         OPCODE_COMMON_GET_PROFILE_CONFIG = 164,
 807         OPCODE_COMMON_SET_PROFILE_CONFIG = 165,
 808         OPCODE_COMMON_GET_PROFILE_LIST = 166,
 809         OPCODE_COMMON_GET_ACTIVE_PROFILE = 167,
 810         OPCODE_COMMON_SET_ACTIVE_PROFILE = 168,
 811         OPCODE_COMMON_GET_FUNCTION_PRIVILEGES = 170,
 812         OPCODE_COMMON_READ_OBJECT = 171,
 813         OPCODE_COMMON_WRITE_OBJECT = 172
 814 };
 815
 816 /* common ioctl header */
 817 #define OCE_MBX_VER_V2  0x0002          /* Version V2 mailbox command */
 818 #define OCE_MBX_VER_V1  0x0001          /* Version V1 mailbox command */
 819 #define OCE_MBX_VER_V0  0x0000          /* Version V0 mailbox command */
 820 struct mbx_hdr {
 821         union {
 822                 uint32_t dw[4];
 823                 struct {
 824                 #ifdef _BIG_ENDIAN
 825                         /* dw 0 */
 826                         uint32_t domain:8;
 827                         uint32_t port_number:8;
 828                         uint32_t subsystem:8;
 829                         uint32_t opcode:8;
 830                         /* dw 1 */
 831                         uint32_t timeout;
 832                         /* dw 2 */
 833                         uint32_t request_length;
 834                         /* dw 3 */
 835                         uint32_t rsvd0:24;
 836                         uint32_t version:8;
 837                 #else
 838                         /* dw 0 */
 839                         uint32_t opcode:8;
 840                         uint32_t subsystem:8;
 841                         uint32_t port_number:8;
 842                         uint32_t domain:8;
 843                         /* dw 1 */
 844                         uint32_t timeout;
 845                         /* dw 2 */
 846                         uint32_t request_length;
 847                         /* dw 3 */
 848                         uint32_t version:8;
 849                         uint32_t rsvd0:24;
 850                 #endif
 851                 } req;
 852                 struct {
 853                 #ifdef _BIG_ENDIAN
 854                         /* dw 0 */
 855                         uint32_t domain:8;
 856                         uint32_t rsvd0:8;
 857                         uint32_t subsystem:8;
 858                         uint32_t opcode:8;
 859                         /* dw 1 */
 860                         uint32_t rsvd1:16;
 861                         uint32_t additional_status:8;
 862                         uint32_t status:8;
 863                 #else
 864                         /* dw 0 */
 865                         uint32_t opcode:8;
 866                         uint32_t subsystem:8;
 867                         uint32_t rsvd0:8;
 868                         uint32_t domain:8;
 869                         /* dw 1 */
 870                         uint32_t status:8;
 871                         uint32_t additional_status:8;
 872                         uint32_t rsvd1:16;
 873                 #endif
 874                         uint32_t rsp_length;
 875                         uint32_t actual_rsp_length;
 876                 } rsp;
 877         } u0;
 878 };
 879 #define OCE_BMBX_RHDR_SZ 20
 880 #define OCE_MBX_RRHDR_SZ sizeof (struct mbx_hdr)
 881 #define OCE_MBX_ADDL_STATUS(_MHDR) ((_MHDR)->u0.rsp.additional_status)
 882 #define OCE_MBX_STATUS(_MHDR) ((_MHDR)->u0.rsp.status)
 883
 884 /* [05] OPCODE_COMMON_QUERY_LINK_CONFIG */
 885 struct mbx_query_common_link_config {
 886         struct mbx_hdr hdr;
 887         union {
 888                 struct {
 889                         uint32_t rsvd0;
 890                 } req;
 891
 892                 struct {
 893                         /* dw 0 */
 894                         uint8_t physical_port;
 895                         uint8_t mac_duplex;
 896                         uint8_t mac_speed;
 897                         uint8_t mac_fault;
 898                         /* dw 1 */
 899                         uint8_t mgmt_mac_duplex;
 900                         uint8_t mgmt_mac_speed;
 901                         uint16_t qos_link_speed;
 902                         uint32_t logical_link_status;
 903                 } rsp;
 904         } params;
 905 };
 906
 907 /* [57] OPCODE_COMMON_SET_LINK_SPEED */
 908 struct mbx_set_common_link_speed {
 909         struct mbx_hdr hdr;
 910         union {
 911                 struct {
 912 #ifdef _BIG_ENDIAN
 913                         uint8_t rsvd0;
 914                         uint8_t mac_speed;
 915                         uint8_t virtual_port;
 916                         uint8_t physical_port;
 917 #else
 918                         uint8_t physical_port;
 919                         uint8_t virtual_port;
 920                         uint8_t mac_speed;
 921                         uint8_t rsvd0;
 922 #endif
 923                 } req;
 924
 925                 struct {
 926                         uint32_t rsvd0;
 927                 } rsp;
 928
 929                 uint32_t dw;
 930         } params;
 931 };
 932
 933 struct mac_address_format {
 934         uint16_t size_of_struct;
 935         uint8_t mac_addr[6];
 936 };
 937
 938 /* [01] OPCODE_COMMON_QUERY_IFACE_MAC */
 939 struct mbx_query_common_iface_mac {
 940         struct mbx_hdr hdr;
 941         union {
 942                 struct {
 943 #ifdef _BIG_ENDIAN
 944                         uint16_t if_id;
 945                         uint8_t permanent;
 946                         uint8_t type;
 947 #else
 948                         uint8_t type;
 949                         uint8_t permanent;
 950                         uint16_t if_id;
 951 #endif
 952
 953                 } req;
 954
 955                 struct {
 956                         struct mac_address_format mac;
 957                 } rsp;
 958         } params;
 959 };
 960
 961 /* [02] OPCODE_COMMON_SET_IFACE_MAC */
 962 struct mbx_set_common_iface_mac {
 963         struct mbx_hdr hdr;
 964         union {
 965                 struct {
 966 #ifdef _BIG_ENDIAN
 967                         /* dw 0 */
 968                         uint16_t if_id;
 969                         uint8_t invalidate;
 970                         uint8_t type;
 971 #else
 972                         /* dw 0 */
 973                         uint8_t type;
 974                         uint8_t invalidate;
 975                         uint16_t if_id;
 976 #endif
 977                         /* dw 1 */
 978                         struct mac_address_format mac;
 979                 } req;
 980
 981                 struct {
 982                         uint32_t rsvd0;
 983                 } rsp;
 984
 985                 uint32_t dw[2];
 986         } params;
 987 };
 988
 989 /* [03] OPCODE_COMMON_SET_IFACE_MULTICAST */
 990 struct mbx_set_common_iface_multicast {
 991         struct mbx_hdr hdr;
 992         union {
 993                 struct {
 994                         /* dw 0 */
 995                         uint16_t num_mac;
 996                         uint8_t promiscuous;
 997                         uint8_t if_id;
 998                         /* dw 1-48 */
 999                         struct {
1000                                 uint8_t byte[6];
1001                         } mac[32];
1002
1003                 } req;
1004
1005                 struct {
1006                         uint32_t rsvd0;
1007                 } rsp;
1008
1009                 uint32_t dw[49];
1010         } params;
1011 };
1012
1013 struct qinq_vlan {
1014 #ifdef _BIG_ENDIAN
1015         uint16_t inner;
1016         uint16_t outer;
1017 #else
1018         uint16_t outer;
1019         uint16_t inner;
1020 #endif
1021 };
1022
1023 struct normal_vlan {
1024         uint16_t vtag;
1025 };
1026
1027 struct ntwk_if_vlan_tag {
1028         union {
1029                 struct normal_vlan normal;
1030                 struct qinq_vlan qinq;
1031         } u0;
1032 };
1033
1034 /* [50] OPCODE_COMMON_CREATE_IFACE */
1035 struct mbx_create_common_iface {
1036         struct mbx_hdr hdr;
1037         union {
1038                 struct {
1039                         uint32_t version;
1040                         uint32_t cap_flags;
1041                         uint32_t enable_flags;
1042                         uint8_t mac_addr[6];
1043                         uint8_t rsvd0;
1044                         uint8_t mac_invalid;
1045                         struct ntwk_if_vlan_tag vlan_tag;
1046                 } req;
1047
1048                 struct {
1049                         uint32_t if_id;
1050                         uint32_t pmac_id;
1051                 } rsp;
1052                 uint32_t dw[4];
1053         } params;
1054 };
1055
1056 /* [51] OPCODE_COMMON_DESTROY_IFACE */
1057 struct mbx_destroy_common_iface {
1058         struct mbx_hdr hdr;
1059         union {
1060                 struct {
1061                         uint32_t if_id;
1062                 } req;
1063
1064                 struct {
1065                         uint32_t rsvd0;
1066                 } rsp;
1067
1068                 uint32_t dw;
1069         } params;
1070 };
1071
1072 /* event queue context structure */
1073 struct oce_eq_ctx {
1074 #ifdef _BIG_ENDIAN
1075         uint32_t dw4rsvd1:16;
1076         uint32_t num_pages:16;
1077
1078         uint32_t size:1;
1079         uint32_t dw5rsvd2:1;
1080         uint32_t valid:1;
1081         uint32_t dw5rsvd1:29;
1082
1083         uint32_t armed:1;
1084         uint32_t dw6rsvd2:2;
1085         uint32_t count:3;
1086         uint32_t dw6rsvd1:26;
1087
1088         uint32_t dw7rsvd2:9;
1089         uint32_t delay_mult:10;
1090         uint32_t dw7rsvd1:13;
1091
1092         uint32_t dw8rsvd1;
1093 #else
1094         uint32_t num_pages:16;
1095         uint32_t dw4rsvd1:16;
1096
1097         uint32_t dw5rsvd1:29;
1098         uint32_t valid:1;
1099         uint32_t dw5rsvd2:1;
1100         uint32_t size:1;
1101
1102         uint32_t dw6rsvd1:26;
1103         uint32_t count:3;
1104         uint32_t dw6rsvd2:2;
1105         uint32_t armed:1;
1106
1107         uint32_t dw7rsvd1:13;
1108         uint32_t delay_mult:10;
1109         uint32_t dw7rsvd2:9;
1110
1111         uint32_t dw8rsvd1;
1112 #endif
1113 };
1114
1115 /* [13] OPCODE_COMMON_CREATE_EQ */
1116 struct mbx_create_common_eq {
1117         struct mbx_hdr hdr;
1118         union {
1119                 struct {
1120                         struct oce_eq_ctx ctx;
1121                         struct phys_addr pages[8];
1122                 } req;
1123
1124                 struct {
1125                         uint16_t eq_id;
1126                         uint16_t rsvd0;
1127                 } rsp;
1128         } params;
1129 };
1130
1131 /* [55] OPCODE_COMMON_DESTROY_EQ */
1132 struct mbx_destroy_common_eq {
1133         struct mbx_hdr hdr;
1134         union {
1135                 struct {
1136 #ifdef _BIG_ENDIAN
1137                         uint16_t rsvd0;
1138                         uint16_t id;
1139 #else
1140                         uint16_t id;
1141                         uint16_t rsvd0;
1142 #endif
1143                 } req;
1144
1145                 struct {
1146                         uint32_t rsvd0;
1147                 } rsp;
1148         } params;
1149 };
1150
1151 /* SLI-4 CQ context - use version V0 for B3, version V2 for Lancer */
1152 typedef union oce_cq_ctx_u {
1153         uint32_t dw[5];
1154         struct {
1155         #ifdef _BIG_ENDIAN
1156                 /* dw4 */
1157                 uint32_t dw4rsvd1:16;
1158                 uint32_t num_pages:16;
1159                 /* dw5 */
1160                 uint32_t eventable:1;
1161                 uint32_t dw5rsvd3:1;
1162                 uint32_t valid:1;
1163                 uint32_t count:2;
1164                 uint32_t dw5rsvd2:12;
1165                 uint32_t nodelay:1;
1166                 uint32_t coalesce_wm:2;
1167                 uint32_t dw5rsvd1:12;
1168                 /* dw6 */
1169                 uint32_t armed:1;
1170                 uint32_t dw6rsvd2:1;
1171                 uint32_t eq_id:8;
1172                 uint32_t dw6rsvd1:22;
1173         #else
1174                 /* dw4 */
1175                 uint32_t num_pages:16;
1176                 uint32_t dw4rsvd1:16;
1177                 /* dw5 */
1178                 uint32_t dw5rsvd1:12;
1179                 uint32_t coalesce_wm:2;
1180                 uint32_t nodelay:1;
1181                 uint32_t dw5rsvd2:12;
1182                 uint32_t count:2;
1183                 uint32_t valid:1;
1184                 uint32_t dw5rsvd3:1;
1185                 uint32_t eventable:1;
1186                 /* dw6 */
1187                 uint32_t dw6rsvd1:22;
1188                 uint32_t eq_id:8;
1189                 uint32_t dw6rsvd2:1;
1190                 uint32_t armed:1;
1191         #endif
1192                 /* dw7 */
1193                 uint32_t dw7rsvd1;
1194                 /* dw8 */
1195                 uint32_t dw8rsvd1;
1196         } v0;
1197         struct {
1198         #ifdef _BIG_ENDIAN
1199                 /* dw4 */
1200                 uint32_t dw4rsvd1:8;
1201                 uint32_t page_size:8;
1202                 uint32_t num_pages:16;
1203                 /* dw5 */
1204                 uint32_t eventable:1;
1205                 uint32_t dw5rsvd3:1;
1206                 uint32_t valid:1;
1207                 uint32_t count:2;
1208                 uint32_t dw5rsvd2:11;
1209                 uint32_t autovalid:1;
1210                 uint32_t nodelay:1;
1211                 uint32_t coalesce_wm:2;
1212                 uint32_t dw5rsvd1:12;
1213                 /* dw6 */
1214                 uint32_t armed:1;
1215                 uint32_t dw6rsvd1:15;
1216                 uint32_t eq_id:16;
1217                 /* dw7 */
1218                 uint32_t dw7rsvd1:16;
1219                 uint32_t cqe_count:16;
1220         #else
1221                 /* dw4 */
1222                 uint32_t num_pages:16;
1223                 uint32_t page_size:8;
1224                 uint32_t dw4rsvd1:8;
1225                 /* dw5 */
1226                 uint32_t dw5rsvd1:12;
1227                 uint32_t coalesce_wm:2;
1228                 uint32_t nodelay:1;
1229                 uint32_t autovalid:1;
1230                 uint32_t dw5rsvd2:11;
1231                 uint32_t count:2;
1232                 uint32_t valid:1;
1233                 uint32_t dw5rsvd3:1;
1234                 uint32_t eventable:1;
1235                 /* dw6 */
1236                 uint32_t eq_id:8;
1237                 uint32_t dw6rsvd1:15;
1238                 uint32_t armed:1;
1239                 /* dw7 */
1240                 uint32_t cqe_count:16;
1241                 uint32_t dw7rsvd1:16;
1242         #endif
1243                 /* dw8 */
1244                 uint32_t dw8rsvd1;
1245         } v2;
1246 } oce_cq_ctx_t;
1247
1248 /* [12] OPCODE_COMMON_CREATE_CQ */
1249 struct mbx_create_common_cq {
1250         struct mbx_hdr hdr;
1251         union {
1252                 struct {
1253                         oce_cq_ctx_t cq_ctx;
1254                         struct phys_addr pages[4];
1255                 } req;
1256
1257                 struct {
1258                         uint16_t cq_id;
1259                         uint16_t rsvd0;
1260                 } rsp;
1261         } params;
1262 };
1263
1264 /* [54] OPCODE_COMMON_DESTROY_CQ */
1265 struct mbx_destroy_common_cq {
1266         struct mbx_hdr hdr;
1267         union {
1268                 struct {
1269 #ifdef _BIG_ENDIAN
1270                         uint16_t rsvd0;
1271                         uint16_t id;
1272 #else
1273                         uint16_t id;
1274                         uint16_t rsvd0;
1275 #endif
1276                 } req;
1277
1278                 struct {
1279                         uint32_t rsvd0;
1280                 } rsp;
1281         } params;
1282 };
1283
1284 typedef union oce_mq_ctx_u {
1285         uint32_t dw[5];
1286         struct {
1287         #ifdef _BIG_ENDIAN
1288                 /* dw4 */
1289                 uint32_t dw4rsvd1:16;
1290                 uint32_t num_pages:16;
1291                 /* dw5 */
1292                 uint32_t cq_id:10;
1293                 uint32_t dw5rsvd2:2;
1294                 uint32_t ring_size:4;
1295                 uint32_t dw5rsvd1:16;
1296                 /* dw6 */
1297                 uint32_t valid:1;
1298                 uint32_t dw6rsvd1:31;
1299                 /* dw7 */
1300                 uint32_t dw7rsvd1:21;
1301                 uint32_t async_cq_id:10;
1302                 uint32_t async_cq_valid:1;
1303         #else
1304                 /* dw4 */
1305                 uint32_t num_pages:16;
1306                 uint32_t dw4rsvd1:16;
1307                 /* dw5 */
1308                 uint32_t dw5rsvd1:16;
1309                 uint32_t ring_size:4;
1310                 uint32_t dw5rsvd2:2;
1311                 uint32_t cq_id:10;
1312                 /* dw6 */
1313                 uint32_t dw6rsvd1:31;
1314                 uint32_t valid:1;
1315                 /* dw7 */
1316                 uint32_t async_cq_valid:1;
1317                 uint32_t async_cq_id:10;
1318                 uint32_t dw7rsvd1:21;
1319         #endif
1320                 /* dw8 */
1321                 uint32_t dw8rsvd1;
1322         } v0;
1323 } oce_mq_ctx_t;
1324
1325 /**
1326  * @brief [21] OPCODE_COMMON_CREATE_MQ
1327  * A MQ must be at least 16 entries deep (corresponding to 1 page) and
1328  * at most 128 entries deep (corresponding to 8 pages).
1329  */
1330 struct mbx_create_common_mq {
1331         struct mbx_hdr hdr;
1332         union {
1333                 struct {
1334                         oce_mq_ctx_t context;
1335                         struct phys_addr pages[8];
1336                 } req;
1337
1338                 struct {
1339                         uint32_t mq_id:16;
1340                         uint32_t rsvd0:16;
1341                 } rsp;
1342         } params;
1343 };
1344
1345 /* [53] OPCODE_COMMON_DESTROY_MQ */
1346 struct mbx_destroy_common_mq {
1347         struct mbx_hdr hdr;
1348         union {
1349                 struct {
1350 #ifdef _BIG_ENDIAN
1351                         uint16_t rsvd0;
1352                         uint16_t id;
1353 #else
1354                         uint16_t id;
1355                         uint16_t rsvd0;
1356 #endif
1357                 } req;
1358
1359                 struct {
1360                         uint32_t rsvd0;
1361                 } rsp;
1362         } params;
1363 };
1364
1365 /* [35] OPCODE_COMMON_GET_ FW_VERSION */
1366 struct mbx_get_common_fw_version {
1367         struct mbx_hdr hdr;
1368         union {
1369                 struct {
1370                         uint32_t rsvd0;
1371                 } req;
1372
1373                 struct {
1374                         uint8_t fw_ver_str[32];
1375                         uint8_t fw_on_flash_ver_str[32];
1376                 } rsp;
1377         } params;
1378 };
1379
1380 /* [52] OPCODE_COMMON_CEV_MODIFY_MSI_MESSAGES */
1381 struct mbx_common_cev_modify_msi_messages {
1382         struct mbx_hdr hdr;
1383         union {
1384                 struct {
1385                         uint32_t num_msi_msgs;
1386                 } req;
1387
1388                 struct {
1389                         uint32_t rsvd0;
1390                 } rsp;
1391         } params;
1392 };
1393
1394 /* [36] OPCODE_COMMON_SET_FLOW_CONTROL */
1395 /* [37] OPCODE_COMMON_GET_FLOW_CONTROL */
1396 struct mbx_common_get_set_flow_control {
1397         struct mbx_hdr hdr;
1398 #ifdef _BIG_ENDIAN
1399         uint16_t tx_flow_control;
1400         uint16_t rx_flow_control;
1401 #else
1402         uint16_t rx_flow_control;
1403         uint16_t tx_flow_control;
1404 #endif
1405 };
1406
1407 enum e_flash_opcode {
1408         MGMT_FLASHROM_OPCODE_FLASH = 1,
1409         MGMT_FLASHROM_OPCODE_SAVE = 2
1410 };
1411
1412 /* [06] OPCODE_READ_COMMON_FLASHROM */
1413 /* [07] OPCODE_WRITE_COMMON_FLASHROM */
1414
1415 struct mbx_common_read_write_flashrom {
1416         struct mbx_hdr hdr;
1417         uint32_t flash_op_code;
1418         uint32_t flash_op_type;
1419         uint32_t data_buffer_size;
1420         uint32_t data_offset;
1421         uint8_t  data_buffer[4];        /* + IMAGE_TRANSFER_SIZE */
1422 };
1423
1424 struct oce_phy_info {
1425         uint16_t phy_type;
1426         uint16_t interface_type;
1427         uint32_t misc_params;
1428         uint16_t ext_phy_details;
1429         uint16_t rsvd;
1430         uint16_t auto_speeds_supported;
1431         uint16_t fixed_speeds_supported;
1432         uint32_t future_use[2];
1433 };
1434
1435 struct mbx_common_phy_info {
1436         struct mbx_hdr hdr;
1437         union {
1438                 struct {
1439                         uint32_t rsvd0[4];
1440                 } req;
1441                 struct {
1442                         struct oce_phy_info phy_info;
1443                 } rsp;
1444         } params;
1445 };
1446
1447 /*Lancer firmware*/
1448
1449 struct mbx_lancer_common_write_object {
1450         union {
1451                 struct {
1452                         struct   mbx_hdr hdr;
1453                         uint32_t write_length: 24;
1454                         uint32_t rsvd: 7;
1455                         uint32_t eof: 1;
1456                         uint32_t write_offset;
1457                         uint8_t  object_name[104];
1458                         uint32_t descriptor_count;
1459                         uint32_t buffer_length;
1460                         uint32_t address_lower;
1461                         uint32_t address_upper;
1462                 } req;
1463                 struct {
1464                         uint8_t  opcode;
1465                         uint8_t  subsystem;
1466                         uint8_t  rsvd1[2];
1467                         uint8_t  status;
1468                         uint8_t  additional_status;
1469                         uint8_t  rsvd2[2];
1470                         uint32_t response_length;
1471                         uint32_t actual_response_length;
1472                         uint32_t actual_write_length;
1473                 } rsp;
1474         } params;
1475 };
1476
1477 /**
1478  * @brief MBX Common Quiery Firmaware Config
1479  * This command retrieves firmware configuration parameters and adapter
1480  * resources available to the driver originating the request. The firmware
1481  * configuration defines supported protocols by the installed adapter firmware.
1482  * This includes which ULP processors support the specified protocols and
1483  * the number of TCP connections allowed for that protocol.
1484  */
1485 struct mbx_common_query_fw_config {
1486         struct mbx_hdr hdr;
1487         union {
1488                 struct {
1489                         uint32_t rsvd0[30];
1490                 } req;
1491
1492                 struct {
1493                         uint32_t config_number;
1494                         uint32_t asic_revision;
1495                         uint32_t port_id;       /* used for stats retrieval */
1496                         uint32_t function_mode;
1497                         struct {
1498
1499                                 uint32_t ulp_mode;
1500                                 uint32_t nic_wqid_base;
1501                                 uint32_t nic_wq_tot;
1502                                 uint32_t toe_wqid_base;
1503                                 uint32_t toe_wq_tot;
1504                                 uint32_t toe_rqid_base;
1505                                 uint32_t toe_rqid_tot;
1506                                 uint32_t toe_defrqid_base;
1507                                 uint32_t toe_defrqid_count;
1508                                 uint32_t lro_rqid_base;
1509                                 uint32_t lro_rqid_tot;
1510                                 uint32_t iscsi_icd_base;
1511                                 uint32_t iscsi_icd_count;
1512                         } ulp[2];
1513                         uint32_t function_caps;
1514                         uint32_t cqid_base;
1515                         uint32_t cqid_tot;
1516                         uint32_t eqid_base;
1517                         uint32_t eqid_tot;
1518                 } rsp;
1519         } params;
1520 };
1521
1522 enum CQFW_CONFIG_NUMBER {
1523         FCN_NIC_ISCSI_Initiator = 0x0,
1524         FCN_ISCSI_Target = 0x3,
1525         FCN_FCoE = 0x7,
1526         FCN_ISCSI_Initiator_Target = 0x9,
1527         FCN_NIC_RDMA_TOE = 0xA,
1528         FCN_NIC_RDMA_FCoE = 0xB,
1529         FCN_NIC_RDMA_iSCSI = 0xC,
1530         FCN_NIC_iSCSI_FCoE = 0xD
1531 };
1532
1533 /**
1534  * @brief Function Capabilites
1535  * This field contains the flags indicating the capabilities of
1536  * the SLI Host’s PCI function.
1537  */
1538 enum CQFW_FUNCTION_CAPABILITIES {
1539         FNC_UNCLASSIFIED_STATS = 0x1,
1540         FNC_RSS = 0x2,
1541         FNC_PROMISCUOUS = 0x4,
1542         FNC_LEGACY_MODE = 0x8,
1543         FNC_HDS = 0x4000,
1544         FNC_VMQ = 0x10000,
1545         FNC_NETQ = 0x20000,
1546         FNC_QGROUPS = 0x40000,
1547         FNC_LRO = 0x100000,
1548         FNC_VLAN_OFFLOAD = 0x800000
1549 };
1550
1551 enum CQFW_ULP_MODES_SUPPORTED {
1552         ULP_TOE_MODE = 0x1,
1553         ULP_NIC_MODE = 0x2,
1554         ULP_RDMA_MODE = 0x4,
1555         ULP_ISCSI_INI_MODE = 0x10,
1556         ULP_ISCSI_TGT_MODE = 0x20,
1557         ULP_FCOE_INI_MODE = 0x40,
1558         ULP_FCOE_TGT_MODE = 0x80,
1559         ULP_DAL_MODE = 0x100,
1560         ULP_LRO_MODE = 0x200
1561 };
1562
1563 /**
1564  * @brief Function Modes Supported
1565  * Valid function modes (or protocol-types) supported on the SLI-Host’s
1566  * PCIe function.  This field is a logical OR of the following values:
1567  */
1568 enum CQFW_FUNCTION_MODES_SUPPORTED {
1569         FNM_TOE_MODE = 0x1,             /* TCP offload supported */
1570         FNM_NIC_MODE = 0x2,             /* Raw Ethernet supported */
1571         FNM_RDMA_MODE = 0x4,            /* RDMA protocol supported */
1572         FNM_VM_MODE = 0x8,              /* Virtual Machines supported  */
1573         FNM_ISCSI_INI_MODE = 0x10,      /* iSCSI initiator supported */
1574         FNM_ISCSI_TGT_MODE = 0x20,      /* iSCSI target plus initiator */
1575         FNM_FCOE_INI_MODE = 0x40,       /* FCoE Initiator supported */
1576         FNM_FCOE_TGT_MODE = 0x80,       /* FCoE target supported */
1577         FNM_DAL_MODE = 0x100,           /* DAL supported */
1578         FNM_LRO_MODE = 0x200,           /* LRO supported */
1579         FNM_FLEX10_MODE = 0x400,        /* QinQ, FLEX-10 or VNIC */
1580         FNM_NCSI_MODE = 0x800,          /* NCSI supported */
1581         FNM_IPV6_MODE = 0x1000,         /* IPV6 stack enabled */
1582         FNM_BE2_COMPAT_MODE = 0x2000,   /* BE2 compatibility (BE3 disable)*/
1583         FNM_INVALID_MODE = 0x8000,      /* Invalid */
1584         FNM_BE3_COMPAT_MODE = 0x10000,  /* BE3 features */
1585         FNM_VNIC_MODE = 0x20000,        /* Set when IBM vNIC mode is set */
1586         FNM_VNTAG_MODE = 0x40000,       /* Set when VNTAG mode is set */
1587         FNM_UMC_MODE = 0x80000,         /* Set when UMC mode is set */
1588         FNM_UMC_DEF_EN = 0x100000,      /* Set when UMC Default is set */
1589         FNM_ONE_GB_EN = 0x200000,       /* Set when 1GB Default is set */
1590         FNM_VNIC_DEF_VALID = 0x400000,  /* Set when VNIC_DEF_EN is valid */
1591         FNM_VNIC_DEF_EN = 0x800000      /* Set when VNIC Default enabled */
1592 };
1593
1594
1595 struct mbx_common_config_vlan {
1596         struct mbx_hdr hdr;
1597         union {
1598                 struct {
1599 #ifdef _BIG_ENDIAN
1600                         uint8_t num_vlans;
1601                         uint8_t untagged;
1602                         uint8_t promisc;
1603                         uint8_t if_id;
1604 #else
1605                         uint8_t if_id;
1606                         uint8_t promisc;
1607                         uint8_t untagged;
1608                         uint8_t num_vlans;
1609 #endif
1610                         union {
1611                                 struct normal_vlan normal_vlans[64];
1612                                 struct qinq_vlan qinq_vlans[32];
1613                         } tags;
1614                 } req;
1615
1616                 struct {
1617                         uint32_t rsvd;
1618                 } rsp;
1619         } params;
1620 };
1621
1622 typedef struct iface_rx_filter_ctx {
1623         uint32_t global_flags_mask;
1624         uint32_t global_flags;
1625         uint32_t iface_flags_mask;
1626         uint32_t iface_flags;
1627         uint32_t if_id;
1628         #define IFACE_RX_NUM_MCAST_MAX          64
1629         uint32_t num_mcast;
1630         struct mbx_mcast_addr {
1631                 uint8_t byte[6];
1632         } mac[IFACE_RX_NUM_MCAST_MAX];
1633 } iface_rx_filter_ctx_t;
1634
1635 /* [34] OPCODE_COMMON_SET_IFACE_RX_FILTER */
1636 struct mbx_set_common_iface_rx_filter {
1637         struct mbx_hdr hdr;
1638         union {
1639                 iface_rx_filter_ctx_t req;
1640                 iface_rx_filter_ctx_t rsp;
1641         } params;
1642 };
1643
1644 /* [41] OPCODE_COMMON_MODIFY_EQ_DELAY */
1645 struct mbx_modify_common_eq_delay {
1646         struct mbx_hdr hdr;
1647         union {
1648                 struct {
1649                         uint32_t num_eq;
1650                         struct {
1651                                 uint32_t eq_id;
1652                                 uint32_t phase;
1653                                 uint32_t dm;
1654                         } delay[8];
1655                 } req;
1656
1657                 struct {
1658                         uint32_t rsvd0;
1659                 } rsp;
1660         } params;
1661 };
1662
1663 /* [59] OPCODE_ADD_COMMON_IFACE_MAC */
1664 struct mbx_add_common_iface_mac {
1665         struct mbx_hdr hdr;
1666         union {
1667                 struct {
1668                         uint32_t if_id;
1669                         uint8_t mac_address[6];
1670                         uint8_t rsvd0[2];
1671                 } req;
1672                 struct {
1673                         uint32_t pmac_id;
1674                 } rsp;
1675         } params;
1676 };
1677
1678 /* [60] OPCODE_DEL_COMMON_IFACE_MAC */
1679 struct mbx_del_common_iface_mac {
1680         struct mbx_hdr hdr;
1681         union {
1682                 struct {
1683                         uint32_t if_id;
1684                         uint32_t pmac_id;
1685                 } req;
1686                 struct {
1687                         uint32_t rsvd0;
1688                 } rsp;
1689         } params;
1690 };
1691
1692 /* [8] OPCODE_QUERY_COMMON_MAX_MBX_BUFFER_SIZE */
1693 struct mbx_query_common_max_mbx_buffer_size {
1694         struct mbx_hdr hdr;
1695         struct {
1696                 uint32_t max_ioctl_bufsz;
1697         } rsp;
1698 };
1699
1700 /* [61] OPCODE_COMMON_FUNCTION_RESET */
1701 struct ioctl_common_function_reset {
1702         struct mbx_hdr hdr;
1703 };
1704
1705 /* [80] OPCODE_COMMON_FUNCTION_LINK_CONFIG */
1706 struct mbx_common_func_link_cfg {
1707         struct mbx_hdr hdr;
1708         union {
1709                 struct {
1710                         uint32_t enable;
1711                 } req;
1712                 struct {
1713                         uint32_t rsvd0;
1714                 } rsp;
1715         } params;
1716 };
1717
1718 /* [103] OPCODE_COMMON_SET_FUNCTIONAL_CAPS */
1719 #define CAP_SW_TIMESTAMPS       2
1720 #define CAP_BE3_NATIVE_ERX_API  4
1721
1722 struct mbx_common_set_function_cap {
1723         struct mbx_hdr hdr;
1724         union {
1725                 struct {
1726                         uint32_t valid_capability_flags;
1727                         uint32_t capability_flags;
1728                         uint8_t  sbz[212];
1729                 } req;
1730                 struct {
1731                         uint32_t valid_capability_flags;
1732                         uint32_t capability_flags;
1733                         uint8_t  sbz[212];
1734                 } rsp;
1735         } params;
1736 };
1737 struct mbx_lowlevel_test_loopback_mode {
1738         struct mbx_hdr hdr;
1739         union {
1740                 struct {
1741                         uint32_t loopback_type;
1742                         uint32_t num_pkts;
1743                         uint64_t pattern;
1744                         uint32_t src_port;
1745                         uint32_t dest_port;
1746                         uint32_t pkt_size;
1747                 }req;
1748                 struct {
1749                         uint32_t    status;
1750                         uint32_t    num_txfer;
1751                         uint32_t    num_rx;
1752                         uint32_t    miscomp_off;
1753                         uint32_t    ticks_compl;
1754                 }rsp;
1755         } params;
1756 };
1757
1758 struct mbx_lowlevel_set_loopback_mode {
1759         struct mbx_hdr hdr;
1760         union {
1761                 struct {
1762                         uint8_t src_port;
1763                         uint8_t dest_port;
1764                         uint8_t loopback_type;
1765                         uint8_t loopback_state;
1766                 } req;
1767                 struct {
1768                         uint8_t rsvd0[4];
1769                 } rsp;
1770         } params;
1771 };
1772
1773 struct flash_file_hdr {
1774         uint8_t  sign[52];
1775         uint8_t  ufi_version[4];
1776         uint32_t file_len;
1777         uint32_t cksum;
1778         uint32_t antidote;
1779         uint32_t num_imgs;
1780         uint8_t  build[24];
1781         uint8_t  rsvd[32];
1782 };
1783
1784 struct image_hdr {
1785         uint32_t imageid;
1786         uint32_t imageoffset;
1787         uint32_t imagelength;
1788         uint32_t image_checksum;
1789         uint8_t  image_version[32];
1790 };
1791
1792 struct flash_section_hdr {
1793         uint32_t format_rev;
1794         uint32_t cksum;
1795         uint32_t antidote;
1796         uint32_t num_images;
1797         uint8_t  id_string[128];
1798         uint32_t rsvd[4];
1799 };
1800
1801 struct flash_section_entry {
1802         uint32_t type;
1803         uint32_t offset;
1804         uint32_t pad_size;
1805         uint32_t image_size;
1806         uint32_t cksum;
1807         uint32_t entry_point;
1808         uint32_t rsvd0;
1809         uint32_t rsvd1;
1810         uint8_t  ver_data[32];
1811 };
1812
1813 struct flash_sec_info {
1814         uint8_t cookie[32];
1815         struct  flash_section_hdr fsec_hdr;
1816         struct  flash_section_entry fsec_entry[32];
1817 };
1818
1819
1820 enum LOWLEVEL_SUBSYSTEM_OPCODES {
1821 /* Opcodes used for lowlevel functions common to many subystems.
1822  * Some of these opcodes are used for diagnostic functions only.
1823  * These opcodes use the MBX_SUBSYSTEM_LOWLEVEL subsystem code.
1824  */
1825         OPCODE_LOWLEVEL_TEST_LOOPBACK = 18,
1826         OPCODE_LOWLEVEL_SET_LOOPBACK_MODE = 19,
1827         OPCODE_LOWLEVEL_GET_LOOPBACK_MODE = 20
1828 };
1829
1830 enum LLDP_SUBSYSTEM_OPCODES {
1831 /* Opcodes used for LLDP susbsytem for configuring the LLDP state machines. */
1832         OPCODE_LLDP_GET_CFG = 1,
1833         OPCODE_LLDP_SET_CFG = 2,
1834         OPCODE_LLDP_GET_STATS = 3
1835 };
1836
1837 enum DCBX_SUBSYSTEM_OPCODES {
1838 /* Opcodes used for DCBX. */
1839         OPCODE_DCBX_GET_CFG = 1,
1840         OPCODE_DCBX_SET_CFG = 2,
1841         OPCODE_DCBX_GET_MIB_INFO = 3,
1842         OPCODE_DCBX_GET_DCBX_MODE = 4,
1843         OPCODE_DCBX_SET_MODE = 5
1844 };
1845
1846 enum DMTF_SUBSYSTEM_OPCODES {
1847 /* Opcodes used for DCBX subsystem. */
1848         OPCODE_DMTF_EXEC_CLP_CMD = 1
1849 };
1850
1851 enum DIAG_SUBSYSTEM_OPCODES {
1852 /* Opcodes used for diag functions common to many subsystems. */
1853         OPCODE_DIAG_RUN_DMA_TEST = 1,
1854         OPCODE_DIAG_RUN_MDIO_TEST = 2,
1855         OPCODE_DIAG_RUN_NLB_TEST = 3,
1856         OPCODE_DIAG_RUN_ARM_TIMER_TEST = 4,
1857         OPCODE_DIAG_GET_MAC = 5
1858 };
1859
1860 enum VENDOR_SUBSYSTEM_OPCODES {
1861 /* Opcodes used for Vendor subsystem. */
1862         OPCODE_VENDOR_SLI = 1
1863 };
1864
1865 /* Management Status Codes */
1866 enum MGMT_STATUS_SUCCESS {
1867         MGMT_SUCCESS = 0,
1868         MGMT_FAILED = 1,
1869         MGMT_ILLEGAL_REQUEST = 2,
1870         MGMT_ILLEGAL_FIELD = 3,
1871         MGMT_INSUFFICIENT_BUFFER = 4,
1872         MGMT_UNAUTHORIZED_REQUEST = 5,
1873         MGMT_INVALID_ISNS_ADDRESS = 10,
1874         MGMT_INVALID_IPADDR = 11,
1875         MGMT_INVALID_GATEWAY = 12,
1876         MGMT_INVALID_SUBNETMASK = 13,
1877         MGMT_INVALID_TARGET_IPADDR = 16,
1878         MGMT_TGTTBL_FULL = 20,
1879         MGMT_FLASHROM_SAVE_FAILED = 23,
1880         MGMT_IOCTLHANDLE_ALLOC_FAILED = 27,
1881         MGMT_INVALID_SESSION = 31,
1882         MGMT_INVALID_CONNECTION = 32,
1883         MGMT_BTL_PATH_EXCEEDS_OSM_LIMIT = 33,
1884         MGMT_BTL_TGTID_EXCEEDS_OSM_LIMIT = 34,
1885         MGMT_BTL_PATH_TGTID_OCCUPIED = 35,
1886         MGMT_BTL_NO_FREE_SLOT_PATH = 36,
1887         MGMT_BTL_NO_FREE_SLOT_TGTID = 37,
1888         MGMT_POLL_IOCTL_TIMEOUT = 40,
1889         MGMT_ERROR_ACITISCSI = 41,
1890         MGMT_BUFFER_SIZE_EXCEED_OSM_OR_OS_LIMIT = 43,
1891         MGMT_REBOOT_REQUIRED = 44,
1892         MGMT_INSUFFICIENT_TIMEOUT = 45,
1893         MGMT_IPADDR_NOT_SET = 46,
1894         MGMT_IPADDR_DUP_DETECTED = 47,
1895         MGMT_CANT_REMOVE_LAST_CONNECTION = 48,
1896         MGMT_TARGET_BUSY = 49,
1897         MGMT_TGT_ERR_LISTEN_SOCKET = 50,
1898         MGMT_TGT_ERR_BIND_SOCKET = 51,
1899         MGMT_TGT_ERR_NO_SOCKET = 52,
1900         MGMT_TGT_ERR_ISNS_COMM_FAILED = 55,
1901         MGMT_CANNOT_DELETE_BOOT_TARGET = 56,
1902         MGMT_TGT_PORTAL_MODE_IN_LISTEN = 57,
1903         MGMT_FCF_IN_USE = 58 ,
1904         MGMT_NO_CQE = 59,
1905         MGMT_TARGET_NOT_FOUND = 65,
1906         MGMT_NOT_SUPPORTED = 66,
1907         MGMT_NO_FCF_RECORDS = 67,
1908         MGMT_FEATURE_NOT_SUPPORTED = 68,
1909         MGMT_VPD_FUNCTION_OUT_OF_RANGE = 69,
1910         MGMT_VPD_FUNCTION_TYPE_INCORRECT = 70,
1911         MGMT_INVALID_NON_EMBEDDED_WRB = 71,
1912         MGMT_OOR = 100,
1913         MGMT_INVALID_PD = 101,
1914         MGMT_STATUS_PD_INUSE = 102,
1915         MGMT_INVALID_CQ = 103,
1916         MGMT_INVALID_QP = 104,
1917         MGMT_INVALID_STAG = 105,
1918         MGMT_ORD_EXCEEDS = 106,
1919         MGMT_IRD_EXCEEDS = 107,
1920         MGMT_SENDQ_WQE_EXCEEDS = 108,
1921         MGMT_RECVQ_RQE_EXCEEDS = 109,
1922         MGMT_SGE_SEND_EXCEEDS = 110,
1923         MGMT_SGE_WRITE_EXCEEDS = 111,
1924         MGMT_SGE_RECV_EXCEEDS = 112,
1925         MGMT_INVALID_STATE_CHANGE = 113,
1926         MGMT_MW_BOUND = 114,
1927         MGMT_INVALID_VA = 115,
1928         MGMT_INVALID_LENGTH = 116,
1929         MGMT_INVALID_FBO = 117,
1930         MGMT_INVALID_ACC_RIGHTS = 118,
1931         MGMT_INVALID_PBE_SIZE = 119,
1932         MGMT_INVALID_PBL_ENTRY = 120,
1933         MGMT_INVALID_PBL_OFFSET = 121,
1934         MGMT_ADDR_NON_EXIST = 122,
1935         MGMT_INVALID_VLANID = 123,
1936         MGMT_INVALID_MTU = 124,
1937         MGMT_INVALID_BACKLOG = 125,
1938         MGMT_CONNECTION_INPROGRESS = 126,
1939         MGMT_INVALID_RQE_SIZE = 127,
1940         MGMT_INVALID_RQE_ENTRY = 128
1941 };
1942
1943 /* Additional Management Status Codes */
1944 enum MGMT_ADDI_STATUS {
1945         MGMT_ADDI_NO_STATUS = 0,
1946         MGMT_ADDI_INVALID_IPTYPE = 1,
1947         MGMT_ADDI_TARGET_HANDLE_NOT_FOUND = 9,
1948         MGMT_ADDI_SESSION_HANDLE_NOT_FOUND = 10,
1949         MGMT_ADDI_CONNECTION_HANDLE_NOT_FOUND = 11,
1950         MGMT_ADDI_ACTIVE_SESSIONS_PRESENT = 16,
1951         MGMT_ADDI_SESSION_ALREADY_OPENED = 17,
1952         MGMT_ADDI_SESSION_ALREADY_CLOSED = 18,
1953         MGMT_ADDI_DEST_HOST_UNREACHABLE = 19,
1954         MGMT_ADDI_LOGIN_IN_PROGRESS = 20,
1955         MGMT_ADDI_TCP_CONNECT_FAILED = 21,
1956         MGMT_ADDI_INSUFFICIENT_RESOURCES = 22,
1957         MGMT_ADDI_LINK_DOWN = 23,
1958         MGMT_ADDI_DHCP_ERROR = 24,
1959         MGMT_ADDI_CONNECTION_OFFLOADED = 25,
1960         MGMT_ADDI_CONNECTION_NOT_OFFLOADED = 26,
1961         MGMT_ADDI_CONNECTION_UPLOAD_IN_PROGRESS = 27,
1962         MGMT_ADDI_REQUEST_REJECTED = 28,
1963         MGMT_ADDI_INVALID_SUBSYSTEM = 29,
1964         MGMT_ADDI_INVALID_OPCODE = 30,
1965         MGMT_ADDI_INVALID_MAXCONNECTION_PARAM = 31,
1966         MGMT_ADDI_INVALID_KEY = 32,
1967         MGMT_ADDI_INVALID_DOMAIN = 35,
1968         MGMT_ADDI_LOGIN_INITIATOR_ERROR = 43,
1969         MGMT_ADDI_LOGIN_AUTHENTICATION_ERROR = 44,
1970         MGMT_ADDI_LOGIN_AUTHORIZATION_ERROR = 45,
1971         MGMT_ADDI_LOGIN_NOT_FOUND = 46,
1972         MGMT_ADDI_LOGIN_TARGET_REMOVED = 47,
1973         MGMT_ADDI_LOGIN_UNSUPPORTED_VERSION = 48,
1974         MGMT_ADDI_LOGIN_TOO_MANY_CONNECTIONS = 49,
1975         MGMT_ADDI_LOGIN_MISSING_PARAMETER = 50,
1976         MGMT_ADDI_LOGIN_NO_SESSION_SPANNING = 51,
1977         MGMT_ADDI_LOGIN_SESSION_TYPE_NOT_SUPPORTED = 52,
1978         MGMT_ADDI_LOGIN_SESSION_DOES_NOT_EXIST = 53,
1979         MGMT_ADDI_LOGIN_INVALID_DURING_LOGIN = 54,
1980         MGMT_ADDI_LOGIN_TARGET_ERROR = 55,
1981         MGMT_ADDI_LOGIN_SERVICE_UNAVAILABLE = 56,
1982         MGMT_ADDI_LOGIN_OUT_OF_RESOURCES = 57,
1983         MGMT_ADDI_SAME_CHAP_SECRET = 58,
1984         MGMT_ADDI_INVALID_SECRET_LENGTH = 59,
1985         MGMT_ADDI_DUPLICATE_ENTRY = 60,
1986         MGMT_ADDI_SETTINGS_MODIFIED_REBOOT_REQD = 63,
1987         MGMT_ADDI_INVALID_EXTENDED_TIMEOUT = 64,
1988         MGMT_ADDI_INVALID_INTERFACE_HANDLE = 65,
1989         MGMT_ADDI_ERR_VLAN_ON_DEF_INTERFACE = 66,
1990         MGMT_ADDI_INTERFACE_DOES_NOT_EXIST = 67,
1991         MGMT_ADDI_INTERFACE_ALREADY_EXISTS = 68,
1992         MGMT_ADDI_INVALID_VLAN_RANGE = 69,
1993         MGMT_ADDI_ERR_SET_VLAN = 70,
1994         MGMT_ADDI_ERR_DEL_VLAN = 71,
1995         MGMT_ADDI_CANNOT_DEL_DEF_INTERFACE = 72,
1996         MGMT_ADDI_DHCP_REQ_ALREADY_PENDING = 73,
1997         MGMT_ADDI_TOO_MANY_INTERFACES = 74,
1998         MGMT_ADDI_INVALID_REQUEST = 75
1999 };
2000
2001 enum NIC_SUBSYSTEM_OPCODES {
2002 /**
2003  * @brief NIC Subsystem Opcodes (see Network SLI-4 manual >= Rev4, v21-2)
2004  * These opcodes are used for configuring the Ethernet interfaces.
2005  * These opcodes all use the MBX_SUBSYSTEM_NIC subsystem code.
2006  */
2007         NIC_CONFIG_RSS = 1,
2008         NIC_CONFIG_ACPI = 2,
2009         NIC_CONFIG_PROMISCUOUS = 3,
2010         NIC_GET_STATS = 4,
2011         NIC_CREATE_WQ = 7,
2012         NIC_CREATE_RQ = 8,
2013         NIC_DELETE_WQ = 9,
2014         NIC_DELETE_RQ = 10,
2015         NIC_CONFIG_ACPI_WOL_MAGIC = 12,
2016         NIC_GET_NETWORK_STATS = 13,
2017         NIC_CREATE_HDS_RQ = 16,
2018         NIC_DELETE_HDS_RQ = 17,
2019         NIC_GET_PPORT_STATS = 18,
2020         NIC_GET_VPORT_STATS = 19,
2021         NIC_GET_QUEUE_STATS = 20
2022 };
2023
2024 /* Hash option flags for RSS enable */
2025 enum RSS_ENABLE_FLAGS {
2026         RSS_ENABLE_NONE         = 0x0,  /* (No RSS) */
2027         RSS_ENABLE_IPV4         = 0x1,  /* (IPV4 HASH enabled ) */
2028         RSS_ENABLE_TCP_IPV4     = 0x2,  /* (TCP IPV4 Hash enabled) */
2029         RSS_ENABLE_IPV6         = 0x4,  /* (IPV6 HASH enabled) */
2030         RSS_ENABLE_TCP_IPV6     = 0x8   /* (TCP IPV6 HASH */
2031 };
2032 #define RSS_ENABLE (RSS_ENABLE_IPV4 | RSS_ENABLE_TCP_IPV4)
2033 #define RSS_DISABLE RSS_ENABLE_NONE
2034
2035 /* NIC header WQE */
2036 struct oce_nic_hdr_wqe {
2037         union {
2038                 struct {
2039 #ifdef _BIG_ENDIAN
2040                         /* dw0 */
2041                         uint32_t rsvd0;
2042
2043                         /* dw1 */
2044                         uint32_t last_seg_udp_len:14;
2045                         uint32_t rsvd1:18;
2046
2047                         /* dw2 */
2048                         uint32_t lso_mss:14;
2049                         uint32_t num_wqe:5;
2050                         uint32_t rsvd4:2;
2051                         uint32_t vlan:1;
2052                         uint32_t lso:1;
2053                         uint32_t tcpcs:1;
2054                         uint32_t udpcs:1;
2055                         uint32_t ipcs:1;
2056                         uint32_t rsvd3:1;
2057                         uint32_t rsvd2:1;
2058                         uint32_t forward:1;
2059                         uint32_t crc:1;
2060                         uint32_t event:1;
2061                         uint32_t complete:1;
2062
2063                         /* dw3 */
2064                         uint32_t vlan_tag:16;
2065                         uint32_t total_length:16;
2066 #else
2067                         /* dw0 */
2068                         uint32_t rsvd0;
2069
2070                         /* dw1 */
2071                         uint32_t rsvd1:18;
2072                         uint32_t last_seg_udp_len:14;
2073
2074                         /* dw2 */
2075                         uint32_t complete:1;
2076                         uint32_t event:1;
2077                         uint32_t crc:1;
2078                         uint32_t forward:1;
2079                         uint32_t rsvd2:1;
2080                         uint32_t rsvd3:1;
2081                         uint32_t ipcs:1;
2082                         uint32_t udpcs:1;
2083                         uint32_t tcpcs:1;
2084                         uint32_t lso:1;
2085                         uint32_t vlan:1;
2086                         uint32_t rsvd4:2;
2087                         uint32_t num_wqe:5;
2088                         uint32_t lso_mss:14;
2089
2090                         /* dw3 */
2091                         uint32_t total_length:16;
2092                         uint32_t vlan_tag:16;
2093 #endif
2094                 } s;
2095                 uint32_t dw[4];
2096         } u0;
2097 };
2098
2099 /* NIC fragment WQE */
2100 struct oce_nic_frag_wqe {
2101         union {
2102                 struct {
2103                         /* dw0 */
2104                         uint32_t frag_pa_hi;
2105                         /* dw1 */
2106                         uint32_t frag_pa_lo;
2107                         /* dw2 */
2108                         uint32_t rsvd0;
2109                         uint32_t frag_len;
2110                 } s;
2111                 uint32_t dw[4];
2112         } u0;
2113 };
2114
2115 /* Ethernet Tx Completion Descriptor */
2116 struct oce_nic_tx_cqe {
2117         union {
2118                 struct {
2119 #ifdef _BIG_ENDIAN
2120                         /* dw 0 */
2121                         uint32_t status:4;
2122                         uint32_t rsvd0:8;
2123                         uint32_t port:2;
2124                         uint32_t ct:2;
2125                         uint32_t wqe_index:16;
2126
2127                         /* dw 1 */
2128                         uint32_t rsvd1:5;
2129                         uint32_t cast_enc:2;
2130                         uint32_t lso:1;
2131                         uint32_t nwh_bytes:8;
2132                         uint32_t user_bytes:16;
2133
2134                         /* dw 2 */
2135                         uint32_t rsvd2;
2136
2137                         /* dw 3 */
2138                         uint32_t valid:1;
2139                         uint32_t rsvd3:4;
2140                         uint32_t wq_id:11;
2141                         uint32_t num_pkts:16;
2142 #else
2143                         /* dw 0 */
2144                         uint32_t wqe_index:16;
2145                         uint32_t ct:2;
2146                         uint32_t port:2;
2147                         uint32_t rsvd0:8;
2148                         uint32_t status:4;
2149
2150                         /* dw 1 */
2151                         uint32_t user_bytes:16;
2152                         uint32_t nwh_bytes:8;
2153                         uint32_t lso:1;
2154                         uint32_t cast_enc:2;
2155                         uint32_t rsvd1:5;
2156                         /* dw 2 */
2157                         uint32_t rsvd2;
2158
2159                         /* dw 3 */
2160                         uint32_t num_pkts:16;
2161                         uint32_t wq_id:11;
2162                         uint32_t rsvd3:4;
2163                         uint32_t valid:1;
2164 #endif
2165                 } s;
2166                 uint32_t dw[4];
2167         } u0;
2168 };
2169 #define WQ_CQE_VALID(_cqe)  (_cqe->u0.dw[3])
2170 #define WQ_CQE_INVALIDATE(_cqe)  (_cqe->u0.dw[3] = 0)
2171
2172 /* Receive Queue Entry (RQE) */
2173 struct oce_nic_rqe {
2174         union {
2175                 struct {
2176                         uint32_t frag_pa_hi;
2177                         uint32_t frag_pa_lo;
2178                 } s;
2179                 uint32_t dw[2];
2180         } u0;
2181 };
2182
2183 /* NIC Receive CQE */
2184 struct oce_nic_rx_cqe {
2185         union {
2186                 struct {
2187 #ifdef _BIG_ENDIAN
2188                         /* dw 0 */
2189                         uint32_t ip_options:1;
2190                         uint32_t port:1;
2191                         uint32_t pkt_size:14;
2192                         uint32_t vlan_tag:16;
2193
2194                         /* dw 1 */
2195                         uint32_t num_fragments:3;
2196                         uint32_t switched:1;
2197                         uint32_t ct:2;
2198                         uint32_t frag_index:10;
2199                         uint32_t rsvd0:1;
2200                         uint32_t vlan_tag_present:1;
2201                         uint32_t mac_dst:6;
2202                         uint32_t ip_ver:1;
2203                         uint32_t l4_cksum_pass:1;
2204                         uint32_t ip_cksum_pass:1;
2205                         uint32_t udpframe:1;
2206                         uint32_t tcpframe:1;
2207                         uint32_t ipframe:1;
2208                         uint32_t rss_hp:1;
2209                         uint32_t error:1;
2210
2211                         /* dw 2 */
2212                         uint32_t valid:1;
2213                         uint32_t hds_type:2;
2214                         uint32_t lro_pkt:1;
2215                         uint32_t rsvd4:1;
2216                         uint32_t hds_hdr_size:12;
2217                         uint32_t hds_hdr_frag_index:10;
2218                         uint32_t rss_bank:1;
2219                         uint32_t qnq:1;
2220                         uint32_t pkt_type:2;
2221                         uint32_t rss_flush:1;
2222
2223                         /* dw 3 */
2224                         uint32_t rss_hash_value;
2225 #else
2226                         /* dw 0 */
2227                         uint32_t vlan_tag:16;
2228                         uint32_t pkt_size:14;
2229                         uint32_t port:1;
2230                         uint32_t ip_options:1;
2231                         /* dw 1 */
2232                         uint32_t error:1;
2233                         uint32_t rss_hp:1;
2234                         uint32_t ipframe:1;
2235                         uint32_t tcpframe:1;
2236                         uint32_t udpframe:1;
2237                         uint32_t ip_cksum_pass:1;
2238                         uint32_t l4_cksum_pass:1;
2239                         uint32_t ip_ver:1;
2240                         uint32_t mac_dst:6;
2241                         uint32_t vlan_tag_present:1;
2242                         uint32_t rsvd0:1;
2243                         uint32_t frag_index:10;
2244                         uint32_t ct:2;
2245                         uint32_t switched:1;
2246                         uint32_t num_fragments:3;
2247
2248                         /* dw 2 */
2249                         uint32_t rss_flush:1;
2250                         uint32_t pkt_type:2;
2251                         uint32_t qnq:1;
2252                         uint32_t rss_bank:1;
2253                         uint32_t hds_hdr_frag_index:10;
2254                         uint32_t hds_hdr_size:12;
2255                         uint32_t rsvd4:1;
2256                         uint32_t lro_pkt:1;
2257                         uint32_t hds_type:2;
2258                         uint32_t valid:1;
2259                         /* dw 3 */
2260                         uint32_t rss_hash_value;
2261 #endif
2262                 } s;
2263                 uint32_t dw[4];
2264         } u0;
2265 };
2266 /* NIC Receive CQE_v1 */
2267 struct oce_nic_rx_cqe_v1 {
2268         union {
2269                 struct {
2270 #ifdef _BIG_ENDIAN
2271                         /* dw 0 */
2272                         uint32_t ip_options:1;
2273                         uint32_t vlan_tag_present:1;
2274                         uint32_t pkt_size:14;
2275                         uint32_t vlan_tag:16;
2276
2277                         /* dw 1 */
2278                         uint32_t num_fragments:3;
2279                         uint32_t switched:1;
2280                         uint32_t ct:2;
2281                         uint32_t frag_index:10;
2282                         uint32_t rsvd0:1;
2283                         uint32_t mac_dst:7;
2284                         uint32_t ip_ver:1;
2285                         uint32_t l4_cksum_pass:1;
2286                         uint32_t ip_cksum_pass:1;
2287                         uint32_t udpframe:1;
2288                         uint32_t tcpframe:1;
2289                         uint32_t ipframe:1;
2290                         uint32_t rss_hp:1;
2291                         uint32_t error:1;
2292
2293                         /* dw 2 */
2294                         uint32_t valid:1;
2295                         uint32_t rsvd4:13;
2296                         uint32_t hds_hdr_size:
2297                         uint32_t hds_hdr_frag_index:8;
2298                         uint32_t vlantag:1;
2299                         uint32_t port:2;
2300                         uint32_t rss_bank:1;
2301                         uint32_t qnq:1;
2302                         uint32_t pkt_type:2;
2303                         uint32_t rss_flush:1;
2304
2305                         /* dw 3 */
2306                         uint32_t rss_hash_value;
2307         #else
2308                         /* dw 0 */
2309                         uint32_t vlan_tag:16;
2310                         uint32_t pkt_size:14;
2311                         uint32_t vlan_tag_present:1;
2312                         uint32_t ip_options:1;
2313                         /* dw 1 */
2314                         uint32_t error:1;
2315                         uint32_t rss_hp:1;
2316                         uint32_t ipframe:1;
2317                         uint32_t tcpframe:1;
2318                         uint32_t udpframe:1;
2319                         uint32_t ip_cksum_pass:1;
2320                         uint32_t l4_cksum_pass:1;
2321                         uint32_t ip_ver:1;
2322                         uint32_t mac_dst:7;
2323                         uint32_t rsvd0:1;
2324                         uint32_t frag_index:10;
2325                         uint32_t ct:2;
2326                         uint32_t switched:1;
2327                         uint32_t num_fragments:3;
2328
2329                         /* dw 2 */
2330                         uint32_t rss_flush:1;
2331                         uint32_t pkt_type:2;
2332                         uint32_t qnq:1;
2333                         uint32_t rss_bank:1;
2334                         uint32_t port:2;
2335                         uint32_t vlantag:1;
2336                         uint32_t hds_hdr_frag_index:8;
2337                         uint32_t hds_hdr_size:2;
2338                         uint32_t rsvd4:13;
2339                         uint32_t valid:1;
2340                         /* dw 3 */
2341                         uint32_t rss_hash_value;
2342 #endif
2343                 } s;
2344                 uint32_t dw[4];
2345         } u0;
2346 };
2347
2348 #define RQ_CQE_VALID_MASK  0x80
2349 #define RQ_CQE_VALID(_cqe) (_cqe->u0.dw[2])
2350 #define RQ_CQE_INVALIDATE(_cqe) (_cqe->u0.dw[2] = 0)
2351
2352 struct mbx_config_nic_promiscuous {
2353         struct mbx_hdr hdr;
2354         union {
2355                 struct {
2356 #ifdef _BIG_ENDIAN
2357                         uint16_t rsvd0;
2358                         uint8_t port1_promisc;
2359                         uint8_t port0_promisc;
2360 #else
2361                         uint8_t port0_promisc;
2362                         uint8_t port1_promisc;
2363                         uint16_t rsvd0;
2364 #endif
2365                 } req;
2366
2367                 struct {
2368                         uint32_t rsvd0;
2369                 } rsp;
2370         } params;
2371 };
2372
2373 typedef union oce_wq_ctx_u {
2374                 uint32_t dw[17];
2375                 struct {
2376 #ifdef _BIG_ENDIAN
2377                         /* dw4 */
2378                         uint32_t dw4rsvd2:8;
2379                         uint32_t nic_wq_type:8;
2380                         uint32_t dw4rsvd1:8;
2381                         uint32_t num_pages:8;
2382                         /* dw5 */
2383                         uint32_t dw5rsvd2:12;
2384                         uint32_t wq_size:4;
2385                         uint32_t dw5rsvd1:16;
2386                         /* dw6 */
2387                         uint32_t valid:1;
2388                         uint32_t dw6rsvd1:31;
2389                         /* dw7 */
2390                         uint32_t dw7rsvd1:16;
2391                         uint32_t cq_id:16;
2392 #else
2393                         /* dw4 */
2394                         uint32_t num_pages:8;
2395 #if 0
2396                         uint32_t dw4rsvd1:8;
2397 #else
2398 /* PSP: this workaround is not documented: fill 0x01 for ulp_mask */
2399                         uint32_t ulp_mask:8;
2400 #endif
2401                         uint32_t nic_wq_type:8;
2402                         uint32_t dw4rsvd2:8;
2403                         /* dw5 */
2404                         uint32_t dw5rsvd1:16;
2405                         uint32_t wq_size:4;
2406                         uint32_t dw5rsvd2:12;
2407                         /* dw6 */
2408                         uint32_t dw6rsvd1:31;
2409                         uint32_t valid:1;
2410                         /* dw7 */
2411                         uint32_t cq_id:16;
2412                         uint32_t dw7rsvd1:16;
2413 #endif
2414                         /* dw8 - dw20 */
2415                         uint32_t dw8_20rsvd1[13];
2416                 } v0;
2417                 struct {
2418 #ifdef _BIG_ENDIAN
2419                         /* dw4 */
2420                         uint32_t dw4rsvd2:8;
2421                         uint32_t nic_wq_type:8;
2422                         uint32_t dw4rsvd1:8;
2423                         uint32_t num_pages:8;
2424                         /* dw5 */
2425                         uint32_t dw5rsvd2:12;
2426                         uint32_t wq_size:4;
2427                         uint32_t iface_id:16;
2428                         /* dw6 */
2429                         uint32_t valid:1;
2430                         uint32_t dw6rsvd1:31;
2431                         /* dw7 */
2432                         uint32_t dw7rsvd1:16;
2433                         uint32_t cq_id:16;
2434 #else
2435                         /* dw4 */
2436                         uint32_t num_pages:8;
2437                         uint32_t dw4rsvd1:8;
2438                         uint32_t nic_wq_type:8;
2439                         uint32_t dw4rsvd2:8;
2440                         /* dw5 */
2441                         uint32_t iface_id:16;
2442                         uint32_t wq_size:4;
2443                         uint32_t dw5rsvd2:12;
2444                         /* dw6 */
2445                         uint32_t dw6rsvd1:31;
2446                         uint32_t valid:1;
2447                         /* dw7 */
2448                         uint32_t cq_id:16;
2449                         uint32_t dw7rsvd1:16;
2450 #endif
2451                         /* dw8 - dw20 */
2452                         uint32_t dw8_20rsvd1[13];
2453                 } v1;
2454 } oce_wq_ctx_t;
2455
2456 /**
2457  * @brief [07] NIC_CREATE_WQ
2458  * @note
2459  * Lancer requires an InterfaceID to be specified with every WQ. This
2460  * is the basis for NIC IOV where the Interface maps to a vPort and maps
2461  * to both Tx and Rx sides.
2462  */
2463 #define OCE_WQ_TYPE_FORWARDING  0x1     /* wq forwards pkts to TOE */
2464 #define OCE_WQ_TYPE_STANDARD    0x2     /* wq sends network pkts */
2465 struct mbx_create_nic_wq {
2466         struct mbx_hdr hdr;
2467         union {
2468                 struct {
2469                         uint8_t num_pages;
2470                         uint8_t ulp_num;
2471                         uint16_t nic_wq_type;
2472                         uint16_t if_id;
2473                         uint8_t wq_size;
2474                         uint8_t rsvd1;
2475                         uint32_t rsvd2;
2476                         uint16_t cq_id;
2477                         uint16_t rsvd3;
2478                         uint32_t rsvd4[13];
2479                         struct phys_addr pages[8];
2480
2481                 } req;
2482
2483                 struct {
2484                         uint16_t wq_id;
2485                         uint16_t rid;
2486                         uint32_t db_offset;
2487                         uint8_t tc_id;
2488                         uint8_t rsvd0[3];
2489                 } rsp;
2490         } params;
2491 };
2492
2493 /* [09] NIC_DELETE_WQ */
2494 struct mbx_delete_nic_wq {
2495         /* dw0 - dw3 */
2496         struct mbx_hdr hdr;
2497         union {
2498                 struct {
2499 #ifdef _BIG_ENDIAN
2500                         /* dw4 */
2501                         uint16_t rsvd0;
2502                         uint16_t wq_id;
2503 #else
2504                         /* dw4 */
2505                         uint16_t wq_id;
2506                         uint16_t rsvd0;
2507 #endif
2508                 } req;
2509                 struct {
2510                         uint32_t rsvd0;
2511                 } rsp;
2512         } params;
2513 };
2514
2515
2516
2517 struct mbx_create_nic_rq {
2518         struct mbx_hdr hdr;
2519         union {
2520                 struct {
2521                         uint16_t cq_id;
2522                         uint8_t frag_size;
2523                         uint8_t num_pages;
2524                         struct phys_addr pages[2];
2525                         uint32_t if_id;
2526                         uint16_t max_frame_size;
2527                         uint16_t page_size;
2528                         uint32_t is_rss_queue;
2529                 } req;
2530
2531                 struct {
2532                         uint16_t rq_id;
2533                         uint8_t rss_cpuid;
2534                         uint8_t rsvd0;
2535                 } rsp;
2536
2537         } params;
2538 };
2539
2540
2541
2542 /* [10] NIC_DELETE_RQ */
2543 struct mbx_delete_nic_rq {
2544         /* dw0 - dw3 */
2545         struct mbx_hdr hdr;
2546         union {
2547                 struct {
2548 #ifdef _BIG_ENDIAN
2549                         /* dw4 */
2550                         uint16_t bypass_flush;
2551                         uint16_t rq_id;
2552 #else
2553                         /* dw4 */
2554                         uint16_t rq_id;
2555                         uint16_t bypass_flush;
2556 #endif
2557                 } req;
2558
2559                 struct {
2560                         /* dw4 */
2561                         uint32_t rsvd0;
2562                 } rsp;
2563         } params;
2564 };
2565
2566
2567
2568
2569 struct oce_port_rxf_stats_v0 {
2570         uint32_t rx_bytes_lsd;                  /* dword 0*/
2571         uint32_t rx_bytes_msd;                  /* dword 1*/
2572         uint32_t rx_total_frames;               /* dword 2*/
2573         uint32_t rx_unicast_frames;             /* dword 3*/
2574         uint32_t rx_multicast_frames;           /* dword 4*/
2575         uint32_t rx_broadcast_frames;           /* dword 5*/
2576         uint32_t rx_crc_errors;                 /* dword 6*/
2577         uint32_t rx_alignment_symbol_errors;    /* dword 7*/
2578         uint32_t rx_pause_frames;               /* dword 8*/
2579         uint32_t rx_control_frames;             /* dword 9*/
2580         uint32_t rx_in_range_errors;            /* dword 10*/
2581         uint32_t rx_out_range_errors;           /* dword 11*/
2582         uint32_t rx_frame_too_long;             /* dword 12*/
2583         uint32_t rx_address_match_errors;       /* dword 13*/
2584         uint32_t rx_vlan_mismatch;              /* dword 14*/
2585         uint32_t rx_dropped_too_small;          /* dword 15*/
2586         uint32_t rx_dropped_too_short;          /* dword 16*/
2587         uint32_t rx_dropped_header_too_small;   /* dword 17*/
2588         uint32_t rx_dropped_tcp_length;         /* dword 18*/
2589         uint32_t rx_dropped_runt;               /* dword 19*/
2590         uint32_t rx_64_byte_packets;            /* dword 20*/
2591         uint32_t rx_65_127_byte_packets;        /* dword 21*/
2592         uint32_t rx_128_256_byte_packets;       /* dword 22*/
2593         uint32_t rx_256_511_byte_packets;       /* dword 23*/
2594         uint32_t rx_512_1023_byte_packets;      /* dword 24*/
2595         uint32_t rx_1024_1518_byte_packets;     /* dword 25*/
2596         uint32_t rx_1519_2047_byte_packets;     /* dword 26*/
2597         uint32_t rx_2048_4095_byte_packets;     /* dword 27*/
2598         uint32_t rx_4096_8191_byte_packets;     /* dword 28*/
2599         uint32_t rx_8192_9216_byte_packets;     /* dword 29*/
2600         uint32_t rx_ip_checksum_errs;           /* dword 30*/
2601         uint32_t rx_tcp_checksum_errs;          /* dword 31*/
2602         uint32_t rx_udp_checksum_errs;          /* dword 32*/
2603         uint32_t rx_non_rss_packets;            /* dword 33*/
2604         uint32_t rx_ipv4_packets;               /* dword 34*/
2605         uint32_t rx_ipv6_packets;               /* dword 35*/
2606         uint32_t rx_ipv4_bytes_lsd;             /* dword 36*/
2607         uint32_t rx_ipv4_bytes_msd;             /* dword 37*/
2608         uint32_t rx_ipv6_bytes_lsd;             /* dword 38*/
2609         uint32_t rx_ipv6_bytes_msd;             /* dword 39*/
2610         uint32_t rx_chute1_packets;             /* dword 40*/
2611         uint32_t rx_chute2_packets;             /* dword 41*/
2612         uint32_t rx_chute3_packets;             /* dword 42*/
2613         uint32_t rx_management_packets;         /* dword 43*/
2614         uint32_t rx_switched_unicast_packets;   /* dword 44*/
2615         uint32_t rx_switched_multicast_packets; /* dword 45*/
2616         uint32_t rx_switched_broadcast_packets; /* dword 46*/
2617         uint32_t tx_bytes_lsd;                  /* dword 47*/
2618         uint32_t tx_bytes_msd;                  /* dword 48*/
2619         uint32_t tx_unicastframes;              /* dword 49*/
2620         uint32_t tx_multicastframes;            /* dword 50*/
2621         uint32_t tx_broadcastframes;            /* dword 51*/
2622         uint32_t tx_pauseframes;                /* dword 52*/
2623         uint32_t tx_controlframes;              /* dword 53*/
2624         uint32_t tx_64_byte_packets;            /* dword 54*/
2625         uint32_t tx_65_127_byte_packets;        /* dword 55*/
2626         uint32_t tx_128_256_byte_packets;       /* dword 56*/
2627         uint32_t tx_256_511_byte_packets;       /* dword 57*/
2628         uint32_t tx_512_1023_byte_packets;      /* dword 58*/
2629         uint32_t tx_1024_1518_byte_packets;     /* dword 59*/
2630         uint32_t tx_1519_2047_byte_packets;     /* dword 60*/
2631         uint32_t tx_2048_4095_byte_packets;     /* dword 61*/
2632         uint32_t tx_4096_8191_byte_packets;     /* dword 62*/
2633         uint32_t tx_8192_9216_byte_packets;     /* dword 63*/
2634         uint32_t rxpp_fifo_overflow_drop;       /* dword 64*/
2635         uint32_t rx_input_fifo_overflow_drop;   /* dword 65*/
2636 };
2637
2638
2639 struct oce_rxf_stats_v0 {
2640         struct oce_port_rxf_stats_v0 port[2];
2641         uint32_t rx_drops_no_pbuf;              /* dword 132*/
2642         uint32_t rx_drops_no_txpb;              /* dword 133*/
2643         uint32_t rx_drops_no_erx_descr;         /* dword 134*/
2644         uint32_t rx_drops_no_tpre_descr;        /* dword 135*/
2645         uint32_t management_rx_port_packets;    /* dword 136*/
2646         uint32_t management_rx_port_bytes;      /* dword 137*/
2647         uint32_t management_rx_port_pause_frames;/* dword 138*/
2648         uint32_t management_rx_port_errors;     /* dword 139*/
2649         uint32_t management_tx_port_packets;    /* dword 140*/
2650         uint32_t management_tx_port_bytes;      /* dword 141*/
2651         uint32_t management_tx_port_pause;      /* dword 142*/
2652         uint32_t management_rx_port_rxfifo_overflow; /* dword 143*/
2653         uint32_t rx_drops_too_many_frags;       /* dword 144*/
2654         uint32_t rx_drops_invalid_ring;         /* dword 145*/
2655         uint32_t forwarded_packets;             /* dword 146*/
2656         uint32_t rx_drops_mtu;                  /* dword 147*/
2657         uint32_t rsvd0[7];
2658         uint32_t port0_jabber_events;
2659         uint32_t port1_jabber_events;
2660         uint32_t rsvd1[6];
2661 };
2662
2663 struct oce_port_rxf_stats_v1 {
2664         uint32_t rsvd0[12];
2665         uint32_t rx_crc_errors;
2666         uint32_t rx_alignment_symbol_errors;
2667         uint32_t rx_pause_frames;
2668         uint32_t rx_priority_pause_frames;
2669         uint32_t rx_control_frames;
2670         uint32_t rx_in_range_errors;
2671         uint32_t rx_out_range_errors;
2672         uint32_t rx_frame_too_long;
2673         uint32_t rx_address_match_errors;
2674         uint32_t rx_dropped_too_small;
2675         uint32_t rx_dropped_too_short;
2676         uint32_t rx_dropped_header_too_small;
2677         uint32_t rx_dropped_tcp_length;
2678         uint32_t rx_dropped_runt;
2679         uint32_t rsvd1[10];
2680         uint32_t rx_ip_checksum_errs;
2681         uint32_t rx_tcp_checksum_errs;
2682         uint32_t rx_udp_checksum_errs;
2683         uint32_t rsvd2[7];
2684         uint32_t rx_switched_unicast_packets;
2685         uint32_t rx_switched_multicast_packets;
2686         uint32_t rx_switched_broadcast_packets;
2687         uint32_t rsvd3[3];
2688         uint32_t tx_pauseframes;
2689         uint32_t tx_priority_pauseframes;
2690         uint32_t tx_controlframes;
2691         uint32_t rsvd4[10];
2692         uint32_t rxpp_fifo_overflow_drop;
2693         uint32_t rx_input_fifo_overflow_drop;
2694         uint32_t pmem_fifo_overflow_drop;
2695         uint32_t jabber_events;
2696         uint32_t rsvd5[3];
2697 };
2698
2699
2700 struct oce_rxf_stats_v1 {
2701         struct oce_port_rxf_stats_v1 port[4];
2702         uint32_t rsvd0[2];
2703         uint32_t rx_drops_no_pbuf;
2704         uint32_t rx_drops_no_txpb;
2705         uint32_t rx_drops_no_erx_descr;
2706         uint32_t rx_drops_no_tpre_descr;
2707         uint32_t rsvd1[6];
2708         uint32_t rx_drops_too_many_frags;
2709         uint32_t rx_drops_invalid_ring;
2710         uint32_t forwarded_packets;
2711         uint32_t rx_drops_mtu;
2712         uint32_t rsvd2[14];
2713 };
2714
2715 struct oce_erx_stats_v1 {
2716         uint32_t rx_drops_no_fragments[68];
2717         uint32_t rsvd[4];
2718 };
2719
2720
2721 struct oce_erx_stats_v0 {
2722         uint32_t rx_drops_no_fragments[44];
2723         uint32_t rsvd[4];
2724 };
2725
2726 struct oce_pmem_stats {
2727         uint32_t eth_red_drops;
2728         uint32_t rsvd[5];
2729 };
2730
2731 struct oce_hw_stats_v1 {
2732         struct oce_rxf_stats_v1 rxf;
2733         uint32_t rsvd0[OCE_TXP_SW_SZ];
2734         struct oce_erx_stats_v1 erx;
2735         struct oce_pmem_stats pmem;
2736         uint32_t rsvd1[18];
2737 };
2738
2739 struct oce_hw_stats_v0 {
2740         struct oce_rxf_stats_v0 rxf;
2741         uint32_t rsvd[48];
2742         struct oce_erx_stats_v0 erx;
2743         struct oce_pmem_stats pmem;
2744 };
2745
2746 struct mbx_get_nic_stats_v0 {
2747         struct mbx_hdr hdr;
2748         union {
2749                 struct {
2750                         uint32_t rsvd0;
2751                 } req;
2752
2753                 union {
2754                         struct oce_hw_stats_v0 stats;
2755                 } rsp;
2756         } params;
2757 };
2758
2759 struct mbx_get_nic_stats {
2760         struct mbx_hdr hdr;
2761         union {
2762                 struct {
2763                         uint32_t rsvd0;
2764                 } req;
2765
2766                 struct {
2767                         struct oce_hw_stats_v1 stats;
2768                 } rsp;
2769         } params;
2770 };
2771
2772
2773 /* [18(0x12)] NIC_GET_PPORT_STATS */
2774 struct pport_stats {
2775         uint64_t tx_pkts;
2776         uint64_t tx_unicast_pkts;
2777         uint64_t tx_multicast_pkts;
2778         uint64_t tx_broadcast_pkts;
2779         uint64_t tx_bytes;
2780         uint64_t tx_unicast_bytes;
2781         uint64_t tx_multicast_bytes;
2782         uint64_t tx_broadcast_bytes;
2783         uint64_t tx_discards;
2784         uint64_t tx_errors;
2785         uint64_t tx_pause_frames;
2786         uint64_t tx_pause_on_frames;
2787         uint64_t tx_pause_off_frames;
2788         uint64_t tx_internal_mac_errors;
2789         uint64_t tx_control_frames;
2790         uint64_t tx_pkts_64_bytes;
2791         uint64_t tx_pkts_65_to_127_bytes;
2792         uint64_t tx_pkts_128_to_255_bytes;
2793         uint64_t tx_pkts_256_to_511_bytes;
2794         uint64_t tx_pkts_512_to_1023_bytes;
2795         uint64_t tx_pkts_1024_to_1518_bytes;
2796         uint64_t tx_pkts_1519_to_2047_bytes;
2797         uint64_t tx_pkts_2048_to_4095_bytes;
2798         uint64_t tx_pkts_4096_to_8191_bytes;
2799         uint64_t tx_pkts_8192_to_9216_bytes;
2800         uint64_t tx_lso_pkts;
2801         uint64_t rx_pkts;
2802         uint64_t rx_unicast_pkts;
2803         uint64_t rx_multicast_pkts;
2804         uint64_t rx_broadcast_pkts;
2805         uint64_t rx_bytes;
2806         uint64_t rx_unicast_bytes;
2807         uint64_t rx_multicast_bytes;
2808         uint64_t rx_broadcast_bytes;
2809         uint32_t rx_unknown_protos;
2810         uint32_t reserved_word69;
2811         uint64_t rx_discards;
2812         uint64_t rx_errors;
2813         uint64_t rx_crc_errors;
2814         uint64_t rx_alignment_errors;
2815         uint64_t rx_symbol_errors;
2816         uint64_t rx_pause_frames;
2817         uint64_t rx_pause_on_frames;
2818         uint64_t rx_pause_off_frames;
2819         uint64_t rx_frames_too_long;
2820         uint64_t rx_internal_mac_errors;
2821         uint32_t rx_undersize_pkts;
2822         uint32_t rx_oversize_pkts;
2823         uint32_t rx_fragment_pkts;
2824         uint32_t rx_jabbers;
2825         uint64_t rx_control_frames;
2826         uint64_t rx_control_frames_unknown_opcode;
2827         uint32_t rx_in_range_errors;
2828         uint32_t rx_out_of_range_errors;
2829         uint32_t rx_address_match_errors;
2830         uint32_t rx_vlan_mismatch_errors;
2831         uint32_t rx_dropped_too_small;
2832         uint32_t rx_dropped_too_short;
2833         uint32_t rx_dropped_header_too_small;
2834         uint32_t rx_dropped_invalid_tcp_length;
2835         uint32_t rx_dropped_runt;
2836         uint32_t rx_ip_checksum_errors;
2837         uint32_t rx_tcp_checksum_errors;
2838         uint32_t rx_udp_checksum_errors;
2839         uint32_t rx_non_rss_pkts;
2840         uint64_t reserved_word111;
2841         uint64_t rx_ipv4_pkts;
2842         uint64_t rx_ipv6_pkts;
2843         uint64_t rx_ipv4_bytes;
2844         uint64_t rx_ipv6_bytes;
2845         uint64_t rx_nic_pkts;
2846         uint64_t rx_tcp_pkts;
2847         uint64_t rx_iscsi_pkts;
2848         uint64_t rx_management_pkts;
2849         uint64_t rx_switched_unicast_pkts;
2850         uint64_t rx_switched_multicast_pkts;
2851         uint64_t rx_switched_broadcast_pkts;
2852         uint64_t num_forwards;
2853         uint32_t rx_fifo_overflow;
2854         uint32_t rx_input_fifo_overflow;
2855         uint64_t rx_drops_too_many_frags;
2856         uint32_t rx_drops_invalid_queue;
2857         uint32_t reserved_word141;
2858         uint64_t rx_drops_mtu;
2859         uint64_t rx_pkts_64_bytes;
2860         uint64_t rx_pkts_65_to_127_bytes;
2861         uint64_t rx_pkts_128_to_255_bytes;
2862         uint64_t rx_pkts_256_to_511_bytes;
2863         uint64_t rx_pkts_512_to_1023_bytes;
2864         uint64_t rx_pkts_1024_to_1518_bytes;
2865         uint64_t rx_pkts_1519_to_2047_bytes;
2866         uint64_t rx_pkts_2048_to_4095_bytes;
2867         uint64_t rx_pkts_4096_to_8191_bytes;
2868         uint64_t rx_pkts_8192_to_9216_bytes;
2869 };
2870
2871 struct mbx_get_pport_stats {
2872         /* dw0 - dw3 */
2873         struct mbx_hdr hdr;
2874         union {
2875                 struct {
2876                         /* dw4 */
2877 #ifdef _BIG_ENDIAN
2878                         uint32_t reset_stats:8;
2879                         uint32_t rsvd0:8;
2880                         uint32_t port_number:16;
2881 #else
2882                         uint32_t port_number:16;
2883                         uint32_t rsvd0:8;
2884                         uint32_t reset_stats:8;
2885 #endif
2886                 } req;
2887
2888                 union {
2889                         struct pport_stats pps;
2890                         uint32_t pport_stats[164 - 4 + 1];
2891                 } rsp;
2892         } params;
2893 };
2894
2895 /* [19(0x13)] NIC_GET_VPORT_STATS */
2896 struct vport_stats {
2897         uint64_t tx_pkts;
2898         uint64_t tx_unicast_pkts;
2899         uint64_t tx_multicast_pkts;
2900         uint64_t tx_broadcast_pkts;
2901         uint64_t tx_bytes;
2902         uint64_t tx_unicast_bytes;
2903         uint64_t tx_multicast_bytes;
2904         uint64_t tx_broadcast_bytes;
2905         uint64_t tx_discards;
2906         uint64_t tx_errors;
2907         uint64_t tx_pkts_64_bytes;
2908         uint64_t tx_pkts_65_to_127_bytes;
2909         uint64_t tx_pkts_128_to_255_bytes;
2910         uint64_t tx_pkts_256_to_511_bytes;
2911         uint64_t tx_pkts_512_to_1023_bytes;
2912         uint64_t tx_pkts_1024_to_1518_bytes;
2913         uint64_t tx_pkts_1519_to_9699_bytes;
2914         uint64_t tx_pkts_over_9699_bytes;
2915         uint64_t rx_pkts;
2916         uint64_t rx_unicast_pkts;
2917         uint64_t rx_multicast_pkts;
2918         uint64_t rx_broadcast_pkts;
2919         uint64_t rx_bytes;
2920         uint64_t rx_unicast_bytes;
2921         uint64_t rx_multicast_bytes;
2922         uint64_t rx_broadcast_bytes;
2923         uint64_t rx_discards;
2924         uint64_t rx_errors;
2925         uint64_t rx_pkts_64_bytes;
2926         uint64_t rx_pkts_65_to_127_bytes;
2927         uint64_t rx_pkts_128_to_255_bytes;
2928         uint64_t rx_pkts_256_to_511_bytes;
2929         uint64_t rx_pkts_512_to_1023_bytes;
2930         uint64_t rx_pkts_1024_to_1518_bytes;
2931         uint64_t rx_pkts_1519_to_9699_bytes;
2932         uint64_t rx_pkts_gt_9699_bytes;
2933 };
2934 struct mbx_get_vport_stats {
2935         /* dw0 - dw3 */
2936         struct mbx_hdr hdr;
2937         union {
2938                 struct {
2939                         /* dw4 */
2940 #ifdef _BIG_ENDIAN
2941                         uint32_t reset_stats:8;
2942                         uint32_t rsvd0:8;
2943                         uint32_t vport_number:16;
2944 #else
2945                         uint32_t vport_number:16;
2946                         uint32_t rsvd0:8;
2947                         uint32_t reset_stats:8;
2948 #endif
2949                 } req;
2950
2951                 union {
2952                         struct vport_stats vps;
2953                         uint32_t vport_stats[75 - 4 + 1];
2954                 } rsp;
2955         } params;
2956 };
2957
2958 /**
2959  * @brief       [20(0x14)] NIC_GET_QUEUE_STATS
2960  * The significant difference between vPort and Queue statistics is
2961  * the packet byte counters.
2962  */
2963 struct queue_stats {
2964         uint64_t packets;
2965         uint64_t bytes;
2966         uint64_t errors;
2967         uint64_t drops;
2968         uint64_t buffer_errors;         /* rsvd when tx */
2969 };
2970
2971 #define QUEUE_TYPE_WQ           0
2972 #define QUEUE_TYPE_RQ           1
2973 #define QUEUE_TYPE_HDS_RQ       1       /* same as RQ */
2974
2975 struct mbx_get_queue_stats {
2976         /* dw0 - dw3 */
2977         struct mbx_hdr hdr;
2978         union {
2979                 struct {
2980                         /* dw4 */
2981 #ifdef _BIG_ENDIAN
2982                         uint32_t reset_stats:8;
2983                         uint32_t queue_type:8;
2984                         uint32_t queue_id:16;
2985 #else
2986                         uint32_t queue_id:16;
2987                         uint32_t queue_type:8;
2988                         uint32_t reset_stats:8;
2989 #endif
2990                 } req;
2991
2992                 union {
2993                         struct queue_stats qs;
2994                         uint32_t queue_stats[13 - 4 + 1];
2995                 } rsp;
2996         } params;
2997 };
2998
2999
3000 /* [01] NIC_CONFIG_RSS */
3001 #define OCE_HASH_TBL_SZ 10
3002 #define OCE_CPU_TBL_SZ  128
3003 #define OCE_FLUSH       1       /* RSS flush completion per CQ port */
3004 struct mbx_config_nic_rss {
3005         struct mbx_hdr hdr;
3006         union {
3007                 struct {
3008 #ifdef _BIG_ENDIAN
3009                         uint32_t if_id;
3010                         uint16_t cpu_tbl_sz_log2;
3011                         uint16_t enable_rss;
3012                         uint32_t hash[OCE_HASH_TBL_SZ];
3013                         uint8_t cputable[OCE_CPU_TBL_SZ];
3014                         uint8_t rsvd[3];
3015                         uint8_t flush;
3016 #else
3017                         uint32_t if_id;
3018                         uint16_t enable_rss;
3019                         uint16_t cpu_tbl_sz_log2;
3020                         uint32_t hash[OCE_HASH_TBL_SZ];
3021                         uint8_t cputable[OCE_CPU_TBL_SZ];
3022                         uint8_t flush;
3023                         uint8_t rsvd[3];
3024 #endif
3025                 } req;
3026                 struct {
3027                         uint8_t rsvd[3];
3028                         uint8_t rss_bank;
3029                 } rsp;
3030         } params;
3031 };
3032
3033
3034 #pragma pack()
3035
3036
3037 typedef uint32_t oce_stat_t;            /* statistic counter */
3038
3039 enum OCE_RXF_PORT_STATS {
3040         RXF_RX_BYTES_LSD,
3041         RXF_RX_BYTES_MSD,
3042         RXF_RX_TOTAL_FRAMES,
3043         RXF_RX_UNICAST_FRAMES,
3044         RXF_RX_MULTICAST_FRAMES,
3045         RXF_RX_BROADCAST_FRAMES,
3046         RXF_RX_CRC_ERRORS,
3047         RXF_RX_ALIGNMENT_SYMBOL_ERRORS,
3048         RXF_RX_PAUSE_FRAMES,
3049         RXF_RX_CONTROL_FRAMES,
3050         RXF_RX_IN_RANGE_ERRORS,
3051         RXF_RX_OUT_RANGE_ERRORS,
3052         RXF_RX_FRAME_TOO_LONG,
3053         RXF_RX_ADDRESS_MATCH_ERRORS,
3054         RXF_RX_VLAN_MISMATCH,
3055         RXF_RX_DROPPED_TOO_SMALL,
3056         RXF_RX_DROPPED_TOO_SHORT,
3057         RXF_RX_DROPPED_HEADER_TOO_SMALL,
3058         RXF_RX_DROPPED_TCP_LENGTH,
3059         RXF_RX_DROPPED_RUNT,
3060         RXF_RX_64_BYTE_PACKETS,
3061         RXF_RX_65_127_BYTE_PACKETS,
3062         RXF_RX_128_256_BYTE_PACKETS,
3063         RXF_RX_256_511_BYTE_PACKETS,
3064         RXF_RX_512_1023_BYTE_PACKETS,
3065         RXF_RX_1024_1518_BYTE_PACKETS,
3066         RXF_RX_1519_2047_BYTE_PACKETS,
3067         RXF_RX_2048_4095_BYTE_PACKETS,
3068         RXF_RX_4096_8191_BYTE_PACKETS,
3069         RXF_RX_8192_9216_BYTE_PACKETS,
3070         RXF_RX_IP_CHECKSUM_ERRS,
3071         RXF_RX_TCP_CHECKSUM_ERRS,
3072         RXF_RX_UDP_CHECKSUM_ERRS,
3073         RXF_RX_NON_RSS_PACKETS,
3074         RXF_RX_IPV4_PACKETS,
3075         RXF_RX_IPV6_PACKETS,
3076         RXF_RX_IPV4_BYTES_LSD,
3077         RXF_RX_IPV4_BYTES_MSD,
3078         RXF_RX_IPV6_BYTES_LSD,
3079         RXF_RX_IPV6_BYTES_MSD,
3080         RXF_RX_CHUTE1_PACKETS,
3081         RXF_RX_CHUTE2_PACKETS,
3082         RXF_RX_CHUTE3_PACKETS,
3083         RXF_RX_MANAGEMENT_PACKETS,
3084         RXF_RX_SWITCHED_UNICAST_PACKETS,
3085         RXF_RX_SWITCHED_MULTICAST_PACKETS,
3086         RXF_RX_SWITCHED_BROADCAST_PACKETS,
3087         RXF_TX_BYTES_LSD,
3088         RXF_TX_BYTES_MSD,
3089         RXF_TX_UNICAST_FRAMES,
3090         RXF_TX_MULTICAST_FRAMES,
3091         RXF_TX_BROADCAST_FRAMES,
3092         RXF_TX_PAUSE_FRAMES,
3093         RXF_TX_CONTROL_FRAMES,
3094         RXF_TX_64_BYTE_PACKETS,
3095         RXF_TX_65_127_BYTE_PACKETS,
3096         RXF_TX_128_256_BYTE_PACKETS,
3097         RXF_TX_256_511_BYTE_PACKETS,
3098         RXF_TX_512_1023_BYTE_PACKETS,
3099         RXF_TX_1024_1518_BYTE_PACKETS,
3100         RXF_TX_1519_2047_BYTE_PACKETS,
3101         RXF_TX_2048_4095_BYTE_PACKETS,
3102         RXF_TX_4096_8191_BYTE_PACKETS,
3103         RXF_TX_8192_9216_BYTE_PACKETS,
3104         RXF_RX_FIFO_OVERFLOW,
3105         RXF_RX_INPUT_FIFO_OVERFLOW,
3106         RXF_PORT_STATS_N_WORDS
3107 };
3108
3109 enum OCE_RXF_ADDL_STATS {
3110         RXF_RX_DROPS_NO_PBUF,
3111         RXF_RX_DROPS_NO_TXPB,
3112         RXF_RX_DROPS_NO_ERX_DESCR,
3113         RXF_RX_DROPS_NO_TPRE_DESCR,
3114         RXF_MANAGEMENT_RX_PORT_PACKETS,
3115         RXF_MANAGEMENT_RX_PORT_BYTES,
3116         RXF_MANAGEMENT_RX_PORT_PAUSE_FRAMES,
3117         RXF_MANAGEMENT_RX_PORT_ERRORS,
3118         RXF_MANAGEMENT_TX_PORT_PACKETS,
3119         RXF_MANAGEMENT_TX_PORT_BYTES,
3120         RXF_MANAGEMENT_TX_PORT_PAUSE,
3121         RXF_MANAGEMENT_RX_PORT_RXFIFO_OVERFLOW,
3122         RXF_RX_DROPS_TOO_MANY_FRAGS,
3123         RXF_RX_DROPS_INVALID_RING,
3124         RXF_FORWARDED_PACKETS,
3125         RXF_RX_DROPS_MTU,
3126         RXF_ADDL_STATS_N_WORDS
3127 };
3128
3129 enum OCE_TX_CHUTE_PORT_STATS {
3130         CTPT_XMT_IPV4_PKTS,
3131         CTPT_XMT_IPV4_LSD,
3132         CTPT_XMT_IPV4_MSD,
3133         CTPT_XMT_IPV6_PKTS,
3134         CTPT_XMT_IPV6_LSD,
3135         CTPT_XMT_IPV6_MSD,
3136         CTPT_REXMT_IPV4_PKTs,
3137         CTPT_REXMT_IPV4_LSD,
3138         CTPT_REXMT_IPV4_MSD,
3139         CTPT_REXMT_IPV6_PKTs,
3140         CTPT_REXMT_IPV6_LSD,
3141         CTPT_REXMT_IPV6_MSD,
3142         CTPT_N_WORDS,
3143 };
3144
3145 enum OCE_RX_ERR_STATS {
3146         RX_DROPS_NO_FRAGMENTS_0,
3147         RX_DROPS_NO_FRAGMENTS_1,
3148         RX_DROPS_NO_FRAGMENTS_2,
3149         RX_DROPS_NO_FRAGMENTS_3,
3150         RX_DROPS_NO_FRAGMENTS_4,
3151         RX_DROPS_NO_FRAGMENTS_5,
3152         RX_DROPS_NO_FRAGMENTS_6,
3153         RX_DROPS_NO_FRAGMENTS_7,
3154         RX_DROPS_NO_FRAGMENTS_8,
3155         RX_DROPS_NO_FRAGMENTS_9,
3156         RX_DROPS_NO_FRAGMENTS_10,
3157         RX_DROPS_NO_FRAGMENTS_11,
3158         RX_DROPS_NO_FRAGMENTS_12,
3159         RX_DROPS_NO_FRAGMENTS_13,
3160         RX_DROPS_NO_FRAGMENTS_14,
3161         RX_DROPS_NO_FRAGMENTS_15,
3162         RX_DROPS_NO_FRAGMENTS_16,
3163         RX_DROPS_NO_FRAGMENTS_17,
3164         RX_DROPS_NO_FRAGMENTS_18,
3165         RX_DROPS_NO_FRAGMENTS_19,
3166         RX_DROPS_NO_FRAGMENTS_20,
3167         RX_DROPS_NO_FRAGMENTS_21,
3168         RX_DROPS_NO_FRAGMENTS_22,
3169         RX_DROPS_NO_FRAGMENTS_23,
3170         RX_DROPS_NO_FRAGMENTS_24,
3171         RX_DROPS_NO_FRAGMENTS_25,
3172         RX_DROPS_NO_FRAGMENTS_26,
3173         RX_DROPS_NO_FRAGMENTS_27,
3174         RX_DROPS_NO_FRAGMENTS_28,
3175         RX_DROPS_NO_FRAGMENTS_29,
3176         RX_DROPS_NO_FRAGMENTS_30,
3177         RX_DROPS_NO_FRAGMENTS_31,
3178         RX_DROPS_NO_FRAGMENTS_32,
3179         RX_DROPS_NO_FRAGMENTS_33,
3180         RX_DROPS_NO_FRAGMENTS_34,
3181         RX_DROPS_NO_FRAGMENTS_35,
3182         RX_DROPS_NO_FRAGMENTS_36,
3183         RX_DROPS_NO_FRAGMENTS_37,
3184         RX_DROPS_NO_FRAGMENTS_38,
3185         RX_DROPS_NO_FRAGMENTS_39,
3186         RX_DROPS_NO_FRAGMENTS_40,
3187         RX_DROPS_NO_FRAGMENTS_41,
3188         RX_DROPS_NO_FRAGMENTS_42,
3189         RX_DROPS_NO_FRAGMENTS_43,
3190         RX_DEBUG_WDMA_SENT_HOLD,
3191         RX_DEBUG_WDMA_PBFREE_SENT_HOLD,
3192         RX_DEBUG_WDMA_0B_PBFREE_SENT_HOLD,
3193         RX_DEBUG_PMEM_PBUF_DEALLOC,
3194         RX_ERRORS_N_WORDS
3195 };
3196
3197 enum OCE_PMEM_ERR_STATS {
3198         PMEM_ETH_RED_DROPS,
3199         PMEM_LRO_RED_DROPS,
3200         PMEM_ULP0_RED_DROPS,
3201         PMEM_ULP1_RED_DROPS,
3202         PMEM_GLOBAL_RED_DROPS,
3203         PMEM_ERRORS_N_WORDS
3204 };
3205
3206 /**
3207  * @brief Statistics for a given Physical Port
3208  * These satisfy all the required BE2 statistics and also the
3209  * following MIB objects:
3210  *
3211  * RFC 2863 - The Interfaces Group MIB
3212  * RFC 2819 - Remote Network Monitoring Management Information Base (RMON)
3213  * RFC 3635 - Managed Objects for the Ethernet-like Interface Types
3214  * RFC 4502 - Remote Network Monitoring Mgmt Information Base Ver-2 (RMON2)
3215  *
3216  */
3217 enum OCE_PPORT_STATS {
3218         PPORT_TX_PKTS = 0,
3219         PPORT_TX_UNICAST_PKTS = 2,
3220         PPORT_TX_MULTICAST_PKTS = 4,
3221         PPORT_TX_BROADCAST_PKTS = 6,
3222         PPORT_TX_BYTES = 8,
3223         PPORT_TX_UNICAST_BYTES = 10,
3224         PPORT_TX_MULTICAST_BYTES = 12,
3225         PPORT_TX_BROADCAST_BYTES = 14,
3226         PPORT_TX_DISCARDS = 16,
3227         PPORT_TX_ERRORS = 18,
3228         PPORT_TX_PAUSE_FRAMES = 20,
3229         PPORT_TX_PAUSE_ON_FRAMES = 22,
3230         PPORT_TX_PAUSE_OFF_FRAMES = 24,
3231         PPORT_TX_INTERNAL_MAC_ERRORS = 26,
3232         PPORT_TX_CONTROL_FRAMES = 28,
3233         PPORT_TX_PKTS_64_BYTES = 30,
3234         PPORT_TX_PKTS_65_TO_127_BYTES = 32,
3235         PPORT_TX_PKTS_128_TO_255_BYTES = 34,
3236         PPORT_TX_PKTS_256_TO_511_BYTES = 36,
3237         PPORT_TX_PKTS_512_TO_1023_BYTES = 38,
3238         PPORT_TX_PKTS_1024_TO_1518_BYTES = 40,
3239         PPORT_TX_PKTS_1519_TO_2047_BYTES = 42,
3240         PPORT_TX_PKTS_2048_TO_4095_BYTES = 44,
3241         PPORT_TX_PKTS_4096_TO_8191_BYTES = 46,
3242         PPORT_TX_PKTS_8192_TO_9216_BYTES = 48,
3243         PPORT_TX_LSO_PKTS = 50,
3244         PPORT_RX_PKTS = 52,
3245         PPORT_RX_UNICAST_PKTS = 54,
3246         PPORT_RX_MULTICAST_PKTS = 56,
3247         PPORT_RX_BROADCAST_PKTS = 58,
3248         PPORT_RX_BYTES = 60,
3249         PPORT_RX_UNICAST_BYTES = 62,
3250         PPORT_RX_MULTICAST_BYTES = 64,
3251         PPORT_RX_BROADCAST_BYTES = 66,
3252         PPORT_RX_UNKNOWN_PROTOS = 68,
3253         PPORT_RESERVED_WORD69 = 69,
3254         PPORT_RX_DISCARDS = 70,
3255         PPORT_RX_ERRORS = 72,
3256         PPORT_RX_CRC_ERRORS = 74,
3257         PPORT_RX_ALIGNMENT_ERRORS = 76,
3258         PPORT_RX_SYMBOL_ERRORS = 78,
3259         PPORT_RX_PAUSE_FRAMES = 80,
3260         PPORT_RX_PAUSE_ON_FRAMES = 82,
3261         PPORT_RX_PAUSE_OFF_FRAMES = 84,
3262         PPORT_RX_FRAMES_TOO_LONG = 86,
3263         PPORT_RX_INTERNAL_MAC_ERRORS = 88,
3264         PPORT_RX_UNDERSIZE_PKTS = 90,
3265         PPORT_RX_OVERSIZE_PKTS = 91,
3266         PPORT_RX_FRAGMENT_PKTS = 92,
3267         PPORT_RX_JABBERS = 93,
3268         PPORT_RX_CONTROL_FRAMES = 94,
3269         PPORT_RX_CONTROL_FRAMES_UNK_OPCODE = 96,
3270         PPORT_RX_IN_RANGE_ERRORS = 98,
3271         PPORT_RX_OUT_OF_RANGE_ERRORS = 99,
3272         PPORT_RX_ADDRESS_MATCH_ERRORS = 100,
3273         PPORT_RX_VLAN_MISMATCH_ERRORS = 101,
3274         PPORT_RX_DROPPED_TOO_SMALL = 102,
3275         PPORT_RX_DROPPED_TOO_SHORT = 103,
3276         PPORT_RX_DROPPED_HEADER_TOO_SMALL = 104,
3277         PPORT_RX_DROPPED_INVALID_TCP_LENGTH = 105,
3278         PPORT_RX_DROPPED_RUNT = 106,
3279         PPORT_RX_IP_CHECKSUM_ERRORS = 107,
3280         PPORT_RX_TCP_CHECKSUM_ERRORS = 108,
3281         PPORT_RX_UDP_CHECKSUM_ERRORS = 109,
3282         PPORT_RX_NON_RSS_PKTS = 110,
3283         PPORT_RESERVED_WORD111 = 111,
3284         PPORT_RX_IPV4_PKTS = 112,
3285         PPORT_RX_IPV6_PKTS = 114,
3286         PPORT_RX_IPV4_BYTES = 116,
3287         PPORT_RX_IPV6_BYTES = 118,
3288         PPORT_RX_NIC_PKTS = 120,
3289         PPORT_RX_TCP_PKTS = 122,
3290         PPORT_RX_ISCSI_PKTS = 124,
3291         PPORT_RX_MANAGEMENT_PKTS = 126,
3292         PPORT_RX_SWITCHED_UNICAST_PKTS = 128,
3293         PPORT_RX_SWITCHED_MULTICAST_PKTS = 130,
3294         PPORT_RX_SWITCHED_BROADCAST_PKTS = 132,
3295         PPORT_NUM_FORWARDS = 134,
3296         PPORT_RX_FIFO_OVERFLOW = 136,
3297         PPORT_RX_INPUT_FIFO_OVERFLOW = 137,
3298         PPORT_RX_DROPS_TOO_MANY_FRAGS = 138,
3299         PPORT_RX_DROPS_INVALID_QUEUE = 140,
3300         PPORT_RESERVED_WORD141 = 141,
3301         PPORT_RX_DROPS_MTU = 142,
3302         PPORT_RX_PKTS_64_BYTES = 144,
3303         PPORT_RX_PKTS_65_TO_127_BYTES = 146,
3304         PPORT_RX_PKTS_128_TO_255_BYTES = 148,
3305         PPORT_RX_PKTS_256_TO_511_BYTES = 150,
3306         PPORT_RX_PKTS_512_TO_1023_BYTES = 152,
3307         PPORT_RX_PKTS_1024_TO_1518_BYTES = 154,
3308         PPORT_RX_PKTS_1519_TO_2047_BYTES = 156,
3309         PPORT_RX_PKTS_2048_TO_4095_BYTES = 158,
3310         PPORT_RX_PKTS_4096_TO_8191_BYTES = 160,
3311         PPORT_RX_PKTS_8192_TO_9216_BYTES = 162,
3312         PPORT_N_WORDS = 164
3313 };
3314
3315 /**
3316  * @brief Statistics for a given Virtual Port (vPort)
3317  * The following describes the vPort statistics satisfying
3318  * requirements of Linux/VMWare netdev statistics and
3319  * Microsoft Windows Statistics along with other Operating Systems.
3320  */
3321 enum OCE_VPORT_STATS {
3322         VPORT_TX_PKTS = 0,
3323         VPORT_TX_UNICAST_PKTS = 2,
3324         VPORT_TX_MULTICAST_PKTS = 4,
3325         VPORT_TX_BROADCAST_PKTS = 6,
3326         VPORT_TX_BYTES = 8,
3327         VPORT_TX_UNICAST_BYTES = 10,
3328         VPORT_TX_MULTICAST_BYTES = 12,
3329         VPORT_TX_BROADCAST_BYTES = 14,
3330         VPORT_TX_DISCARDS = 16,
3331         VPORT_TX_ERRORS = 18,
3332         VPORT_TX_PKTS_64_BYTES = 20,
3333         VPORT_TX_PKTS_65_TO_127_BYTES = 22,
3334         VPORT_TX_PKTS_128_TO_255_BYTES = 24,
3335         VPORT_TX_PKTS_256_TO_511_BYTES = 26,
3336         VPORT_TX_PKTS_512_TO_1023_BYTEs = 28,
3337         VPORT_TX_PKTS_1024_TO_1518_BYTEs = 30,
3338         VPORT_TX_PKTS_1519_TO_9699_BYTEs = 32,
3339         VPORT_TX_PKTS_OVER_9699_BYTES = 34,
3340         VPORT_RX_PKTS = 36,
3341         VPORT_RX_UNICAST_PKTS = 38,
3342         VPORT_RX_MULTICAST_PKTS = 40,
3343         VPORT_RX_BROADCAST_PKTS = 42,
3344         VPORT_RX_BYTES = 44,
3345         VPORT_RX_UNICAST_BYTES = 46,
3346         VPORT_RX_MULTICAST_BYTES = 48,
3347         VPORT_RX_BROADCAST_BYTES = 50,
3348         VPORT_RX_DISCARDS = 52,
3349         VPORT_RX_ERRORS = 54,
3350         VPORT_RX_PKTS_64_BYTES = 56,
3351         VPORT_RX_PKTS_65_TO_127_BYTES = 58,
3352         VPORT_RX_PKTS_128_TO_255_BYTES = 60,
3353         VPORT_RX_PKTS_256_TO_511_BYTES = 62,
3354         VPORT_RX_PKTS_512_TO_1023_BYTEs = 64,
3355         VPORT_RX_PKTS_1024_TO_1518_BYTEs = 66,
3356         VPORT_RX_PKTS_1519_TO_9699_BYTEs = 68,
3357         VPORT_RX_PKTS_OVER_9699_BYTES = 70,
3358         VPORT_N_WORDS = 72
3359 };
3360
3361 /**
3362  * @brief Statistics for a given queue (NIC WQ, RQ, or HDS RQ)
3363  * This set satisfies requirements of VMQare NetQueue and Microsoft VMQ
3364  */
3365 enum OCE_QUEUE_TX_STATS {
3366         QUEUE_TX_PKTS = 0,
3367         QUEUE_TX_BYTES = 2,
3368         QUEUE_TX_ERRORS = 4,
3369         QUEUE_TX_DROPS = 6,
3370         QUEUE_TX_N_WORDS = 8
3371 };
3372
3373 enum OCE_QUEUE_RX_STATS {
3374         QUEUE_RX_PKTS = 0,
3375         QUEUE_RX_BYTES = 2,
3376         QUEUE_RX_ERRORS = 4,
3377         QUEUE_RX_DROPS = 6,
3378         QUEUE_RX_BUFFER_ERRORS = 8,
3379         QUEUE_RX_N_WORDS = 10
3380 };
3381