2 * Copyright (C) 2013 Emulex
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of the Emulex Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
31 * Contact Information:
32 * freebsd-drivers@emulex.com
36 * Costa Mesa, CA 92626
41 #include <sys/types.h>
43 #undef _BIG_ENDIAN /* TODO */
46 #define OC_CNA_GEN2 0x2
47 #define OC_CNA_GEN3 0x3
48 #define DEVID_TIGERSHARK 0x700
49 #define DEVID_TOMCAT 0x710
52 #define PCICFG_F1_CSR 0x0 /* F1 for NIC */
53 #define PCICFG_SEMAPHORE 0xbc
54 #define PCICFG_SOFT_RESET 0x5c
55 #define PCICFG_UE_STATUS_HI_MASK 0xac
56 #define PCICFG_UE_STATUS_LO_MASK 0xa8
57 #define PCICFG_ONLINE0 0xb0
58 #define PCICFG_ONLINE1 0xb4
59 #define INTR_EN 0x20000000
60 #define IMAGE_TRANSFER_SIZE (32 * 1024) /* 32K at a time */
63 /********* UE Status and Mask Registers ***/
64 #define PCICFG_UE_STATUS_LOW 0xA0
65 #define PCICFG_UE_STATUS_HIGH 0xA4
66 #define PCICFG_UE_STATUS_LOW_MASK 0xA8
68 /* Lancer SLIPORT registers */
69 #define SLIPORT_STATUS_OFFSET 0x404
70 #define SLIPORT_CONTROL_OFFSET 0x408
71 #define SLIPORT_ERROR1_OFFSET 0x40C
72 #define SLIPORT_ERROR2_OFFSET 0x410
73 #define PHYSDEV_CONTROL_OFFSET 0x414
75 #define SLIPORT_STATUS_ERR_MASK 0x80000000
76 #define SLIPORT_STATUS_DIP_MASK 0x02000000
77 #define SLIPORT_STATUS_RN_MASK 0x01000000
78 #define SLIPORT_STATUS_RDY_MASK 0x00800000
79 #define SLI_PORT_CONTROL_IP_MASK 0x08000000
80 #define PHYSDEV_CONTROL_FW_RESET_MASK 0x00000002
81 #define PHYSDEV_CONTROL_DD_MASK 0x00000004
82 #define PHYSDEV_CONTROL_INP_MASK 0x40000000
84 #define SLIPORT_ERROR_NO_RESOURCE1 0x2
85 #define SLIPORT_ERROR_NO_RESOURCE2 0x9
86 /* CSR register offsets */
87 #define MPU_EP_CONTROL 0
88 #define MPU_EP_SEMAPHORE_BE3 0xac
89 #define MPU_EP_SEMAPHORE_XE201 0x400
90 #define MPU_EP_SEMAPHORE_SH 0x94
91 #define PCICFG_INTR_CTRL 0xfc
92 #define HOSTINTR_MASK (1 << 29)
93 #define HOSTINTR_PFUNC_SHIFT 26
94 #define HOSTINTR_PFUNC_MASK 7
96 /* POST status reg struct */
97 #define POST_STAGE_POWER_ON_RESET 0x00
98 #define POST_STAGE_AWAITING_HOST_RDY 0x01
99 #define POST_STAGE_HOST_RDY 0x02
100 #define POST_STAGE_CHIP_RESET 0x03
101 #define POST_STAGE_ARMFW_READY 0xc000
102 #define POST_STAGE_ARMFW_UE 0xf000
104 /* DOORBELL registers */
105 #define PD_RXULP_DB 0x0100
106 #define PD_TXULP_DB 0x0060
107 #define DB_RQ_ID_MASK 0x3FF
109 #define PD_CQ_DB 0x0120
110 #define PD_EQ_DB PD_CQ_DB
111 #define PD_MPU_MBOX_DB 0x0160
112 #define PD_MQ_DB 0x0140
114 #define DB_OFFSET 0xc0
115 #define DB_LRO_RQ_ID_MASK 0x7FF
117 /* EQE completion types */
118 #define EQ_MINOR_CODE_COMPLETION 0x00
119 #define EQ_MINOR_CODE_OTHER 0x01
120 #define EQ_MAJOR_CODE_COMPLETION 0x00
122 /* Link Status field values */
123 #define PHY_LINK_FAULT_NONE 0x0
124 #define PHY_LINK_FAULT_LOCAL 0x01
125 #define PHY_LINK_FAULT_REMOTE 0x02
127 #define PHY_LINK_SPEED_ZERO 0x0 /* No link */
128 #define PHY_LINK_SPEED_10MBPS 0x1 /* (10 Mbps) */
129 #define PHY_LINK_SPEED_100MBPS 0x2 /* (100 Mbps) */
130 #define PHY_LINK_SPEED_1GBPS 0x3 /* (1 Gbps) */
131 #define PHY_LINK_SPEED_10GBPS 0x4 /* (10 Gbps) */
133 #define PHY_LINK_DUPLEX_NONE 0x0
134 #define PHY_LINK_DUPLEX_HALF 0x1
135 #define PHY_LINK_DUPLEX_FULL 0x2
137 #define NTWK_PORT_A 0x0 /* (Port A) */
138 #define NTWK_PORT_B 0x1 /* (Port B) */
140 #define PHY_LINK_SPEED_ZERO 0x0 /* (No link.) */
141 #define PHY_LINK_SPEED_10MBPS 0x1 /* (10 Mbps) */
142 #define PHY_LINK_SPEED_100MBPS 0x2 /* (100 Mbps) */
143 #define PHY_LINK_SPEED_1GBPS 0x3 /* (1 Gbps) */
144 #define PHY_LINK_SPEED_10GBPS 0x4 /* (10 Gbps) */
146 /* Hardware Address types */
147 #define MAC_ADDRESS_TYPE_STORAGE 0x0 /* (Storage MAC Address) */
148 #define MAC_ADDRESS_TYPE_NETWORK 0x1 /* (Network MAC Address) */
149 #define MAC_ADDRESS_TYPE_PD 0x2 /* (Protection Domain MAC Addr) */
150 #define MAC_ADDRESS_TYPE_MANAGEMENT 0x3 /* (Management MAC Address) */
151 #define MAC_ADDRESS_TYPE_FCOE 0x4 /* (FCoE MAC Address) */
153 /* CREATE_IFACE capability and cap_en flags */
154 #define MBX_RX_IFACE_FLAGS_RSS 0x4
155 #define MBX_RX_IFACE_FLAGS_PROMISCUOUS 0x8
156 #define MBX_RX_IFACE_FLAGS_BROADCAST 0x10
157 #define MBX_RX_IFACE_FLAGS_UNTAGGED 0x20
158 #define MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS 0x80
159 #define MBX_RX_IFACE_FLAGS_VLAN 0x100
160 #define MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS 0x200
161 #define MBX_RX_IFACE_FLAGS_PASS_L2_ERR 0x400
162 #define MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR 0x800
163 #define MBX_RX_IFACE_FLAGS_MULTICAST 0x1000
164 #define MBX_RX_IFACE_RX_FILTER_IF_MULTICAST_HASH 0x2000
165 #define MBX_RX_IFACE_FLAGS_HDS 0x4000
166 #define MBX_RX_IFACE_FLAGS_DIRECTED 0x8000
167 #define MBX_RX_IFACE_FLAGS_VMQ 0x10000
168 #define MBX_RX_IFACE_FLAGS_NETQ 0x20000
169 #define MBX_RX_IFACE_FLAGS_QGROUPS 0x40000
170 #define MBX_RX_IFACE_FLAGS_LSO 0x80000
171 #define MBX_RX_IFACE_FLAGS_LRO 0x100000
173 #define MQ_RING_CONTEXT_SIZE_16 0x5 /* (16 entries) */
174 #define MQ_RING_CONTEXT_SIZE_32 0x6 /* (32 entries) */
175 #define MQ_RING_CONTEXT_SIZE_64 0x7 /* (64 entries) */
176 #define MQ_RING_CONTEXT_SIZE_128 0x8 /* (128 entries) */
178 #define MBX_DB_READY_BIT 0x1
179 #define MBX_DB_HI_BIT 0x2
180 #define ASYNC_EVENT_CODE_LINK_STATE 0x1
181 #define ASYNC_EVENT_LINK_UP 0x1
182 #define ASYNC_EVENT_LINK_DOWN 0x0
183 #define ASYNC_EVENT_GRP5 0x5
184 #define ASYNC_EVENT_CODE_DEBUG 0x6
185 #define ASYNC_EVENT_PVID_STATE 0x3
186 #define ASYNC_EVENT_OS2BMC 0x5
187 #define ASYNC_EVENT_DEBUG_QNQ 0x1
188 #define ASYNC_EVENT_CODE_SLIPORT 0x11
189 #define VLAN_VID_MASK 0x0FFF
191 /* port link_status */
192 #define ASYNC_EVENT_LOGICAL 0x02
194 /* Logical Link Status */
195 #define NTWK_LOGICAL_LINK_DOWN 0
196 #define NTWK_LOGICAL_LINK_UP 1
199 #define NTWK_RX_FILTER_IP_CKSUM 0x1
200 #define NTWK_RX_FILTER_TCP_CKSUM 0x2
201 #define NTWK_RX_FILTER_UDP_CKSUM 0x4
202 #define NTWK_RX_FILTER_STRIP_CRC 0x8
204 /* max SGE per mbx */
205 #define MAX_MBX_SGE 19
207 /* Max multicast filter size*/
208 #define OCE_MAX_MC_FILTER_SIZE 64
210 /* PCI SLI (Service Level Interface) capabilities register */
211 #define OCE_INTF_REG_OFFSET 0x58
212 #define OCE_INTF_VALID_SIG 6 /* register's signature */
213 #define OCE_INTF_FUNC_RESET_REQD 1
214 #define OCE_INTF_HINT1_NOHINT 0
215 #define OCE_INTF_HINT1_SEMAINIT 1
216 #define OCE_INTF_HINT1_STATCTRL 2
217 #define OCE_INTF_IF_TYPE_0 0
218 #define OCE_INTF_IF_TYPE_1 1
219 #define OCE_INTF_IF_TYPE_2 2
220 #define OCE_INTF_IF_TYPE_3 3
221 #define OCE_INTF_SLI_REV3 3 /* not supported by driver */
222 #define OCE_INTF_SLI_REV4 4 /* driver supports SLI-4 */
223 #define OCE_INTF_PHYS_FUNC 0
224 #define OCE_INTF_VIRT_FUNC 1
225 #define OCE_INTF_FAMILY_BE2 0 /* not supported by driver */
226 #define OCE_INTF_FAMILY_BE3 1 /* driver supports BE3 */
227 #define OCE_INTF_FAMILY_A0_CHIP 0xA /* Lancer A0 chip (supported) */
228 #define OCE_INTF_FAMILY_B0_CHIP 0xB /* Lancer B0 chip (future) */
230 #define NIC_WQE_SIZE 16
231 #define NIC_UNICAST 0x00
232 #define NIC_MULTICAST 0x01
233 #define NIC_BROADCAST 0x02
235 #define NIC_HDS_NO_SPLIT 0x00
236 #define NIC_HDS_SPLIT_L3PL 0x01
237 #define NIC_HDS_SPLIT_L4PL 0x02
239 #define NIC_WQ_TYPE_FORWARDING 0x01
240 #define NIC_WQ_TYPE_STANDARD 0x02
241 #define NIC_WQ_TYPE_LOW_LATENCY 0x04
243 #define OCE_RESET_STATS 1
244 #define OCE_RETAIN_STATS 0
245 #define OCE_TXP_SW_SZ 48
247 typedef union pci_sli_intf_u {
251 uint32_t sli_valid:3;
252 uint32_t sli_hint2:5;
253 uint32_t sli_hint1:8;
254 uint32_t sli_if_type:4;
255 uint32_t sli_family:4;
258 uint32_t sli_func_type:1;
260 uint32_t sli_func_type:1;
263 uint32_t sli_family:4;
264 uint32_t sli_if_type:4;
265 uint32_t sli_hint1:8;
266 uint32_t sli_hint2:5;
267 uint32_t sli_valid:3;
274 /* physical address structure to be used in MBX */
284 typedef union pcicfg_intr_ctl_u {
288 uint32_t winselect:2;
291 uint32_t vf_cev_int_line_en:1;
293 uint32_t membarwinen:1;
295 uint32_t membarwinen:1;
297 uint32_t vf_cev_int_line_en:1;
300 uint32_t winselect:2;
308 typedef union pcicfg_semaphore_u {
319 } pcicfg_semaphore_t;
324 typedef union pcicfg_soft_reset_u {
328 uint32_t nec_ll_rcvdetect:8;
329 uint32_t dbg_all_reqs_62_49:14;
330 uint32_t scratchpad0:1;
331 uint32_t exception_oe:1;
332 uint32_t soft_reset:1;
336 uint32_t soft_reset:1;
337 uint32_t exception_oe:1;
338 uint32_t scratchpad0:1;
339 uint32_t dbg_all_reqs_62_49:14;
340 uint32_t nec_ll_rcvdetect:8;
343 } pcicfg_soft_reset_t;
348 typedef union pcicfg_online1_u {
352 uint32_t host8_online:1;
353 uint32_t host7_online:1;
354 uint32_t host6_online:1;
355 uint32_t host5_online:1;
356 uint32_t host4_online:1;
357 uint32_t host3_online:1;
358 uint32_t host2_online:1;
359 uint32_t ipc_online:1;
360 uint32_t arm_online:1;
361 uint32_t txp_online:1;
362 uint32_t xaui_online:1;
363 uint32_t rxpp_online:1;
364 uint32_t txpb_online:1;
365 uint32_t rr_online:1;
366 uint32_t pmem_online:1;
367 uint32_t pctl1_online:1;
368 uint32_t pctl0_online:1;
369 uint32_t pcs1online_online:1;
370 uint32_t mpu_iram_online:1;
371 uint32_t pcs0online_online:1;
372 uint32_t mgmt_mac_online:1;
373 uint32_t lpcmemhost_online:1;
375 uint32_t lpcmemhost_online:1;
376 uint32_t mgmt_mac_online:1;
377 uint32_t pcs0online_online:1;
378 uint32_t mpu_iram_online:1;
379 uint32_t pcs1online_online:1;
380 uint32_t pctl0_online:1;
381 uint32_t pctl1_online:1;
382 uint32_t pmem_online:1;
383 uint32_t rr_online:1;
384 uint32_t txpb_online:1;
385 uint32_t rxpp_online:1;
386 uint32_t xaui_online:1;
387 uint32_t txp_online:1;
388 uint32_t arm_online:1;
389 uint32_t ipc_online:1;
390 uint32_t host2_online:1;
391 uint32_t host3_online:1;
392 uint32_t host4_online:1;
393 uint32_t host5_online:1;
394 uint32_t host6_online:1;
395 uint32_t host7_online:1;
396 uint32_t host8_online:1;
403 typedef union mpu_ep_semaphore_u {
408 uint32_t backup_fw:1;
409 uint32_t iscsi_no_ip:1;
410 uint32_t iscsi_ip_conflict:1;
411 uint32_t option_rom_installed:1;
412 uint32_t iscsi_drv_loaded:1;
418 uint32_t iscsi_drv_loaded:1;
419 uint32_t option_rom_installed:1;
420 uint32_t iscsi_ip_conflict:1;
421 uint32_t iscsi_no_ip:1;
422 uint32_t backup_fw:1;
426 } mpu_ep_semaphore_t;
431 typedef union mpu_ep_control_u {
435 uint32_t cpu_reset:1;
437 uint32_t ep_ram_init_status:1;
439 uint32_t m2_rxpbuf:1;
440 uint32_t m1_rxpbuf:1;
441 uint32_t m0_rxpbuf:1;
443 uint32_t m0_rxpbuf:1;
444 uint32_t m1_rxpbuf:1;
445 uint32_t m2_rxpbuf:1;
447 uint32_t ep_ram_init_status:1;
449 uint32_t cpu_reset:1;
458 typedef union pd_rxulp_db_u {
462 uint32_t num_posted:8;
463 uint32_t invalidate:1;
469 uint32_t invalidate:1;
470 uint32_t num_posted:8;
477 typedef union pd_txulp_db_u {
482 uint32_t num_posted:14;
488 uint32_t num_posted:14;
495 typedef union cq_db_u {
501 uint32_t num_popped:13;
509 uint32_t num_popped:13;
517 typedef union eq_db_u {
523 uint32_t num_popped:13;
533 uint32_t num_popped:13;
540 /* bootstrap mbox doorbell */
541 typedef union pd_mpu_mbox_db_u {
556 /* MQ ring doorbell */
557 typedef union pd_mq_db_u {
562 uint32_t num_posted:14;
568 uint32_t num_posted:14;
581 /* MQ scatter gather entry. Array of these make an SGL */
589 * payload can contain an SGL or an embedded array of upto 59 dwords
591 struct oce_mbx_payload {
594 struct oce_mq_sge sgl[MAX_MBX_SGE];
595 uint32_t embedded[59];
610 uint32_t sge_count:5;
616 uint32_t sge_count:5;
624 uint32_t payload_length;
627 struct oce_mbx_payload payload;
630 /* completion queue entry for MQ */
636 uint32_t extended_status:16;
637 uint32_t completion_status:16;
642 uint32_t async_event:1;
643 uint32_t hpi_buffer_cmpl:1;
644 uint32_t completed:1;
647 uint32_t async_type:8;
648 uint32_t event_type:8;
652 uint32_t completion_status:16;
653 uint32_t extended_status:16;
658 uint32_t event_type:8;
659 uint32_t async_type:8;
662 uint32_t completed:1;
663 uint32_t hpi_buffer_cmpl:1;
664 uint32_t async_event:1;
672 /* Mailbox Completion Status Codes */
673 enum MBX_COMPLETION_STATUS {
674 MBX_CQE_STATUS_SUCCESS = 0x00,
675 MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES = 0x01,
676 MBX_CQE_STATUS_INVALID_PARAMETER = 0x02,
677 MBX_CQE_STATUS_INSUFFICIENT_RESOURCES = 0x03,
678 MBX_CQE_STATUS_QUEUE_FLUSHING = 0x04,
679 MBX_CQE_STATUS_DMA_FAILED = 0x05
682 struct oce_async_cqe_link_state {
692 uint16_t qos_link_speed;
699 uint32_t async_event:1;
701 uint32_t event_type:8;
702 uint32_t event_code:8;
713 uint16_t qos_link_speed;
718 uint32_t event_code:8;
719 uint32_t event_type:8;
721 uint32_t async_event:1;
729 /* OS2BMC async event */
730 struct oce_async_evt_grp5_os2bmc {
733 uint32_t lrn_enable:1;
734 uint32_t lrn_disable:1;
735 uint32_t mgmt_enable:1;
736 uint32_t mgmt_disable:1;
738 uint32_t vlan_tag:16;
739 uint32_t arp_filter:1;
740 uint32_t dhcp_client_filt:1;
741 uint32_t dhcp_server_filt:1;
742 uint32_t net_bios_filt:1;
744 uint32_t bcast_filt:1;
745 uint32_t ipv6_nbr_filt:1;
746 uint32_t ipv6_ra_filt:1;
747 uint32_t ipv6_ras_filt:1;
749 uint32_t mcast_filt:1;
758 /* PVID aync event */
759 struct oce_async_event_grp5_pvid_state {
768 /* async event indicating outer VLAN tag in QnQ */
769 struct oce_async_event_qnq {
770 uint8_t valid; /* Indicates if outer VLAN is valid */
779 typedef union oce_mq_ext_ctx_u {
784 uint32_t dw4rsvd1:16;
785 uint32_t num_pages:16;
787 uint32_t async_evt_bitmap;
791 uint32_t ring_size:4;
792 uint32_t dw5rsvd1:16;
795 uint32_t dw6rsvd1:31;
797 uint32_t dw7rsvd1:21;
798 uint32_t async_cq_id:10;
799 uint32_t async_cq_valid:1;
802 uint32_t num_pages:16;
803 uint32_t dw4rsvd1:16;
805 uint32_t async_evt_bitmap;
807 uint32_t dw5rsvd1:16;
808 uint32_t ring_size:4;
812 uint32_t dw6rsvd1:31;
815 uint32_t async_cq_valid:1;
816 uint32_t async_cq_id:10;
817 uint32_t dw7rsvd1:21;
826 uint32_t num_pages:16;
828 uint32_t async_evt_bitmap;
830 uint32_t dw5rsvd2:12;
831 uint32_t ring_size:4;
832 uint32_t async_cq_id:16;
835 uint32_t dw6rsvd1:31;
837 uint32_t dw7rsvd1:31;
838 uint32_t async_cq_valid:1;
841 uint32_t num_pages:16;
844 uint32_t async_evt_bitmap;
846 uint32_t async_cq_id:16;
847 uint32_t ring_size:4;
848 uint32_t dw5rsvd2:12;
850 uint32_t dw6rsvd1:31;
853 uint32_t async_cq_valid:1;
854 uint32_t dw7rsvd1:31;
863 /* MQ mailbox structure */
866 struct oce_mq_cqe cqe;
869 /* ---[ MBXs start here ]---------------------------------------------- */
870 /* MBXs sub system codes */
871 enum MBX_SUBSYSTEM_CODES {
872 MBX_SUBSYSTEM_RSVD = 0,
873 MBX_SUBSYSTEM_COMMON = 1,
874 MBX_SUBSYSTEM_COMMON_ISCSI = 2,
875 MBX_SUBSYSTEM_NIC = 3,
876 MBX_SUBSYSTEM_TOE = 4,
877 MBX_SUBSYSTEM_PXE_UNDI = 5,
878 MBX_SUBSYSTEM_ISCSI_INI = 6,
879 MBX_SUBSYSTEM_ISCSI_TGT = 7,
880 MBX_SUBSYSTEM_MILI_PTL = 8,
881 MBX_SUBSYSTEM_MILI_TMD = 9,
882 MBX_SUBSYSTEM_RDMA = 10,
883 MBX_SUBSYSTEM_LOWLEVEL = 11,
884 MBX_SUBSYSTEM_LRO = 13,
885 IOCBMBX_SUBSYSTEM_DCBX = 15,
886 IOCBMBX_SUBSYSTEM_DIAG = 16,
887 IOCBMBX_SUBSYSTEM_VENDOR = 17
890 /* common ioctl opcodes */
891 enum COMMON_SUBSYSTEM_OPCODES {
892 /* These opcodes are common to both networking and storage PCI functions
893 * They are used to reserve resources and configure CNA. These opcodes
894 * all use the MBX_SUBSYSTEM_COMMON subsystem code.
896 OPCODE_COMMON_QUERY_IFACE_MAC = 1,
897 OPCODE_COMMON_SET_IFACE_MAC = 2,
898 OPCODE_COMMON_SET_IFACE_MULTICAST = 3,
899 OPCODE_COMMON_CONFIG_IFACE_VLAN = 4,
900 OPCODE_COMMON_QUERY_LINK_CONFIG = 5,
901 OPCODE_COMMON_READ_FLASHROM = 6,
902 OPCODE_COMMON_WRITE_FLASHROM = 7,
903 OPCODE_COMMON_QUERY_MAX_MBX_BUFFER_SIZE = 8,
904 OPCODE_COMMON_CREATE_CQ = 12,
905 OPCODE_COMMON_CREATE_EQ = 13,
906 OPCODE_COMMON_CREATE_MQ = 21,
907 OPCODE_COMMON_GET_QOS = 27,
908 OPCODE_COMMON_SET_QOS = 28,
909 OPCODE_COMMON_READ_EPROM = 30,
910 OPCODE_COMMON_GET_CNTL_ATTRIBUTES = 32,
911 OPCODE_COMMON_NOP = 33,
912 OPCODE_COMMON_SET_IFACE_RX_FILTER = 34,
913 OPCODE_COMMON_GET_FW_VERSION = 35,
914 OPCODE_COMMON_SET_FLOW_CONTROL = 36,
915 OPCODE_COMMON_GET_FLOW_CONTROL = 37,
916 OPCODE_COMMON_SET_FRAME_SIZE = 39,
917 OPCODE_COMMON_MODIFY_EQ_DELAY = 41,
918 OPCODE_COMMON_CREATE_IFACE = 50,
919 OPCODE_COMMON_DESTROY_IFACE = 51,
920 OPCODE_COMMON_MODIFY_MSI_MESSAGES = 52,
921 OPCODE_COMMON_DESTROY_MQ = 53,
922 OPCODE_COMMON_DESTROY_CQ = 54,
923 OPCODE_COMMON_DESTROY_EQ = 55,
924 OPCODE_COMMON_UPLOAD_TCP = 56,
925 OPCODE_COMMON_SET_NTWK_LINK_SPEED = 57,
926 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG = 58,
927 OPCODE_COMMON_ADD_IFACE_MAC = 59,
928 OPCODE_COMMON_DEL_IFACE_MAC = 60,
929 OPCODE_COMMON_FUNCTION_RESET = 61,
930 OPCODE_COMMON_SET_PHYSICAL_LINK_CONFIG = 62,
931 OPCODE_COMMON_GET_BOOT_CONFIG = 66,
932 OPCPDE_COMMON_SET_BOOT_CONFIG = 67,
933 OPCODE_COMMON_SET_BEACON_CONFIG = 69,
934 OPCODE_COMMON_GET_BEACON_CONFIG = 70,
935 OPCODE_COMMON_GET_PHYSICAL_LINK_CONFIG = 71,
936 OPCODE_COMMON_READ_TRANSRECEIVER_DATA = 73,
937 OPCODE_COMMON_GET_OEM_ATTRIBUTES = 76,
938 OPCODE_COMMON_GET_PORT_NAME = 77,
939 OPCODE_COMMON_GET_CONFIG_SIGNATURE = 78,
940 OPCODE_COMMON_SET_CONFIG_SIGNATURE = 79,
941 OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG = 80,
942 OPCODE_COMMON_GET_BE_CONFIGURATION_RESOURCES = 81,
943 OPCODE_COMMON_SET_BE_CONFIGURATION_RESOURCES = 82,
944 OPCODE_COMMON_GET_RESET_NEEDED = 84,
945 OPCODE_COMMON_GET_SERIAL_NUMBER = 85,
946 OPCODE_COMMON_GET_NCSI_CONFIG = 86,
947 OPCODE_COMMON_SET_NCSI_CONFIG = 87,
948 OPCODE_COMMON_CREATE_MQ_EXT = 90,
949 OPCODE_COMMON_SET_FUNCTION_PRIVILEGES = 100,
950 OPCODE_COMMON_SET_VF_PORT_TYPE = 101,
951 OPCODE_COMMON_GET_PHY_CONFIG = 102,
952 OPCODE_COMMON_SET_FUNCTIONAL_CAPS = 103,
953 OPCODE_COMMON_GET_ADAPTER_ID = 110,
954 OPCODE_COMMON_GET_UPGRADE_FEATURES = 111,
955 OPCODE_COMMON_GET_INSTALLED_FEATURES = 112,
956 OPCODE_COMMON_GET_AVAIL_PERSONALITIES = 113,
957 OPCODE_COMMON_GET_CONFIG_PERSONALITIES = 114,
958 OPCODE_COMMON_SEND_ACTIVATION = 115,
959 OPCODE_COMMON_RESET_LICENSES = 116,
960 OPCODE_COMMON_GET_CNTL_ADDL_ATTRIBUTES = 121,
961 OPCODE_COMMON_QUERY_TCB = 144,
962 OPCODE_COMMON_ADD_IFACE_QUEUE_FILTER = 145,
963 OPCODE_COMMON_DEL_IFACE_QUEUE_FILTER = 146,
964 OPCODE_COMMON_GET_IFACE_MAC_LIST = 147,
965 OPCODE_COMMON_SET_IFACE_MAC_LIST = 148,
966 OPCODE_COMMON_MODIFY_CQ = 149,
967 OPCODE_COMMON_GET_IFACE_VLAN_LIST = 150,
968 OPCODE_COMMON_SET_IFACE_VLAN_LIST = 151,
969 OPCODE_COMMON_GET_HSW_CONFIG = 152,
970 OPCODE_COMMON_SET_HSW_CONFIG = 153,
971 OPCODE_COMMON_GET_RESOURCE_EXTENT_INFO = 154,
972 OPCODE_COMMON_GET_ALLOCATED_RESOURCE_EXTENTS = 155,
973 OPCODE_COMMON_ALLOC_RESOURCE_EXTENTS = 156,
974 OPCODE_COMMON_DEALLOC_RESOURCE_EXTENTS = 157,
975 OPCODE_COMMON_SET_DIAG_REGISTERS = 158,
976 OPCODE_COMMON_GET_FUNCTION_CONFIG = 160,
977 OPCODE_COMMON_GET_PROFILE_CAPACITIES = 161,
978 OPCODE_COMMON_GET_MR_PROFILE_CAPACITIES = 162,
979 OPCODE_COMMON_SET_MR_PROFILE_CAPACITIES = 163,
980 OPCODE_COMMON_GET_PROFILE_CONFIG = 164,
981 OPCODE_COMMON_SET_PROFILE_CONFIG = 165,
982 OPCODE_COMMON_GET_PROFILE_LIST = 166,
983 OPCODE_COMMON_GET_ACTIVE_PROFILE = 167,
984 OPCODE_COMMON_SET_ACTIVE_PROFILE = 168,
985 OPCODE_COMMON_GET_FUNCTION_PRIVILEGES = 170,
986 OPCODE_COMMON_READ_OBJECT = 171,
987 OPCODE_COMMON_WRITE_OBJECT = 172
990 /* common ioctl header */
991 #define OCE_MBX_VER_V2 0x0002 /* Version V2 mailbox command */
992 #define OCE_MBX_VER_V1 0x0001 /* Version V1 mailbox command */
993 #define OCE_MBX_VER_V0 0x0000 /* Version V0 mailbox command */
1001 uint32_t port_number:8;
1002 uint32_t subsystem:8;
1007 uint32_t request_length;
1014 uint32_t subsystem:8;
1015 uint32_t port_number:8;
1020 uint32_t request_length;
1031 uint32_t subsystem:8;
1035 uint32_t additional_status:8;
1040 uint32_t subsystem:8;
1045 uint32_t additional_status:8;
1048 uint32_t rsp_length;
1049 uint32_t actual_rsp_length;
1053 #define OCE_BMBX_RHDR_SZ 20
1054 #define OCE_MBX_RRHDR_SZ sizeof (struct mbx_hdr)
1055 #define OCE_MBX_ADDL_STATUS(_MHDR) ((_MHDR)->u0.rsp.additional_status)
1056 #define OCE_MBX_STATUS(_MHDR) ((_MHDR)->u0.rsp.status)
1058 /* [05] OPCODE_COMMON_QUERY_LINK_CONFIG_V1 */
1059 struct mbx_query_common_link_config {
1068 uint32_t physical_port_fault:8;
1069 uint32_t physical_port_speed:8;
1070 uint32_t link_duplex:8;
1072 uint32_t port_number:6;
1074 uint16_t qos_link_speed;
1078 uint32_t phys_fcv:1;
1079 uint32_t phys_rxf:1;
1080 uint32_t phys_txf:1;
1081 uint32_t logical_link_status:8;
1083 uint32_t port_number:6;
1085 uint32_t link_duplex:8;
1086 uint32_t physical_port_speed:8;
1087 uint32_t physical_port_fault:8;
1090 uint16_t qos_link_speed;
1092 uint32_t logical_link_status:8;
1093 uint32_t phys_txf:1;
1094 uint32_t phys_rxf:1;
1095 uint32_t phys_fcv:1;
1102 /* [57] OPCODE_COMMON_SET_LINK_SPEED */
1103 struct mbx_set_common_link_speed {
1110 uint8_t virtual_port;
1111 uint8_t physical_port;
1113 uint8_t physical_port;
1114 uint8_t virtual_port;
1128 struct mac_address_format {
1129 uint16_t size_of_struct;
1130 uint8_t mac_addr[6];
1133 /* [01] OPCODE_COMMON_QUERY_IFACE_MAC */
1134 struct mbx_query_common_iface_mac {
1151 struct mac_address_format mac;
1156 /* [02] OPCODE_COMMON_SET_IFACE_MAC */
1157 struct mbx_set_common_iface_mac {
1173 struct mac_address_format mac;
1184 /* [03] OPCODE_COMMON_SET_IFACE_MULTICAST */
1185 struct mbx_set_common_iface_multicast {
1191 uint8_t promiscuous;
1218 struct normal_vlan {
1222 struct ntwk_if_vlan_tag {
1224 struct normal_vlan normal;
1225 struct qinq_vlan qinq;
1229 /* [50] OPCODE_COMMON_CREATE_IFACE */
1230 struct mbx_create_common_iface {
1236 uint32_t enable_flags;
1237 uint8_t mac_addr[6];
1239 uint8_t mac_invalid;
1240 struct ntwk_if_vlan_tag vlan_tag;
1251 /* [51] OPCODE_COMMON_DESTROY_IFACE */
1252 struct mbx_destroy_common_iface {
1267 /* event queue context structure */
1270 uint32_t dw4rsvd1:16;
1271 uint32_t num_pages:16;
1274 uint32_t dw5rsvd2:1;
1276 uint32_t dw5rsvd1:29;
1279 uint32_t dw6rsvd2:2;
1281 uint32_t dw6rsvd1:26;
1283 uint32_t dw7rsvd2:9;
1284 uint32_t delay_mult:10;
1285 uint32_t dw7rsvd1:13;
1289 uint32_t num_pages:16;
1290 uint32_t dw4rsvd1:16;
1292 uint32_t dw5rsvd1:29;
1294 uint32_t dw5rsvd2:1;
1297 uint32_t dw6rsvd1:26;
1299 uint32_t dw6rsvd2:2;
1302 uint32_t dw7rsvd1:13;
1303 uint32_t delay_mult:10;
1304 uint32_t dw7rsvd2:9;
1310 /* [13] OPCODE_COMMON_CREATE_EQ */
1311 struct mbx_create_common_eq {
1315 struct oce_eq_ctx ctx;
1316 struct phys_addr pages[8];
1326 /* [55] OPCODE_COMMON_DESTROY_EQ */
1327 struct mbx_destroy_common_eq {
1346 /* SLI-4 CQ context - use version V0 for B3, version V2 for Lancer */
1347 typedef union oce_cq_ctx_u {
1352 uint32_t dw4rsvd1:16;
1353 uint32_t num_pages:16;
1355 uint32_t eventable:1;
1356 uint32_t dw5rsvd3:1;
1359 uint32_t dw5rsvd2:12;
1361 uint32_t coalesce_wm:2;
1362 uint32_t dw5rsvd1:12;
1365 uint32_t dw6rsvd2:1;
1367 uint32_t dw6rsvd1:22;
1370 uint32_t num_pages:16;
1371 uint32_t dw4rsvd1:16;
1373 uint32_t dw5rsvd1:12;
1374 uint32_t coalesce_wm:2;
1376 uint32_t dw5rsvd2:12;
1379 uint32_t dw5rsvd3:1;
1380 uint32_t eventable:1;
1382 uint32_t dw6rsvd1:22;
1384 uint32_t dw6rsvd2:1;
1395 uint32_t dw4rsvd1:8;
1396 uint32_t page_size:8;
1397 uint32_t num_pages:16;
1399 uint32_t eventable:1;
1400 uint32_t dw5rsvd3:1;
1403 uint32_t dw5rsvd2:11;
1404 uint32_t autovalid:1;
1406 uint32_t coalesce_wm:2;
1407 uint32_t dw5rsvd1:12;
1410 uint32_t dw6rsvd1:15;
1413 uint32_t dw7rsvd1:16;
1414 uint32_t cqe_count:16;
1417 uint32_t num_pages:16;
1418 uint32_t page_size:8;
1419 uint32_t dw4rsvd1:8;
1421 uint32_t dw5rsvd1:12;
1422 uint32_t coalesce_wm:2;
1424 uint32_t autovalid:1;
1425 uint32_t dw5rsvd2:11;
1428 uint32_t dw5rsvd3:1;
1429 uint32_t eventable:1;
1432 uint32_t dw6rsvd1:15;
1435 uint32_t cqe_count:16;
1436 uint32_t dw7rsvd1:16;
1443 /* [12] OPCODE_COMMON_CREATE_CQ */
1444 struct mbx_create_common_cq {
1448 oce_cq_ctx_t cq_ctx;
1449 struct phys_addr pages[4];
1459 /* [54] OPCODE_COMMON_DESTROY_CQ */
1460 struct mbx_destroy_common_cq {
1479 typedef union oce_mq_ctx_u {
1484 uint32_t dw4rsvd1:16;
1485 uint32_t num_pages:16;
1488 uint32_t dw5rsvd2:2;
1489 uint32_t ring_size:4;
1490 uint32_t dw5rsvd1:16;
1493 uint32_t dw6rsvd1:31;
1495 uint32_t dw7rsvd1:21;
1496 uint32_t async_cq_id:10;
1497 uint32_t async_cq_valid:1;
1500 uint32_t num_pages:16;
1501 uint32_t dw4rsvd1:16;
1503 uint32_t dw5rsvd1:16;
1504 uint32_t ring_size:4;
1505 uint32_t dw5rsvd2:2;
1508 uint32_t dw6rsvd1:31;
1511 uint32_t async_cq_valid:1;
1512 uint32_t async_cq_id:10;
1513 uint32_t dw7rsvd1:21;
1521 * @brief [21] OPCODE_COMMON_CREATE_MQ
1522 * A MQ must be at least 16 entries deep (corresponding to 1 page) and
1523 * at most 128 entries deep (corresponding to 8 pages).
1525 struct mbx_create_common_mq {
1529 oce_mq_ctx_t context;
1530 struct phys_addr pages[8];
1540 struct mbx_create_common_mq_ex {
1544 oce_mq_ext_ctx_t context;
1545 struct phys_addr pages[8];
1557 /* [53] OPCODE_COMMON_DESTROY_MQ */
1558 struct mbx_destroy_common_mq {
1577 /* [35] OPCODE_COMMON_GET_ FW_VERSION */
1578 struct mbx_get_common_fw_version {
1586 uint8_t fw_ver_str[32];
1587 uint8_t fw_on_flash_ver_str[32];
1592 /* [52] OPCODE_COMMON_CEV_MODIFY_MSI_MESSAGES */
1593 struct mbx_common_cev_modify_msi_messages {
1597 uint32_t num_msi_msgs;
1606 /* [36] OPCODE_COMMON_SET_FLOW_CONTROL */
1607 /* [37] OPCODE_COMMON_GET_FLOW_CONTROL */
1608 struct mbx_common_get_set_flow_control {
1611 uint16_t tx_flow_control;
1612 uint16_t rx_flow_control;
1614 uint16_t rx_flow_control;
1615 uint16_t tx_flow_control;
1619 enum e_flash_opcode {
1620 MGMT_FLASHROM_OPCODE_FLASH = 1,
1621 MGMT_FLASHROM_OPCODE_SAVE = 2
1624 /* [06] OPCODE_READ_COMMON_FLASHROM */
1625 /* [07] OPCODE_WRITE_COMMON_FLASHROM */
1627 struct mbx_common_read_write_flashrom {
1629 uint32_t flash_op_code;
1630 uint32_t flash_op_type;
1631 uint32_t data_buffer_size;
1632 uint32_t data_offset;
1633 uint8_t data_buffer[32768]; /* + IMAGE_TRANSFER_SIZE */
1637 struct oce_phy_info {
1639 uint16_t interface_type;
1640 uint32_t misc_params;
1641 uint16_t ext_phy_details;
1643 uint16_t auto_speeds_supported;
1644 uint16_t fixed_speeds_supported;
1645 uint32_t future_use[2];
1648 struct mbx_common_phy_info {
1655 struct oce_phy_info phy_info;
1662 struct mbx_lancer_common_write_object {
1666 uint32_t write_length: 24;
1669 uint32_t write_offset;
1670 uint8_t object_name[104];
1671 uint32_t descriptor_count;
1672 uint32_t buffer_length;
1673 uint32_t address_lower;
1674 uint32_t address_upper;
1681 uint8_t additional_status;
1683 uint32_t response_length;
1684 uint32_t actual_response_length;
1685 uint32_t actual_write_length;
1691 * @brief MBX Common Quiery Firmaware Config
1692 * This command retrieves firmware configuration parameters and adapter
1693 * resources available to the driver originating the request. The firmware
1694 * configuration defines supported protocols by the installed adapter firmware.
1695 * This includes which ULP processors support the specified protocols and
1696 * the number of TCP connections allowed for that protocol.
1698 struct mbx_common_query_fw_config {
1706 uint32_t config_number;
1707 uint32_t asic_revision;
1708 uint32_t port_id; /* used for stats retrieval */
1709 uint32_t function_mode;
1713 uint32_t nic_wqid_base;
1714 uint32_t nic_wq_tot;
1715 uint32_t toe_wqid_base;
1716 uint32_t toe_wq_tot;
1717 uint32_t toe_rqid_base;
1718 uint32_t toe_rqid_tot;
1719 uint32_t toe_defrqid_base;
1720 uint32_t toe_defrqid_count;
1721 uint32_t lro_rqid_base;
1722 uint32_t lro_rqid_tot;
1723 uint32_t iscsi_icd_base;
1724 uint32_t iscsi_icd_count;
1726 uint32_t function_caps;
1735 enum CQFW_CONFIG_NUMBER {
1736 FCN_NIC_ISCSI_Initiator = 0x0,
1737 FCN_ISCSI_Target = 0x3,
1739 FCN_ISCSI_Initiator_Target = 0x9,
1740 FCN_NIC_RDMA_TOE = 0xA,
1741 FCN_NIC_RDMA_FCoE = 0xB,
1742 FCN_NIC_RDMA_iSCSI = 0xC,
1743 FCN_NIC_iSCSI_FCoE = 0xD
1747 * @brief Function Capabilites
1748 * This field contains the flags indicating the capabilities of
1749 * the SLI Host’s PCI function.
1751 enum CQFW_FUNCTION_CAPABILITIES {
1752 FNC_UNCLASSIFIED_STATS = 0x1,
1754 FNC_PROMISCUOUS = 0x4,
1755 FNC_LEGACY_MODE = 0x8,
1759 FNC_QGROUPS = 0x40000,
1761 FNC_VLAN_OFFLOAD = 0x800000
1764 enum CQFW_ULP_MODES_SUPPORTED {
1767 ULP_RDMA_MODE = 0x4,
1768 ULP_ISCSI_INI_MODE = 0x10,
1769 ULP_ISCSI_TGT_MODE = 0x20,
1770 ULP_FCOE_INI_MODE = 0x40,
1771 ULP_FCOE_TGT_MODE = 0x80,
1772 ULP_DAL_MODE = 0x100,
1773 ULP_LRO_MODE = 0x200
1777 * @brief Function Modes Supported
1778 * Valid function modes (or protocol-types) supported on the SLI-Host’s
1779 * PCIe function. This field is a logical OR of the following values:
1781 enum CQFW_FUNCTION_MODES_SUPPORTED {
1782 FNM_TOE_MODE = 0x1, /* TCP offload supported */
1783 FNM_NIC_MODE = 0x2, /* Raw Ethernet supported */
1784 FNM_RDMA_MODE = 0x4, /* RDMA protocol supported */
1785 FNM_VM_MODE = 0x8, /* Virtual Machines supported */
1786 FNM_ISCSI_INI_MODE = 0x10, /* iSCSI initiator supported */
1787 FNM_ISCSI_TGT_MODE = 0x20, /* iSCSI target plus initiator */
1788 FNM_FCOE_INI_MODE = 0x40, /* FCoE Initiator supported */
1789 FNM_FCOE_TGT_MODE = 0x80, /* FCoE target supported */
1790 FNM_DAL_MODE = 0x100, /* DAL supported */
1791 FNM_LRO_MODE = 0x200, /* LRO supported */
1792 FNM_FLEX10_MODE = 0x400, /* QinQ, FLEX-10 or VNIC */
1793 FNM_NCSI_MODE = 0x800, /* NCSI supported */
1794 FNM_IPV6_MODE = 0x1000, /* IPV6 stack enabled */
1795 FNM_BE2_COMPAT_MODE = 0x2000, /* BE2 compatibility (BE3 disable)*/
1796 FNM_INVALID_MODE = 0x8000, /* Invalid */
1797 FNM_BE3_COMPAT_MODE = 0x10000, /* BE3 features */
1798 FNM_VNIC_MODE = 0x20000, /* Set when IBM vNIC mode is set */
1799 FNM_VNTAG_MODE = 0x40000, /* Set when VNTAG mode is set */
1800 FNM_UMC_MODE = 0x1000000, /* Set when UMC mode is set */
1801 FNM_UMC_DEF_EN = 0x100000, /* Set when UMC Default is set */
1802 FNM_ONE_GB_EN = 0x200000, /* Set when 1GB Default is set */
1803 FNM_VNIC_DEF_VALID = 0x400000, /* Set when VNIC_DEF_EN is valid */
1804 FNM_VNIC_DEF_EN = 0x800000 /* Set when VNIC Default enabled */
1808 struct mbx_common_config_vlan {
1824 struct normal_vlan normal_vlans[64];
1825 struct qinq_vlan qinq_vlans[32];
1835 typedef struct iface_rx_filter_ctx {
1836 uint32_t global_flags_mask;
1837 uint32_t global_flags;
1838 uint32_t iface_flags_mask;
1839 uint32_t iface_flags;
1841 #define IFACE_RX_NUM_MCAST_MAX 64
1843 struct mbx_mcast_addr {
1845 } mac[IFACE_RX_NUM_MCAST_MAX];
1846 } iface_rx_filter_ctx_t;
1848 /* [34] OPCODE_COMMON_SET_IFACE_RX_FILTER */
1849 struct mbx_set_common_iface_rx_filter {
1852 iface_rx_filter_ctx_t req;
1853 iface_rx_filter_ctx_t rsp;
1863 /* [41] OPCODE_COMMON_MODIFY_EQ_DELAY */
1864 struct mbx_modify_common_eq_delay {
1882 /* [32] OPCODE_COMMON_GET_CNTL_ATTRIBUTES */
1884 struct mgmt_hba_attr {
1885 int8_t flashrom_ver_str[32];
1886 int8_t manufac_name[32];
1887 uint32_t supp_modes;
1888 int8_t seeprom_ver_lo;
1889 int8_t seeprom_ver_hi;
1891 uint32_t ioctl_data_struct_ver;
1892 uint32_t ep_fw_data_struct_ver;
1893 uint8_t ncsi_ver_str[12];
1894 uint32_t def_ext_to;
1895 int8_t cntl_mod_num[32];
1896 int8_t cntl_desc[64];
1897 int8_t cntl_ser_num[32];
1898 int8_t ip_ver_str[32];
1899 int8_t fw_ver_str[32];
1900 int8_t bios_ver_str[32];
1901 int8_t redboot_ver_str[32];
1902 int8_t drv_ver_str[32];
1903 int8_t fw_on_flash_ver_str[32];
1904 uint32_t funcs_supp;
1905 uint16_t max_cdblen;
1907 uint8_t gen_guid[16];
1908 uint8_t hba_port_count;
1909 uint16_t default_link_down_timeout;
1910 uint8_t iscsi_ver_min_max;
1911 uint8_t multifunc_dev;
1912 uint8_t cache_valid;
1914 uint8_t max_domains_supp;
1916 uint32_t fw_post_status;
1917 uint32_t hba_mtu[8];
1920 uint8_t future_u8[2];
1921 uint32_t future_u32[3];
1924 struct mgmt_cntl_attr {
1925 struct mgmt_hba_attr hba_attr;
1926 uint16_t pci_vendor_id;
1927 uint16_t pci_device_id;
1928 uint16_t pci_sub_vendor_id;
1929 uint16_t pci_sub_system_id;
1930 uint8_t pci_bus_num;
1931 uint8_t pci_dev_num;
1932 uint8_t pci_func_num;
1933 uint8_t interface_type;
1937 uint32_t future_u32[4];
1940 struct mbx_common_get_cntl_attr {
1947 struct mgmt_cntl_attr cntl_attr_info;
1952 /* [59] OPCODE_ADD_COMMON_IFACE_MAC */
1953 struct mbx_add_common_iface_mac {
1958 uint8_t mac_address[6];
1967 /* [60] OPCODE_DEL_COMMON_IFACE_MAC */
1968 struct mbx_del_common_iface_mac {
1981 /* [8] OPCODE_QUERY_COMMON_MAX_MBX_BUFFER_SIZE */
1982 struct mbx_query_common_max_mbx_buffer_size {
1985 uint32_t max_ioctl_bufsz;
1989 /* [61] OPCODE_COMMON_FUNCTION_RESET */
1990 struct ioctl_common_function_reset {
1994 /* [73] OPCODE_COMMON_READ_TRANSRECEIVER_DATA */
1995 struct mbx_read_common_transrecv_data {
2005 uint32_t page_data[32];
2011 /* [80] OPCODE_COMMON_FUNCTION_LINK_CONFIG */
2012 struct mbx_common_func_link_cfg {
2024 /* [103] OPCODE_COMMON_SET_FUNCTIONAL_CAPS */
2025 #define CAP_SW_TIMESTAMPS 2
2026 #define CAP_BE3_NATIVE_ERX_API 4
2028 struct mbx_common_set_function_cap {
2032 uint32_t valid_capability_flags;
2033 uint32_t capability_flags;
2037 uint32_t valid_capability_flags;
2038 uint32_t capability_flags;
2043 struct mbx_lowlevel_test_loopback_mode {
2047 uint32_t loopback_type;
2058 uint32_t miscomp_off;
2059 uint32_t ticks_compl;
2064 struct mbx_lowlevel_set_loopback_mode {
2070 uint8_t loopback_type;
2071 uint8_t loopback_state;
2078 #define MAX_RESC_DESC 256
2079 #define RESC_DESC_SIZE 88
2080 #define ACTIVE_PROFILE 2
2081 #define NIC_RESC_DESC_TYPE_V0 0x41
2082 #define NIC_RESC_DESC_TYPE_V1 0x51
2083 /* OPCODE_COMMON_GET_FUNCTION_CONFIG */
2084 struct mbx_common_get_func_config {
2093 uint32_t desc_count;
2094 uint8_t resources[MAX_RESC_DESC * RESC_DESC_SIZE];
2100 /* OPCODE_COMMON_GET_PROFILE_CONFIG */
2102 struct mbx_common_get_profile_config {
2111 uint32_t desc_count;
2112 uint8_t resources[MAX_RESC_DESC * RESC_DESC_SIZE];
2117 struct oce_nic_resc_desc {
2126 uint16_t unicast_mac_count;
2129 uint16_t vlan_count;
2130 uint16_t mcast_mac_count;
2133 uint16_t rssq_count;
2136 uint16_t toe_conn_count;
2144 uint8_t acpi_params;
2152 struct flash_file_hdr {
2154 uint8_t ufi_version[4];
2160 uint8_t asic_type_rev;
2166 uint32_t imageoffset;
2167 uint32_t imagelength;
2168 uint32_t image_checksum;
2169 uint8_t image_version[32];
2172 struct flash_section_hdr {
2173 uint32_t format_rev;
2176 uint32_t num_images;
2177 uint8_t id_string[128];
2181 struct flash_section_entry {
2185 uint32_t image_size;
2187 uint32_t entry_point;
2190 uint8_t ver_data[32];
2193 struct flash_sec_info {
2195 struct flash_section_hdr fsec_hdr;
2196 struct flash_section_entry fsec_entry[32];
2200 enum LOWLEVEL_SUBSYSTEM_OPCODES {
2201 /* Opcodes used for lowlevel functions common to many subystems.
2202 * Some of these opcodes are used for diagnostic functions only.
2203 * These opcodes use the MBX_SUBSYSTEM_LOWLEVEL subsystem code.
2205 OPCODE_LOWLEVEL_TEST_LOOPBACK = 18,
2206 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE = 19,
2207 OPCODE_LOWLEVEL_GET_LOOPBACK_MODE = 20
2210 enum LLDP_SUBSYSTEM_OPCODES {
2211 /* Opcodes used for LLDP susbsytem for configuring the LLDP state machines. */
2212 OPCODE_LLDP_GET_CFG = 1,
2213 OPCODE_LLDP_SET_CFG = 2,
2214 OPCODE_LLDP_GET_STATS = 3
2217 enum DCBX_SUBSYSTEM_OPCODES {
2218 /* Opcodes used for DCBX. */
2219 OPCODE_DCBX_GET_CFG = 1,
2220 OPCODE_DCBX_SET_CFG = 2,
2221 OPCODE_DCBX_GET_MIB_INFO = 3,
2222 OPCODE_DCBX_GET_DCBX_MODE = 4,
2223 OPCODE_DCBX_SET_MODE = 5
2226 enum DMTF_SUBSYSTEM_OPCODES {
2227 /* Opcodes used for DCBX subsystem. */
2228 OPCODE_DMTF_EXEC_CLP_CMD = 1
2231 enum DIAG_SUBSYSTEM_OPCODES {
2232 /* Opcodes used for diag functions common to many subsystems. */
2233 OPCODE_DIAG_RUN_DMA_TEST = 1,
2234 OPCODE_DIAG_RUN_MDIO_TEST = 2,
2235 OPCODE_DIAG_RUN_NLB_TEST = 3,
2236 OPCODE_DIAG_RUN_ARM_TIMER_TEST = 4,
2237 OPCODE_DIAG_GET_MAC = 5
2240 enum VENDOR_SUBSYSTEM_OPCODES {
2241 /* Opcodes used for Vendor subsystem. */
2242 OPCODE_VENDOR_SLI = 1
2245 /* Management Status Codes */
2246 enum MGMT_STATUS_SUCCESS {
2249 MGMT_ILLEGAL_REQUEST = 2,
2250 MGMT_ILLEGAL_FIELD = 3,
2251 MGMT_INSUFFICIENT_BUFFER = 4,
2252 MGMT_UNAUTHORIZED_REQUEST = 5,
2253 MGMT_INVALID_ISNS_ADDRESS = 10,
2254 MGMT_INVALID_IPADDR = 11,
2255 MGMT_INVALID_GATEWAY = 12,
2256 MGMT_INVALID_SUBNETMASK = 13,
2257 MGMT_INVALID_TARGET_IPADDR = 16,
2258 MGMT_TGTTBL_FULL = 20,
2259 MGMT_FLASHROM_SAVE_FAILED = 23,
2260 MGMT_IOCTLHANDLE_ALLOC_FAILED = 27,
2261 MGMT_INVALID_SESSION = 31,
2262 MGMT_INVALID_CONNECTION = 32,
2263 MGMT_BTL_PATH_EXCEEDS_OSM_LIMIT = 33,
2264 MGMT_BTL_TGTID_EXCEEDS_OSM_LIMIT = 34,
2265 MGMT_BTL_PATH_TGTID_OCCUPIED = 35,
2266 MGMT_BTL_NO_FREE_SLOT_PATH = 36,
2267 MGMT_BTL_NO_FREE_SLOT_TGTID = 37,
2268 MGMT_POLL_IOCTL_TIMEOUT = 40,
2269 MGMT_ERROR_ACITISCSI = 41,
2270 MGMT_BUFFER_SIZE_EXCEED_OSM_OR_OS_LIMIT = 43,
2271 MGMT_REBOOT_REQUIRED = 44,
2272 MGMT_INSUFFICIENT_TIMEOUT = 45,
2273 MGMT_IPADDR_NOT_SET = 46,
2274 MGMT_IPADDR_DUP_DETECTED = 47,
2275 MGMT_CANT_REMOVE_LAST_CONNECTION = 48,
2276 MGMT_TARGET_BUSY = 49,
2277 MGMT_TGT_ERR_LISTEN_SOCKET = 50,
2278 MGMT_TGT_ERR_BIND_SOCKET = 51,
2279 MGMT_TGT_ERR_NO_SOCKET = 52,
2280 MGMT_TGT_ERR_ISNS_COMM_FAILED = 55,
2281 MGMT_CANNOT_DELETE_BOOT_TARGET = 56,
2282 MGMT_TGT_PORTAL_MODE_IN_LISTEN = 57,
2283 MGMT_FCF_IN_USE = 58 ,
2285 MGMT_TARGET_NOT_FOUND = 65,
2286 MGMT_NOT_SUPPORTED = 66,
2287 MGMT_NO_FCF_RECORDS = 67,
2288 MGMT_FEATURE_NOT_SUPPORTED = 68,
2289 MGMT_VPD_FUNCTION_OUT_OF_RANGE = 69,
2290 MGMT_VPD_FUNCTION_TYPE_INCORRECT = 70,
2291 MGMT_INVALID_NON_EMBEDDED_WRB = 71,
2293 MGMT_INVALID_PD = 101,
2294 MGMT_STATUS_PD_INUSE = 102,
2295 MGMT_INVALID_CQ = 103,
2296 MGMT_INVALID_QP = 104,
2297 MGMT_INVALID_STAG = 105,
2298 MGMT_ORD_EXCEEDS = 106,
2299 MGMT_IRD_EXCEEDS = 107,
2300 MGMT_SENDQ_WQE_EXCEEDS = 108,
2301 MGMT_RECVQ_RQE_EXCEEDS = 109,
2302 MGMT_SGE_SEND_EXCEEDS = 110,
2303 MGMT_SGE_WRITE_EXCEEDS = 111,
2304 MGMT_SGE_RECV_EXCEEDS = 112,
2305 MGMT_INVALID_STATE_CHANGE = 113,
2306 MGMT_MW_BOUND = 114,
2307 MGMT_INVALID_VA = 115,
2308 MGMT_INVALID_LENGTH = 116,
2309 MGMT_INVALID_FBO = 117,
2310 MGMT_INVALID_ACC_RIGHTS = 118,
2311 MGMT_INVALID_PBE_SIZE = 119,
2312 MGMT_INVALID_PBL_ENTRY = 120,
2313 MGMT_INVALID_PBL_OFFSET = 121,
2314 MGMT_ADDR_NON_EXIST = 122,
2315 MGMT_INVALID_VLANID = 123,
2316 MGMT_INVALID_MTU = 124,
2317 MGMT_INVALID_BACKLOG = 125,
2318 MGMT_CONNECTION_INPROGRESS = 126,
2319 MGMT_INVALID_RQE_SIZE = 127,
2320 MGMT_INVALID_RQE_ENTRY = 128
2323 /* Additional Management Status Codes */
2324 enum MGMT_ADDI_STATUS {
2325 MGMT_ADDI_NO_STATUS = 0,
2326 MGMT_ADDI_INVALID_IPTYPE = 1,
2327 MGMT_ADDI_TARGET_HANDLE_NOT_FOUND = 9,
2328 MGMT_ADDI_SESSION_HANDLE_NOT_FOUND = 10,
2329 MGMT_ADDI_CONNECTION_HANDLE_NOT_FOUND = 11,
2330 MGMT_ADDI_ACTIVE_SESSIONS_PRESENT = 16,
2331 MGMT_ADDI_SESSION_ALREADY_OPENED = 17,
2332 MGMT_ADDI_SESSION_ALREADY_CLOSED = 18,
2333 MGMT_ADDI_DEST_HOST_UNREACHABLE = 19,
2334 MGMT_ADDI_LOGIN_IN_PROGRESS = 20,
2335 MGMT_ADDI_TCP_CONNECT_FAILED = 21,
2336 MGMT_ADDI_INSUFFICIENT_RESOURCES = 22,
2337 MGMT_ADDI_LINK_DOWN = 23,
2338 MGMT_ADDI_DHCP_ERROR = 24,
2339 MGMT_ADDI_CONNECTION_OFFLOADED = 25,
2340 MGMT_ADDI_CONNECTION_NOT_OFFLOADED = 26,
2341 MGMT_ADDI_CONNECTION_UPLOAD_IN_PROGRESS = 27,
2342 MGMT_ADDI_REQUEST_REJECTED = 28,
2343 MGMT_ADDI_INVALID_SUBSYSTEM = 29,
2344 MGMT_ADDI_INVALID_OPCODE = 30,
2345 MGMT_ADDI_INVALID_MAXCONNECTION_PARAM = 31,
2346 MGMT_ADDI_INVALID_KEY = 32,
2347 MGMT_ADDI_INVALID_DOMAIN = 35,
2348 MGMT_ADDI_LOGIN_INITIATOR_ERROR = 43,
2349 MGMT_ADDI_LOGIN_AUTHENTICATION_ERROR = 44,
2350 MGMT_ADDI_LOGIN_AUTHORIZATION_ERROR = 45,
2351 MGMT_ADDI_LOGIN_NOT_FOUND = 46,
2352 MGMT_ADDI_LOGIN_TARGET_REMOVED = 47,
2353 MGMT_ADDI_LOGIN_UNSUPPORTED_VERSION = 48,
2354 MGMT_ADDI_LOGIN_TOO_MANY_CONNECTIONS = 49,
2355 MGMT_ADDI_LOGIN_MISSING_PARAMETER = 50,
2356 MGMT_ADDI_LOGIN_NO_SESSION_SPANNING = 51,
2357 MGMT_ADDI_LOGIN_SESSION_TYPE_NOT_SUPPORTED = 52,
2358 MGMT_ADDI_LOGIN_SESSION_DOES_NOT_EXIST = 53,
2359 MGMT_ADDI_LOGIN_INVALID_DURING_LOGIN = 54,
2360 MGMT_ADDI_LOGIN_TARGET_ERROR = 55,
2361 MGMT_ADDI_LOGIN_SERVICE_UNAVAILABLE = 56,
2362 MGMT_ADDI_LOGIN_OUT_OF_RESOURCES = 57,
2363 MGMT_ADDI_SAME_CHAP_SECRET = 58,
2364 MGMT_ADDI_INVALID_SECRET_LENGTH = 59,
2365 MGMT_ADDI_DUPLICATE_ENTRY = 60,
2366 MGMT_ADDI_SETTINGS_MODIFIED_REBOOT_REQD = 63,
2367 MGMT_ADDI_INVALID_EXTENDED_TIMEOUT = 64,
2368 MGMT_ADDI_INVALID_INTERFACE_HANDLE = 65,
2369 MGMT_ADDI_ERR_VLAN_ON_DEF_INTERFACE = 66,
2370 MGMT_ADDI_INTERFACE_DOES_NOT_EXIST = 67,
2371 MGMT_ADDI_INTERFACE_ALREADY_EXISTS = 68,
2372 MGMT_ADDI_INVALID_VLAN_RANGE = 69,
2373 MGMT_ADDI_ERR_SET_VLAN = 70,
2374 MGMT_ADDI_ERR_DEL_VLAN = 71,
2375 MGMT_ADDI_CANNOT_DEL_DEF_INTERFACE = 72,
2376 MGMT_ADDI_DHCP_REQ_ALREADY_PENDING = 73,
2377 MGMT_ADDI_TOO_MANY_INTERFACES = 74,
2378 MGMT_ADDI_INVALID_REQUEST = 75
2381 enum NIC_SUBSYSTEM_OPCODES {
2383 * @brief NIC Subsystem Opcodes (see Network SLI-4 manual >= Rev4, v21-2)
2384 * These opcodes are used for configuring the Ethernet interfaces.
2385 * These opcodes all use the MBX_SUBSYSTEM_NIC subsystem code.
2388 NIC_CONFIG_ACPI = 2,
2389 NIC_CONFIG_PROMISCUOUS = 3,
2395 NIC_CONFIG_ACPI_WOL_MAGIC = 12,
2396 NIC_GET_NETWORK_STATS = 13,
2397 NIC_CREATE_HDS_RQ = 16,
2398 NIC_DELETE_HDS_RQ = 17,
2399 NIC_GET_PPORT_STATS = 18,
2400 NIC_GET_VPORT_STATS = 19,
2401 NIC_GET_QUEUE_STATS = 20
2404 /* Hash option flags for RSS enable */
2405 enum RSS_ENABLE_FLAGS {
2406 RSS_ENABLE_NONE = 0x0, /* (No RSS) */
2407 RSS_ENABLE_IPV4 = 0x1, /* (IPV4 HASH enabled ) */
2408 RSS_ENABLE_TCP_IPV4 = 0x2, /* (TCP IPV4 Hash enabled) */
2409 RSS_ENABLE_IPV6 = 0x4, /* (IPV6 HASH enabled) */
2410 RSS_ENABLE_TCP_IPV6 = 0x8, /* (TCP IPV6 HASH */
2411 RSS_ENABLE_UDP_IPV4 = 0x10, /* UDP IPV4 HASH */
2412 RSS_ENABLE_UDP_IPV6 = 0x20 /* UDP IPV6 HASH */
2414 #define RSS_ENABLE (RSS_ENABLE_IPV4 | RSS_ENABLE_TCP_IPV4)
2415 #define RSS_DISABLE RSS_ENABLE_NONE
2417 /* NIC header WQE */
2418 struct oce_nic_hdr_wqe {
2426 uint32_t last_seg_udp_len:14;
2430 uint32_t lso_mss:14;
2443 uint32_t complete:1;
2446 uint32_t vlan_tag:16;
2447 uint32_t total_length:16;
2454 uint32_t last_seg_udp_len:14;
2457 uint32_t complete:1;
2470 uint32_t lso_mss:14;
2473 uint32_t total_length:16;
2474 uint32_t vlan_tag:16;
2481 /* NIC fragment WQE */
2482 struct oce_nic_frag_wqe {
2486 uint32_t frag_pa_hi;
2488 uint32_t frag_pa_lo;
2497 /* Ethernet Tx Completion Descriptor */
2498 struct oce_nic_tx_cqe {
2507 uint32_t wqe_index:16;
2511 uint32_t cast_enc:2;
2513 uint32_t nwh_bytes:8;
2514 uint32_t user_bytes:16;
2523 uint32_t num_pkts:16;
2526 uint32_t wqe_index:16;
2533 uint32_t user_bytes:16;
2534 uint32_t nwh_bytes:8;
2536 uint32_t cast_enc:2;
2542 uint32_t num_pkts:16;
2551 #define WQ_CQE_VALID(_cqe) (_cqe->u0.dw[3])
2552 #define WQ_CQE_INVALIDATE(_cqe) (_cqe->u0.dw[3] = 0)
2554 /* Receive Queue Entry (RQE) */
2555 struct oce_nic_rqe {
2558 uint32_t frag_pa_hi;
2559 uint32_t frag_pa_lo;
2565 /* NIC Receive CQE */
2566 struct oce_nic_rx_cqe {
2571 uint32_t ip_options:1;
2573 uint32_t pkt_size:14;
2574 uint32_t vlan_tag:16;
2577 uint32_t num_fragments:3;
2578 uint32_t switched:1;
2580 uint32_t frag_index:10;
2582 uint32_t vlan_tag_present:1;
2585 uint32_t l4_cksum_pass:1;
2586 uint32_t ip_cksum_pass:1;
2587 uint32_t udpframe:1;
2588 uint32_t tcpframe:1;
2595 uint32_t hds_type:2;
2598 uint32_t hds_hdr_size:12;
2599 uint32_t hds_hdr_frag_index:10;
2600 uint32_t rss_bank:1;
2602 uint32_t pkt_type:2;
2603 uint32_t rss_flush:1;
2606 uint32_t rss_hash_value;
2609 uint32_t vlan_tag:16;
2610 uint32_t pkt_size:14;
2612 uint32_t ip_options:1;
2617 uint32_t tcpframe:1;
2618 uint32_t udpframe:1;
2619 uint32_t ip_cksum_pass:1;
2620 uint32_t l4_cksum_pass:1;
2623 uint32_t vlan_tag_present:1;
2625 uint32_t frag_index:10;
2627 uint32_t switched:1;
2628 uint32_t num_fragments:3;
2631 uint32_t rss_flush:1;
2632 uint32_t pkt_type:2;
2634 uint32_t rss_bank:1;
2635 uint32_t hds_hdr_frag_index:10;
2636 uint32_t hds_hdr_size:12;
2639 uint32_t hds_type:2;
2642 uint32_t rss_hash_value;
2648 /* NIC Receive CQE_v1 */
2649 struct oce_nic_rx_cqe_v1 {
2654 uint32_t ip_options:1;
2655 uint32_t vlan_tag_present:1;
2656 uint32_t pkt_size:14;
2657 uint32_t vlan_tag:16;
2660 uint32_t num_fragments:3;
2661 uint32_t switched:1;
2663 uint32_t frag_index:10;
2667 uint32_t l4_cksum_pass:1;
2668 uint32_t ip_cksum_pass:1;
2669 uint32_t udpframe:1;
2670 uint32_t tcpframe:1;
2678 uint32_t hds_hdr_size:
2679 uint32_t hds_hdr_frag_index:8;
2682 uint32_t rss_bank:1;
2684 uint32_t pkt_type:2;
2685 uint32_t rss_flush:1;
2688 uint32_t rss_hash_value;
2691 uint32_t vlan_tag:16;
2692 uint32_t pkt_size:14;
2693 uint32_t vlan_tag_present:1;
2694 uint32_t ip_options:1;
2699 uint32_t tcpframe:1;
2700 uint32_t udpframe:1;
2701 uint32_t ip_cksum_pass:1;
2702 uint32_t l4_cksum_pass:1;
2706 uint32_t frag_index:10;
2708 uint32_t switched:1;
2709 uint32_t num_fragments:3;
2712 uint32_t rss_flush:1;
2713 uint32_t pkt_type:2;
2715 uint32_t rss_bank:1;
2718 uint32_t hds_hdr_frag_index:8;
2719 uint32_t hds_hdr_size:2;
2723 uint32_t rss_hash_value;
2730 #define RQ_CQE_VALID_MASK 0x80
2731 #define RQ_CQE_VALID(_cqe) (_cqe->u0.dw[2])
2732 #define RQ_CQE_INVALIDATE(_cqe) (_cqe->u0.dw[2] = 0)
2734 struct mbx_config_nic_promiscuous {
2740 uint8_t port1_promisc;
2741 uint8_t port0_promisc;
2743 uint8_t port0_promisc;
2744 uint8_t port1_promisc;
2755 typedef union oce_wq_ctx_u {
2760 uint32_t dw4rsvd2:8;
2761 uint32_t nic_wq_type:8;
2762 uint32_t dw4rsvd1:8;
2763 uint32_t num_pages:8;
2765 uint32_t dw5rsvd2:12;
2767 uint32_t dw5rsvd1:16;
2770 uint32_t dw6rsvd1:31;
2772 uint32_t dw7rsvd1:16;
2776 uint32_t num_pages:8;
2778 uint32_t dw4rsvd1:8;
2780 /* PSP: this workaround is not documented: fill 0x01 for ulp_mask */
2781 uint32_t ulp_mask:8;
2783 uint32_t nic_wq_type:8;
2784 uint32_t dw4rsvd2:8;
2786 uint32_t dw5rsvd1:16;
2788 uint32_t dw5rsvd2:12;
2790 uint32_t dw6rsvd1:31;
2794 uint32_t dw7rsvd1:16;
2797 uint32_t dw8_20rsvd1[13];
2802 uint32_t dw4rsvd2:8;
2803 uint32_t nic_wq_type:8;
2804 uint32_t dw4rsvd1:8;
2805 uint32_t num_pages:8;
2807 uint32_t dw5rsvd2:12;
2809 uint32_t iface_id:16;
2812 uint32_t dw6rsvd1:31;
2814 uint32_t dw7rsvd1:16;
2818 uint32_t num_pages:8;
2819 uint32_t dw4rsvd1:8;
2820 uint32_t nic_wq_type:8;
2821 uint32_t dw4rsvd2:8;
2823 uint32_t iface_id:16;
2825 uint32_t dw5rsvd2:12;
2827 uint32_t dw6rsvd1:31;
2831 uint32_t dw7rsvd1:16;
2834 uint32_t dw8_20rsvd1[13];
2839 * @brief [07] NIC_CREATE_WQ
2841 * Lancer requires an InterfaceID to be specified with every WQ. This
2842 * is the basis for NIC IOV where the Interface maps to a vPort and maps
2843 * to both Tx and Rx sides.
2845 #define OCE_WQ_TYPE_FORWARDING 0x1 /* wq forwards pkts to TOE */
2846 #define OCE_WQ_TYPE_STANDARD 0x2 /* wq sends network pkts */
2847 struct mbx_create_nic_wq {
2853 uint16_t nic_wq_type;
2861 struct phys_addr pages[8];
2875 /* [09] NIC_DELETE_WQ */
2876 struct mbx_delete_nic_wq {
2899 struct mbx_create_nic_rq {
2906 struct phys_addr pages[2];
2908 uint16_t max_frame_size;
2910 uint32_t is_rss_queue;
2924 /* [10] NIC_DELETE_RQ */
2925 struct mbx_delete_nic_rq {
2932 uint16_t bypass_flush;
2937 uint16_t bypass_flush;
2951 struct oce_port_rxf_stats_v0 {
2952 uint32_t rx_bytes_lsd; /* dword 0*/
2953 uint32_t rx_bytes_msd; /* dword 1*/
2954 uint32_t rx_total_frames; /* dword 2*/
2955 uint32_t rx_unicast_frames; /* dword 3*/
2956 uint32_t rx_multicast_frames; /* dword 4*/
2957 uint32_t rx_broadcast_frames; /* dword 5*/
2958 uint32_t rx_crc_errors; /* dword 6*/
2959 uint32_t rx_alignment_symbol_errors; /* dword 7*/
2960 uint32_t rx_pause_frames; /* dword 8*/
2961 uint32_t rx_control_frames; /* dword 9*/
2962 uint32_t rx_in_range_errors; /* dword 10*/
2963 uint32_t rx_out_range_errors; /* dword 11*/
2964 uint32_t rx_frame_too_long; /* dword 12*/
2965 uint32_t rx_address_match_errors; /* dword 13*/
2966 uint32_t rx_vlan_mismatch; /* dword 14*/
2967 uint32_t rx_dropped_too_small; /* dword 15*/
2968 uint32_t rx_dropped_too_short; /* dword 16*/
2969 uint32_t rx_dropped_header_too_small; /* dword 17*/
2970 uint32_t rx_dropped_tcp_length; /* dword 18*/
2971 uint32_t rx_dropped_runt; /* dword 19*/
2972 uint32_t rx_64_byte_packets; /* dword 20*/
2973 uint32_t rx_65_127_byte_packets; /* dword 21*/
2974 uint32_t rx_128_256_byte_packets; /* dword 22*/
2975 uint32_t rx_256_511_byte_packets; /* dword 23*/
2976 uint32_t rx_512_1023_byte_packets; /* dword 24*/
2977 uint32_t rx_1024_1518_byte_packets; /* dword 25*/
2978 uint32_t rx_1519_2047_byte_packets; /* dword 26*/
2979 uint32_t rx_2048_4095_byte_packets; /* dword 27*/
2980 uint32_t rx_4096_8191_byte_packets; /* dword 28*/
2981 uint32_t rx_8192_9216_byte_packets; /* dword 29*/
2982 uint32_t rx_ip_checksum_errs; /* dword 30*/
2983 uint32_t rx_tcp_checksum_errs; /* dword 31*/
2984 uint32_t rx_udp_checksum_errs; /* dword 32*/
2985 uint32_t rx_non_rss_packets; /* dword 33*/
2986 uint32_t rx_ipv4_packets; /* dword 34*/
2987 uint32_t rx_ipv6_packets; /* dword 35*/
2988 uint32_t rx_ipv4_bytes_lsd; /* dword 36*/
2989 uint32_t rx_ipv4_bytes_msd; /* dword 37*/
2990 uint32_t rx_ipv6_bytes_lsd; /* dword 38*/
2991 uint32_t rx_ipv6_bytes_msd; /* dword 39*/
2992 uint32_t rx_chute1_packets; /* dword 40*/
2993 uint32_t rx_chute2_packets; /* dword 41*/
2994 uint32_t rx_chute3_packets; /* dword 42*/
2995 uint32_t rx_management_packets; /* dword 43*/
2996 uint32_t rx_switched_unicast_packets; /* dword 44*/
2997 uint32_t rx_switched_multicast_packets; /* dword 45*/
2998 uint32_t rx_switched_broadcast_packets; /* dword 46*/
2999 uint32_t tx_bytes_lsd; /* dword 47*/
3000 uint32_t tx_bytes_msd; /* dword 48*/
3001 uint32_t tx_unicastframes; /* dword 49*/
3002 uint32_t tx_multicastframes; /* dword 50*/
3003 uint32_t tx_broadcastframes; /* dword 51*/
3004 uint32_t tx_pauseframes; /* dword 52*/
3005 uint32_t tx_controlframes; /* dword 53*/
3006 uint32_t tx_64_byte_packets; /* dword 54*/
3007 uint32_t tx_65_127_byte_packets; /* dword 55*/
3008 uint32_t tx_128_256_byte_packets; /* dword 56*/
3009 uint32_t tx_256_511_byte_packets; /* dword 57*/
3010 uint32_t tx_512_1023_byte_packets; /* dword 58*/
3011 uint32_t tx_1024_1518_byte_packets; /* dword 59*/
3012 uint32_t tx_1519_2047_byte_packets; /* dword 60*/
3013 uint32_t tx_2048_4095_byte_packets; /* dword 61*/
3014 uint32_t tx_4096_8191_byte_packets; /* dword 62*/
3015 uint32_t tx_8192_9216_byte_packets; /* dword 63*/
3016 uint32_t rxpp_fifo_overflow_drop; /* dword 64*/
3017 uint32_t rx_input_fifo_overflow_drop; /* dword 65*/
3021 struct oce_rxf_stats_v0 {
3022 struct oce_port_rxf_stats_v0 port[2];
3023 uint32_t rx_drops_no_pbuf; /* dword 132*/
3024 uint32_t rx_drops_no_txpb; /* dword 133*/
3025 uint32_t rx_drops_no_erx_descr; /* dword 134*/
3026 uint32_t rx_drops_no_tpre_descr; /* dword 135*/
3027 uint32_t management_rx_port_packets; /* dword 136*/
3028 uint32_t management_rx_port_bytes; /* dword 137*/
3029 uint32_t management_rx_port_pause_frames;/* dword 138*/
3030 uint32_t management_rx_port_errors; /* dword 139*/
3031 uint32_t management_tx_port_packets; /* dword 140*/
3032 uint32_t management_tx_port_bytes; /* dword 141*/
3033 uint32_t management_tx_port_pause; /* dword 142*/
3034 uint32_t management_rx_port_rxfifo_overflow; /* dword 143*/
3035 uint32_t rx_drops_too_many_frags; /* dword 144*/
3036 uint32_t rx_drops_invalid_ring; /* dword 145*/
3037 uint32_t forwarded_packets; /* dword 146*/
3038 uint32_t rx_drops_mtu; /* dword 147*/
3040 uint32_t port0_jabber_events;
3041 uint32_t port1_jabber_events;
3045 struct oce_port_rxf_stats_v2 {
3047 uint32_t roce_bytes_received_lsd;
3048 uint32_t roce_bytes_received_msd;
3050 uint32_t roce_frames_received;
3051 uint32_t rx_crc_errors;
3052 uint32_t rx_alignment_symbol_errors;
3053 uint32_t rx_pause_frames;
3054 uint32_t rx_priority_pause_frames;
3055 uint32_t rx_control_frames;
3056 uint32_t rx_in_range_errors;
3057 uint32_t rx_out_range_errors;
3058 uint32_t rx_frame_too_long;
3059 uint32_t rx_address_match_errors;
3060 uint32_t rx_dropped_too_small;
3061 uint32_t rx_dropped_too_short;
3062 uint32_t rx_dropped_header_too_small;
3063 uint32_t rx_dropped_tcp_length;
3064 uint32_t rx_dropped_runt;
3066 uint32_t rx_ip_checksum_errs;
3067 uint32_t rx_tcp_checksum_errs;
3068 uint32_t rx_udp_checksum_errs;
3070 uint32_t rx_switched_unicast_packets;
3071 uint32_t rx_switched_multicast_packets;
3072 uint32_t rx_switched_broadcast_packets;
3074 uint32_t tx_pauseframes;
3075 uint32_t tx_priority_pauseframes;
3076 uint32_t tx_controlframes;
3078 uint32_t rxpp_fifo_overflow_drop;
3079 uint32_t rx_input_fifo_overflow_drop;
3080 uint32_t pmem_fifo_overflow_drop;
3081 uint32_t jabber_events;
3083 uint32_t rx_drops_payload_size;
3084 uint32_t rx_drops_clipped_header;
3085 uint32_t rx_drops_crc;
3086 uint32_t roce_drops_payload_len;
3087 uint32_t roce_drops_crc;
3092 struct oce_port_rxf_stats_v1 {
3094 uint32_t rx_crc_errors;
3095 uint32_t rx_alignment_symbol_errors;
3096 uint32_t rx_pause_frames;
3097 uint32_t rx_priority_pause_frames;
3098 uint32_t rx_control_frames;
3099 uint32_t rx_in_range_errors;
3100 uint32_t rx_out_range_errors;
3101 uint32_t rx_frame_too_long;
3102 uint32_t rx_address_match_errors;
3103 uint32_t rx_dropped_too_small;
3104 uint32_t rx_dropped_too_short;
3105 uint32_t rx_dropped_header_too_small;
3106 uint32_t rx_dropped_tcp_length;
3107 uint32_t rx_dropped_runt;
3109 uint32_t rx_ip_checksum_errs;
3110 uint32_t rx_tcp_checksum_errs;
3111 uint32_t rx_udp_checksum_errs;
3113 uint32_t rx_switched_unicast_packets;
3114 uint32_t rx_switched_multicast_packets;
3115 uint32_t rx_switched_broadcast_packets;
3117 uint32_t tx_pauseframes;
3118 uint32_t tx_priority_pauseframes;
3119 uint32_t tx_controlframes;
3121 uint32_t rxpp_fifo_overflow_drop;
3122 uint32_t rx_input_fifo_overflow_drop;
3123 uint32_t pmem_fifo_overflow_drop;
3124 uint32_t jabber_events;
3128 struct oce_rxf_stats_v2 {
3129 struct oce_port_rxf_stats_v2 port[4];
3131 uint32_t rx_drops_no_pbuf;
3132 uint32_t rx_drops_no_txpb;
3133 uint32_t rx_drops_no_erx_descr;
3134 uint32_t rx_drops_no_tpre_descr;
3136 uint32_t rx_drops_too_many_frags;
3137 uint32_t rx_drops_invalid_ring;
3138 uint32_t forwarded_packets;
3139 uint32_t rx_drops_mtu;
3143 struct oce_rxf_stats_v1 {
3144 struct oce_port_rxf_stats_v1 port[4];
3146 uint32_t rx_drops_no_pbuf;
3147 uint32_t rx_drops_no_txpb;
3148 uint32_t rx_drops_no_erx_descr;
3149 uint32_t rx_drops_no_tpre_descr;
3151 uint32_t rx_drops_too_many_frags;
3152 uint32_t rx_drops_invalid_ring;
3153 uint32_t forwarded_packets;
3154 uint32_t rx_drops_mtu;
3158 struct oce_erx_stats_v2 {
3159 uint32_t rx_drops_no_fragments[136];
3163 struct oce_erx_stats_v1 {
3164 uint32_t rx_drops_no_fragments[68];
3169 struct oce_erx_stats_v0 {
3170 uint32_t rx_drops_no_fragments[44];
3174 struct oce_pmem_stats {
3175 uint32_t eth_red_drops;
3179 struct oce_hw_stats_v2 {
3180 struct oce_rxf_stats_v2 rxf;
3181 uint32_t rsvd0[OCE_TXP_SW_SZ];
3182 struct oce_erx_stats_v2 erx;
3183 struct oce_pmem_stats pmem;
3188 struct oce_hw_stats_v1 {
3189 struct oce_rxf_stats_v1 rxf;
3190 uint32_t rsvd0[OCE_TXP_SW_SZ];
3191 struct oce_erx_stats_v1 erx;
3192 struct oce_pmem_stats pmem;
3196 struct oce_hw_stats_v0 {
3197 struct oce_rxf_stats_v0 rxf;
3199 struct oce_erx_stats_v0 erx;
3200 struct oce_pmem_stats pmem;
3203 #define MBX_GET_NIC_STATS(version) \
3204 struct mbx_get_nic_stats_v##version { \
3205 struct mbx_hdr hdr; \
3211 struct oce_hw_stats_v##version stats; \
3216 MBX_GET_NIC_STATS(0);
3217 MBX_GET_NIC_STATS(1);
3218 MBX_GET_NIC_STATS(2);
3220 /* [18(0x12)] NIC_GET_PPORT_STATS */
3221 struct pport_stats {
3223 uint64_t tx_unicast_pkts;
3224 uint64_t tx_multicast_pkts;
3225 uint64_t tx_broadcast_pkts;
3227 uint64_t tx_unicast_bytes;
3228 uint64_t tx_multicast_bytes;
3229 uint64_t tx_broadcast_bytes;
3230 uint64_t tx_discards;
3232 uint64_t tx_pause_frames;
3233 uint64_t tx_pause_on_frames;
3234 uint64_t tx_pause_off_frames;
3235 uint64_t tx_internal_mac_errors;
3236 uint64_t tx_control_frames;
3237 uint64_t tx_pkts_64_bytes;
3238 uint64_t tx_pkts_65_to_127_bytes;
3239 uint64_t tx_pkts_128_to_255_bytes;
3240 uint64_t tx_pkts_256_to_511_bytes;
3241 uint64_t tx_pkts_512_to_1023_bytes;
3242 uint64_t tx_pkts_1024_to_1518_bytes;
3243 uint64_t tx_pkts_1519_to_2047_bytes;
3244 uint64_t tx_pkts_2048_to_4095_bytes;
3245 uint64_t tx_pkts_4096_to_8191_bytes;
3246 uint64_t tx_pkts_8192_to_9216_bytes;
3247 uint64_t tx_lso_pkts;
3249 uint64_t rx_unicast_pkts;
3250 uint64_t rx_multicast_pkts;
3251 uint64_t rx_broadcast_pkts;
3253 uint64_t rx_unicast_bytes;
3254 uint64_t rx_multicast_bytes;
3255 uint64_t rx_broadcast_bytes;
3256 uint32_t rx_unknown_protos;
3257 uint32_t reserved_word69;
3258 uint64_t rx_discards;
3260 uint64_t rx_crc_errors;
3261 uint64_t rx_alignment_errors;
3262 uint64_t rx_symbol_errors;
3263 uint64_t rx_pause_frames;
3264 uint64_t rx_pause_on_frames;
3265 uint64_t rx_pause_off_frames;
3266 uint64_t rx_frames_too_long;
3267 uint64_t rx_internal_mac_errors;
3268 uint32_t rx_undersize_pkts;
3269 uint32_t rx_oversize_pkts;
3270 uint32_t rx_fragment_pkts;
3271 uint32_t rx_jabbers;
3272 uint64_t rx_control_frames;
3273 uint64_t rx_control_frames_unknown_opcode;
3274 uint32_t rx_in_range_errors;
3275 uint32_t rx_out_of_range_errors;
3276 uint32_t rx_address_match_errors;
3277 uint32_t rx_vlan_mismatch_errors;
3278 uint32_t rx_dropped_too_small;
3279 uint32_t rx_dropped_too_short;
3280 uint32_t rx_dropped_header_too_small;
3281 uint32_t rx_dropped_invalid_tcp_length;
3282 uint32_t rx_dropped_runt;
3283 uint32_t rx_ip_checksum_errors;
3284 uint32_t rx_tcp_checksum_errors;
3285 uint32_t rx_udp_checksum_errors;
3286 uint32_t rx_non_rss_pkts;
3287 uint64_t reserved_word111;
3288 uint64_t rx_ipv4_pkts;
3289 uint64_t rx_ipv6_pkts;
3290 uint64_t rx_ipv4_bytes;
3291 uint64_t rx_ipv6_bytes;
3292 uint64_t rx_nic_pkts;
3293 uint64_t rx_tcp_pkts;
3294 uint64_t rx_iscsi_pkts;
3295 uint64_t rx_management_pkts;
3296 uint64_t rx_switched_unicast_pkts;
3297 uint64_t rx_switched_multicast_pkts;
3298 uint64_t rx_switched_broadcast_pkts;
3299 uint64_t num_forwards;
3300 uint32_t rx_fifo_overflow;
3301 uint32_t rx_input_fifo_overflow;
3302 uint64_t rx_drops_too_many_frags;
3303 uint32_t rx_drops_invalid_queue;
3304 uint32_t reserved_word141;
3305 uint64_t rx_drops_mtu;
3306 uint64_t rx_pkts_64_bytes;
3307 uint64_t rx_pkts_65_to_127_bytes;
3308 uint64_t rx_pkts_128_to_255_bytes;
3309 uint64_t rx_pkts_256_to_511_bytes;
3310 uint64_t rx_pkts_512_to_1023_bytes;
3311 uint64_t rx_pkts_1024_to_1518_bytes;
3312 uint64_t rx_pkts_1519_to_2047_bytes;
3313 uint64_t rx_pkts_2048_to_4095_bytes;
3314 uint64_t rx_pkts_4096_to_8191_bytes;
3315 uint64_t rx_pkts_8192_to_9216_bytes;
3318 struct mbx_get_pport_stats {
3325 uint32_t reset_stats:8;
3327 uint32_t port_number:16;
3329 uint32_t port_number:16;
3331 uint32_t reset_stats:8;
3336 struct pport_stats pps;
3337 uint32_t pport_stats[164 - 4 + 1];
3342 /* [19(0x13)] NIC_GET_VPORT_STATS */
3343 struct vport_stats {
3345 uint64_t tx_unicast_pkts;
3346 uint64_t tx_multicast_pkts;
3347 uint64_t tx_broadcast_pkts;
3349 uint64_t tx_unicast_bytes;
3350 uint64_t tx_multicast_bytes;
3351 uint64_t tx_broadcast_bytes;
3352 uint64_t tx_discards;
3354 uint64_t tx_pkts_64_bytes;
3355 uint64_t tx_pkts_65_to_127_bytes;
3356 uint64_t tx_pkts_128_to_255_bytes;
3357 uint64_t tx_pkts_256_to_511_bytes;
3358 uint64_t tx_pkts_512_to_1023_bytes;
3359 uint64_t tx_pkts_1024_to_1518_bytes;
3360 uint64_t tx_pkts_1519_to_9699_bytes;
3361 uint64_t tx_pkts_over_9699_bytes;
3363 uint64_t rx_unicast_pkts;
3364 uint64_t rx_multicast_pkts;
3365 uint64_t rx_broadcast_pkts;
3367 uint64_t rx_unicast_bytes;
3368 uint64_t rx_multicast_bytes;
3369 uint64_t rx_broadcast_bytes;
3370 uint64_t rx_discards;
3372 uint64_t rx_pkts_64_bytes;
3373 uint64_t rx_pkts_65_to_127_bytes;
3374 uint64_t rx_pkts_128_to_255_bytes;
3375 uint64_t rx_pkts_256_to_511_bytes;
3376 uint64_t rx_pkts_512_to_1023_bytes;
3377 uint64_t rx_pkts_1024_to_1518_bytes;
3378 uint64_t rx_pkts_1519_to_9699_bytes;
3379 uint64_t rx_pkts_gt_9699_bytes;
3381 struct mbx_get_vport_stats {
3388 uint32_t reset_stats:8;
3390 uint32_t vport_number:16;
3392 uint32_t vport_number:16;
3394 uint32_t reset_stats:8;
3399 struct vport_stats vps;
3400 uint32_t vport_stats[75 - 4 + 1];
3406 * @brief [20(0x14)] NIC_GET_QUEUE_STATS
3407 * The significant difference between vPort and Queue statistics is
3408 * the packet byte counters.
3410 struct queue_stats {
3415 uint64_t buffer_errors; /* rsvd when tx */
3418 #define QUEUE_TYPE_WQ 0
3419 #define QUEUE_TYPE_RQ 1
3420 #define QUEUE_TYPE_HDS_RQ 1 /* same as RQ */
3422 struct mbx_get_queue_stats {
3429 uint32_t reset_stats:8;
3430 uint32_t queue_type:8;
3431 uint32_t queue_id:16;
3433 uint32_t queue_id:16;
3434 uint32_t queue_type:8;
3435 uint32_t reset_stats:8;
3440 struct queue_stats qs;
3441 uint32_t queue_stats[13 - 4 + 1];
3447 /* [01] NIC_CONFIG_RSS */
3448 #define OCE_HASH_TBL_SZ 10
3449 #define OCE_CPU_TBL_SZ 128
3450 #define OCE_FLUSH 1 /* RSS flush completion per CQ port */
3451 struct mbx_config_nic_rss {
3457 uint16_t cpu_tbl_sz_log2;
3458 uint16_t enable_rss;
3459 uint32_t hash[OCE_HASH_TBL_SZ];
3460 uint8_t cputable[OCE_CPU_TBL_SZ];
3465 uint16_t enable_rss;
3466 uint16_t cpu_tbl_sz_log2;
3467 uint32_t hash[OCE_HASH_TBL_SZ];
3468 uint8_t cputable[OCE_CPU_TBL_SZ];
3484 typedef uint32_t oce_stat_t; /* statistic counter */
3486 enum OCE_RXF_PORT_STATS {
3489 RXF_RX_TOTAL_FRAMES,
3490 RXF_RX_UNICAST_FRAMES,
3491 RXF_RX_MULTICAST_FRAMES,
3492 RXF_RX_BROADCAST_FRAMES,
3494 RXF_RX_ALIGNMENT_SYMBOL_ERRORS,
3495 RXF_RX_PAUSE_FRAMES,
3496 RXF_RX_CONTROL_FRAMES,
3497 RXF_RX_IN_RANGE_ERRORS,
3498 RXF_RX_OUT_RANGE_ERRORS,
3499 RXF_RX_FRAME_TOO_LONG,
3500 RXF_RX_ADDRESS_MATCH_ERRORS,
3501 RXF_RX_VLAN_MISMATCH,
3502 RXF_RX_DROPPED_TOO_SMALL,
3503 RXF_RX_DROPPED_TOO_SHORT,
3504 RXF_RX_DROPPED_HEADER_TOO_SMALL,
3505 RXF_RX_DROPPED_TCP_LENGTH,
3506 RXF_RX_DROPPED_RUNT,
3507 RXF_RX_64_BYTE_PACKETS,
3508 RXF_RX_65_127_BYTE_PACKETS,
3509 RXF_RX_128_256_BYTE_PACKETS,
3510 RXF_RX_256_511_BYTE_PACKETS,
3511 RXF_RX_512_1023_BYTE_PACKETS,
3512 RXF_RX_1024_1518_BYTE_PACKETS,
3513 RXF_RX_1519_2047_BYTE_PACKETS,
3514 RXF_RX_2048_4095_BYTE_PACKETS,
3515 RXF_RX_4096_8191_BYTE_PACKETS,
3516 RXF_RX_8192_9216_BYTE_PACKETS,
3517 RXF_RX_IP_CHECKSUM_ERRS,
3518 RXF_RX_TCP_CHECKSUM_ERRS,
3519 RXF_RX_UDP_CHECKSUM_ERRS,
3520 RXF_RX_NON_RSS_PACKETS,
3521 RXF_RX_IPV4_PACKETS,
3522 RXF_RX_IPV6_PACKETS,
3523 RXF_RX_IPV4_BYTES_LSD,
3524 RXF_RX_IPV4_BYTES_MSD,
3525 RXF_RX_IPV6_BYTES_LSD,
3526 RXF_RX_IPV6_BYTES_MSD,
3527 RXF_RX_CHUTE1_PACKETS,
3528 RXF_RX_CHUTE2_PACKETS,
3529 RXF_RX_CHUTE3_PACKETS,
3530 RXF_RX_MANAGEMENT_PACKETS,
3531 RXF_RX_SWITCHED_UNICAST_PACKETS,
3532 RXF_RX_SWITCHED_MULTICAST_PACKETS,
3533 RXF_RX_SWITCHED_BROADCAST_PACKETS,
3536 RXF_TX_UNICAST_FRAMES,
3537 RXF_TX_MULTICAST_FRAMES,
3538 RXF_TX_BROADCAST_FRAMES,
3539 RXF_TX_PAUSE_FRAMES,
3540 RXF_TX_CONTROL_FRAMES,
3541 RXF_TX_64_BYTE_PACKETS,
3542 RXF_TX_65_127_BYTE_PACKETS,
3543 RXF_TX_128_256_BYTE_PACKETS,
3544 RXF_TX_256_511_BYTE_PACKETS,
3545 RXF_TX_512_1023_BYTE_PACKETS,
3546 RXF_TX_1024_1518_BYTE_PACKETS,
3547 RXF_TX_1519_2047_BYTE_PACKETS,
3548 RXF_TX_2048_4095_BYTE_PACKETS,
3549 RXF_TX_4096_8191_BYTE_PACKETS,
3550 RXF_TX_8192_9216_BYTE_PACKETS,
3551 RXF_RX_FIFO_OVERFLOW,
3552 RXF_RX_INPUT_FIFO_OVERFLOW,
3553 RXF_PORT_STATS_N_WORDS
3556 enum OCE_RXF_ADDL_STATS {
3557 RXF_RX_DROPS_NO_PBUF,
3558 RXF_RX_DROPS_NO_TXPB,
3559 RXF_RX_DROPS_NO_ERX_DESCR,
3560 RXF_RX_DROPS_NO_TPRE_DESCR,
3561 RXF_MANAGEMENT_RX_PORT_PACKETS,
3562 RXF_MANAGEMENT_RX_PORT_BYTES,
3563 RXF_MANAGEMENT_RX_PORT_PAUSE_FRAMES,
3564 RXF_MANAGEMENT_RX_PORT_ERRORS,
3565 RXF_MANAGEMENT_TX_PORT_PACKETS,
3566 RXF_MANAGEMENT_TX_PORT_BYTES,
3567 RXF_MANAGEMENT_TX_PORT_PAUSE,
3568 RXF_MANAGEMENT_RX_PORT_RXFIFO_OVERFLOW,
3569 RXF_RX_DROPS_TOO_MANY_FRAGS,
3570 RXF_RX_DROPS_INVALID_RING,
3571 RXF_FORWARDED_PACKETS,
3573 RXF_ADDL_STATS_N_WORDS
3576 enum OCE_TX_CHUTE_PORT_STATS {
3583 CTPT_REXMT_IPV4_PKTs,
3584 CTPT_REXMT_IPV4_LSD,
3585 CTPT_REXMT_IPV4_MSD,
3586 CTPT_REXMT_IPV6_PKTs,
3587 CTPT_REXMT_IPV6_LSD,
3588 CTPT_REXMT_IPV6_MSD,
3592 enum OCE_RX_ERR_STATS {
3593 RX_DROPS_NO_FRAGMENTS_0,
3594 RX_DROPS_NO_FRAGMENTS_1,
3595 RX_DROPS_NO_FRAGMENTS_2,
3596 RX_DROPS_NO_FRAGMENTS_3,
3597 RX_DROPS_NO_FRAGMENTS_4,
3598 RX_DROPS_NO_FRAGMENTS_5,
3599 RX_DROPS_NO_FRAGMENTS_6,
3600 RX_DROPS_NO_FRAGMENTS_7,
3601 RX_DROPS_NO_FRAGMENTS_8,
3602 RX_DROPS_NO_FRAGMENTS_9,
3603 RX_DROPS_NO_FRAGMENTS_10,
3604 RX_DROPS_NO_FRAGMENTS_11,
3605 RX_DROPS_NO_FRAGMENTS_12,
3606 RX_DROPS_NO_FRAGMENTS_13,
3607 RX_DROPS_NO_FRAGMENTS_14,
3608 RX_DROPS_NO_FRAGMENTS_15,
3609 RX_DROPS_NO_FRAGMENTS_16,
3610 RX_DROPS_NO_FRAGMENTS_17,
3611 RX_DROPS_NO_FRAGMENTS_18,
3612 RX_DROPS_NO_FRAGMENTS_19,
3613 RX_DROPS_NO_FRAGMENTS_20,
3614 RX_DROPS_NO_FRAGMENTS_21,
3615 RX_DROPS_NO_FRAGMENTS_22,
3616 RX_DROPS_NO_FRAGMENTS_23,
3617 RX_DROPS_NO_FRAGMENTS_24,
3618 RX_DROPS_NO_FRAGMENTS_25,
3619 RX_DROPS_NO_FRAGMENTS_26,
3620 RX_DROPS_NO_FRAGMENTS_27,
3621 RX_DROPS_NO_FRAGMENTS_28,
3622 RX_DROPS_NO_FRAGMENTS_29,
3623 RX_DROPS_NO_FRAGMENTS_30,
3624 RX_DROPS_NO_FRAGMENTS_31,
3625 RX_DROPS_NO_FRAGMENTS_32,
3626 RX_DROPS_NO_FRAGMENTS_33,
3627 RX_DROPS_NO_FRAGMENTS_34,
3628 RX_DROPS_NO_FRAGMENTS_35,
3629 RX_DROPS_NO_FRAGMENTS_36,
3630 RX_DROPS_NO_FRAGMENTS_37,
3631 RX_DROPS_NO_FRAGMENTS_38,
3632 RX_DROPS_NO_FRAGMENTS_39,
3633 RX_DROPS_NO_FRAGMENTS_40,
3634 RX_DROPS_NO_FRAGMENTS_41,
3635 RX_DROPS_NO_FRAGMENTS_42,
3636 RX_DROPS_NO_FRAGMENTS_43,
3637 RX_DEBUG_WDMA_SENT_HOLD,
3638 RX_DEBUG_WDMA_PBFREE_SENT_HOLD,
3639 RX_DEBUG_WDMA_0B_PBFREE_SENT_HOLD,
3640 RX_DEBUG_PMEM_PBUF_DEALLOC,
3644 enum OCE_PMEM_ERR_STATS {
3647 PMEM_ULP0_RED_DROPS,
3648 PMEM_ULP1_RED_DROPS,
3649 PMEM_GLOBAL_RED_DROPS,
3654 * @brief Statistics for a given Physical Port
3655 * These satisfy all the required BE2 statistics and also the
3656 * following MIB objects:
3658 * RFC 2863 - The Interfaces Group MIB
3659 * RFC 2819 - Remote Network Monitoring Management Information Base (RMON)
3660 * RFC 3635 - Managed Objects for the Ethernet-like Interface Types
3661 * RFC 4502 - Remote Network Monitoring Mgmt Information Base Ver-2 (RMON2)
3664 enum OCE_PPORT_STATS {
3666 PPORT_TX_UNICAST_PKTS = 2,
3667 PPORT_TX_MULTICAST_PKTS = 4,
3668 PPORT_TX_BROADCAST_PKTS = 6,
3670 PPORT_TX_UNICAST_BYTES = 10,
3671 PPORT_TX_MULTICAST_BYTES = 12,
3672 PPORT_TX_BROADCAST_BYTES = 14,
3673 PPORT_TX_DISCARDS = 16,
3674 PPORT_TX_ERRORS = 18,
3675 PPORT_TX_PAUSE_FRAMES = 20,
3676 PPORT_TX_PAUSE_ON_FRAMES = 22,
3677 PPORT_TX_PAUSE_OFF_FRAMES = 24,
3678 PPORT_TX_INTERNAL_MAC_ERRORS = 26,
3679 PPORT_TX_CONTROL_FRAMES = 28,
3680 PPORT_TX_PKTS_64_BYTES = 30,
3681 PPORT_TX_PKTS_65_TO_127_BYTES = 32,
3682 PPORT_TX_PKTS_128_TO_255_BYTES = 34,
3683 PPORT_TX_PKTS_256_TO_511_BYTES = 36,
3684 PPORT_TX_PKTS_512_TO_1023_BYTES = 38,
3685 PPORT_TX_PKTS_1024_TO_1518_BYTES = 40,
3686 PPORT_TX_PKTS_1519_TO_2047_BYTES = 42,
3687 PPORT_TX_PKTS_2048_TO_4095_BYTES = 44,
3688 PPORT_TX_PKTS_4096_TO_8191_BYTES = 46,
3689 PPORT_TX_PKTS_8192_TO_9216_BYTES = 48,
3690 PPORT_TX_LSO_PKTS = 50,
3692 PPORT_RX_UNICAST_PKTS = 54,
3693 PPORT_RX_MULTICAST_PKTS = 56,
3694 PPORT_RX_BROADCAST_PKTS = 58,
3695 PPORT_RX_BYTES = 60,
3696 PPORT_RX_UNICAST_BYTES = 62,
3697 PPORT_RX_MULTICAST_BYTES = 64,
3698 PPORT_RX_BROADCAST_BYTES = 66,
3699 PPORT_RX_UNKNOWN_PROTOS = 68,
3700 PPORT_RESERVED_WORD69 = 69,
3701 PPORT_RX_DISCARDS = 70,
3702 PPORT_RX_ERRORS = 72,
3703 PPORT_RX_CRC_ERRORS = 74,
3704 PPORT_RX_ALIGNMENT_ERRORS = 76,
3705 PPORT_RX_SYMBOL_ERRORS = 78,
3706 PPORT_RX_PAUSE_FRAMES = 80,
3707 PPORT_RX_PAUSE_ON_FRAMES = 82,
3708 PPORT_RX_PAUSE_OFF_FRAMES = 84,
3709 PPORT_RX_FRAMES_TOO_LONG = 86,
3710 PPORT_RX_INTERNAL_MAC_ERRORS = 88,
3711 PPORT_RX_UNDERSIZE_PKTS = 90,
3712 PPORT_RX_OVERSIZE_PKTS = 91,
3713 PPORT_RX_FRAGMENT_PKTS = 92,
3714 PPORT_RX_JABBERS = 93,
3715 PPORT_RX_CONTROL_FRAMES = 94,
3716 PPORT_RX_CONTROL_FRAMES_UNK_OPCODE = 96,
3717 PPORT_RX_IN_RANGE_ERRORS = 98,
3718 PPORT_RX_OUT_OF_RANGE_ERRORS = 99,
3719 PPORT_RX_ADDRESS_MATCH_ERRORS = 100,
3720 PPORT_RX_VLAN_MISMATCH_ERRORS = 101,
3721 PPORT_RX_DROPPED_TOO_SMALL = 102,
3722 PPORT_RX_DROPPED_TOO_SHORT = 103,
3723 PPORT_RX_DROPPED_HEADER_TOO_SMALL = 104,
3724 PPORT_RX_DROPPED_INVALID_TCP_LENGTH = 105,
3725 PPORT_RX_DROPPED_RUNT = 106,
3726 PPORT_RX_IP_CHECKSUM_ERRORS = 107,
3727 PPORT_RX_TCP_CHECKSUM_ERRORS = 108,
3728 PPORT_RX_UDP_CHECKSUM_ERRORS = 109,
3729 PPORT_RX_NON_RSS_PKTS = 110,
3730 PPORT_RESERVED_WORD111 = 111,
3731 PPORT_RX_IPV4_PKTS = 112,
3732 PPORT_RX_IPV6_PKTS = 114,
3733 PPORT_RX_IPV4_BYTES = 116,
3734 PPORT_RX_IPV6_BYTES = 118,
3735 PPORT_RX_NIC_PKTS = 120,
3736 PPORT_RX_TCP_PKTS = 122,
3737 PPORT_RX_ISCSI_PKTS = 124,
3738 PPORT_RX_MANAGEMENT_PKTS = 126,
3739 PPORT_RX_SWITCHED_UNICAST_PKTS = 128,
3740 PPORT_RX_SWITCHED_MULTICAST_PKTS = 130,
3741 PPORT_RX_SWITCHED_BROADCAST_PKTS = 132,
3742 PPORT_NUM_FORWARDS = 134,
3743 PPORT_RX_FIFO_OVERFLOW = 136,
3744 PPORT_RX_INPUT_FIFO_OVERFLOW = 137,
3745 PPORT_RX_DROPS_TOO_MANY_FRAGS = 138,
3746 PPORT_RX_DROPS_INVALID_QUEUE = 140,
3747 PPORT_RESERVED_WORD141 = 141,
3748 PPORT_RX_DROPS_MTU = 142,
3749 PPORT_RX_PKTS_64_BYTES = 144,
3750 PPORT_RX_PKTS_65_TO_127_BYTES = 146,
3751 PPORT_RX_PKTS_128_TO_255_BYTES = 148,
3752 PPORT_RX_PKTS_256_TO_511_BYTES = 150,
3753 PPORT_RX_PKTS_512_TO_1023_BYTES = 152,
3754 PPORT_RX_PKTS_1024_TO_1518_BYTES = 154,
3755 PPORT_RX_PKTS_1519_TO_2047_BYTES = 156,
3756 PPORT_RX_PKTS_2048_TO_4095_BYTES = 158,
3757 PPORT_RX_PKTS_4096_TO_8191_BYTES = 160,
3758 PPORT_RX_PKTS_8192_TO_9216_BYTES = 162,
3763 * @brief Statistics for a given Virtual Port (vPort)
3764 * The following describes the vPort statistics satisfying
3765 * requirements of Linux/VMWare netdev statistics and
3766 * Microsoft Windows Statistics along with other Operating Systems.
3768 enum OCE_VPORT_STATS {
3770 VPORT_TX_UNICAST_PKTS = 2,
3771 VPORT_TX_MULTICAST_PKTS = 4,
3772 VPORT_TX_BROADCAST_PKTS = 6,
3774 VPORT_TX_UNICAST_BYTES = 10,
3775 VPORT_TX_MULTICAST_BYTES = 12,
3776 VPORT_TX_BROADCAST_BYTES = 14,
3777 VPORT_TX_DISCARDS = 16,
3778 VPORT_TX_ERRORS = 18,
3779 VPORT_TX_PKTS_64_BYTES = 20,
3780 VPORT_TX_PKTS_65_TO_127_BYTES = 22,
3781 VPORT_TX_PKTS_128_TO_255_BYTES = 24,
3782 VPORT_TX_PKTS_256_TO_511_BYTES = 26,
3783 VPORT_TX_PKTS_512_TO_1023_BYTEs = 28,
3784 VPORT_TX_PKTS_1024_TO_1518_BYTEs = 30,
3785 VPORT_TX_PKTS_1519_TO_9699_BYTEs = 32,
3786 VPORT_TX_PKTS_OVER_9699_BYTES = 34,
3788 VPORT_RX_UNICAST_PKTS = 38,
3789 VPORT_RX_MULTICAST_PKTS = 40,
3790 VPORT_RX_BROADCAST_PKTS = 42,
3791 VPORT_RX_BYTES = 44,
3792 VPORT_RX_UNICAST_BYTES = 46,
3793 VPORT_RX_MULTICAST_BYTES = 48,
3794 VPORT_RX_BROADCAST_BYTES = 50,
3795 VPORT_RX_DISCARDS = 52,
3796 VPORT_RX_ERRORS = 54,
3797 VPORT_RX_PKTS_64_BYTES = 56,
3798 VPORT_RX_PKTS_65_TO_127_BYTES = 58,
3799 VPORT_RX_PKTS_128_TO_255_BYTES = 60,
3800 VPORT_RX_PKTS_256_TO_511_BYTES = 62,
3801 VPORT_RX_PKTS_512_TO_1023_BYTEs = 64,
3802 VPORT_RX_PKTS_1024_TO_1518_BYTEs = 66,
3803 VPORT_RX_PKTS_1519_TO_9699_BYTEs = 68,
3804 VPORT_RX_PKTS_OVER_9699_BYTES = 70,
3809 * @brief Statistics for a given queue (NIC WQ, RQ, or HDS RQ)
3810 * This set satisfies requirements of VMQare NetQueue and Microsoft VMQ
3812 enum OCE_QUEUE_TX_STATS {
3815 QUEUE_TX_ERRORS = 4,
3817 QUEUE_TX_N_WORDS = 8
3820 enum OCE_QUEUE_RX_STATS {
3823 QUEUE_RX_ERRORS = 4,
3825 QUEUE_RX_BUFFER_ERRORS = 8,
3826 QUEUE_RX_N_WORDS = 10
3829 /* HW LRO structures */
3830 struct mbx_nic_query_lro_capabilities {
3839 uint16_t lro_rq_cnt;
3840 uint16_t plro_max_offload;
3844 uint16_t plro_max_offload;
3845 uint16_t lro_rq_cnt;
3852 struct mbx_nic_set_iface_lro_config {
3859 uint32_t max_clsc_byte_cnt;
3860 uint32_t max_clsc_seg_cnt;
3861 uint32_t max_clsc_usec_delay;
3862 uint32_t min_clsc_frame_byte_cnt;
3867 uint32_t max_clsc_byte_cnt;
3868 uint32_t max_clsc_seg_cnt;
3869 uint32_t max_clsc_usec_delay;
3870 uint32_t min_clsc_frame_byte_cnt;
3887 struct mbx_create_nic_rq_v2 {
3899 uint16_t max_frame_size;
3907 uint16_t hds_fixed_offset;
3911 uint16_t hds_backfill_size;
3912 uint16_t hds_frag_size;
3918 struct phys_addr pages[2];
3926 uint16_t max_frame_size;
3937 uint16_t hds_fixed_offset;
3939 uint16_t hds_frag_size;
3940 uint16_t hds_backfill_size;
3946 struct phys_addr pages[2];
3987 struct mbx_delete_nic_rq_v1 {
3992 uint16_t bypass_flush;
3998 uint16_t bypass_flush;
4009 struct nic_hwlro_singleton_cqe {
4014 uint32_t pkt_size:14;
4015 uint32_t vlan_tag:16;
4018 uint32_t num_frags:3;
4020 uint32_t frag_index:10;
4022 uint32_t ipv6_frame:1;
4023 uint32_t l4_cksum_pass:1;
4024 uint32_t ip_cksum_pass:1;
4025 uint32_t udpframe:1;
4026 uint32_t tcpframe:1;
4033 uint32_t cqe_type:2;
4036 uint32_t data_offset:8;
4038 uint32_t rss_bank:1;
4043 uint32_t rss_hash_value;
4046 uint32_t vlan_tag:16;
4047 uint32_t pkt_size:14;
4055 uint32_t tcpframe:1;
4056 uint32_t udpframe:1;
4057 uint32_t ip_cksum_pass:1;
4058 uint32_t l4_cksum_pass:1;
4059 uint32_t ipv6_frame:1;
4061 uint32_t frag_index:10;
4063 uint32_t num_frags:3;
4068 uint32_t rss_bank:1;
4070 uint32_t data_offset:8;
4073 uint32_t cqe_type:2;
4077 uint32_t rss_hash_value;
4081 struct nic_hwlro_cqe_part1 {
4084 uint32_t tcp_timestamp_val;
4087 uint32_t tcp_timestamp_ecr;
4091 uint32_t cqe_type:2;
4093 uint32_t rss_policy:4;
4095 uint32_t data_offset:8;
4097 uint32_t lro_desc:1;
4098 uint32_t lro_timer_pop:1;
4099 uint32_t rss_bank:1;
4102 uint32_t rss_flush:1;
4105 uint32_t rss_hash_value;
4108 uint32_t tcp_timestamp_val;
4111 uint32_t tcp_timestamp_ecr;
4114 uint32_t rss_flush:1;
4117 uint32_t rss_bank:1;
4118 uint32_t lro_timer_pop:1;
4119 uint32_t lro_desc:1;
4121 uint32_t data_offset:8;
4123 uint32_t rss_policy:4;
4125 uint32_t cqe_type:2;
4129 uint32_t rss_hash_value;
4133 struct nic_hwlro_cqe_part2 {
4138 uint32_t pkt_size:14;
4139 uint32_t vlan_tag:16;
4142 uint32_t tcp_window:16;
4143 uint32_t coalesced_size:16;
4147 uint32_t cqe_type:2;
4151 uint32_t threshold:1;
4153 uint32_t frame_lifespan:8;
4154 uint32_t ipv6_frame:1;
4155 uint32_t l4_cksum_pass:1;
4156 uint32_t ip_cksum_pass:1;
4157 uint32_t udpframe:1;
4158 uint32_t tcpframe:1;
4164 uint32_t tcp_ack_num;
4167 uint32_t vlan_tag:16;
4168 uint32_t pkt_size:14;
4173 uint32_t coalesced_size:16;
4174 uint32_t tcp_window:16;
4180 uint32_t tcpframe:1;
4181 uint32_t udpframe:1;
4182 uint32_t ip_cksum_pass:1;
4183 uint32_t l4_cksum_pass:1;
4184 uint32_t ipv6_frame:1;
4185 uint32_t frame_lifespan:8;
4187 uint32_t threshold:1;
4191 uint32_t cqe_type:2;
4195 uint32_t tcp_ack_num;