2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (C) 2013 Emulex
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of the Emulex Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
33 * Contact Information:
34 * freebsd-drivers@emulex.com
38 * Costa Mesa, CA 92626
43 #include "opt_inet6.h"
49 #define is_tso_pkt(m) (m->m_pkthdr.csum_flags & CSUM_TSO)
51 /* UE Status Low CSR */
52 static char *ue_status_low_desc[] = {
87 /* UE Status High CSR */
88 static char *ue_status_hi_desc[] = {
123 struct oce_common_cqe_info{
125 uint8_t l4_cksum_pass:1;
126 uint8_t ip_cksum_pass:1;
127 uint8_t ipv6_frame:1;
135 /* Driver entry points prototypes */
136 static int oce_probe(device_t dev);
137 static int oce_attach(device_t dev);
138 static int oce_detach(device_t dev);
139 static int oce_shutdown(device_t dev);
140 static int oce_ioctl(if_t ifp, u_long command, caddr_t data);
141 static void oce_init(void *xsc);
142 static int oce_multiq_start(if_t ifp, struct mbuf *m);
143 static void oce_multiq_flush(if_t ifp);
145 /* Driver interrupt routines protypes */
146 static void oce_intr(void *arg, int pending);
147 static int oce_setup_intr(POCE_SOFTC sc);
148 static int oce_fast_isr(void *arg);
149 static int oce_alloc_intr(POCE_SOFTC sc, int vector,
150 void (*isr) (void *arg, int pending));
152 /* Media callbacks prototypes */
153 static void oce_media_status(if_t ifp, struct ifmediareq *req);
154 static int oce_media_change(if_t ifp);
156 /* Transmit routines prototypes */
157 static int oce_tx(POCE_SOFTC sc, struct mbuf **mpp, int wq_index);
158 static void oce_tx_restart(POCE_SOFTC sc, struct oce_wq *wq);
159 static void oce_process_tx_completion(struct oce_wq *wq);
160 static int oce_multiq_transmit(if_t ifp, struct mbuf *m,
163 /* Receive routines prototypes */
164 static int oce_cqe_vtp_valid(POCE_SOFTC sc, struct oce_nic_rx_cqe *cqe);
165 static int oce_cqe_portid_valid(POCE_SOFTC sc, struct oce_nic_rx_cqe *cqe);
166 static void oce_rx(struct oce_rq *rq, struct oce_nic_rx_cqe *cqe);
167 static void oce_check_rx_bufs(POCE_SOFTC sc, uint32_t num_cqes, struct oce_rq *rq);
168 static uint16_t oce_rq_handler_lro(void *arg);
169 static void oce_correct_header(struct mbuf *m, struct nic_hwlro_cqe_part1 *cqe1, struct nic_hwlro_cqe_part2 *cqe2);
170 static void oce_rx_lro(struct oce_rq *rq, struct nic_hwlro_singleton_cqe *cqe, struct nic_hwlro_cqe_part2 *cqe2);
171 static void oce_rx_mbuf_chain(struct oce_rq *rq, struct oce_common_cqe_info *cqe_info, struct mbuf **m);
173 /* Helper function prototypes in this file */
174 static int oce_attach_ifp(POCE_SOFTC sc);
175 static void oce_add_vlan(void *arg, if_t ifp, uint16_t vtag);
176 static void oce_del_vlan(void *arg, if_t ifp, uint16_t vtag);
177 static int oce_vid_config(POCE_SOFTC sc);
178 static void oce_mac_addr_set(POCE_SOFTC sc);
179 static int oce_handle_passthrough(if_t ifp, caddr_t data);
180 static void oce_local_timer(void *arg);
181 static void oce_if_deactivate(POCE_SOFTC sc);
182 static void oce_if_activate(POCE_SOFTC sc);
183 static void setup_max_queues_want(POCE_SOFTC sc);
184 static void update_queues_got(POCE_SOFTC sc);
185 static void process_link_state(POCE_SOFTC sc,
186 struct oce_async_cqe_link_state *acqe);
187 static int oce_tx_asic_stall_verify(POCE_SOFTC sc, struct mbuf *m);
188 static void oce_get_config(POCE_SOFTC sc);
189 static struct mbuf *oce_insert_vlan_tag(POCE_SOFTC sc, struct mbuf *m, boolean_t *complete);
190 static void oce_read_env_variables(POCE_SOFTC sc);
193 #if defined(INET6) || defined(INET)
194 static int oce_init_lro(POCE_SOFTC sc);
195 static struct mbuf * oce_tso_setup(POCE_SOFTC sc, struct mbuf **mpp);
198 static device_method_t oce_dispatch[] = {
199 DEVMETHOD(device_probe, oce_probe),
200 DEVMETHOD(device_attach, oce_attach),
201 DEVMETHOD(device_detach, oce_detach),
202 DEVMETHOD(device_shutdown, oce_shutdown),
207 static driver_t oce_driver = {
214 const char component_revision[32] = {"///" COMPONENT_REVISION "///"};
216 /* Module capabilites and parameters */
217 uint32_t oce_max_rsp_handled = OCE_MAX_RSP_HANDLED;
218 uint32_t oce_enable_rss = OCE_MODCAP_RSS;
219 uint32_t oce_rq_buf_size = 2048;
221 TUNABLE_INT("hw.oce.max_rsp_handled", &oce_max_rsp_handled);
222 TUNABLE_INT("hw.oce.enable_rss", &oce_enable_rss);
224 /* Supported devices table */
225 static uint32_t supportedDevices[] = {
226 (PCI_VENDOR_SERVERENGINES << 16) | PCI_PRODUCT_BE2,
227 (PCI_VENDOR_SERVERENGINES << 16) | PCI_PRODUCT_BE3,
228 (PCI_VENDOR_EMULEX << 16) | PCI_PRODUCT_BE3,
229 (PCI_VENDOR_EMULEX << 16) | PCI_PRODUCT_XE201,
230 (PCI_VENDOR_EMULEX << 16) | PCI_PRODUCT_XE201_VF,
231 (PCI_VENDOR_EMULEX << 16) | PCI_PRODUCT_SH
234 DRIVER_MODULE(oce, pci, oce_driver, 0, 0);
235 MODULE_PNP_INFO("W32:vendor/device", pci, oce, supportedDevices,
236 nitems(supportedDevices));
237 MODULE_DEPEND(oce, pci, 1, 1, 1);
238 MODULE_DEPEND(oce, ether, 1, 1, 1);
239 MODULE_VERSION(oce, 1);
241 POCE_SOFTC softc_head = NULL;
242 POCE_SOFTC softc_tail = NULL;
244 struct oce_rdma_if *oce_rdma_if = NULL;
246 /*****************************************************************************
247 * Driver entry points functions *
248 *****************************************************************************/
251 oce_probe(device_t dev)
259 sc = device_get_softc(dev);
260 bzero(sc, sizeof(OCE_SOFTC));
263 vendor = pci_get_vendor(dev);
264 device = pci_get_device(dev);
266 for (i = 0; i < (sizeof(supportedDevices) / sizeof(uint32_t)); i++) {
267 if (vendor == ((supportedDevices[i] >> 16) & 0xffff)) {
268 if (device == (supportedDevices[i] & 0xffff)) {
269 sprintf(str, "%s:%s", "Emulex CNA NIC function",
271 device_set_desc_copy(dev, str);
274 case PCI_PRODUCT_BE2:
275 sc->flags |= OCE_FLAGS_BE2;
277 case PCI_PRODUCT_BE3:
278 sc->flags |= OCE_FLAGS_BE3;
280 case PCI_PRODUCT_XE201:
281 case PCI_PRODUCT_XE201_VF:
282 sc->flags |= OCE_FLAGS_XE201;
285 sc->flags |= OCE_FLAGS_SH;
290 return BUS_PROBE_DEFAULT;
299 oce_attach(device_t dev)
304 sc = device_get_softc(dev);
306 rc = oce_hw_pci_alloc(sc);
310 sc->tx_ring_size = OCE_TX_RING_SIZE;
311 sc->rx_ring_size = OCE_RX_RING_SIZE;
312 /* receive fragment size should be multiple of 2K */
313 sc->rq_frag_size = ((oce_rq_buf_size / 2048) * 2048);
314 sc->flow_control = OCE_DEFAULT_FLOW_CONTROL;
315 sc->promisc = OCE_DEFAULT_PROMISCUOUS;
317 LOCK_CREATE(&sc->bmbx_lock, "Mailbox_lock");
318 LOCK_CREATE(&sc->dev_lock, "Device_lock");
320 /* initialise the hardware */
321 rc = oce_hw_init(sc);
325 oce_read_env_variables(sc);
329 setup_max_queues_want(sc);
331 rc = oce_setup_intr(sc);
335 rc = oce_queue_init_all(sc);
339 rc = oce_attach_ifp(sc);
343 #if defined(INET6) || defined(INET)
344 rc = oce_init_lro(sc);
349 rc = oce_hw_start(sc);
353 sc->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
354 oce_add_vlan, sc, EVENTHANDLER_PRI_FIRST);
355 sc->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
356 oce_del_vlan, sc, EVENTHANDLER_PRI_FIRST);
358 rc = oce_stats_init(sc);
364 callout_init(&sc->timer, CALLOUT_MPSAFE);
365 rc = callout_reset(&sc->timer, 2 * hz, oce_local_timer, sc);
370 if (softc_tail != NULL) {
371 softc_tail->next = sc;
380 callout_drain(&sc->timer);
384 EVENTHANDLER_DEREGISTER(vlan_config, sc->vlan_attach);
386 EVENTHANDLER_DEREGISTER(vlan_unconfig, sc->vlan_detach);
387 oce_hw_intr_disable(sc);
389 #if defined(INET6) || defined(INET)
393 ether_ifdetach(sc->ifp);
396 oce_queue_release_all(sc);
400 oce_dma_free(sc, &sc->bsmbx);
403 LOCK_DESTROY(&sc->dev_lock);
404 LOCK_DESTROY(&sc->bmbx_lock);
410 oce_detach(device_t dev)
412 POCE_SOFTC sc = device_get_softc(dev);
413 POCE_SOFTC poce_sc_tmp, *ppoce_sc_tmp1, poce_sc_tmp2 = NULL;
415 poce_sc_tmp = softc_head;
416 ppoce_sc_tmp1 = &softc_head;
417 while (poce_sc_tmp != NULL) {
418 if (poce_sc_tmp == sc) {
419 *ppoce_sc_tmp1 = sc->next;
420 if (sc->next == NULL) {
421 softc_tail = poce_sc_tmp2;
425 poce_sc_tmp2 = poce_sc_tmp;
426 ppoce_sc_tmp1 = &poce_sc_tmp->next;
427 poce_sc_tmp = poce_sc_tmp->next;
431 oce_if_deactivate(sc);
432 UNLOCK(&sc->dev_lock);
434 callout_drain(&sc->timer);
436 if (sc->vlan_attach != NULL)
437 EVENTHANDLER_DEREGISTER(vlan_config, sc->vlan_attach);
438 if (sc->vlan_detach != NULL)
439 EVENTHANDLER_DEREGISTER(vlan_unconfig, sc->vlan_detach);
441 ether_ifdetach(sc->ifp);
447 bus_generic_detach(dev);
453 oce_shutdown(device_t dev)
457 rc = oce_detach(dev);
463 oce_ioctl(if_t ifp, u_long command, caddr_t data)
465 struct ifreq *ifr = (struct ifreq *)data;
466 POCE_SOFTC sc = if_getsoftc(ifp);
474 rc = ifmedia_ioctl(ifp, ifr, &sc->media, command);
478 if (ifr->ifr_mtu > OCE_MAX_MTU)
481 if_setmtu(ifp, ifr->ifr_mtu);
485 if (if_getflags(ifp) & IFF_UP) {
486 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
487 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
490 device_printf(sc->dev, "Interface Up\n");
494 if_setdrvflagbits(sc->ifp, 0,
495 IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
496 oce_if_deactivate(sc);
498 UNLOCK(&sc->dev_lock);
500 device_printf(sc->dev, "Interface Down\n");
503 if ((if_getflags(ifp) & IFF_PROMISC) && !sc->promisc) {
504 if (!oce_rxf_set_promiscuous(sc, (1 | (1 << 1))))
506 } else if (!(if_getflags(ifp) & IFF_PROMISC) && sc->promisc) {
507 if (!oce_rxf_set_promiscuous(sc, 0))
515 rc = oce_hw_update_multicast(sc);
517 device_printf(sc->dev,
518 "Update multicast address failed\n");
522 u = ifr->ifr_reqcap ^ if_getcapenable(ifp);
524 if (u & IFCAP_TXCSUM) {
525 if_togglecapenable(ifp, IFCAP_TXCSUM);
526 if_togglehwassist(ifp, (CSUM_TCP | CSUM_UDP | CSUM_IP));
528 if (IFCAP_TSO & if_getcapenable(ifp) &&
529 !(IFCAP_TXCSUM & if_getcapenable(ifp))) {
531 if_setcapenablebit(ifp, 0, IFCAP_TSO);
532 if_sethwassistbits(ifp, 0, CSUM_TSO);
534 "TSO disabled due to -txcsum.\n");
538 if (u & IFCAP_RXCSUM)
539 if_togglecapenable(ifp, IFCAP_RXCSUM);
541 if (u & IFCAP_TSO4) {
542 if_togglecapenable(ifp, IFCAP_TSO4);
544 if (IFCAP_TSO & if_getcapenable(ifp)) {
545 if (IFCAP_TXCSUM & if_getcapenable(ifp))
546 if_sethwassistbits(ifp, CSUM_TSO, 0);
548 if_setcapenablebit(ifp, 0, IFCAP_TSO);
549 if_sethwassistbits(ifp, 0, CSUM_TSO);
551 "Enable txcsum first.\n");
555 if_sethwassistbits(ifp, 0, CSUM_TSO);
558 if (u & IFCAP_VLAN_HWTAGGING)
559 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
561 if (u & IFCAP_VLAN_HWFILTER) {
562 if_togglecapenable(ifp, IFCAP_VLAN_HWFILTER);
565 #if defined(INET6) || defined(INET)
567 if_togglecapenable(ifp, IFCAP_LRO);
568 if(sc->enable_hwlro) {
569 if(if_getcapenable(ifp) & IFCAP_LRO) {
570 rc = oce_mbox_nic_set_iface_lro_config(sc, 1);
572 rc = oce_mbox_nic_set_iface_lro_config(sc, 0);
581 rc = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
585 if (i2c.dev_addr == PAGE_NUM_A0) {
587 } else if (i2c.dev_addr == PAGE_NUM_A2) {
588 offset = TRANSCEIVER_A0_SIZE + i2c.offset;
594 if (i2c.len > sizeof(i2c.data) ||
595 i2c.len + offset > sizeof(sfp_vpd_dump_buffer)) {
600 rc = oce_mbox_read_transrecv_data(sc, i2c.dev_addr);
606 memcpy(&i2c.data[0], &sfp_vpd_dump_buffer[offset], i2c.len);
608 rc = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
612 rc = priv_check(curthread, PRIV_DRIVER);
615 rc = oce_handle_passthrough(ifp, data);
618 rc = ether_ioctl(ifp, command, data);
632 if (if_getflags(sc->ifp) & IFF_UP) {
633 oce_if_deactivate(sc);
637 UNLOCK(&sc->dev_lock);
642 oce_multiq_start(if_t ifp, struct mbuf *m)
644 POCE_SOFTC sc = if_getsoftc(ifp);
645 struct oce_wq *wq = NULL;
649 if (!sc->link_status)
652 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)
653 queue_index = m->m_pkthdr.flowid % sc->nwqs;
655 wq = sc->wq[queue_index];
658 status = oce_multiq_transmit(ifp, m, wq);
659 UNLOCK(&wq->tx_lock);
666 oce_multiq_flush(if_t ifp)
668 POCE_SOFTC sc = if_getsoftc(ifp);
672 for (i = 0; i < sc->nwqs; i++) {
673 while ((m = buf_ring_dequeue_sc(sc->wq[i]->br)) != NULL)
679 /*****************************************************************************
680 * Driver interrupt routines functions *
681 *****************************************************************************/
684 oce_intr(void *arg, int pending)
687 POCE_INTR_INFO ii = (POCE_INTR_INFO) arg;
688 POCE_SOFTC sc = ii->sc;
689 struct oce_eq *eq = ii->eq;
691 struct oce_cq *cq = NULL;
694 bus_dmamap_sync(eq->ring->dma.tag, eq->ring->dma.map,
695 BUS_DMASYNC_POSTWRITE);
697 eqe = RING_GET_CONSUMER_ITEM_VA(eq->ring, struct oce_eqe);
701 bus_dmamap_sync(eq->ring->dma.tag, eq->ring->dma.map,
702 BUS_DMASYNC_POSTWRITE);
703 RING_GET(eq->ring, 1);
709 goto eq_arm; /* Spurious */
711 /* Clear EQ entries, but dont arm */
712 oce_arm_eq(sc, eq->eq_id, num_eqes, FALSE, FALSE);
714 /* Process TX, RX and MCC. But dont arm CQ*/
715 for (i = 0; i < eq->cq_valid; i++) {
717 (*cq->cq_handler)(cq->cb_arg);
720 /* Arm all cqs connected to this EQ */
721 for (i = 0; i < eq->cq_valid; i++) {
723 oce_arm_cq(sc, cq->cq_id, 0, TRUE);
727 oce_arm_eq(sc, eq->eq_id, 0, TRUE, FALSE);
733 oce_setup_intr(POCE_SOFTC sc)
735 int rc = 0, use_intx = 0;
736 int vector = 0, req_vectors = 0;
737 int tot_req_vectors, tot_vectors;
739 if (is_rss_enabled(sc))
740 req_vectors = MAX((sc->nrqs - 1), sc->nwqs);
744 tot_req_vectors = req_vectors;
745 if (sc->rdma_flags & OCE_RDMA_FLAG_SUPPORTED) {
746 if (req_vectors > 1) {
747 tot_req_vectors += OCE_RDMA_VECTORS;
748 sc->roce_intr_count = OCE_RDMA_VECTORS;
752 if (sc->flags & OCE_FLAGS_MSIX_CAPABLE) {
753 sc->intr_count = req_vectors;
754 tot_vectors = tot_req_vectors;
755 rc = pci_alloc_msix(sc->dev, &tot_vectors);
758 pci_release_msi(sc->dev);
760 if (sc->rdma_flags & OCE_RDMA_FLAG_SUPPORTED) {
761 if (tot_vectors < tot_req_vectors) {
762 if (sc->intr_count < (2 * OCE_RDMA_VECTORS)) {
763 sc->roce_intr_count = (tot_vectors / 2);
765 sc->intr_count = tot_vectors - sc->roce_intr_count;
768 sc->intr_count = tot_vectors;
770 sc->flags |= OCE_FLAGS_USING_MSIX;
778 /* Scale number of queues based on intr we got */
779 update_queues_got(sc);
782 device_printf(sc->dev, "Using legacy interrupt\n");
783 rc = oce_alloc_intr(sc, vector, oce_intr);
787 for (; vector < sc->intr_count; vector++) {
788 rc = oce_alloc_intr(sc, vector, oce_intr);
801 oce_fast_isr(void *arg)
803 POCE_INTR_INFO ii = (POCE_INTR_INFO) arg;
804 POCE_SOFTC sc = ii->sc;
809 oce_arm_eq(sc, ii->eq->eq_id, 0, FALSE, TRUE);
811 taskqueue_enqueue(ii->tq, &ii->task);
815 return FILTER_HANDLED;
819 oce_alloc_intr(POCE_SOFTC sc, int vector, void (*isr) (void *arg, int pending))
824 if (vector >= OCE_MAX_EQ)
827 ii = &sc->intrs[vector];
829 /* Set the resource id for the interrupt.
830 * MSIx is vector + 1 for the resource id,
831 * INTx is 0 for the resource id.
833 if (sc->flags & OCE_FLAGS_USING_MSIX)
837 ii->intr_res = bus_alloc_resource_any(sc->dev,
839 &rr, RF_ACTIVE|RF_SHAREABLE);
841 if (ii->intr_res == NULL) {
842 device_printf(sc->dev,
843 "Could not allocate interrupt\n");
848 TASK_INIT(&ii->task, 0, isr, ii);
850 sprintf(ii->task_name, "oce_task[%d]", ii->vector);
851 ii->tq = taskqueue_create_fast(ii->task_name,
853 taskqueue_thread_enqueue,
855 taskqueue_start_threads(&ii->tq, 1, PI_NET, "%s taskq",
856 device_get_nameunit(sc->dev));
859 rc = bus_setup_intr(sc->dev,
862 oce_fast_isr, NULL, ii, &ii->tag);
868 oce_intr_free(POCE_SOFTC sc)
872 for (i = 0; i < sc->intr_count; i++) {
874 if (sc->intrs[i].tag != NULL)
875 bus_teardown_intr(sc->dev, sc->intrs[i].intr_res,
877 if (sc->intrs[i].tq != NULL)
878 taskqueue_free(sc->intrs[i].tq);
880 if (sc->intrs[i].intr_res != NULL)
881 bus_release_resource(sc->dev, SYS_RES_IRQ,
883 sc->intrs[i].intr_res);
884 sc->intrs[i].tag = NULL;
885 sc->intrs[i].intr_res = NULL;
888 if (sc->flags & OCE_FLAGS_USING_MSIX)
889 pci_release_msi(sc->dev);
893 /******************************************************************************
894 * Media callbacks functions *
895 ******************************************************************************/
898 oce_media_status(if_t ifp, struct ifmediareq *req)
900 POCE_SOFTC sc = (POCE_SOFTC) if_getsoftc(ifp);
902 req->ifm_status = IFM_AVALID;
903 req->ifm_active = IFM_ETHER;
905 if (sc->link_status == 1)
906 req->ifm_status |= IFM_ACTIVE;
910 switch (sc->link_speed) {
911 case 1: /* 10 Mbps */
912 req->ifm_active |= IFM_10_T | IFM_FDX;
915 case 2: /* 100 Mbps */
916 req->ifm_active |= IFM_100_TX | IFM_FDX;
920 req->ifm_active |= IFM_1000_T | IFM_FDX;
923 case 4: /* 10 Gbps */
924 req->ifm_active |= IFM_10G_SR | IFM_FDX;
927 case 5: /* 20 Gbps */
928 req->ifm_active |= IFM_10G_SR | IFM_FDX;
931 case 6: /* 25 Gbps */
932 req->ifm_active |= IFM_10G_SR | IFM_FDX;
935 case 7: /* 40 Gbps */
936 req->ifm_active |= IFM_40G_SR4 | IFM_FDX;
948 oce_media_change(if_t ifp)
953 static void oce_is_pkt_dest_bmc(POCE_SOFTC sc,
954 struct mbuf *m, boolean_t *os2bmc,
957 struct ether_header *eh = NULL;
959 eh = mtod(m, struct ether_header *);
961 if (!is_os2bmc_enabled(sc) || *os2bmc) {
965 if (!ETHER_IS_MULTICAST(eh->ether_dhost))
968 if (is_mc_allowed_on_bmc(sc, eh) ||
969 is_bc_allowed_on_bmc(sc, eh) ||
970 is_arp_allowed_on_bmc(sc, ntohs(eh->ether_type))) {
975 if (mtod(m, struct ip *)->ip_p == IPPROTO_IPV6) {
976 struct ip6_hdr *ip6 = mtod(m, struct ip6_hdr *);
977 uint8_t nexthdr = ip6->ip6_nxt;
978 if (nexthdr == IPPROTO_ICMPV6) {
979 struct icmp6_hdr *icmp6 = (struct icmp6_hdr *)(ip6 + 1);
980 switch (icmp6->icmp6_type) {
981 case ND_ROUTER_ADVERT:
982 *os2bmc = is_ipv6_ra_filt_enabled(sc);
984 case ND_NEIGHBOR_ADVERT:
985 *os2bmc = is_ipv6_na_filt_enabled(sc);
993 if (mtod(m, struct ip *)->ip_p == IPPROTO_UDP) {
994 struct ip *ip = mtod(m, struct ip *);
995 int iphlen = ip->ip_hl << 2;
996 struct udphdr *uh = (struct udphdr *)((caddr_t)ip + iphlen);
997 switch (uh->uh_dport) {
998 case DHCP_CLIENT_PORT:
999 *os2bmc = is_dhcp_client_filt_enabled(sc);
1001 case DHCP_SERVER_PORT:
1002 *os2bmc = is_dhcp_srvr_filt_enabled(sc);
1004 case NET_BIOS_PORT1:
1005 case NET_BIOS_PORT2:
1006 *os2bmc = is_nbios_filt_enabled(sc);
1008 case DHCPV6_RAS_PORT:
1009 *os2bmc = is_ipv6_ras_filt_enabled(sc);
1017 *m_new = m_dup(m, M_NOWAIT);
1022 *m_new = oce_insert_vlan_tag(sc, *m_new, NULL);
1026 /*****************************************************************************
1027 * Transmit routines functions *
1028 *****************************************************************************/
1031 oce_tx(POCE_SOFTC sc, struct mbuf **mpp, int wq_index)
1033 int rc = 0, i, retry_cnt = 0;
1034 bus_dma_segment_t segs[OCE_MAX_TX_ELEMENTS];
1035 struct mbuf *m, *m_temp, *m_new = NULL;
1036 struct oce_wq *wq = sc->wq[wq_index];
1037 struct oce_packet_desc *pd;
1038 struct oce_nic_hdr_wqe *nichdr;
1039 struct oce_nic_frag_wqe *nicfrag;
1040 struct ether_header *eh = NULL;
1043 boolean_t complete = TRUE;
1044 boolean_t os2bmc = FALSE;
1050 if (!(m->m_flags & M_PKTHDR)) {
1055 /* Don't allow non-TSO packets longer than MTU */
1056 if (!is_tso_pkt(m)) {
1057 eh = mtod(m, struct ether_header *);
1058 if(m->m_pkthdr.len > ETHER_MAX_FRAME(sc->ifp, eh->ether_type, FALSE))
1062 if(oce_tx_asic_stall_verify(sc, m)) {
1063 m = oce_insert_vlan_tag(sc, m, &complete);
1065 device_printf(sc->dev, "Insertion unsuccessful\n");
1070 /* Lancer, SH ASIC has a bug wherein Packets that are 32 bytes or less
1071 * may cause a transmit stall on that port. So the work-around is to
1072 * pad short packets (<= 32 bytes) to a 36-byte length.
1074 if(IS_SH(sc) || IS_XE201(sc) ) {
1075 if(m->m_pkthdr.len <= 32) {
1077 bzero((void *)buf, 36);
1078 m_append(m, (36 - m->m_pkthdr.len), buf);
1083 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1084 /* consolidate packet buffers for TSO/LSO segment offload */
1085 #if defined(INET6) || defined(INET)
1086 m = oce_tso_setup(sc, mpp);
1096 pd = &wq->pckts[wq->pkt_desc_head];
1099 rc = bus_dmamap_load_mbuf_sg(wq->tag,
1101 m, segs, &pd->nsegs, BUS_DMA_NOWAIT);
1103 num_wqes = pd->nsegs + 1;
1104 if (IS_BE(sc) || IS_SH(sc)) {
1105 /*Dummy required only for BE3.*/
1109 if (num_wqes >= RING_NUM_FREE(wq->ring)) {
1110 bus_dmamap_unload(wq->tag, pd->map);
1113 atomic_store_rel_int(&wq->pkt_desc_head,
1114 (wq->pkt_desc_head + 1) % \
1115 OCE_WQ_PACKET_ARRAY_SIZE);
1116 bus_dmamap_sync(wq->tag, pd->map, BUS_DMASYNC_PREWRITE);
1120 RING_GET_PRODUCER_ITEM_VA(wq->ring, struct oce_nic_hdr_wqe);
1121 nichdr->u0.dw[0] = 0;
1122 nichdr->u0.dw[1] = 0;
1123 nichdr->u0.dw[2] = 0;
1124 nichdr->u0.dw[3] = 0;
1126 nichdr->u0.s.complete = complete;
1127 nichdr->u0.s.mgmt = os2bmc;
1128 nichdr->u0.s.event = 1;
1129 nichdr->u0.s.crc = 1;
1130 nichdr->u0.s.forward = 0;
1131 nichdr->u0.s.ipcs = (m->m_pkthdr.csum_flags & CSUM_IP) ? 1 : 0;
1132 nichdr->u0.s.udpcs =
1133 (m->m_pkthdr.csum_flags & CSUM_UDP) ? 1 : 0;
1134 nichdr->u0.s.tcpcs =
1135 (m->m_pkthdr.csum_flags & CSUM_TCP) ? 1 : 0;
1136 nichdr->u0.s.num_wqe = num_wqes;
1137 nichdr->u0.s.total_length = m->m_pkthdr.len;
1139 if (m->m_flags & M_VLANTAG) {
1140 nichdr->u0.s.vlan = 1; /*Vlan present*/
1141 nichdr->u0.s.vlan_tag = m->m_pkthdr.ether_vtag;
1144 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1145 if (m->m_pkthdr.tso_segsz) {
1146 nichdr->u0.s.lso = 1;
1147 nichdr->u0.s.lso_mss = m->m_pkthdr.tso_segsz;
1149 if (!IS_BE(sc) || !IS_SH(sc))
1150 nichdr->u0.s.ipcs = 1;
1153 RING_PUT(wq->ring, 1);
1154 atomic_add_int(&wq->ring->num_used, 1);
1156 for (i = 0; i < pd->nsegs; i++) {
1158 RING_GET_PRODUCER_ITEM_VA(wq->ring,
1159 struct oce_nic_frag_wqe);
1160 nicfrag->u0.s.rsvd0 = 0;
1161 nicfrag->u0.s.frag_pa_hi = ADDR_HI(segs[i].ds_addr);
1162 nicfrag->u0.s.frag_pa_lo = ADDR_LO(segs[i].ds_addr);
1163 nicfrag->u0.s.frag_len = segs[i].ds_len;
1164 pd->wqe_idx = wq->ring->pidx;
1165 RING_PUT(wq->ring, 1);
1166 atomic_add_int(&wq->ring->num_used, 1);
1168 if (num_wqes > (pd->nsegs + 1)) {
1170 RING_GET_PRODUCER_ITEM_VA(wq->ring,
1171 struct oce_nic_frag_wqe);
1172 nicfrag->u0.dw[0] = 0;
1173 nicfrag->u0.dw[1] = 0;
1174 nicfrag->u0.dw[2] = 0;
1175 nicfrag->u0.dw[3] = 0;
1176 pd->wqe_idx = wq->ring->pidx;
1177 RING_PUT(wq->ring, 1);
1178 atomic_add_int(&wq->ring->num_used, 1);
1182 if_inc_counter(sc->ifp, IFCOUNTER_OPACKETS, 1);
1183 wq->tx_stats.tx_reqs++;
1184 wq->tx_stats.tx_wrbs += num_wqes;
1185 wq->tx_stats.tx_bytes += m->m_pkthdr.len;
1186 wq->tx_stats.tx_pkts++;
1188 bus_dmamap_sync(wq->ring->dma.tag, wq->ring->dma.map,
1189 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1190 reg_value = (num_wqes << 16) | wq->wq_id;
1192 /* if os2bmc is not enabled or if the pkt is already tagged as
1195 oce_is_pkt_dest_bmc(sc, m, &os2bmc, &m_new);
1197 if_inc_counter(sc->ifp, IFCOUNTER_OBYTES, m->m_pkthdr.len);
1198 if (m->m_flags & M_MCAST)
1199 if_inc_counter(sc->ifp, IFCOUNTER_OMCASTS, 1);
1200 ETHER_BPF_MTAP(sc->ifp, m);
1202 OCE_WRITE_REG32(sc, db, wq->db_offset, reg_value);
1204 } else if (rc == EFBIG) {
1205 if (retry_cnt == 0) {
1206 m_temp = m_defrag(m, M_NOWAIT);
1211 retry_cnt = retry_cnt + 1;
1215 } else if (rc == ENOMEM)
1234 oce_process_tx_completion(struct oce_wq *wq)
1236 struct oce_packet_desc *pd;
1237 POCE_SOFTC sc = (POCE_SOFTC) wq->parent;
1240 pd = &wq->pckts[wq->pkt_desc_tail];
1241 atomic_store_rel_int(&wq->pkt_desc_tail,
1242 (wq->pkt_desc_tail + 1) % OCE_WQ_PACKET_ARRAY_SIZE);
1243 atomic_subtract_int(&wq->ring->num_used, pd->nsegs + 1);
1244 bus_dmamap_sync(wq->tag, pd->map, BUS_DMASYNC_POSTWRITE);
1245 bus_dmamap_unload(wq->tag, pd->map);
1251 if (if_getdrvflags(sc->ifp) & IFF_DRV_OACTIVE) {
1252 if (wq->ring->num_used < (wq->ring->num_items / 2)) {
1253 if_setdrvflagbits(sc->ifp, 0, (IFF_DRV_OACTIVE));
1254 oce_tx_restart(sc, wq);
1260 oce_tx_restart(POCE_SOFTC sc, struct oce_wq *wq)
1263 if ((if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) != IFF_DRV_RUNNING)
1266 if (!drbr_empty(sc->ifp, wq->br))
1267 taskqueue_enqueue(taskqueue_swi, &wq->txtask);
1271 #if defined(INET6) || defined(INET)
1272 static struct mbuf *
1273 oce_tso_setup(POCE_SOFTC sc, struct mbuf **mpp)
1280 struct ip6_hdr *ip6;
1282 struct ether_vlan_header *eh;
1285 int total_len = 0, ehdrlen = 0;
1289 if (M_WRITABLE(m) == 0) {
1290 m = m_dup(*mpp, M_NOWAIT);
1297 eh = mtod(m, struct ether_vlan_header *);
1298 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
1299 etype = ntohs(eh->evl_proto);
1300 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
1302 etype = ntohs(eh->evl_encap_proto);
1303 ehdrlen = ETHER_HDR_LEN;
1309 ip = (struct ip *)(m->m_data + ehdrlen);
1310 if (ip->ip_p != IPPROTO_TCP)
1312 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
1314 total_len = ehdrlen + (ip->ip_hl << 2) + (th->th_off << 2);
1318 case ETHERTYPE_IPV6:
1319 ip6 = (struct ip6_hdr *)(m->m_data + ehdrlen);
1320 if (ip6->ip6_nxt != IPPROTO_TCP)
1322 th = (struct tcphdr *)((caddr_t)ip6 + sizeof(struct ip6_hdr));
1324 total_len = ehdrlen + sizeof(struct ip6_hdr) + (th->th_off << 2);
1331 m = m_pullup(m, total_len);
1335 #endif /* INET6 || INET */
1338 oce_tx_task(void *arg, int npending)
1340 struct oce_wq *wq = arg;
1341 POCE_SOFTC sc = wq->parent;
1346 rc = oce_multiq_transmit(ifp, NULL, wq);
1348 device_printf(sc->dev,
1349 "TX[%d] restart failed\n", wq->queue_index);
1351 UNLOCK(&wq->tx_lock);
1357 POCE_SOFTC sc = if_getsoftc(ifp);
1360 int def_q = 0; /* Defualt tx queue is 0*/
1362 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1366 if (!sc->link_status)
1370 m = if_dequeue(sc->ifp);
1374 LOCK(&sc->wq[def_q]->tx_lock);
1375 rc = oce_tx(sc, &m, def_q);
1376 UNLOCK(&sc->wq[def_q]->tx_lock);
1379 sc->wq[def_q]->tx_stats.tx_stops ++;
1380 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
1381 if_sendq_prepend(ifp, m);
1389 /* Handle the Completion Queue for transmit */
1391 oce_wq_handler(void *arg)
1393 struct oce_wq *wq = (struct oce_wq *)arg;
1394 POCE_SOFTC sc = wq->parent;
1395 struct oce_cq *cq = wq->cq;
1396 struct oce_nic_tx_cqe *cqe;
1399 LOCK(&wq->tx_compl_lock);
1400 bus_dmamap_sync(cq->ring->dma.tag,
1401 cq->ring->dma.map, BUS_DMASYNC_POSTWRITE);
1402 cqe = RING_GET_CONSUMER_ITEM_VA(cq->ring, struct oce_nic_tx_cqe);
1403 while (cqe->u0.dw[3]) {
1404 DW_SWAP((uint32_t *) cqe, sizeof(oce_wq_cqe));
1406 wq->ring->cidx = cqe->u0.s.wqe_index + 1;
1407 if (wq->ring->cidx >= wq->ring->num_items)
1408 wq->ring->cidx -= wq->ring->num_items;
1410 oce_process_tx_completion(wq);
1411 wq->tx_stats.tx_compl++;
1413 RING_GET(cq->ring, 1);
1414 bus_dmamap_sync(cq->ring->dma.tag,
1415 cq->ring->dma.map, BUS_DMASYNC_POSTWRITE);
1417 RING_GET_CONSUMER_ITEM_VA(cq->ring, struct oce_nic_tx_cqe);
1422 oce_arm_cq(sc, cq->cq_id, num_cqes, FALSE);
1424 UNLOCK(&wq->tx_compl_lock);
1429 oce_multiq_transmit(if_t ifp, struct mbuf *m, struct oce_wq *wq)
1431 POCE_SOFTC sc = if_getsoftc(ifp);
1432 int status = 0, queue_index = 0;
1433 struct mbuf *next = NULL;
1434 struct buf_ring *br = NULL;
1437 queue_index = wq->queue_index;
1439 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1442 status = drbr_enqueue(ifp, br, m);
1447 if ((status = drbr_enqueue(ifp, br, m)) != 0)
1450 while ((next = drbr_peek(ifp, br)) != NULL) {
1451 if (oce_tx(sc, &next, queue_index)) {
1453 drbr_advance(ifp, br);
1455 drbr_putback(ifp, br, next);
1456 wq->tx_stats.tx_stops ++;
1457 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
1461 drbr_advance(ifp, br);
1467 /*****************************************************************************
1468 * Receive routines functions *
1469 *****************************************************************************/
1472 oce_correct_header(struct mbuf *m, struct nic_hwlro_cqe_part1 *cqe1, struct nic_hwlro_cqe_part2 *cqe2)
1475 struct ether_header *eh = NULL;
1476 struct tcphdr *tcp_hdr = NULL;
1477 struct ip *ip4_hdr = NULL;
1478 struct ip6_hdr *ip6 = NULL;
1479 uint32_t payload_len = 0;
1481 eh = mtod(m, struct ether_header *);
1482 /* correct IP header */
1483 if(!cqe2->ipv6_frame) {
1484 ip4_hdr = (struct ip *)((char*)eh + sizeof(struct ether_header));
1485 ip4_hdr->ip_ttl = cqe2->frame_lifespan;
1486 ip4_hdr->ip_len = htons(cqe2->coalesced_size - sizeof(struct ether_header));
1487 tcp_hdr = (struct tcphdr *)((char*)ip4_hdr + sizeof(struct ip));
1489 ip6 = (struct ip6_hdr *)((char*)eh + sizeof(struct ether_header));
1490 ip6->ip6_ctlun.ip6_un1.ip6_un1_hlim = cqe2->frame_lifespan;
1491 payload_len = cqe2->coalesced_size - sizeof(struct ether_header)
1492 - sizeof(struct ip6_hdr);
1493 ip6->ip6_ctlun.ip6_un1.ip6_un1_plen = htons(payload_len);
1494 tcp_hdr = (struct tcphdr *)((char*)ip6 + sizeof(struct ip6_hdr));
1497 /* correct tcp header */
1498 tcp_hdr->th_ack = htonl(cqe2->tcp_ack_num);
1500 tcp_hdr->th_flags |= TH_PUSH;
1502 tcp_hdr->th_win = htons(cqe2->tcp_window);
1503 tcp_hdr->th_sum = 0xffff;
1505 p = (uint32_t *)((char*)tcp_hdr + sizeof(struct tcphdr) + 2);
1506 *p = cqe1->tcp_timestamp_val;
1507 *(p+1) = cqe1->tcp_timestamp_ecr;
1514 oce_rx_mbuf_chain(struct oce_rq *rq, struct oce_common_cqe_info *cqe_info, struct mbuf **m)
1516 POCE_SOFTC sc = (POCE_SOFTC) rq->parent;
1517 uint32_t i = 0, frag_len = 0;
1518 uint32_t len = cqe_info->pkt_size;
1519 struct oce_packet_desc *pd;
1520 struct mbuf *tail = NULL;
1522 for (i = 0; i < cqe_info->num_frags; i++) {
1523 if (rq->ring->cidx == rq->ring->pidx) {
1524 device_printf(sc->dev,
1525 "oce_rx_mbuf_chain: Invalid RX completion - Queue is empty\n");
1528 pd = &rq->pckts[rq->ring->cidx];
1530 bus_dmamap_sync(rq->tag, pd->map, BUS_DMASYNC_POSTWRITE);
1531 bus_dmamap_unload(rq->tag, pd->map);
1532 RING_GET(rq->ring, 1);
1535 frag_len = (len > rq->cfg.frag_size) ? rq->cfg.frag_size : len;
1536 pd->mbuf->m_len = frag_len;
1539 /* additional fragments */
1540 pd->mbuf->m_flags &= ~M_PKTHDR;
1541 tail->m_next = pd->mbuf;
1543 tail->m_nextpkt = NULL;
1546 /* first fragment, fill out much of the packet header */
1547 pd->mbuf->m_pkthdr.len = len;
1549 pd->mbuf->m_nextpkt = NULL;
1550 pd->mbuf->m_pkthdr.csum_flags = 0;
1551 if (IF_CSUM_ENABLED(sc)) {
1552 if (cqe_info->l4_cksum_pass) {
1553 if(!cqe_info->ipv6_frame) { /* IPV4 */
1554 pd->mbuf->m_pkthdr.csum_flags |=
1555 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
1556 }else { /* IPV6 frame */
1558 pd->mbuf->m_pkthdr.csum_flags |=
1559 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
1562 pd->mbuf->m_pkthdr.csum_data = 0xffff;
1564 if (cqe_info->ip_cksum_pass) {
1565 pd->mbuf->m_pkthdr.csum_flags |=
1566 (CSUM_IP_CHECKED|CSUM_IP_VALID);
1569 *m = tail = pd->mbuf;
1579 oce_rx_lro(struct oce_rq *rq, struct nic_hwlro_singleton_cqe *cqe, struct nic_hwlro_cqe_part2 *cqe2)
1581 POCE_SOFTC sc = (POCE_SOFTC) rq->parent;
1582 struct nic_hwlro_cqe_part1 *cqe1 = NULL;
1583 struct mbuf *m = NULL;
1584 struct oce_common_cqe_info cq_info;
1588 cq_info.pkt_size = cqe->pkt_size;
1589 cq_info.vtag = cqe->vlan_tag;
1590 cq_info.l4_cksum_pass = cqe->l4_cksum_pass;
1591 cq_info.ip_cksum_pass = cqe->ip_cksum_pass;
1592 cq_info.ipv6_frame = cqe->ipv6_frame;
1593 cq_info.vtp = cqe->vtp;
1594 cq_info.qnq = cqe->qnq;
1596 cqe1 = (struct nic_hwlro_cqe_part1 *)cqe;
1597 cq_info.pkt_size = cqe2->coalesced_size;
1598 cq_info.vtag = cqe2->vlan_tag;
1599 cq_info.l4_cksum_pass = cqe2->l4_cksum_pass;
1600 cq_info.ip_cksum_pass = cqe2->ip_cksum_pass;
1601 cq_info.ipv6_frame = cqe2->ipv6_frame;
1602 cq_info.vtp = cqe2->vtp;
1603 cq_info.qnq = cqe1->qnq;
1606 cq_info.vtag = BSWAP_16(cq_info.vtag);
1608 cq_info.num_frags = cq_info.pkt_size / rq->cfg.frag_size;
1609 if(cq_info.pkt_size % rq->cfg.frag_size)
1610 cq_info.num_frags++;
1612 oce_rx_mbuf_chain(rq, &cq_info, &m);
1616 //assert(cqe2->valid != 0);
1618 //assert(cqe2->cqe_type != 2);
1619 oce_correct_header(m, cqe1, cqe2);
1622 m->m_pkthdr.rcvif = sc->ifp;
1623 if (rq->queue_index)
1624 m->m_pkthdr.flowid = (rq->queue_index - 1);
1626 m->m_pkthdr.flowid = rq->queue_index;
1627 M_HASHTYPE_SET(m, M_HASHTYPE_OPAQUE);
1629 /* This deternies if vlan tag is Valid */
1631 if (sc->function_mode & FNM_FLEX10_MODE) {
1632 /* FLEX10. If QnQ is not set, neglect VLAN */
1634 m->m_pkthdr.ether_vtag = cq_info.vtag;
1635 m->m_flags |= M_VLANTAG;
1637 } else if (sc->pvid != (cq_info.vtag & VLAN_VID_MASK)) {
1638 /* In UMC mode generally pvid will be striped by
1639 hw. But in some cases we have seen it comes
1640 with pvid. So if pvid == vlan, neglect vlan.
1642 m->m_pkthdr.ether_vtag = cq_info.vtag;
1643 m->m_flags |= M_VLANTAG;
1646 if_inc_counter(sc->ifp, IFCOUNTER_IPACKETS, 1);
1648 if_input(sc->ifp, m);
1650 /* Update rx stats per queue */
1651 rq->rx_stats.rx_pkts++;
1652 rq->rx_stats.rx_bytes += cq_info.pkt_size;
1653 rq->rx_stats.rx_frags += cq_info.num_frags;
1654 rq->rx_stats.rx_ucast_pkts++;
1660 oce_rx(struct oce_rq *rq, struct oce_nic_rx_cqe *cqe)
1662 POCE_SOFTC sc = (POCE_SOFTC) rq->parent;
1664 struct mbuf *m = NULL;
1665 struct oce_common_cqe_info cq_info;
1668 /* Is it a flush compl that has no data */
1669 if(!cqe->u0.s.num_fragments)
1672 len = cqe->u0.s.pkt_size;
1674 /*partial DMA workaround for Lancer*/
1675 oce_discard_rx_comp(rq, cqe->u0.s.num_fragments);
1679 if (!oce_cqe_portid_valid(sc, cqe)) {
1680 oce_discard_rx_comp(rq, cqe->u0.s.num_fragments);
1684 /* Get vlan_tag value */
1685 if(IS_BE(sc) || IS_SH(sc))
1686 vtag = BSWAP_16(cqe->u0.s.vlan_tag);
1688 vtag = cqe->u0.s.vlan_tag;
1690 cq_info.l4_cksum_pass = cqe->u0.s.l4_cksum_pass;
1691 cq_info.ip_cksum_pass = cqe->u0.s.ip_cksum_pass;
1692 cq_info.ipv6_frame = cqe->u0.s.ip_ver;
1693 cq_info.num_frags = cqe->u0.s.num_fragments;
1694 cq_info.pkt_size = cqe->u0.s.pkt_size;
1696 oce_rx_mbuf_chain(rq, &cq_info, &m);
1699 m->m_pkthdr.rcvif = sc->ifp;
1700 if (rq->queue_index)
1701 m->m_pkthdr.flowid = (rq->queue_index - 1);
1703 m->m_pkthdr.flowid = rq->queue_index;
1704 M_HASHTYPE_SET(m, M_HASHTYPE_OPAQUE);
1706 /* This deternies if vlan tag is Valid */
1707 if (oce_cqe_vtp_valid(sc, cqe)) {
1708 if (sc->function_mode & FNM_FLEX10_MODE) {
1709 /* FLEX10. If QnQ is not set, neglect VLAN */
1710 if (cqe->u0.s.qnq) {
1711 m->m_pkthdr.ether_vtag = vtag;
1712 m->m_flags |= M_VLANTAG;
1714 } else if (sc->pvid != (vtag & VLAN_VID_MASK)) {
1715 /* In UMC mode generally pvid will be striped by
1716 hw. But in some cases we have seen it comes
1717 with pvid. So if pvid == vlan, neglect vlan.
1719 m->m_pkthdr.ether_vtag = vtag;
1720 m->m_flags |= M_VLANTAG;
1724 if_inc_counter(sc->ifp, IFCOUNTER_IPACKETS, 1);
1725 #if defined(INET6) || defined(INET)
1726 /* Try to queue to LRO */
1727 if (IF_LRO_ENABLED(sc) &&
1728 (cqe->u0.s.ip_cksum_pass) &&
1729 (cqe->u0.s.l4_cksum_pass) &&
1730 (!cqe->u0.s.ip_ver) &&
1731 (rq->lro.lro_cnt != 0)) {
1732 if (tcp_lro_rx(&rq->lro, m, 0) == 0) {
1733 rq->lro_pkts_queued ++;
1736 /* If LRO posting fails then try to post to STACK */
1740 if_input(sc->ifp, m);
1741 #if defined(INET6) || defined(INET)
1744 /* Update rx stats per queue */
1745 rq->rx_stats.rx_pkts++;
1746 rq->rx_stats.rx_bytes += cqe->u0.s.pkt_size;
1747 rq->rx_stats.rx_frags += cqe->u0.s.num_fragments;
1748 if (cqe->u0.s.pkt_type == OCE_MULTICAST_PACKET)
1749 rq->rx_stats.rx_mcast_pkts++;
1750 if (cqe->u0.s.pkt_type == OCE_UNICAST_PACKET)
1751 rq->rx_stats.rx_ucast_pkts++;
1758 oce_discard_rx_comp(struct oce_rq *rq, int num_frags)
1761 struct oce_packet_desc *pd;
1762 POCE_SOFTC sc = (POCE_SOFTC) rq->parent;
1764 for (i = 0; i < num_frags; i++) {
1765 if (rq->ring->cidx == rq->ring->pidx) {
1766 device_printf(sc->dev,
1767 "oce_discard_rx_comp: Invalid RX completion - Queue is empty\n");
1770 pd = &rq->pckts[rq->ring->cidx];
1771 bus_dmamap_sync(rq->tag, pd->map, BUS_DMASYNC_POSTWRITE);
1772 bus_dmamap_unload(rq->tag, pd->map);
1773 if (pd->mbuf != NULL) {
1778 RING_GET(rq->ring, 1);
1784 oce_cqe_vtp_valid(POCE_SOFTC sc, struct oce_nic_rx_cqe *cqe)
1786 struct oce_nic_rx_cqe_v1 *cqe_v1;
1789 if (sc->be3_native) {
1790 cqe_v1 = (struct oce_nic_rx_cqe_v1 *)cqe;
1791 vtp = cqe_v1->u0.s.vlan_tag_present;
1793 vtp = cqe->u0.s.vlan_tag_present;
1800 oce_cqe_portid_valid(POCE_SOFTC sc, struct oce_nic_rx_cqe *cqe)
1802 struct oce_nic_rx_cqe_v1 *cqe_v1;
1805 if (sc->be3_native && (IS_BE(sc) || IS_SH(sc))) {
1806 cqe_v1 = (struct oce_nic_rx_cqe_v1 *)cqe;
1807 port_id = cqe_v1->u0.s.port;
1808 if (sc->port_id != port_id)
1811 ;/* For BE3 legacy and Lancer this is dummy */
1817 #if defined(INET6) || defined(INET)
1819 oce_rx_flush_lro(struct oce_rq *rq)
1821 struct lro_ctrl *lro = &rq->lro;
1822 POCE_SOFTC sc = (POCE_SOFTC) rq->parent;
1824 if (!IF_LRO_ENABLED(sc))
1827 tcp_lro_flush_all(lro);
1828 rq->lro_pkts_queued = 0;
1834 oce_init_lro(POCE_SOFTC sc)
1836 struct lro_ctrl *lro = NULL;
1839 for (i = 0; i < sc->nrqs; i++) {
1840 lro = &sc->rq[i]->lro;
1841 rc = tcp_lro_init(lro);
1843 device_printf(sc->dev, "LRO init failed\n");
1853 oce_free_lro(POCE_SOFTC sc)
1855 struct lro_ctrl *lro = NULL;
1858 for (i = 0; i < sc->nrqs; i++) {
1859 lro = &sc->rq[i]->lro;
1867 oce_alloc_rx_bufs(struct oce_rq *rq, int count)
1869 POCE_SOFTC sc = (POCE_SOFTC) rq->parent;
1871 struct oce_packet_desc *pd;
1872 bus_dma_segment_t segs[6];
1873 int nsegs, added = 0;
1874 struct oce_nic_rqe *rqe;
1875 pd_rxulp_db_t rxdb_reg;
1877 uint32_t oce_max_rq_posts = 64;
1879 bzero(&rxdb_reg, sizeof(pd_rxulp_db_t));
1880 for (i = 0; i < count; i++) {
1881 pd = &rq->pckts[rq->ring->pidx];
1882 pd->mbuf = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, oce_rq_buf_size);
1883 if (pd->mbuf == NULL) {
1884 device_printf(sc->dev, "mbuf allocation failed, size = %d\n",oce_rq_buf_size);
1887 pd->mbuf->m_nextpkt = NULL;
1889 pd->mbuf->m_len = pd->mbuf->m_pkthdr.len = rq->cfg.frag_size;
1891 rc = bus_dmamap_load_mbuf_sg(rq->tag,
1894 segs, &nsegs, BUS_DMA_NOWAIT);
1897 device_printf(sc->dev, "bus_dmamap_load_mbuf_sg failed rc = %d\n", rc);
1906 bus_dmamap_sync(rq->tag, pd->map, BUS_DMASYNC_PREREAD);
1908 rqe = RING_GET_PRODUCER_ITEM_VA(rq->ring, struct oce_nic_rqe);
1909 rqe->u0.s.frag_pa_hi = ADDR_HI(segs[0].ds_addr);
1910 rqe->u0.s.frag_pa_lo = ADDR_LO(segs[0].ds_addr);
1911 DW_SWAP(u32ptr(rqe), sizeof(struct oce_nic_rqe));
1912 RING_PUT(rq->ring, 1);
1916 oce_max_rq_posts = sc->enable_hwlro ? OCE_HWLRO_MAX_RQ_POSTS : OCE_MAX_RQ_POSTS;
1918 for (i = added / oce_max_rq_posts; i > 0; i--) {
1919 rxdb_reg.bits.num_posted = oce_max_rq_posts;
1920 rxdb_reg.bits.qid = rq->rq_id;
1922 val |= rq->rq_id & DB_LRO_RQ_ID_MASK;
1923 val |= oce_max_rq_posts << 16;
1924 OCE_WRITE_REG32(sc, db, DB_OFFSET, val);
1926 OCE_WRITE_REG32(sc, db, PD_RXULP_DB, rxdb_reg.dw0);
1928 added -= oce_max_rq_posts;
1931 rxdb_reg.bits.qid = rq->rq_id;
1932 rxdb_reg.bits.num_posted = added;
1934 val |= rq->rq_id & DB_LRO_RQ_ID_MASK;
1936 OCE_WRITE_REG32(sc, db, DB_OFFSET, val);
1938 OCE_WRITE_REG32(sc, db, PD_RXULP_DB, rxdb_reg.dw0);
1947 oce_check_rx_bufs(POCE_SOFTC sc, uint32_t num_cqes, struct oce_rq *rq)
1950 oce_arm_cq(sc, rq->cq->cq_id, num_cqes, FALSE);
1951 if(!sc->enable_hwlro) {
1952 if((OCE_RQ_PACKET_ARRAY_SIZE - rq->pending) > 1)
1953 oce_alloc_rx_bufs(rq, ((OCE_RQ_PACKET_ARRAY_SIZE - rq->pending) - 1));
1955 if ((OCE_RQ_PACKET_ARRAY_SIZE -1 - rq->pending) > 64)
1956 oce_alloc_rx_bufs(rq, 64);
1964 oce_rq_handler_lro(void *arg)
1966 struct oce_rq *rq = (struct oce_rq *)arg;
1967 struct oce_cq *cq = rq->cq;
1968 POCE_SOFTC sc = rq->parent;
1969 struct nic_hwlro_singleton_cqe *cqe;
1970 struct nic_hwlro_cqe_part2 *cqe2;
1974 bus_dmamap_sync(cq->ring->dma.tag,cq->ring->dma.map, BUS_DMASYNC_POSTWRITE);
1975 cqe = RING_GET_CONSUMER_ITEM_VA(cq->ring, struct nic_hwlro_singleton_cqe);
1976 while (cqe->valid) {
1977 if(cqe->cqe_type == 0) { /* singleton cqe */
1978 /* we should not get singleton cqe after cqe1 on same rq */
1979 if(rq->cqe_firstpart != NULL) {
1980 device_printf(sc->dev, "Got singleton cqe after cqe1 \n");
1981 goto exit_rq_handler_lro;
1983 if(cqe->error != 0) {
1984 rq->rx_stats.rxcp_err++;
1985 if_inc_counter(sc->ifp, IFCOUNTER_IERRORS, 1);
1987 oce_rx_lro(rq, cqe, NULL);
1988 rq->rx_stats.rx_compl++;
1990 RING_GET(cq->ring, 1);
1992 if (num_cqes >= (IS_XE201(sc) ? 8 : oce_max_rsp_handled))
1994 }else if(cqe->cqe_type == 0x1) { /* first part */
1995 /* we should not get cqe1 after cqe1 on same rq */
1996 if(rq->cqe_firstpart != NULL) {
1997 device_printf(sc->dev, "Got cqe1 after cqe1 \n");
1998 goto exit_rq_handler_lro;
2000 rq->cqe_firstpart = (struct nic_hwlro_cqe_part1 *)cqe;
2001 RING_GET(cq->ring, 1);
2002 }else if(cqe->cqe_type == 0x2) { /* second part */
2003 cqe2 = (struct nic_hwlro_cqe_part2 *)cqe;
2004 if(cqe2->error != 0) {
2005 rq->rx_stats.rxcp_err++;
2006 if_inc_counter(sc->ifp, IFCOUNTER_IERRORS, 1);
2008 /* We should not get cqe2 without cqe1 */
2009 if(rq->cqe_firstpart == NULL) {
2010 device_printf(sc->dev, "Got cqe2 without cqe1 \n");
2011 goto exit_rq_handler_lro;
2013 oce_rx_lro(rq, (struct nic_hwlro_singleton_cqe *)rq->cqe_firstpart, cqe2);
2015 rq->rx_stats.rx_compl++;
2016 rq->cqe_firstpart->valid = 0;
2018 rq->cqe_firstpart = NULL;
2020 RING_GET(cq->ring, 1);
2022 if (num_cqes >= (IS_XE201(sc) ? 8 : oce_max_rsp_handled))
2026 bus_dmamap_sync(cq->ring->dma.tag,cq->ring->dma.map, BUS_DMASYNC_POSTWRITE);
2027 cqe = RING_GET_CONSUMER_ITEM_VA(cq->ring, struct nic_hwlro_singleton_cqe);
2029 oce_check_rx_bufs(sc, num_cqes, rq);
2030 exit_rq_handler_lro:
2031 UNLOCK(&rq->rx_lock);
2035 /* Handle the Completion Queue for receive */
2037 oce_rq_handler(void *arg)
2039 struct epoch_tracker et;
2040 struct oce_rq *rq = (struct oce_rq *)arg;
2041 struct oce_cq *cq = rq->cq;
2042 POCE_SOFTC sc = rq->parent;
2043 struct oce_nic_rx_cqe *cqe;
2046 NET_EPOCH_ENTER(et);
2048 oce_rq_handler_lro(arg);
2053 bus_dmamap_sync(cq->ring->dma.tag,
2054 cq->ring->dma.map, BUS_DMASYNC_POSTWRITE);
2055 cqe = RING_GET_CONSUMER_ITEM_VA(cq->ring, struct oce_nic_rx_cqe);
2056 while (cqe->u0.dw[2]) {
2057 DW_SWAP((uint32_t *) cqe, sizeof(oce_rq_cqe));
2059 if (cqe->u0.s.error == 0) {
2062 rq->rx_stats.rxcp_err++;
2063 if_inc_counter(sc->ifp, IFCOUNTER_IERRORS, 1);
2064 /* Post L3/L4 errors to stack.*/
2067 rq->rx_stats.rx_compl++;
2070 #if defined(INET6) || defined(INET)
2071 if (IF_LRO_ENABLED(sc) && rq->lro_pkts_queued >= 16) {
2072 oce_rx_flush_lro(rq);
2076 RING_GET(cq->ring, 1);
2077 bus_dmamap_sync(cq->ring->dma.tag,
2078 cq->ring->dma.map, BUS_DMASYNC_POSTWRITE);
2080 RING_GET_CONSUMER_ITEM_VA(cq->ring, struct oce_nic_rx_cqe);
2082 if (num_cqes >= (IS_XE201(sc) ? 8 : oce_max_rsp_handled))
2086 #if defined(INET6) || defined(INET)
2087 if (IF_LRO_ENABLED(sc))
2088 oce_rx_flush_lro(rq);
2091 oce_check_rx_bufs(sc, num_cqes, rq);
2092 UNLOCK(&rq->rx_lock);
2098 /*****************************************************************************
2099 * Helper function prototypes in this file *
2100 *****************************************************************************/
2103 oce_attach_ifp(POCE_SOFTC sc)
2106 sc->ifp = if_alloc(IFT_ETHER);
2110 ifmedia_init(&sc->media, IFM_IMASK, oce_media_change, oce_media_status);
2111 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2112 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
2114 if_setflags(sc->ifp, IFF_BROADCAST | IFF_MULTICAST);
2115 if_setioctlfn(sc->ifp, oce_ioctl);
2116 if_setstartfn(sc->ifp, oce_start);
2117 if_setinitfn(sc->ifp, oce_init);
2118 if_setmtu(sc->ifp, ETHERMTU);
2119 if_setsoftc(sc->ifp, sc);
2120 if_settransmitfn(sc->ifp, oce_multiq_start);
2121 if_setqflushfn(sc->ifp, oce_multiq_flush);
2123 if_initname(sc->ifp,
2124 device_get_name(sc->dev), device_get_unit(sc->dev));
2126 if_setsendqlen(sc->ifp, OCE_MAX_TX_DESC - 1);
2127 if_setsendqready(sc->ifp);
2129 if_sethwassist(sc->ifp, OCE_IF_HWASSIST);
2130 if_sethwassistbits(sc->ifp, CSUM_TSO, 0);
2131 if_sethwassistbits(sc->ifp, (CSUM_IP | CSUM_TCP | CSUM_UDP), 0);
2133 if_setcapabilities(sc->ifp, OCE_IF_CAPABILITIES);
2134 if_setcapabilitiesbit(sc->ifp, IFCAP_HWCSUM, 0);
2135 if_setcapabilitiesbit(sc->ifp, IFCAP_VLAN_HWFILTER, 0);
2137 #if defined(INET6) || defined(INET)
2138 if_setcapabilitiesbit(sc->ifp, IFCAP_TSO, 0);
2139 if_setcapabilitiesbit(sc->ifp, IFCAP_LRO, 0);
2140 if_setcapabilitiesbit(sc->ifp, IFCAP_VLAN_HWTSO, 0);
2143 if_setcapenable(sc->ifp, if_getcapabilities(sc->ifp));
2144 if_setbaudrate(sc->ifp, IF_Gbps(10));
2146 if_sethwtsomax(sc->ifp, 65536 - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN));
2147 if_sethwtsomaxsegcount(sc->ifp, OCE_MAX_TX_ELEMENTS);
2148 if_sethwtsomaxsegsize(sc->ifp, 4096);
2150 ether_ifattach(sc->ifp, sc->macaddr.mac_addr);
2156 oce_add_vlan(void *arg, if_t ifp, uint16_t vtag)
2158 POCE_SOFTC sc = if_getsoftc(ifp);
2160 if (if_getsoftc(ifp) != arg)
2162 if ((vtag == 0) || (vtag > 4095))
2165 sc->vlan_tag[vtag] = 1;
2167 if (sc->vlans_added <= (sc->max_vlans + 1))
2172 oce_del_vlan(void *arg, if_t ifp, uint16_t vtag)
2174 POCE_SOFTC sc = if_getsoftc(ifp);
2176 if (if_getsoftc(ifp) != arg)
2178 if ((vtag == 0) || (vtag > 4095))
2181 sc->vlan_tag[vtag] = 0;
2187 * A max of 64 vlans can be configured in BE. If the user configures
2188 * more, place the card in vlan promiscuous mode.
2191 oce_vid_config(POCE_SOFTC sc)
2193 struct normal_vlan vtags[MAX_VLANFILTER_SIZE];
2194 uint16_t ntags = 0, i;
2197 if ((sc->vlans_added <= MAX_VLANFILTER_SIZE) &&
2198 (if_getcapenable(sc->ifp) & IFCAP_VLAN_HWFILTER)) {
2199 for (i = 0; i < MAX_VLANS; i++) {
2200 if (sc->vlan_tag[i]) {
2201 vtags[ntags].vtag = i;
2206 status = oce_config_vlan(sc, (uint8_t) sc->if_id,
2207 vtags, ntags, 1, 0);
2209 status = oce_config_vlan(sc, (uint8_t) sc->if_id,
2215 oce_mac_addr_set(POCE_SOFTC sc)
2217 uint32_t old_pmac_id = sc->pmac_id;
2220 status = bcmp((if_getlladdr(sc->ifp)), sc->macaddr.mac_addr,
2221 sc->macaddr.size_of_struct);
2225 status = oce_mbox_macaddr_add(sc, (uint8_t *)(if_getlladdr(sc->ifp)),
2226 sc->if_id, &sc->pmac_id);
2228 status = oce_mbox_macaddr_del(sc, sc->if_id, old_pmac_id);
2229 bcopy((if_getlladdr(sc->ifp)), sc->macaddr.mac_addr,
2230 sc->macaddr.size_of_struct);
2233 device_printf(sc->dev, "Failed update macaddress\n");
2238 oce_handle_passthrough(if_t ifp, caddr_t data)
2240 POCE_SOFTC sc = if_getsoftc(ifp);
2241 struct ifreq *ifr = (struct ifreq *)data;
2243 char cookie[32] = {0};
2244 void *priv_data = ifr_data_get_ptr(ifr);
2248 OCE_DMA_MEM dma_mem;
2250 if (copyin(priv_data, cookie, strlen(IOCTL_COOKIE)))
2253 if (memcmp(cookie, IOCTL_COOKIE, strlen(IOCTL_COOKIE)))
2256 ioctl_ptr = (char *)priv_data + strlen(IOCTL_COOKIE);
2257 if (copyin(ioctl_ptr, &req, sizeof(struct mbx_hdr)))
2260 req_size = le32toh(req.u0.req.request_length);
2261 if (req_size > 65536)
2264 req_size += sizeof(struct mbx_hdr);
2265 rc = oce_dma_alloc(sc, req_size, &dma_mem, 0);
2269 if (copyin(ioctl_ptr, OCE_DMAPTR(&dma_mem,char), req_size)) {
2274 rc = oce_pass_through_mbox(sc, &dma_mem, req_size);
2280 if (copyout(OCE_DMAPTR(&dma_mem,char), ioctl_ptr, req_size)) {
2286 firmware is filling all the attributes for this ioctl except
2287 the driver version..so fill it
2289 if(req.u0.rsp.opcode == OPCODE_COMMON_GET_CNTL_ATTRIBUTES) {
2290 struct mbx_common_get_cntl_attr *fw_cmd =
2291 (struct mbx_common_get_cntl_attr *)ioctl_ptr;
2292 _Static_assert(sizeof(COMPONENT_REVISION) <=
2293 sizeof(fw_cmd->params.rsp.cntl_attr_info.hba_attr.drv_ver_str),
2294 "driver version string too long");
2296 rc = copyout(COMPONENT_REVISION,
2297 fw_cmd->params.rsp.cntl_attr_info.hba_attr.drv_ver_str,
2298 sizeof(COMPONENT_REVISION));
2302 oce_dma_free(sc, &dma_mem);
2308 oce_eqd_set_periodic(POCE_SOFTC sc)
2310 struct oce_set_eqd set_eqd[OCE_MAX_EQ];
2311 struct oce_aic_obj *aic;
2313 uint64_t now = 0, delta;
2314 int eqd, i, num = 0;
2315 uint32_t tx_reqs = 0, rxpkts = 0, pps;
2319 #define ticks_to_msecs(t) (1000 * (t) / hz)
2321 for (i = 0 ; i < sc->neqs; i++) {
2323 aic = &sc->aic_obj[i];
2324 /* When setting the static eq delay from the user space */
2334 rxpkts = rq->rx_stats.rx_pkts;
2337 if (i + 1 < sc->nrqs) {
2339 rxpkts += rq->rx_stats.rx_pkts;
2343 tx_reqs = wq->tx_stats.tx_reqs;
2348 if (!aic->ticks || now < aic->ticks ||
2349 rxpkts < aic->prev_rxpkts || tx_reqs < aic->prev_txreqs) {
2350 aic->prev_rxpkts = rxpkts;
2351 aic->prev_txreqs = tx_reqs;
2356 delta = ticks_to_msecs(now - aic->ticks);
2358 pps = (((uint32_t)(rxpkts - aic->prev_rxpkts) * 1000) / delta) +
2359 (((uint32_t)(tx_reqs - aic->prev_txreqs) * 1000) / delta);
2360 eqd = (pps / 15000) << 2;
2364 /* Make sure that the eq delay is in the known range */
2365 eqd = min(eqd, aic->max_eqd);
2366 eqd = max(eqd, aic->min_eqd);
2368 aic->prev_rxpkts = rxpkts;
2369 aic->prev_txreqs = tx_reqs;
2373 if (eqd != aic->cur_eqd) {
2374 set_eqd[num].delay_multiplier = (eqd * 65)/100;
2375 set_eqd[num].eq_id = eqo->eq_id;
2381 /* Is there atleast one eq that needs to be modified? */
2382 for(i = 0; i < num; i += 8) {
2384 oce_mbox_eqd_modify_periodic(sc, &set_eqd[i], 8);
2386 oce_mbox_eqd_modify_periodic(sc, &set_eqd[i], (num - i));
2391 static void oce_detect_hw_error(POCE_SOFTC sc)
2394 uint32_t ue_low = 0, ue_high = 0, ue_low_mask = 0, ue_high_mask = 0;
2395 uint32_t sliport_status = 0, sliport_err1 = 0, sliport_err2 = 0;
2402 sliport_status = OCE_READ_REG32(sc, db, SLIPORT_STATUS_OFFSET);
2403 if (sliport_status & SLIPORT_STATUS_ERR_MASK) {
2404 sliport_err1 = OCE_READ_REG32(sc, db, SLIPORT_ERROR1_OFFSET);
2405 sliport_err2 = OCE_READ_REG32(sc, db, SLIPORT_ERROR2_OFFSET);
2408 ue_low = OCE_READ_REG32(sc, devcfg, PCICFG_UE_STATUS_LOW);
2409 ue_high = OCE_READ_REG32(sc, devcfg, PCICFG_UE_STATUS_HIGH);
2410 ue_low_mask = OCE_READ_REG32(sc, devcfg, PCICFG_UE_STATUS_LOW_MASK);
2411 ue_high_mask = OCE_READ_REG32(sc, devcfg, PCICFG_UE_STATUS_HI_MASK);
2413 ue_low = (ue_low & ~ue_low_mask);
2414 ue_high = (ue_high & ~ue_high_mask);
2417 /* On certain platforms BE hardware can indicate spurious UEs.
2418 * Allow the h/w to stop working completely in case of a real UE.
2419 * Hence not setting the hw_error for UE detection.
2421 if (sliport_status & SLIPORT_STATUS_ERR_MASK) {
2422 sc->hw_error = TRUE;
2423 device_printf(sc->dev, "Error detected in the card\n");
2426 if (sliport_status & SLIPORT_STATUS_ERR_MASK) {
2427 device_printf(sc->dev,
2428 "ERR: sliport status 0x%x\n", sliport_status);
2429 device_printf(sc->dev,
2430 "ERR: sliport error1 0x%x\n", sliport_err1);
2431 device_printf(sc->dev,
2432 "ERR: sliport error2 0x%x\n", sliport_err2);
2436 for (i = 0; ue_low; ue_low >>= 1, i++) {
2438 device_printf(sc->dev, "UE: %s bit set\n",
2439 ue_status_low_desc[i]);
2444 for (i = 0; ue_high; ue_high >>= 1, i++) {
2446 device_printf(sc->dev, "UE: %s bit set\n",
2447 ue_status_hi_desc[i]);
2454 oce_local_timer(void *arg)
2456 POCE_SOFTC sc = arg;
2459 oce_detect_hw_error(sc);
2460 oce_refresh_nic_stats(sc);
2461 oce_refresh_queue_stats(sc);
2462 oce_mac_addr_set(sc);
2465 for (i = 0; i < sc->nwqs; i++)
2466 oce_tx_restart(sc, sc->wq[i]);
2468 /* calculate and set the eq delay for optimal interrupt rate */
2469 if (IS_BE(sc) || IS_SH(sc))
2470 oce_eqd_set_periodic(sc);
2472 callout_reset(&sc->timer, hz, oce_local_timer, sc);
2476 oce_tx_compl_clean(POCE_SOFTC sc)
2479 int i = 0, timeo = 0, num_wqes = 0;
2480 int pending_txqs = sc->nwqs;
2482 /* Stop polling for compls when HW has been silent for 10ms or
2483 * hw_error or no outstanding completions expected
2486 pending_txqs = sc->nwqs;
2488 for_all_wq_queues(sc, wq, i) {
2489 num_wqes = oce_wq_handler(wq);
2494 if(!wq->ring->num_used)
2498 if (pending_txqs == 0 || ++timeo > 10 || sc->hw_error)
2504 for_all_wq_queues(sc, wq, i) {
2505 while(wq->ring->num_used) {
2506 LOCK(&wq->tx_compl_lock);
2507 oce_process_tx_completion(wq);
2508 UNLOCK(&wq->tx_compl_lock);
2514 /* NOTE : This should only be called holding
2518 oce_if_deactivate(POCE_SOFTC sc)
2525 if_setdrvflagbits(sc->ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
2527 oce_tx_compl_clean(sc);
2529 /* Stop intrs and finish any bottom halves pending */
2530 oce_hw_intr_disable(sc);
2532 /* Since taskqueue_drain takes a Gaint Lock, We should not acquire
2533 any other lock. So unlock device lock and require after
2534 completing taskqueue_drain.
2536 UNLOCK(&sc->dev_lock);
2537 for (i = 0; i < sc->intr_count; i++) {
2538 if (sc->intrs[i].tq != NULL) {
2539 taskqueue_drain(sc->intrs[i].tq, &sc->intrs[i].task);
2542 LOCK(&sc->dev_lock);
2544 /* Delete RX queue in card with flush param */
2547 /* Invalidate any pending cq and eq entries*/
2548 for_all_evnt_queues(sc, eq, i)
2550 for_all_rq_queues(sc, rq, i)
2551 oce_drain_rq_cq(rq);
2552 for_all_wq_queues(sc, wq, i)
2553 oce_drain_wq_cq(wq);
2555 /* But still we need to get MCC aync events.
2556 So enable intrs and also arm first EQ
2558 oce_hw_intr_enable(sc);
2559 oce_arm_eq(sc, sc->eq[0]->eq_id, 0, TRUE, FALSE);
2565 oce_if_activate(POCE_SOFTC sc)
2572 if_setdrvflagbits(sc->ifp, IFF_DRV_RUNNING , 0);
2574 oce_hw_intr_disable(sc);
2578 for_all_rq_queues(sc, rq, i) {
2579 rc = oce_start_rq(rq);
2581 device_printf(sc->dev, "Unable to start RX\n");
2584 for_all_wq_queues(sc, wq, i) {
2585 rc = oce_start_wq(wq);
2587 device_printf(sc->dev, "Unable to start TX\n");
2590 for_all_evnt_queues(sc, eq, i)
2591 oce_arm_eq(sc, eq->eq_id, 0, TRUE, FALSE);
2593 oce_hw_intr_enable(sc);
2598 process_link_state(POCE_SOFTC sc, struct oce_async_cqe_link_state *acqe)
2600 /* Update Link status */
2601 if ((acqe->u0.s.link_status & ~ASYNC_EVENT_LOGICAL) ==
2602 ASYNC_EVENT_LINK_UP) {
2603 sc->link_status = ASYNC_EVENT_LINK_UP;
2604 if_link_state_change(sc->ifp, LINK_STATE_UP);
2606 sc->link_status = ASYNC_EVENT_LINK_DOWN;
2607 if_link_state_change(sc->ifp, LINK_STATE_DOWN);
2611 static void oce_async_grp5_osbmc_process(POCE_SOFTC sc,
2612 struct oce_async_evt_grp5_os2bmc *evt)
2614 DW_SWAP(evt, sizeof(struct oce_async_evt_grp5_os2bmc));
2615 if (evt->u.s.mgmt_enable)
2616 sc->flags |= OCE_FLAGS_OS2BMC;
2620 sc->bmc_filt_mask = evt->u.s.arp_filter;
2621 sc->bmc_filt_mask |= (evt->u.s.dhcp_client_filt << 1);
2622 sc->bmc_filt_mask |= (evt->u.s.dhcp_server_filt << 2);
2623 sc->bmc_filt_mask |= (evt->u.s.net_bios_filt << 3);
2624 sc->bmc_filt_mask |= (evt->u.s.bcast_filt << 4);
2625 sc->bmc_filt_mask |= (evt->u.s.ipv6_nbr_filt << 5);
2626 sc->bmc_filt_mask |= (evt->u.s.ipv6_ra_filt << 6);
2627 sc->bmc_filt_mask |= (evt->u.s.ipv6_ras_filt << 7);
2628 sc->bmc_filt_mask |= (evt->u.s.mcast_filt << 8);
2631 static void oce_process_grp5_events(POCE_SOFTC sc, struct oce_mq_cqe *cqe)
2633 struct oce_async_event_grp5_pvid_state *gcqe;
2634 struct oce_async_evt_grp5_os2bmc *bmccqe;
2636 switch (cqe->u0.s.async_type) {
2637 case ASYNC_EVENT_PVID_STATE:
2639 gcqe = (struct oce_async_event_grp5_pvid_state *)cqe;
2641 sc->pvid = gcqe->tag & VLAN_VID_MASK;
2645 case ASYNC_EVENT_OS2BMC:
2646 bmccqe = (struct oce_async_evt_grp5_os2bmc *)cqe;
2647 oce_async_grp5_osbmc_process(sc, bmccqe);
2654 /* Handle the Completion Queue for the Mailbox/Async notifications */
2656 oce_mq_handler(void *arg)
2658 struct oce_mq *mq = (struct oce_mq *)arg;
2659 POCE_SOFTC sc = mq->parent;
2660 struct oce_cq *cq = mq->cq;
2661 int num_cqes = 0, evt_type = 0, optype = 0;
2662 struct oce_mq_cqe *cqe;
2663 struct oce_async_cqe_link_state *acqe;
2664 struct oce_async_event_qnq *dbgcqe;
2666 bus_dmamap_sync(cq->ring->dma.tag,
2667 cq->ring->dma.map, BUS_DMASYNC_POSTWRITE);
2668 cqe = RING_GET_CONSUMER_ITEM_VA(cq->ring, struct oce_mq_cqe);
2670 while (cqe->u0.dw[3]) {
2671 DW_SWAP((uint32_t *) cqe, sizeof(oce_mq_cqe));
2672 if (cqe->u0.s.async_event) {
2673 evt_type = cqe->u0.s.event_type;
2674 optype = cqe->u0.s.async_type;
2675 if (evt_type == ASYNC_EVENT_CODE_LINK_STATE) {
2676 /* Link status evt */
2677 acqe = (struct oce_async_cqe_link_state *)cqe;
2678 process_link_state(sc, acqe);
2679 } else if (evt_type == ASYNC_EVENT_GRP5) {
2680 oce_process_grp5_events(sc, cqe);
2681 } else if (evt_type == ASYNC_EVENT_CODE_DEBUG &&
2682 optype == ASYNC_EVENT_DEBUG_QNQ) {
2683 dbgcqe = (struct oce_async_event_qnq *)cqe;
2685 sc->qnqid = dbgcqe->vlan_tag;
2686 sc->qnq_debug_event = TRUE;
2690 RING_GET(cq->ring, 1);
2691 bus_dmamap_sync(cq->ring->dma.tag,
2692 cq->ring->dma.map, BUS_DMASYNC_POSTWRITE);
2693 cqe = RING_GET_CONSUMER_ITEM_VA(cq->ring, struct oce_mq_cqe);
2698 oce_arm_cq(sc, cq->cq_id, num_cqes, FALSE);
2704 setup_max_queues_want(POCE_SOFTC sc)
2706 /* Check if it is FLEX machine. Is so dont use RSS */
2707 if ((sc->function_mode & FNM_FLEX10_MODE) ||
2708 (sc->function_mode & FNM_UMC_MODE) ||
2709 (sc->function_mode & FNM_VNIC_MODE) ||
2710 (!is_rss_enabled(sc)) ||
2715 sc->nrqs = MIN(OCE_NCPUS, sc->nrssqs) + 1;
2716 sc->nwqs = MIN(OCE_NCPUS, sc->nrssqs);
2719 if (IS_BE2(sc) && is_rss_enabled(sc))
2720 sc->nrqs = MIN(OCE_NCPUS, sc->nrssqs) + 1;
2724 update_queues_got(POCE_SOFTC sc)
2726 if (is_rss_enabled(sc)) {
2727 sc->nrqs = sc->intr_count + 1;
2728 sc->nwqs = sc->intr_count;
2739 oce_check_ipv6_ext_hdr(struct mbuf *m)
2741 struct ether_header *eh = mtod(m, struct ether_header *);
2742 caddr_t m_datatemp = m->m_data;
2744 if (eh->ether_type == htons(ETHERTYPE_IPV6)) {
2745 m->m_data += sizeof(struct ether_header);
2746 struct ip6_hdr *ip6 = mtod(m, struct ip6_hdr *);
2748 if((ip6->ip6_nxt != IPPROTO_TCP) && \
2749 (ip6->ip6_nxt != IPPROTO_UDP)){
2750 struct ip6_ext *ip6e = NULL;
2751 m->m_data += sizeof(struct ip6_hdr);
2753 ip6e = (struct ip6_ext *) mtod(m, struct ip6_ext *);
2754 if(ip6e->ip6e_len == 0xff) {
2755 m->m_data = m_datatemp;
2759 m->m_data = m_datatemp;
2765 is_be3_a1(POCE_SOFTC sc)
2767 if((sc->flags & OCE_FLAGS_BE3) && ((sc->asic_revision & 0xFF) < 2)) {
2773 static struct mbuf *
2774 oce_insert_vlan_tag(POCE_SOFTC sc, struct mbuf *m, boolean_t *complete)
2776 uint16_t vlan_tag = 0;
2781 /* Embed vlan tag in the packet if it is not part of it */
2782 if(m->m_flags & M_VLANTAG) {
2783 vlan_tag = EVL_VLANOFTAG(m->m_pkthdr.ether_vtag);
2784 m->m_flags &= ~M_VLANTAG;
2787 /* if UMC, ignore vlan tag insertion and instead insert pvid */
2790 vlan_tag = sc->pvid;
2796 m = ether_vlanencap(m, vlan_tag);
2800 m = ether_vlanencap(m, sc->qnqid);
2809 oce_tx_asic_stall_verify(POCE_SOFTC sc, struct mbuf *m)
2811 if(is_be3_a1(sc) && IS_QNQ_OR_UMC(sc) && \
2812 oce_check_ipv6_ext_hdr(m)) {
2819 oce_get_config(POCE_SOFTC sc)
2822 uint32_t max_rss = 0;
2824 if ((IS_BE(sc) || IS_SH(sc)) && (!sc->be3_native))
2825 max_rss = OCE_LEGACY_MODE_RSS;
2827 max_rss = OCE_MAX_RSS;
2830 rc = oce_get_profile_config(sc, max_rss);
2832 sc->nwqs = OCE_MAX_WQ;
2833 sc->nrssqs = max_rss;
2834 sc->nrqs = sc->nrssqs + 1;
2837 else { /* For BE3 don't rely on fw for determining the resources */
2838 sc->nrssqs = max_rss;
2839 sc->nrqs = sc->nrssqs + 1;
2840 sc->nwqs = OCE_MAX_WQ;
2841 sc->max_vlans = MAX_VLANFILTER_SIZE;
2846 oce_rdma_close(void)
2848 if (oce_rdma_if != NULL) {
2854 oce_get_mac_addr(POCE_SOFTC sc, uint8_t *macaddr)
2856 memcpy(macaddr, sc->macaddr.mac_addr, 6);
2860 oce_register_rdma(POCE_RDMA_INFO rdma_info, POCE_RDMA_IF rdma_if)
2863 struct oce_dev_info di;
2866 if ((rdma_info == NULL) || (rdma_if == NULL)) {
2870 if ((rdma_info->size != OCE_RDMA_INFO_SIZE) ||
2871 (rdma_if->size != OCE_RDMA_IF_SIZE)) {
2875 rdma_info->close = oce_rdma_close;
2876 rdma_info->mbox_post = oce_mbox_post;
2877 rdma_info->common_req_hdr_init = mbx_common_req_hdr_init;
2878 rdma_info->get_mac_addr = oce_get_mac_addr;
2880 oce_rdma_if = rdma_if;
2883 while (sc != NULL) {
2884 if (oce_rdma_if->announce != NULL) {
2885 memset(&di, 0, sizeof(di));
2889 di.db_bhandle = sc->db_bhandle;
2890 di.db_btag = sc->db_btag;
2891 di.db_page_size = 4096;
2892 if (sc->flags & OCE_FLAGS_USING_MSIX) {
2893 di.intr_mode = OCE_INTERRUPT_MODE_MSIX;
2894 } else if (sc->flags & OCE_FLAGS_USING_MSI) {
2895 di.intr_mode = OCE_INTERRUPT_MODE_MSI;
2897 di.intr_mode = OCE_INTERRUPT_MODE_INTX;
2899 di.dev_family = OCE_GEN2_FAMILY; // fixme: must detect skyhawk
2900 if (di.intr_mode != OCE_INTERRUPT_MODE_INTX) {
2901 di.msix.num_vectors = sc->intr_count + sc->roce_intr_count;
2902 di.msix.start_vector = sc->intr_count;
2903 for (i=0; i<di.msix.num_vectors; i++) {
2904 di.msix.vector_list[i] = sc->intrs[i].vector;
2908 memcpy(di.mac_addr, sc->macaddr.mac_addr, 6);
2909 di.vendor_id = pci_get_vendor(sc->dev);
2910 di.dev_id = pci_get_device(sc->dev);
2912 if (sc->rdma_flags & OCE_RDMA_FLAG_SUPPORTED) {
2913 di.flags |= OCE_RDMA_INFO_RDMA_SUPPORTED;
2916 rdma_if->announce(&di);
2925 oce_read_env_variables( POCE_SOFTC sc )
2930 /* read if user wants to enable hwlro or swlro */
2931 //value = getenv("oce_enable_hwlro");
2932 if(value && IS_SH(sc)) {
2933 sc->enable_hwlro = strtol(value, NULL, 10);
2934 if(sc->enable_hwlro) {
2935 rc = oce_mbox_nic_query_lro_capabilities(sc, NULL, NULL);
2937 device_printf(sc->dev, "no hardware lro support\n");
2938 device_printf(sc->dev, "software lro enabled\n");
2939 sc->enable_hwlro = 0;
2941 device_printf(sc->dev, "hardware lro enabled\n");
2942 oce_max_rsp_handled = 32;
2945 device_printf(sc->dev, "software lro enabled\n");
2948 sc->enable_hwlro = 0;
2951 /* read mbuf size */
2952 //value = getenv("oce_rq_buf_size");
2953 if(value && IS_SH(sc)) {
2954 oce_rq_buf_size = strtol(value, NULL, 10);
2955 switch(oce_rq_buf_size) {
2963 device_printf(sc->dev, " Supported oce_rq_buf_size values are 2K, 4K, 9K, 16K \n");
2964 oce_rq_buf_size = 2048;