2 * Copyright (C) 2013 Emulex
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of the Emulex Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
31 * Contact Information:
32 * freebsd-drivers@emulex.com
36 * Costa Mesa, CA 92626
41 #include "opt_inet6.h"
47 #define is_tso_pkt(m) (m->m_pkthdr.csum_flags & CSUM_TSO)
49 /* UE Status Low CSR */
50 static char *ue_status_low_desc[] = {
85 /* UE Status High CSR */
86 static char *ue_status_hi_desc[] = {
121 struct oce_common_cqe_info{
123 uint8_t l4_cksum_pass:1;
124 uint8_t ip_cksum_pass:1;
125 uint8_t ipv6_frame:1;
134 /* Driver entry points prototypes */
135 static int oce_probe(device_t dev);
136 static int oce_attach(device_t dev);
137 static int oce_detach(device_t dev);
138 static int oce_shutdown(device_t dev);
139 static int oce_ioctl(struct ifnet *ifp, u_long command, caddr_t data);
140 static void oce_init(void *xsc);
141 static int oce_multiq_start(struct ifnet *ifp, struct mbuf *m);
142 static void oce_multiq_flush(struct ifnet *ifp);
144 /* Driver interrupt routines protypes */
145 static void oce_intr(void *arg, int pending);
146 static int oce_setup_intr(POCE_SOFTC sc);
147 static int oce_fast_isr(void *arg);
148 static int oce_alloc_intr(POCE_SOFTC sc, int vector,
149 void (*isr) (void *arg, int pending));
151 /* Media callbacks prototypes */
152 static void oce_media_status(struct ifnet *ifp, struct ifmediareq *req);
153 static int oce_media_change(struct ifnet *ifp);
155 /* Transmit routines prototypes */
156 static int oce_tx(POCE_SOFTC sc, struct mbuf **mpp, int wq_index);
157 static void oce_tx_restart(POCE_SOFTC sc, struct oce_wq *wq);
158 static void oce_process_tx_completion(struct oce_wq *wq);
159 static int oce_multiq_transmit(struct ifnet *ifp, struct mbuf *m,
162 /* Receive routines prototypes */
163 static int oce_cqe_vtp_valid(POCE_SOFTC sc, struct oce_nic_rx_cqe *cqe);
164 static int oce_cqe_portid_valid(POCE_SOFTC sc, struct oce_nic_rx_cqe *cqe);
165 static void oce_rx(struct oce_rq *rq, struct oce_nic_rx_cqe *cqe);
166 static void oce_check_rx_bufs(POCE_SOFTC sc, uint32_t num_cqes, struct oce_rq *rq);
167 static uint16_t oce_rq_handler_lro(void *arg);
168 static void oce_correct_header(struct mbuf *m, struct nic_hwlro_cqe_part1 *cqe1, struct nic_hwlro_cqe_part2 *cqe2);
169 static void oce_rx_lro(struct oce_rq *rq, struct nic_hwlro_singleton_cqe *cqe, struct nic_hwlro_cqe_part2 *cqe2);
170 static void oce_rx_mbuf_chain(struct oce_rq *rq, struct oce_common_cqe_info *cqe_info, struct mbuf **m);
172 /* Helper function prototypes in this file */
173 static int oce_attach_ifp(POCE_SOFTC sc);
174 static void oce_add_vlan(void *arg, struct ifnet *ifp, uint16_t vtag);
175 static void oce_del_vlan(void *arg, struct ifnet *ifp, uint16_t vtag);
176 static int oce_vid_config(POCE_SOFTC sc);
177 static void oce_mac_addr_set(POCE_SOFTC sc);
178 static int oce_handle_passthrough(struct ifnet *ifp, caddr_t data);
179 static void oce_local_timer(void *arg);
180 static void oce_if_deactivate(POCE_SOFTC sc);
181 static void oce_if_activate(POCE_SOFTC sc);
182 static void setup_max_queues_want(POCE_SOFTC sc);
183 static void update_queues_got(POCE_SOFTC sc);
184 static void process_link_state(POCE_SOFTC sc,
185 struct oce_async_cqe_link_state *acqe);
186 static int oce_tx_asic_stall_verify(POCE_SOFTC sc, struct mbuf *m);
187 static void oce_get_config(POCE_SOFTC sc);
188 static struct mbuf *oce_insert_vlan_tag(POCE_SOFTC sc, struct mbuf *m, boolean_t *complete);
189 static void oce_read_env_variables(POCE_SOFTC sc);
193 #if defined(INET6) || defined(INET)
194 static int oce_init_lro(POCE_SOFTC sc);
195 static struct mbuf * oce_tso_setup(POCE_SOFTC sc, struct mbuf **mpp);
198 static device_method_t oce_dispatch[] = {
199 DEVMETHOD(device_probe, oce_probe),
200 DEVMETHOD(device_attach, oce_attach),
201 DEVMETHOD(device_detach, oce_detach),
202 DEVMETHOD(device_shutdown, oce_shutdown),
207 static driver_t oce_driver = {
212 static devclass_t oce_devclass;
215 DRIVER_MODULE(oce, pci, oce_driver, oce_devclass, 0, 0);
216 MODULE_DEPEND(oce, pci, 1, 1, 1);
217 MODULE_DEPEND(oce, ether, 1, 1, 1);
218 MODULE_VERSION(oce, 1);
222 const char component_revision[32] = {"///" COMPONENT_REVISION "///"};
224 /* Module capabilites and parameters */
225 uint32_t oce_max_rsp_handled = OCE_MAX_RSP_HANDLED;
226 uint32_t oce_enable_rss = OCE_MODCAP_RSS;
227 uint32_t oce_rq_buf_size = 2048;
229 TUNABLE_INT("hw.oce.max_rsp_handled", &oce_max_rsp_handled);
230 TUNABLE_INT("hw.oce.enable_rss", &oce_enable_rss);
233 /* Supported devices table */
234 static uint32_t supportedDevices[] = {
235 (PCI_VENDOR_SERVERENGINES << 16) | PCI_PRODUCT_BE2,
236 (PCI_VENDOR_SERVERENGINES << 16) | PCI_PRODUCT_BE3,
237 (PCI_VENDOR_EMULEX << 16) | PCI_PRODUCT_BE3,
238 (PCI_VENDOR_EMULEX << 16) | PCI_PRODUCT_XE201,
239 (PCI_VENDOR_EMULEX << 16) | PCI_PRODUCT_XE201_VF,
240 (PCI_VENDOR_EMULEX << 16) | PCI_PRODUCT_SH
243 POCE_SOFTC softc_head = NULL;
244 POCE_SOFTC softc_tail = NULL;
246 struct oce_rdma_if *oce_rdma_if = NULL;
248 /*****************************************************************************
249 * Driver entry points functions *
250 *****************************************************************************/
253 oce_probe(device_t dev)
261 sc = device_get_softc(dev);
262 bzero(sc, sizeof(OCE_SOFTC));
265 vendor = pci_get_vendor(dev);
266 device = pci_get_device(dev);
268 for (i = 0; i < (sizeof(supportedDevices) / sizeof(uint32_t)); i++) {
269 if (vendor == ((supportedDevices[i] >> 16) & 0xffff)) {
270 if (device == (supportedDevices[i] & 0xffff)) {
271 sprintf(str, "%s:%s", "Emulex CNA NIC function",
273 device_set_desc_copy(dev, str);
276 case PCI_PRODUCT_BE2:
277 sc->flags |= OCE_FLAGS_BE2;
279 case PCI_PRODUCT_BE3:
280 sc->flags |= OCE_FLAGS_BE3;
282 case PCI_PRODUCT_XE201:
283 case PCI_PRODUCT_XE201_VF:
284 sc->flags |= OCE_FLAGS_XE201;
287 sc->flags |= OCE_FLAGS_SH;
292 return BUS_PROBE_DEFAULT;
302 oce_attach(device_t dev)
307 sc = device_get_softc(dev);
309 rc = oce_hw_pci_alloc(sc);
313 sc->tx_ring_size = OCE_TX_RING_SIZE;
314 sc->rx_ring_size = OCE_RX_RING_SIZE;
315 /* receive fragment size should be multiple of 2K */
316 sc->rq_frag_size = ((oce_rq_buf_size / 2048) * 2048);
317 sc->flow_control = OCE_DEFAULT_FLOW_CONTROL;
318 sc->promisc = OCE_DEFAULT_PROMISCUOUS;
320 LOCK_CREATE(&sc->bmbx_lock, "Mailbox_lock");
321 LOCK_CREATE(&sc->dev_lock, "Device_lock");
323 /* initialise the hardware */
324 rc = oce_hw_init(sc);
328 oce_read_env_variables(sc);
332 setup_max_queues_want(sc);
334 rc = oce_setup_intr(sc);
338 rc = oce_queue_init_all(sc);
342 rc = oce_attach_ifp(sc);
346 #if defined(INET6) || defined(INET)
347 rc = oce_init_lro(sc);
352 rc = oce_hw_start(sc);
356 sc->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
357 oce_add_vlan, sc, EVENTHANDLER_PRI_FIRST);
358 sc->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
359 oce_del_vlan, sc, EVENTHANDLER_PRI_FIRST);
361 rc = oce_stats_init(sc);
367 callout_init(&sc->timer, CALLOUT_MPSAFE);
368 rc = callout_reset(&sc->timer, 2 * hz, oce_local_timer, sc);
373 if (softc_tail != NULL) {
374 softc_tail->next = sc;
383 callout_drain(&sc->timer);
387 EVENTHANDLER_DEREGISTER(vlan_config, sc->vlan_attach);
389 EVENTHANDLER_DEREGISTER(vlan_unconfig, sc->vlan_detach);
390 oce_hw_intr_disable(sc);
392 #if defined(INET6) || defined(INET)
396 ether_ifdetach(sc->ifp);
399 oce_queue_release_all(sc);
403 oce_dma_free(sc, &sc->bsmbx);
406 LOCK_DESTROY(&sc->dev_lock);
407 LOCK_DESTROY(&sc->bmbx_lock);
414 oce_detach(device_t dev)
416 POCE_SOFTC sc = device_get_softc(dev);
417 POCE_SOFTC poce_sc_tmp, *ppoce_sc_tmp1, poce_sc_tmp2 = NULL;
419 poce_sc_tmp = softc_head;
420 ppoce_sc_tmp1 = &softc_head;
421 while (poce_sc_tmp != NULL) {
422 if (poce_sc_tmp == sc) {
423 *ppoce_sc_tmp1 = sc->next;
424 if (sc->next == NULL) {
425 softc_tail = poce_sc_tmp2;
429 poce_sc_tmp2 = poce_sc_tmp;
430 ppoce_sc_tmp1 = &poce_sc_tmp->next;
431 poce_sc_tmp = poce_sc_tmp->next;
435 oce_if_deactivate(sc);
436 UNLOCK(&sc->dev_lock);
438 callout_drain(&sc->timer);
440 if (sc->vlan_attach != NULL)
441 EVENTHANDLER_DEREGISTER(vlan_config, sc->vlan_attach);
442 if (sc->vlan_detach != NULL)
443 EVENTHANDLER_DEREGISTER(vlan_unconfig, sc->vlan_detach);
445 ether_ifdetach(sc->ifp);
451 bus_generic_detach(dev);
458 oce_shutdown(device_t dev)
462 rc = oce_detach(dev);
469 oce_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
471 struct ifreq *ifr = (struct ifreq *)data;
472 POCE_SOFTC sc = ifp->if_softc;
479 rc = ifmedia_ioctl(ifp, ifr, &sc->media, command);
483 if (ifr->ifr_mtu > OCE_MAX_MTU)
486 ifp->if_mtu = ifr->ifr_mtu;
490 if (ifp->if_flags & IFF_UP) {
491 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
492 sc->ifp->if_drv_flags |= IFF_DRV_RUNNING;
495 device_printf(sc->dev, "Interface Up\n");
499 sc->ifp->if_drv_flags &=
500 ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
501 oce_if_deactivate(sc);
503 UNLOCK(&sc->dev_lock);
505 device_printf(sc->dev, "Interface Down\n");
508 if ((ifp->if_flags & IFF_PROMISC) && !sc->promisc) {
509 if (!oce_rxf_set_promiscuous(sc, (1 | (1 << 1))))
511 } else if (!(ifp->if_flags & IFF_PROMISC) && sc->promisc) {
512 if (!oce_rxf_set_promiscuous(sc, 0))
520 rc = oce_hw_update_multicast(sc);
522 device_printf(sc->dev,
523 "Update multicast address failed\n");
527 u = ifr->ifr_reqcap ^ ifp->if_capenable;
529 if (u & IFCAP_TXCSUM) {
530 ifp->if_capenable ^= IFCAP_TXCSUM;
531 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
533 if (IFCAP_TSO & ifp->if_capenable &&
534 !(IFCAP_TXCSUM & ifp->if_capenable)) {
535 ifp->if_capenable &= ~IFCAP_TSO;
536 ifp->if_hwassist &= ~CSUM_TSO;
538 "TSO disabled due to -txcsum.\n");
542 if (u & IFCAP_RXCSUM)
543 ifp->if_capenable ^= IFCAP_RXCSUM;
545 if (u & IFCAP_TSO4) {
546 ifp->if_capenable ^= IFCAP_TSO4;
548 if (IFCAP_TSO & ifp->if_capenable) {
549 if (IFCAP_TXCSUM & ifp->if_capenable)
550 ifp->if_hwassist |= CSUM_TSO;
552 ifp->if_capenable &= ~IFCAP_TSO;
553 ifp->if_hwassist &= ~CSUM_TSO;
555 "Enable txcsum first.\n");
559 ifp->if_hwassist &= ~CSUM_TSO;
562 if (u & IFCAP_VLAN_HWTAGGING)
563 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
565 if (u & IFCAP_VLAN_HWFILTER) {
566 ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
569 #if defined(INET6) || defined(INET)
571 ifp->if_capenable ^= IFCAP_LRO;
572 if(sc->enable_hwlro) {
573 if(ifp->if_capenable & IFCAP_LRO) {
574 rc = oce_mbox_nic_set_iface_lro_config(sc, 1);
576 rc = oce_mbox_nic_set_iface_lro_config(sc, 0);
585 rc = oce_handle_passthrough(ifp, data);
588 rc = ether_ioctl(ifp, command, data);
603 if (sc->ifp->if_flags & IFF_UP) {
604 oce_if_deactivate(sc);
608 UNLOCK(&sc->dev_lock);
614 oce_multiq_start(struct ifnet *ifp, struct mbuf *m)
616 POCE_SOFTC sc = ifp->if_softc;
617 struct oce_wq *wq = NULL;
621 if (!sc->link_status)
624 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)
625 queue_index = m->m_pkthdr.flowid % sc->nwqs;
627 wq = sc->wq[queue_index];
630 status = oce_multiq_transmit(ifp, m, wq);
631 UNLOCK(&wq->tx_lock);
639 oce_multiq_flush(struct ifnet *ifp)
641 POCE_SOFTC sc = ifp->if_softc;
645 for (i = 0; i < sc->nwqs; i++) {
646 while ((m = buf_ring_dequeue_sc(sc->wq[i]->br)) != NULL)
654 /*****************************************************************************
655 * Driver interrupt routines functions *
656 *****************************************************************************/
659 oce_intr(void *arg, int pending)
662 POCE_INTR_INFO ii = (POCE_INTR_INFO) arg;
663 POCE_SOFTC sc = ii->sc;
664 struct oce_eq *eq = ii->eq;
666 struct oce_cq *cq = NULL;
670 bus_dmamap_sync(eq->ring->dma.tag, eq->ring->dma.map,
671 BUS_DMASYNC_POSTWRITE);
673 eqe = RING_GET_CONSUMER_ITEM_VA(eq->ring, struct oce_eqe);
677 bus_dmamap_sync(eq->ring->dma.tag, eq->ring->dma.map,
678 BUS_DMASYNC_POSTWRITE);
679 RING_GET(eq->ring, 1);
685 goto eq_arm; /* Spurious */
687 /* Clear EQ entries, but dont arm */
688 oce_arm_eq(sc, eq->eq_id, num_eqes, FALSE, FALSE);
690 /* Process TX, RX and MCC. But dont arm CQ*/
691 for (i = 0; i < eq->cq_valid; i++) {
693 (*cq->cq_handler)(cq->cb_arg);
696 /* Arm all cqs connected to this EQ */
697 for (i = 0; i < eq->cq_valid; i++) {
699 oce_arm_cq(sc, cq->cq_id, 0, TRUE);
703 oce_arm_eq(sc, eq->eq_id, 0, TRUE, FALSE);
710 oce_setup_intr(POCE_SOFTC sc)
712 int rc = 0, use_intx = 0;
713 int vector = 0, req_vectors = 0;
714 int tot_req_vectors, tot_vectors;
716 if (is_rss_enabled(sc))
717 req_vectors = MAX((sc->nrqs - 1), sc->nwqs);
721 tot_req_vectors = req_vectors;
722 if (sc->rdma_flags & OCE_RDMA_FLAG_SUPPORTED) {
723 if (req_vectors > 1) {
724 tot_req_vectors += OCE_RDMA_VECTORS;
725 sc->roce_intr_count = OCE_RDMA_VECTORS;
729 if (sc->flags & OCE_FLAGS_MSIX_CAPABLE) {
730 sc->intr_count = req_vectors;
731 tot_vectors = tot_req_vectors;
732 rc = pci_alloc_msix(sc->dev, &tot_vectors);
735 pci_release_msi(sc->dev);
737 if (sc->rdma_flags & OCE_RDMA_FLAG_SUPPORTED) {
738 if (tot_vectors < tot_req_vectors) {
739 if (sc->intr_count < (2 * OCE_RDMA_VECTORS)) {
740 sc->roce_intr_count = (tot_vectors / 2);
742 sc->intr_count = tot_vectors - sc->roce_intr_count;
745 sc->intr_count = tot_vectors;
747 sc->flags |= OCE_FLAGS_USING_MSIX;
755 /* Scale number of queues based on intr we got */
756 update_queues_got(sc);
759 device_printf(sc->dev, "Using legacy interrupt\n");
760 rc = oce_alloc_intr(sc, vector, oce_intr);
764 for (; vector < sc->intr_count; vector++) {
765 rc = oce_alloc_intr(sc, vector, oce_intr);
779 oce_fast_isr(void *arg)
781 POCE_INTR_INFO ii = (POCE_INTR_INFO) arg;
782 POCE_SOFTC sc = ii->sc;
787 oce_arm_eq(sc, ii->eq->eq_id, 0, FALSE, TRUE);
789 taskqueue_enqueue(ii->tq, &ii->task);
793 return FILTER_HANDLED;
798 oce_alloc_intr(POCE_SOFTC sc, int vector, void (*isr) (void *arg, int pending))
800 POCE_INTR_INFO ii = &sc->intrs[vector];
803 if (vector >= OCE_MAX_EQ)
806 /* Set the resource id for the interrupt.
807 * MSIx is vector + 1 for the resource id,
808 * INTx is 0 for the resource id.
810 if (sc->flags & OCE_FLAGS_USING_MSIX)
814 ii->intr_res = bus_alloc_resource_any(sc->dev,
816 &rr, RF_ACTIVE|RF_SHAREABLE);
818 if (ii->intr_res == NULL) {
819 device_printf(sc->dev,
820 "Could not allocate interrupt\n");
825 TASK_INIT(&ii->task, 0, isr, ii);
827 sprintf(ii->task_name, "oce_task[%d]", ii->vector);
828 ii->tq = taskqueue_create_fast(ii->task_name,
830 taskqueue_thread_enqueue,
832 taskqueue_start_threads(&ii->tq, 1, PI_NET, "%s taskq",
833 device_get_nameunit(sc->dev));
836 rc = bus_setup_intr(sc->dev,
839 oce_fast_isr, NULL, ii, &ii->tag);
846 oce_intr_free(POCE_SOFTC sc)
850 for (i = 0; i < sc->intr_count; i++) {
852 if (sc->intrs[i].tag != NULL)
853 bus_teardown_intr(sc->dev, sc->intrs[i].intr_res,
855 if (sc->intrs[i].tq != NULL)
856 taskqueue_free(sc->intrs[i].tq);
858 if (sc->intrs[i].intr_res != NULL)
859 bus_release_resource(sc->dev, SYS_RES_IRQ,
861 sc->intrs[i].intr_res);
862 sc->intrs[i].tag = NULL;
863 sc->intrs[i].intr_res = NULL;
866 if (sc->flags & OCE_FLAGS_USING_MSIX)
867 pci_release_msi(sc->dev);
873 /******************************************************************************
874 * Media callbacks functions *
875 ******************************************************************************/
878 oce_media_status(struct ifnet *ifp, struct ifmediareq *req)
880 POCE_SOFTC sc = (POCE_SOFTC) ifp->if_softc;
883 req->ifm_status = IFM_AVALID;
884 req->ifm_active = IFM_ETHER;
886 if (sc->link_status == 1)
887 req->ifm_status |= IFM_ACTIVE;
891 switch (sc->link_speed) {
892 case 1: /* 10 Mbps */
893 req->ifm_active |= IFM_10_T | IFM_FDX;
896 case 2: /* 100 Mbps */
897 req->ifm_active |= IFM_100_TX | IFM_FDX;
901 req->ifm_active |= IFM_1000_T | IFM_FDX;
904 case 4: /* 10 Gbps */
905 req->ifm_active |= IFM_10G_SR | IFM_FDX;
908 case 5: /* 20 Gbps */
909 req->ifm_active |= IFM_10G_SR | IFM_FDX;
912 case 6: /* 25 Gbps */
913 req->ifm_active |= IFM_10G_SR | IFM_FDX;
916 case 7: /* 40 Gbps */
917 req->ifm_active |= IFM_40G_SR4 | IFM_FDX;
930 oce_media_change(struct ifnet *ifp)
936 static void oce_is_pkt_dest_bmc(POCE_SOFTC sc,
937 struct mbuf *m, boolean_t *os2bmc,
940 struct ether_header *eh = NULL;
942 eh = mtod(m, struct ether_header *);
944 if (!is_os2bmc_enabled(sc) || *os2bmc) {
948 if (!ETHER_IS_MULTICAST(eh->ether_dhost))
951 if (is_mc_allowed_on_bmc(sc, eh) ||
952 is_bc_allowed_on_bmc(sc, eh) ||
953 is_arp_allowed_on_bmc(sc, ntohs(eh->ether_type))) {
958 if (mtod(m, struct ip *)->ip_p == IPPROTO_IPV6) {
959 struct ip6_hdr *ip6 = mtod(m, struct ip6_hdr *);
960 uint8_t nexthdr = ip6->ip6_nxt;
961 if (nexthdr == IPPROTO_ICMPV6) {
962 struct icmp6_hdr *icmp6 = (struct icmp6_hdr *)(ip6 + 1);
963 switch (icmp6->icmp6_type) {
964 case ND_ROUTER_ADVERT:
965 *os2bmc = is_ipv6_ra_filt_enabled(sc);
967 case ND_NEIGHBOR_ADVERT:
968 *os2bmc = is_ipv6_na_filt_enabled(sc);
976 if (mtod(m, struct ip *)->ip_p == IPPROTO_UDP) {
977 struct ip *ip = mtod(m, struct ip *);
978 int iphlen = ip->ip_hl << 2;
979 struct udphdr *uh = (struct udphdr *)((caddr_t)ip + iphlen);
980 switch (uh->uh_dport) {
981 case DHCP_CLIENT_PORT:
982 *os2bmc = is_dhcp_client_filt_enabled(sc);
984 case DHCP_SERVER_PORT:
985 *os2bmc = is_dhcp_srvr_filt_enabled(sc);
989 *os2bmc = is_nbios_filt_enabled(sc);
991 case DHCPV6_RAS_PORT:
992 *os2bmc = is_ipv6_ras_filt_enabled(sc);
1000 *m_new = m_dup(m, M_NOWAIT);
1005 *m_new = oce_insert_vlan_tag(sc, *m_new, NULL);
1011 /*****************************************************************************
1012 * Transmit routines functions *
1013 *****************************************************************************/
1016 oce_tx(POCE_SOFTC sc, struct mbuf **mpp, int wq_index)
1018 int rc = 0, i, retry_cnt = 0;
1019 bus_dma_segment_t segs[OCE_MAX_TX_ELEMENTS];
1020 struct mbuf *m, *m_temp, *m_new = NULL;
1021 struct oce_wq *wq = sc->wq[wq_index];
1022 struct oce_packet_desc *pd;
1023 struct oce_nic_hdr_wqe *nichdr;
1024 struct oce_nic_frag_wqe *nicfrag;
1025 struct ether_header *eh = NULL;
1028 boolean_t complete = TRUE;
1029 boolean_t os2bmc = FALSE;
1035 if (!(m->m_flags & M_PKTHDR)) {
1040 /* Don't allow non-TSO packets longer than MTU */
1041 if (!is_tso_pkt(m)) {
1042 eh = mtod(m, struct ether_header *);
1043 if(m->m_pkthdr.len > ETHER_MAX_FRAME(sc->ifp, eh->ether_type, FALSE))
1047 if(oce_tx_asic_stall_verify(sc, m)) {
1048 m = oce_insert_vlan_tag(sc, m, &complete);
1050 device_printf(sc->dev, "Insertion unsuccessful\n");
1056 /* Lancer, SH ASIC has a bug wherein Packets that are 32 bytes or less
1057 * may cause a transmit stall on that port. So the work-around is to
1058 * pad short packets (<= 32 bytes) to a 36-byte length.
1060 if(IS_SH(sc) || IS_XE201(sc) ) {
1061 if(m->m_pkthdr.len <= 32) {
1063 bzero((void *)buf, 36);
1064 m_append(m, (36 - m->m_pkthdr.len), buf);
1069 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1070 /* consolidate packet buffers for TSO/LSO segment offload */
1071 #if defined(INET6) || defined(INET)
1072 m = oce_tso_setup(sc, mpp);
1083 pd = &wq->pckts[wq->pkt_desc_head];
1086 rc = bus_dmamap_load_mbuf_sg(wq->tag,
1088 m, segs, &pd->nsegs, BUS_DMA_NOWAIT);
1090 num_wqes = pd->nsegs + 1;
1091 if (IS_BE(sc) || IS_SH(sc)) {
1092 /*Dummy required only for BE3.*/
1096 if (num_wqes >= RING_NUM_FREE(wq->ring)) {
1097 bus_dmamap_unload(wq->tag, pd->map);
1100 atomic_store_rel_int(&wq->pkt_desc_head,
1101 (wq->pkt_desc_head + 1) % \
1102 OCE_WQ_PACKET_ARRAY_SIZE);
1103 bus_dmamap_sync(wq->tag, pd->map, BUS_DMASYNC_PREWRITE);
1107 RING_GET_PRODUCER_ITEM_VA(wq->ring, struct oce_nic_hdr_wqe);
1108 nichdr->u0.dw[0] = 0;
1109 nichdr->u0.dw[1] = 0;
1110 nichdr->u0.dw[2] = 0;
1111 nichdr->u0.dw[3] = 0;
1113 nichdr->u0.s.complete = complete;
1114 nichdr->u0.s.mgmt = os2bmc;
1115 nichdr->u0.s.event = 1;
1116 nichdr->u0.s.crc = 1;
1117 nichdr->u0.s.forward = 0;
1118 nichdr->u0.s.ipcs = (m->m_pkthdr.csum_flags & CSUM_IP) ? 1 : 0;
1119 nichdr->u0.s.udpcs =
1120 (m->m_pkthdr.csum_flags & CSUM_UDP) ? 1 : 0;
1121 nichdr->u0.s.tcpcs =
1122 (m->m_pkthdr.csum_flags & CSUM_TCP) ? 1 : 0;
1123 nichdr->u0.s.num_wqe = num_wqes;
1124 nichdr->u0.s.total_length = m->m_pkthdr.len;
1126 if (m->m_flags & M_VLANTAG) {
1127 nichdr->u0.s.vlan = 1; /*Vlan present*/
1128 nichdr->u0.s.vlan_tag = m->m_pkthdr.ether_vtag;
1131 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1132 if (m->m_pkthdr.tso_segsz) {
1133 nichdr->u0.s.lso = 1;
1134 nichdr->u0.s.lso_mss = m->m_pkthdr.tso_segsz;
1136 if (!IS_BE(sc) || !IS_SH(sc))
1137 nichdr->u0.s.ipcs = 1;
1140 RING_PUT(wq->ring, 1);
1141 atomic_add_int(&wq->ring->num_used, 1);
1143 for (i = 0; i < pd->nsegs; i++) {
1145 RING_GET_PRODUCER_ITEM_VA(wq->ring,
1146 struct oce_nic_frag_wqe);
1147 nicfrag->u0.s.rsvd0 = 0;
1148 nicfrag->u0.s.frag_pa_hi = ADDR_HI(segs[i].ds_addr);
1149 nicfrag->u0.s.frag_pa_lo = ADDR_LO(segs[i].ds_addr);
1150 nicfrag->u0.s.frag_len = segs[i].ds_len;
1151 pd->wqe_idx = wq->ring->pidx;
1152 RING_PUT(wq->ring, 1);
1153 atomic_add_int(&wq->ring->num_used, 1);
1155 if (num_wqes > (pd->nsegs + 1)) {
1157 RING_GET_PRODUCER_ITEM_VA(wq->ring,
1158 struct oce_nic_frag_wqe);
1159 nicfrag->u0.dw[0] = 0;
1160 nicfrag->u0.dw[1] = 0;
1161 nicfrag->u0.dw[2] = 0;
1162 nicfrag->u0.dw[3] = 0;
1163 pd->wqe_idx = wq->ring->pidx;
1164 RING_PUT(wq->ring, 1);
1165 atomic_add_int(&wq->ring->num_used, 1);
1169 if_inc_counter(sc->ifp, IFCOUNTER_OPACKETS, 1);
1170 wq->tx_stats.tx_reqs++;
1171 wq->tx_stats.tx_wrbs += num_wqes;
1172 wq->tx_stats.tx_bytes += m->m_pkthdr.len;
1173 wq->tx_stats.tx_pkts++;
1175 bus_dmamap_sync(wq->ring->dma.tag, wq->ring->dma.map,
1176 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1177 reg_value = (num_wqes << 16) | wq->wq_id;
1179 /* if os2bmc is not enabled or if the pkt is already tagged as
1182 oce_is_pkt_dest_bmc(sc, m, &os2bmc, &m_new);
1184 OCE_WRITE_REG32(sc, db, wq->db_offset, reg_value);
1186 } else if (rc == EFBIG) {
1187 if (retry_cnt == 0) {
1188 m_temp = m_defrag(m, M_NOWAIT);
1193 retry_cnt = retry_cnt + 1;
1197 } else if (rc == ENOMEM)
1217 oce_process_tx_completion(struct oce_wq *wq)
1219 struct oce_packet_desc *pd;
1220 POCE_SOFTC sc = (POCE_SOFTC) wq->parent;
1223 pd = &wq->pckts[wq->pkt_desc_tail];
1224 atomic_store_rel_int(&wq->pkt_desc_tail,
1225 (wq->pkt_desc_tail + 1) % OCE_WQ_PACKET_ARRAY_SIZE);
1226 atomic_subtract_int(&wq->ring->num_used, pd->nsegs + 1);
1227 bus_dmamap_sync(wq->tag, pd->map, BUS_DMASYNC_POSTWRITE);
1228 bus_dmamap_unload(wq->tag, pd->map);
1235 if (sc->ifp->if_drv_flags & IFF_DRV_OACTIVE) {
1236 if (wq->ring->num_used < (wq->ring->num_items / 2)) {
1237 sc->ifp->if_drv_flags &= ~(IFF_DRV_OACTIVE);
1238 oce_tx_restart(sc, wq);
1245 oce_tx_restart(POCE_SOFTC sc, struct oce_wq *wq)
1248 if ((sc->ifp->if_drv_flags & IFF_DRV_RUNNING) != IFF_DRV_RUNNING)
1251 #if __FreeBSD_version >= 800000
1252 if (!drbr_empty(sc->ifp, wq->br))
1254 if (!IFQ_DRV_IS_EMPTY(&sc->ifp->if_snd))
1256 taskqueue_enqueue(taskqueue_swi, &wq->txtask);
1261 #if defined(INET6) || defined(INET)
1262 static struct mbuf *
1263 oce_tso_setup(POCE_SOFTC sc, struct mbuf **mpp)
1270 struct ip6_hdr *ip6;
1272 struct ether_vlan_header *eh;
1275 int total_len = 0, ehdrlen = 0;
1279 if (M_WRITABLE(m) == 0) {
1280 m = m_dup(*mpp, M_NOWAIT);
1287 eh = mtod(m, struct ether_vlan_header *);
1288 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
1289 etype = ntohs(eh->evl_proto);
1290 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
1292 etype = ntohs(eh->evl_encap_proto);
1293 ehdrlen = ETHER_HDR_LEN;
1299 ip = (struct ip *)(m->m_data + ehdrlen);
1300 if (ip->ip_p != IPPROTO_TCP)
1302 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
1304 total_len = ehdrlen + (ip->ip_hl << 2) + (th->th_off << 2);
1308 case ETHERTYPE_IPV6:
1309 ip6 = (struct ip6_hdr *)(m->m_data + ehdrlen);
1310 if (ip6->ip6_nxt != IPPROTO_TCP)
1312 th = (struct tcphdr *)((caddr_t)ip6 + sizeof(struct ip6_hdr));
1314 total_len = ehdrlen + sizeof(struct ip6_hdr) + (th->th_off << 2);
1321 m = m_pullup(m, total_len);
1328 #endif /* INET6 || INET */
1331 oce_tx_task(void *arg, int npending)
1333 struct oce_wq *wq = arg;
1334 POCE_SOFTC sc = wq->parent;
1335 struct ifnet *ifp = sc->ifp;
1338 #if __FreeBSD_version >= 800000
1340 rc = oce_multiq_transmit(ifp, NULL, wq);
1342 device_printf(sc->dev,
1343 "TX[%d] restart failed\n", wq->queue_index);
1345 UNLOCK(&wq->tx_lock);
1354 oce_start(struct ifnet *ifp)
1356 POCE_SOFTC sc = ifp->if_softc;
1359 int def_q = 0; /* Defualt tx queue is 0*/
1361 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1365 if (!sc->link_status)
1369 IF_DEQUEUE(&sc->ifp->if_snd, m);
1373 LOCK(&sc->wq[def_q]->tx_lock);
1374 rc = oce_tx(sc, &m, def_q);
1375 UNLOCK(&sc->wq[def_q]->tx_lock);
1378 sc->wq[def_q]->tx_stats.tx_stops ++;
1379 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1380 IFQ_DRV_PREPEND(&ifp->if_snd, m);
1386 ETHER_BPF_MTAP(ifp, m);
1394 /* Handle the Completion Queue for transmit */
1396 oce_wq_handler(void *arg)
1398 struct oce_wq *wq = (struct oce_wq *)arg;
1399 POCE_SOFTC sc = wq->parent;
1400 struct oce_cq *cq = wq->cq;
1401 struct oce_nic_tx_cqe *cqe;
1404 LOCK(&wq->tx_compl_lock);
1405 bus_dmamap_sync(cq->ring->dma.tag,
1406 cq->ring->dma.map, BUS_DMASYNC_POSTWRITE);
1407 cqe = RING_GET_CONSUMER_ITEM_VA(cq->ring, struct oce_nic_tx_cqe);
1408 while (cqe->u0.dw[3]) {
1409 DW_SWAP((uint32_t *) cqe, sizeof(oce_wq_cqe));
1411 wq->ring->cidx = cqe->u0.s.wqe_index + 1;
1412 if (wq->ring->cidx >= wq->ring->num_items)
1413 wq->ring->cidx -= wq->ring->num_items;
1415 oce_process_tx_completion(wq);
1416 wq->tx_stats.tx_compl++;
1418 RING_GET(cq->ring, 1);
1419 bus_dmamap_sync(cq->ring->dma.tag,
1420 cq->ring->dma.map, BUS_DMASYNC_POSTWRITE);
1422 RING_GET_CONSUMER_ITEM_VA(cq->ring, struct oce_nic_tx_cqe);
1427 oce_arm_cq(sc, cq->cq_id, num_cqes, FALSE);
1429 UNLOCK(&wq->tx_compl_lock);
1435 oce_multiq_transmit(struct ifnet *ifp, struct mbuf *m, struct oce_wq *wq)
1437 POCE_SOFTC sc = ifp->if_softc;
1438 int status = 0, queue_index = 0;
1439 struct mbuf *next = NULL;
1440 struct buf_ring *br = NULL;
1443 queue_index = wq->queue_index;
1445 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1448 status = drbr_enqueue(ifp, br, m);
1453 if ((status = drbr_enqueue(ifp, br, m)) != 0)
1456 while ((next = drbr_peek(ifp, br)) != NULL) {
1457 if (oce_tx(sc, &next, queue_index)) {
1459 drbr_advance(ifp, br);
1461 drbr_putback(ifp, br, next);
1462 wq->tx_stats.tx_stops ++;
1463 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1467 drbr_advance(ifp, br);
1468 if_inc_counter(ifp, IFCOUNTER_OBYTES, next->m_pkthdr.len);
1469 if (next->m_flags & M_MCAST)
1470 if_inc_counter(ifp, IFCOUNTER_OMCASTS, 1);
1471 ETHER_BPF_MTAP(ifp, next);
1480 /*****************************************************************************
1481 * Receive routines functions *
1482 *****************************************************************************/
1485 oce_correct_header(struct mbuf *m, struct nic_hwlro_cqe_part1 *cqe1, struct nic_hwlro_cqe_part2 *cqe2)
1488 struct ether_header *eh = NULL;
1489 struct tcphdr *tcp_hdr = NULL;
1490 struct ip *ip4_hdr = NULL;
1491 struct ip6_hdr *ip6 = NULL;
1492 uint32_t payload_len = 0;
1494 eh = mtod(m, struct ether_header *);
1495 /* correct IP header */
1496 if(!cqe2->ipv6_frame) {
1497 ip4_hdr = (struct ip *)((char*)eh + sizeof(struct ether_header));
1498 ip4_hdr->ip_ttl = cqe2->frame_lifespan;
1499 ip4_hdr->ip_len = htons(cqe2->coalesced_size - sizeof(struct ether_header));
1500 tcp_hdr = (struct tcphdr *)((char*)ip4_hdr + sizeof(struct ip));
1502 ip6 = (struct ip6_hdr *)((char*)eh + sizeof(struct ether_header));
1503 ip6->ip6_ctlun.ip6_un1.ip6_un1_hlim = cqe2->frame_lifespan;
1504 payload_len = cqe2->coalesced_size - sizeof(struct ether_header)
1505 - sizeof(struct ip6_hdr);
1506 ip6->ip6_ctlun.ip6_un1.ip6_un1_plen = htons(payload_len);
1507 tcp_hdr = (struct tcphdr *)((char*)ip6 + sizeof(struct ip6_hdr));
1510 /* correct tcp header */
1511 tcp_hdr->th_ack = htonl(cqe2->tcp_ack_num);
1513 tcp_hdr->th_flags |= TH_PUSH;
1515 tcp_hdr->th_win = htons(cqe2->tcp_window);
1516 tcp_hdr->th_sum = 0xffff;
1518 p = (uint32_t *)((char*)tcp_hdr + sizeof(struct tcphdr) + 2);
1519 *p = cqe1->tcp_timestamp_val;
1520 *(p+1) = cqe1->tcp_timestamp_ecr;
1527 oce_rx_mbuf_chain(struct oce_rq *rq, struct oce_common_cqe_info *cqe_info, struct mbuf **m)
1529 POCE_SOFTC sc = (POCE_SOFTC) rq->parent;
1530 uint32_t i = 0, frag_len = 0;
1531 uint32_t len = cqe_info->pkt_size;
1532 struct oce_packet_desc *pd;
1533 struct mbuf *tail = NULL;
1535 for (i = 0; i < cqe_info->num_frags; i++) {
1536 if (rq->ring->cidx == rq->ring->pidx) {
1537 device_printf(sc->dev,
1538 "oce_rx_mbuf_chain: Invalid RX completion - Queue is empty\n");
1541 pd = &rq->pckts[rq->ring->cidx];
1543 bus_dmamap_sync(rq->tag, pd->map, BUS_DMASYNC_POSTWRITE);
1544 bus_dmamap_unload(rq->tag, pd->map);
1545 RING_GET(rq->ring, 1);
1548 frag_len = (len > rq->cfg.frag_size) ? rq->cfg.frag_size : len;
1549 pd->mbuf->m_len = frag_len;
1552 /* additional fragments */
1553 pd->mbuf->m_flags &= ~M_PKTHDR;
1554 tail->m_next = pd->mbuf;
1556 tail->m_nextpkt = NULL;
1559 /* first fragment, fill out much of the packet header */
1560 pd->mbuf->m_pkthdr.len = len;
1562 pd->mbuf->m_nextpkt = NULL;
1563 pd->mbuf->m_pkthdr.csum_flags = 0;
1564 if (IF_CSUM_ENABLED(sc)) {
1565 if (cqe_info->l4_cksum_pass) {
1566 if(!cqe_info->ipv6_frame) { /* IPV4 */
1567 pd->mbuf->m_pkthdr.csum_flags |=
1568 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
1569 }else { /* IPV6 frame */
1571 pd->mbuf->m_pkthdr.csum_flags |=
1572 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
1575 pd->mbuf->m_pkthdr.csum_data = 0xffff;
1577 if (cqe_info->ip_cksum_pass) {
1578 pd->mbuf->m_pkthdr.csum_flags |=
1579 (CSUM_IP_CHECKED|CSUM_IP_VALID);
1582 *m = tail = pd->mbuf;
1592 oce_rx_lro(struct oce_rq *rq, struct nic_hwlro_singleton_cqe *cqe, struct nic_hwlro_cqe_part2 *cqe2)
1594 POCE_SOFTC sc = (POCE_SOFTC) rq->parent;
1595 struct nic_hwlro_cqe_part1 *cqe1 = NULL;
1596 struct mbuf *m = NULL;
1597 struct oce_common_cqe_info cq_info;
1601 cq_info.pkt_size = cqe->pkt_size;
1602 cq_info.vtag = cqe->vlan_tag;
1603 cq_info.l4_cksum_pass = cqe->l4_cksum_pass;
1604 cq_info.ip_cksum_pass = cqe->ip_cksum_pass;
1605 cq_info.ipv6_frame = cqe->ipv6_frame;
1606 cq_info.vtp = cqe->vtp;
1607 cq_info.qnq = cqe->qnq;
1609 cqe1 = (struct nic_hwlro_cqe_part1 *)cqe;
1610 cq_info.pkt_size = cqe2->coalesced_size;
1611 cq_info.vtag = cqe2->vlan_tag;
1612 cq_info.l4_cksum_pass = cqe2->l4_cksum_pass;
1613 cq_info.ip_cksum_pass = cqe2->ip_cksum_pass;
1614 cq_info.ipv6_frame = cqe2->ipv6_frame;
1615 cq_info.vtp = cqe2->vtp;
1616 cq_info.qnq = cqe1->qnq;
1619 cq_info.vtag = BSWAP_16(cq_info.vtag);
1621 cq_info.num_frags = cq_info.pkt_size / rq->cfg.frag_size;
1622 if(cq_info.pkt_size % rq->cfg.frag_size)
1623 cq_info.num_frags++;
1625 oce_rx_mbuf_chain(rq, &cq_info, &m);
1629 //assert(cqe2->valid != 0);
1631 //assert(cqe2->cqe_type != 2);
1632 oce_correct_header(m, cqe1, cqe2);
1635 m->m_pkthdr.rcvif = sc->ifp;
1636 #if __FreeBSD_version >= 800000
1637 if (rq->queue_index)
1638 m->m_pkthdr.flowid = (rq->queue_index - 1);
1640 m->m_pkthdr.flowid = rq->queue_index;
1641 M_HASHTYPE_SET(m, M_HASHTYPE_OPAQUE);
1643 /* This deternies if vlan tag is Valid */
1645 if (sc->function_mode & FNM_FLEX10_MODE) {
1646 /* FLEX10. If QnQ is not set, neglect VLAN */
1648 m->m_pkthdr.ether_vtag = cq_info.vtag;
1649 m->m_flags |= M_VLANTAG;
1651 } else if (sc->pvid != (cq_info.vtag & VLAN_VID_MASK)) {
1652 /* In UMC mode generally pvid will be striped by
1653 hw. But in some cases we have seen it comes
1654 with pvid. So if pvid == vlan, neglect vlan.
1656 m->m_pkthdr.ether_vtag = cq_info.vtag;
1657 m->m_flags |= M_VLANTAG;
1660 if_inc_counter(sc->ifp, IFCOUNTER_IPACKETS, 1);
1662 (*sc->ifp->if_input) (sc->ifp, m);
1664 /* Update rx stats per queue */
1665 rq->rx_stats.rx_pkts++;
1666 rq->rx_stats.rx_bytes += cq_info.pkt_size;
1667 rq->rx_stats.rx_frags += cq_info.num_frags;
1668 rq->rx_stats.rx_ucast_pkts++;
1674 oce_rx(struct oce_rq *rq, struct oce_nic_rx_cqe *cqe)
1676 POCE_SOFTC sc = (POCE_SOFTC) rq->parent;
1678 struct mbuf *m = NULL;
1679 struct oce_common_cqe_info cq_info;
1682 /* Is it a flush compl that has no data */
1683 if(!cqe->u0.s.num_fragments)
1686 len = cqe->u0.s.pkt_size;
1688 /*partial DMA workaround for Lancer*/
1689 oce_discard_rx_comp(rq, cqe->u0.s.num_fragments);
1693 if (!oce_cqe_portid_valid(sc, cqe)) {
1694 oce_discard_rx_comp(rq, cqe->u0.s.num_fragments);
1698 /* Get vlan_tag value */
1699 if(IS_BE(sc) || IS_SH(sc))
1700 vtag = BSWAP_16(cqe->u0.s.vlan_tag);
1702 vtag = cqe->u0.s.vlan_tag;
1704 cq_info.l4_cksum_pass = cqe->u0.s.l4_cksum_pass;
1705 cq_info.ip_cksum_pass = cqe->u0.s.ip_cksum_pass;
1706 cq_info.ipv6_frame = cqe->u0.s.ip_ver;
1707 cq_info.num_frags = cqe->u0.s.num_fragments;
1708 cq_info.pkt_size = cqe->u0.s.pkt_size;
1710 oce_rx_mbuf_chain(rq, &cq_info, &m);
1713 m->m_pkthdr.rcvif = sc->ifp;
1714 #if __FreeBSD_version >= 800000
1715 if (rq->queue_index)
1716 m->m_pkthdr.flowid = (rq->queue_index - 1);
1718 m->m_pkthdr.flowid = rq->queue_index;
1719 M_HASHTYPE_SET(m, M_HASHTYPE_OPAQUE);
1721 /* This deternies if vlan tag is Valid */
1722 if (oce_cqe_vtp_valid(sc, cqe)) {
1723 if (sc->function_mode & FNM_FLEX10_MODE) {
1724 /* FLEX10. If QnQ is not set, neglect VLAN */
1725 if (cqe->u0.s.qnq) {
1726 m->m_pkthdr.ether_vtag = vtag;
1727 m->m_flags |= M_VLANTAG;
1729 } else if (sc->pvid != (vtag & VLAN_VID_MASK)) {
1730 /* In UMC mode generally pvid will be striped by
1731 hw. But in some cases we have seen it comes
1732 with pvid. So if pvid == vlan, neglect vlan.
1734 m->m_pkthdr.ether_vtag = vtag;
1735 m->m_flags |= M_VLANTAG;
1739 if_inc_counter(sc->ifp, IFCOUNTER_IPACKETS, 1);
1740 #if defined(INET6) || defined(INET)
1741 /* Try to queue to LRO */
1742 if (IF_LRO_ENABLED(sc) &&
1743 (cqe->u0.s.ip_cksum_pass) &&
1744 (cqe->u0.s.l4_cksum_pass) &&
1745 (!cqe->u0.s.ip_ver) &&
1746 (rq->lro.lro_cnt != 0)) {
1748 if (tcp_lro_rx(&rq->lro, m, 0) == 0) {
1749 rq->lro_pkts_queued ++;
1752 /* If LRO posting fails then try to post to STACK */
1756 (*sc->ifp->if_input) (sc->ifp, m);
1757 #if defined(INET6) || defined(INET)
1760 /* Update rx stats per queue */
1761 rq->rx_stats.rx_pkts++;
1762 rq->rx_stats.rx_bytes += cqe->u0.s.pkt_size;
1763 rq->rx_stats.rx_frags += cqe->u0.s.num_fragments;
1764 if (cqe->u0.s.pkt_type == OCE_MULTICAST_PACKET)
1765 rq->rx_stats.rx_mcast_pkts++;
1766 if (cqe->u0.s.pkt_type == OCE_UNICAST_PACKET)
1767 rq->rx_stats.rx_ucast_pkts++;
1775 oce_discard_rx_comp(struct oce_rq *rq, int num_frags)
1778 struct oce_packet_desc *pd;
1779 POCE_SOFTC sc = (POCE_SOFTC) rq->parent;
1781 for (i = 0; i < num_frags; i++) {
1782 if (rq->ring->cidx == rq->ring->pidx) {
1783 device_printf(sc->dev,
1784 "oce_discard_rx_comp: Invalid RX completion - Queue is empty\n");
1787 pd = &rq->pckts[rq->ring->cidx];
1788 bus_dmamap_sync(rq->tag, pd->map, BUS_DMASYNC_POSTWRITE);
1789 bus_dmamap_unload(rq->tag, pd->map);
1790 if (pd->mbuf != NULL) {
1795 RING_GET(rq->ring, 1);
1802 oce_cqe_vtp_valid(POCE_SOFTC sc, struct oce_nic_rx_cqe *cqe)
1804 struct oce_nic_rx_cqe_v1 *cqe_v1;
1807 if (sc->be3_native) {
1808 cqe_v1 = (struct oce_nic_rx_cqe_v1 *)cqe;
1809 vtp = cqe_v1->u0.s.vlan_tag_present;
1811 vtp = cqe->u0.s.vlan_tag_present;
1819 oce_cqe_portid_valid(POCE_SOFTC sc, struct oce_nic_rx_cqe *cqe)
1821 struct oce_nic_rx_cqe_v1 *cqe_v1;
1824 if (sc->be3_native && (IS_BE(sc) || IS_SH(sc))) {
1825 cqe_v1 = (struct oce_nic_rx_cqe_v1 *)cqe;
1826 port_id = cqe_v1->u0.s.port;
1827 if (sc->port_id != port_id)
1830 ;/* For BE3 legacy and Lancer this is dummy */
1836 #if defined(INET6) || defined(INET)
1838 oce_rx_flush_lro(struct oce_rq *rq)
1840 struct lro_ctrl *lro = &rq->lro;
1841 POCE_SOFTC sc = (POCE_SOFTC) rq->parent;
1843 if (!IF_LRO_ENABLED(sc))
1846 tcp_lro_flush_all(lro);
1847 rq->lro_pkts_queued = 0;
1854 oce_init_lro(POCE_SOFTC sc)
1856 struct lro_ctrl *lro = NULL;
1859 for (i = 0; i < sc->nrqs; i++) {
1860 lro = &sc->rq[i]->lro;
1861 rc = tcp_lro_init(lro);
1863 device_printf(sc->dev, "LRO init failed\n");
1874 oce_free_lro(POCE_SOFTC sc)
1876 struct lro_ctrl *lro = NULL;
1879 for (i = 0; i < sc->nrqs; i++) {
1880 lro = &sc->rq[i]->lro;
1888 oce_alloc_rx_bufs(struct oce_rq *rq, int count)
1890 POCE_SOFTC sc = (POCE_SOFTC) rq->parent;
1892 struct oce_packet_desc *pd;
1893 bus_dma_segment_t segs[6];
1894 int nsegs, added = 0;
1895 struct oce_nic_rqe *rqe;
1896 pd_rxulp_db_t rxdb_reg;
1898 uint32_t oce_max_rq_posts = 64;
1900 bzero(&rxdb_reg, sizeof(pd_rxulp_db_t));
1901 for (i = 0; i < count; i++) {
1902 in = (rq->ring->pidx + 1) % OCE_RQ_PACKET_ARRAY_SIZE;
1904 pd = &rq->pckts[rq->ring->pidx];
1905 pd->mbuf = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, oce_rq_buf_size);
1906 if (pd->mbuf == NULL) {
1907 device_printf(sc->dev, "mbuf allocation failed, size = %d\n",oce_rq_buf_size);
1910 pd->mbuf->m_nextpkt = NULL;
1912 pd->mbuf->m_len = pd->mbuf->m_pkthdr.len = rq->cfg.frag_size;
1914 rc = bus_dmamap_load_mbuf_sg(rq->tag,
1917 segs, &nsegs, BUS_DMA_NOWAIT);
1920 device_printf(sc->dev, "bus_dmamap_load_mbuf_sg failed rc = %d\n", rc);
1929 bus_dmamap_sync(rq->tag, pd->map, BUS_DMASYNC_PREREAD);
1931 rqe = RING_GET_PRODUCER_ITEM_VA(rq->ring, struct oce_nic_rqe);
1932 rqe->u0.s.frag_pa_hi = ADDR_HI(segs[0].ds_addr);
1933 rqe->u0.s.frag_pa_lo = ADDR_LO(segs[0].ds_addr);
1934 DW_SWAP(u32ptr(rqe), sizeof(struct oce_nic_rqe));
1935 RING_PUT(rq->ring, 1);
1939 oce_max_rq_posts = sc->enable_hwlro ? OCE_HWLRO_MAX_RQ_POSTS : OCE_MAX_RQ_POSTS;
1941 for (i = added / oce_max_rq_posts; i > 0; i--) {
1942 rxdb_reg.bits.num_posted = oce_max_rq_posts;
1943 rxdb_reg.bits.qid = rq->rq_id;
1945 val |= rq->rq_id & DB_LRO_RQ_ID_MASK;
1946 val |= oce_max_rq_posts << 16;
1947 OCE_WRITE_REG32(sc, db, DB_OFFSET, val);
1949 OCE_WRITE_REG32(sc, db, PD_RXULP_DB, rxdb_reg.dw0);
1951 added -= oce_max_rq_posts;
1954 rxdb_reg.bits.qid = rq->rq_id;
1955 rxdb_reg.bits.num_posted = added;
1957 val |= rq->rq_id & DB_LRO_RQ_ID_MASK;
1959 OCE_WRITE_REG32(sc, db, DB_OFFSET, val);
1961 OCE_WRITE_REG32(sc, db, PD_RXULP_DB, rxdb_reg.dw0);
1970 oce_check_rx_bufs(POCE_SOFTC sc, uint32_t num_cqes, struct oce_rq *rq)
1973 oce_arm_cq(sc, rq->cq->cq_id, num_cqes, FALSE);
1974 if(!sc->enable_hwlro) {
1975 if((OCE_RQ_PACKET_ARRAY_SIZE - rq->pending) > 1)
1976 oce_alloc_rx_bufs(rq, ((OCE_RQ_PACKET_ARRAY_SIZE - rq->pending) - 1));
1978 if ((OCE_RQ_PACKET_ARRAY_SIZE -1 - rq->pending) > 64)
1979 oce_alloc_rx_bufs(rq, 64);
1987 oce_rq_handler_lro(void *arg)
1989 struct oce_rq *rq = (struct oce_rq *)arg;
1990 struct oce_cq *cq = rq->cq;
1991 POCE_SOFTC sc = rq->parent;
1992 struct nic_hwlro_singleton_cqe *cqe;
1993 struct nic_hwlro_cqe_part2 *cqe2;
1997 bus_dmamap_sync(cq->ring->dma.tag,cq->ring->dma.map, BUS_DMASYNC_POSTWRITE);
1998 cqe = RING_GET_CONSUMER_ITEM_VA(cq->ring, struct nic_hwlro_singleton_cqe);
1999 while (cqe->valid) {
2000 if(cqe->cqe_type == 0) { /* singleton cqe */
2001 /* we should not get singleton cqe after cqe1 on same rq */
2002 if(rq->cqe_firstpart != NULL) {
2003 device_printf(sc->dev, "Got singleton cqe after cqe1 \n");
2004 goto exit_rq_handler_lro;
2006 if(cqe->error != 0) {
2007 rq->rx_stats.rxcp_err++;
2008 if_inc_counter(sc->ifp, IFCOUNTER_IERRORS, 1);
2010 oce_rx_lro(rq, cqe, NULL);
2011 rq->rx_stats.rx_compl++;
2013 RING_GET(cq->ring, 1);
2015 if (num_cqes >= (IS_XE201(sc) ? 8 : oce_max_rsp_handled))
2017 }else if(cqe->cqe_type == 0x1) { /* first part */
2018 /* we should not get cqe1 after cqe1 on same rq */
2019 if(rq->cqe_firstpart != NULL) {
2020 device_printf(sc->dev, "Got cqe1 after cqe1 \n");
2021 goto exit_rq_handler_lro;
2023 rq->cqe_firstpart = (struct nic_hwlro_cqe_part1 *)cqe;
2024 RING_GET(cq->ring, 1);
2025 }else if(cqe->cqe_type == 0x2) { /* second part */
2026 cqe2 = (struct nic_hwlro_cqe_part2 *)cqe;
2027 if(cqe2->error != 0) {
2028 rq->rx_stats.rxcp_err++;
2029 if_inc_counter(sc->ifp, IFCOUNTER_IERRORS, 1);
2031 /* We should not get cqe2 without cqe1 */
2032 if(rq->cqe_firstpart == NULL) {
2033 device_printf(sc->dev, "Got cqe2 without cqe1 \n");
2034 goto exit_rq_handler_lro;
2036 oce_rx_lro(rq, (struct nic_hwlro_singleton_cqe *)rq->cqe_firstpart, cqe2);
2038 rq->rx_stats.rx_compl++;
2039 rq->cqe_firstpart->valid = 0;
2041 rq->cqe_firstpart = NULL;
2043 RING_GET(cq->ring, 1);
2045 if (num_cqes >= (IS_XE201(sc) ? 8 : oce_max_rsp_handled))
2049 bus_dmamap_sync(cq->ring->dma.tag,cq->ring->dma.map, BUS_DMASYNC_POSTWRITE);
2050 cqe = RING_GET_CONSUMER_ITEM_VA(cq->ring, struct nic_hwlro_singleton_cqe);
2052 oce_check_rx_bufs(sc, num_cqes, rq);
2053 exit_rq_handler_lro:
2054 UNLOCK(&rq->rx_lock);
2058 /* Handle the Completion Queue for receive */
2060 oce_rq_handler(void *arg)
2062 struct oce_rq *rq = (struct oce_rq *)arg;
2063 struct oce_cq *cq = rq->cq;
2064 POCE_SOFTC sc = rq->parent;
2065 struct oce_nic_rx_cqe *cqe;
2069 oce_rq_handler_lro(arg);
2073 bus_dmamap_sync(cq->ring->dma.tag,
2074 cq->ring->dma.map, BUS_DMASYNC_POSTWRITE);
2075 cqe = RING_GET_CONSUMER_ITEM_VA(cq->ring, struct oce_nic_rx_cqe);
2076 while (cqe->u0.dw[2]) {
2077 DW_SWAP((uint32_t *) cqe, sizeof(oce_rq_cqe));
2079 if (cqe->u0.s.error == 0) {
2082 rq->rx_stats.rxcp_err++;
2083 if_inc_counter(sc->ifp, IFCOUNTER_IERRORS, 1);
2084 /* Post L3/L4 errors to stack.*/
2087 rq->rx_stats.rx_compl++;
2090 #if defined(INET6) || defined(INET)
2091 if (IF_LRO_ENABLED(sc) && rq->lro_pkts_queued >= 16) {
2092 oce_rx_flush_lro(rq);
2096 RING_GET(cq->ring, 1);
2097 bus_dmamap_sync(cq->ring->dma.tag,
2098 cq->ring->dma.map, BUS_DMASYNC_POSTWRITE);
2100 RING_GET_CONSUMER_ITEM_VA(cq->ring, struct oce_nic_rx_cqe);
2102 if (num_cqes >= (IS_XE201(sc) ? 8 : oce_max_rsp_handled))
2106 #if defined(INET6) || defined(INET)
2107 if (IF_LRO_ENABLED(sc))
2108 oce_rx_flush_lro(rq);
2111 oce_check_rx_bufs(sc, num_cqes, rq);
2112 UNLOCK(&rq->rx_lock);
2120 /*****************************************************************************
2121 * Helper function prototypes in this file *
2122 *****************************************************************************/
2125 oce_attach_ifp(POCE_SOFTC sc)
2128 sc->ifp = if_alloc(IFT_ETHER);
2132 ifmedia_init(&sc->media, IFM_IMASK, oce_media_change, oce_media_status);
2133 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2134 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
2136 sc->ifp->if_flags = IFF_BROADCAST | IFF_MULTICAST;
2137 sc->ifp->if_ioctl = oce_ioctl;
2138 sc->ifp->if_start = oce_start;
2139 sc->ifp->if_init = oce_init;
2140 sc->ifp->if_mtu = ETHERMTU;
2141 sc->ifp->if_softc = sc;
2142 #if __FreeBSD_version >= 800000
2143 sc->ifp->if_transmit = oce_multiq_start;
2144 sc->ifp->if_qflush = oce_multiq_flush;
2147 if_initname(sc->ifp,
2148 device_get_name(sc->dev), device_get_unit(sc->dev));
2150 sc->ifp->if_snd.ifq_drv_maxlen = OCE_MAX_TX_DESC - 1;
2151 IFQ_SET_MAXLEN(&sc->ifp->if_snd, sc->ifp->if_snd.ifq_drv_maxlen);
2152 IFQ_SET_READY(&sc->ifp->if_snd);
2154 sc->ifp->if_hwassist = OCE_IF_HWASSIST;
2155 sc->ifp->if_hwassist |= CSUM_TSO;
2156 sc->ifp->if_hwassist |= (CSUM_IP | CSUM_TCP | CSUM_UDP);
2158 sc->ifp->if_capabilities = OCE_IF_CAPABILITIES;
2159 sc->ifp->if_capabilities |= IFCAP_HWCSUM;
2160 sc->ifp->if_capabilities |= IFCAP_VLAN_HWFILTER;
2162 #if defined(INET6) || defined(INET)
2163 sc->ifp->if_capabilities |= IFCAP_TSO;
2164 sc->ifp->if_capabilities |= IFCAP_LRO;
2165 sc->ifp->if_capabilities |= IFCAP_VLAN_HWTSO;
2168 sc->ifp->if_capenable = sc->ifp->if_capabilities;
2169 sc->ifp->if_baudrate = IF_Gbps(10);
2171 #if __FreeBSD_version >= 1000000
2172 sc->ifp->if_hw_tsomax = 65536 - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
2173 sc->ifp->if_hw_tsomaxsegcount = OCE_MAX_TX_ELEMENTS;
2174 sc->ifp->if_hw_tsomaxsegsize = 4096;
2177 ether_ifattach(sc->ifp, sc->macaddr.mac_addr);
2184 oce_add_vlan(void *arg, struct ifnet *ifp, uint16_t vtag)
2186 POCE_SOFTC sc = ifp->if_softc;
2188 if (ifp->if_softc != arg)
2190 if ((vtag == 0) || (vtag > 4095))
2193 sc->vlan_tag[vtag] = 1;
2195 if (sc->vlans_added <= (sc->max_vlans + 1))
2201 oce_del_vlan(void *arg, struct ifnet *ifp, uint16_t vtag)
2203 POCE_SOFTC sc = ifp->if_softc;
2205 if (ifp->if_softc != arg)
2207 if ((vtag == 0) || (vtag > 4095))
2210 sc->vlan_tag[vtag] = 0;
2217 * A max of 64 vlans can be configured in BE. If the user configures
2218 * more, place the card in vlan promiscuous mode.
2221 oce_vid_config(POCE_SOFTC sc)
2223 struct normal_vlan vtags[MAX_VLANFILTER_SIZE];
2224 uint16_t ntags = 0, i;
2227 if ((sc->vlans_added <= MAX_VLANFILTER_SIZE) &&
2228 (sc->ifp->if_capenable & IFCAP_VLAN_HWFILTER)) {
2229 for (i = 0; i < MAX_VLANS; i++) {
2230 if (sc->vlan_tag[i]) {
2231 vtags[ntags].vtag = i;
2236 status = oce_config_vlan(sc, (uint8_t) sc->if_id,
2237 vtags, ntags, 1, 0);
2239 status = oce_config_vlan(sc, (uint8_t) sc->if_id,
2246 oce_mac_addr_set(POCE_SOFTC sc)
2248 uint32_t old_pmac_id = sc->pmac_id;
2252 status = bcmp((IF_LLADDR(sc->ifp)), sc->macaddr.mac_addr,
2253 sc->macaddr.size_of_struct);
2257 status = oce_mbox_macaddr_add(sc, (uint8_t *)(IF_LLADDR(sc->ifp)),
2258 sc->if_id, &sc->pmac_id);
2260 status = oce_mbox_macaddr_del(sc, sc->if_id, old_pmac_id);
2261 bcopy((IF_LLADDR(sc->ifp)), sc->macaddr.mac_addr,
2262 sc->macaddr.size_of_struct);
2265 device_printf(sc->dev, "Failed update macaddress\n");
2271 oce_handle_passthrough(struct ifnet *ifp, caddr_t data)
2273 POCE_SOFTC sc = ifp->if_softc;
2274 struct ifreq *ifr = (struct ifreq *)data;
2276 char cookie[32] = {0};
2277 void *priv_data = (void *)ifr->ifr_data;
2281 OCE_DMA_MEM dma_mem;
2282 struct mbx_common_get_cntl_attr *fw_cmd;
2284 if (copyin(priv_data, cookie, strlen(IOCTL_COOKIE)))
2287 if (memcmp(cookie, IOCTL_COOKIE, strlen(IOCTL_COOKIE)))
2290 ioctl_ptr = (char *)priv_data + strlen(IOCTL_COOKIE);
2291 if (copyin(ioctl_ptr, &req, sizeof(struct mbx_hdr)))
2294 req_size = le32toh(req.u0.req.request_length);
2295 if (req_size > 65536)
2298 req_size += sizeof(struct mbx_hdr);
2299 rc = oce_dma_alloc(sc, req_size, &dma_mem, 0);
2303 if (copyin(ioctl_ptr, OCE_DMAPTR(&dma_mem,char), req_size)) {
2308 rc = oce_pass_through_mbox(sc, &dma_mem, req_size);
2314 if (copyout(OCE_DMAPTR(&dma_mem,char), ioctl_ptr, req_size))
2318 firmware is filling all the attributes for this ioctl except
2319 the driver version..so fill it
2321 if(req.u0.rsp.opcode == OPCODE_COMMON_GET_CNTL_ATTRIBUTES) {
2322 fw_cmd = (struct mbx_common_get_cntl_attr *) ioctl_ptr;
2323 strncpy(fw_cmd->params.rsp.cntl_attr_info.hba_attr.drv_ver_str,
2324 COMPONENT_REVISION, strlen(COMPONENT_REVISION));
2328 oce_dma_free(sc, &dma_mem);
2334 oce_eqd_set_periodic(POCE_SOFTC sc)
2336 struct oce_set_eqd set_eqd[OCE_MAX_EQ];
2337 struct oce_aic_obj *aic;
2339 uint64_t now = 0, delta;
2340 int eqd, i, num = 0;
2341 uint32_t tx_reqs = 0, rxpkts = 0, pps;
2345 #define ticks_to_msecs(t) (1000 * (t) / hz)
2347 for (i = 0 ; i < sc->neqs; i++) {
2349 aic = &sc->aic_obj[i];
2350 /* When setting the static eq delay from the user space */
2359 rxpkts = rq->rx_stats.rx_pkts;
2361 tx_reqs = wq->tx_stats.tx_reqs;
2364 if (!aic->ticks || now < aic->ticks ||
2365 rxpkts < aic->prev_rxpkts || tx_reqs < aic->prev_txreqs) {
2366 aic->prev_rxpkts = rxpkts;
2367 aic->prev_txreqs = tx_reqs;
2372 delta = ticks_to_msecs(now - aic->ticks);
2374 pps = (((uint32_t)(rxpkts - aic->prev_rxpkts) * 1000) / delta) +
2375 (((uint32_t)(tx_reqs - aic->prev_txreqs) * 1000) / delta);
2376 eqd = (pps / 15000) << 2;
2380 /* Make sure that the eq delay is in the known range */
2381 eqd = min(eqd, aic->max_eqd);
2382 eqd = max(eqd, aic->min_eqd);
2384 aic->prev_rxpkts = rxpkts;
2385 aic->prev_txreqs = tx_reqs;
2389 if (eqd != aic->cur_eqd) {
2390 set_eqd[num].delay_multiplier = (eqd * 65)/100;
2391 set_eqd[num].eq_id = eqo->eq_id;
2397 /* Is there atleast one eq that needs to be modified? */
2398 for(i = 0; i < num; i += 8) {
2400 oce_mbox_eqd_modify_periodic(sc, &set_eqd[i], 8);
2402 oce_mbox_eqd_modify_periodic(sc, &set_eqd[i], (num - i));
2407 static void oce_detect_hw_error(POCE_SOFTC sc)
2410 uint32_t ue_low = 0, ue_high = 0, ue_low_mask = 0, ue_high_mask = 0;
2411 uint32_t sliport_status = 0, sliport_err1 = 0, sliport_err2 = 0;
2418 sliport_status = OCE_READ_REG32(sc, db, SLIPORT_STATUS_OFFSET);
2419 if (sliport_status & SLIPORT_STATUS_ERR_MASK) {
2420 sliport_err1 = OCE_READ_REG32(sc, db, SLIPORT_ERROR1_OFFSET);
2421 sliport_err2 = OCE_READ_REG32(sc, db, SLIPORT_ERROR2_OFFSET);
2424 ue_low = OCE_READ_REG32(sc, devcfg, PCICFG_UE_STATUS_LOW);
2425 ue_high = OCE_READ_REG32(sc, devcfg, PCICFG_UE_STATUS_HIGH);
2426 ue_low_mask = OCE_READ_REG32(sc, devcfg, PCICFG_UE_STATUS_LOW_MASK);
2427 ue_high_mask = OCE_READ_REG32(sc, devcfg, PCICFG_UE_STATUS_HI_MASK);
2429 ue_low = (ue_low & ~ue_low_mask);
2430 ue_high = (ue_high & ~ue_high_mask);
2433 /* On certain platforms BE hardware can indicate spurious UEs.
2434 * Allow the h/w to stop working completely in case of a real UE.
2435 * Hence not setting the hw_error for UE detection.
2437 if (sliport_status & SLIPORT_STATUS_ERR_MASK) {
2438 sc->hw_error = TRUE;
2439 device_printf(sc->dev, "Error detected in the card\n");
2442 if (sliport_status & SLIPORT_STATUS_ERR_MASK) {
2443 device_printf(sc->dev,
2444 "ERR: sliport status 0x%x\n", sliport_status);
2445 device_printf(sc->dev,
2446 "ERR: sliport error1 0x%x\n", sliport_err1);
2447 device_printf(sc->dev,
2448 "ERR: sliport error2 0x%x\n", sliport_err2);
2452 for (i = 0; ue_low; ue_low >>= 1, i++) {
2454 device_printf(sc->dev, "UE: %s bit set\n",
2455 ue_status_low_desc[i]);
2460 for (i = 0; ue_high; ue_high >>= 1, i++) {
2462 device_printf(sc->dev, "UE: %s bit set\n",
2463 ue_status_hi_desc[i]);
2471 oce_local_timer(void *arg)
2473 POCE_SOFTC sc = arg;
2476 oce_detect_hw_error(sc);
2477 oce_refresh_nic_stats(sc);
2478 oce_refresh_queue_stats(sc);
2479 oce_mac_addr_set(sc);
2482 for (i = 0; i < sc->nwqs; i++)
2483 oce_tx_restart(sc, sc->wq[i]);
2485 /* calculate and set the eq delay for optimal interrupt rate */
2486 if (IS_BE(sc) || IS_SH(sc))
2487 oce_eqd_set_periodic(sc);
2489 callout_reset(&sc->timer, hz, oce_local_timer, sc);
2493 oce_tx_compl_clean(POCE_SOFTC sc)
2496 int i = 0, timeo = 0, num_wqes = 0;
2497 int pending_txqs = sc->nwqs;
2499 /* Stop polling for compls when HW has been silent for 10ms or
2500 * hw_error or no outstanding completions expected
2503 pending_txqs = sc->nwqs;
2505 for_all_wq_queues(sc, wq, i) {
2506 num_wqes = oce_wq_handler(wq);
2511 if(!wq->ring->num_used)
2515 if (pending_txqs == 0 || ++timeo > 10 || sc->hw_error)
2521 for_all_wq_queues(sc, wq, i) {
2522 while(wq->ring->num_used) {
2523 LOCK(&wq->tx_compl_lock);
2524 oce_process_tx_completion(wq);
2525 UNLOCK(&wq->tx_compl_lock);
2531 /* NOTE : This should only be called holding
2535 oce_if_deactivate(POCE_SOFTC sc)
2542 sc->ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2544 oce_tx_compl_clean(sc);
2546 /* Stop intrs and finish any bottom halves pending */
2547 oce_hw_intr_disable(sc);
2549 /* Since taskqueue_drain takes a Gaint Lock, We should not acquire
2550 any other lock. So unlock device lock and require after
2551 completing taskqueue_drain.
2553 UNLOCK(&sc->dev_lock);
2554 for (i = 0; i < sc->intr_count; i++) {
2555 if (sc->intrs[i].tq != NULL) {
2556 taskqueue_drain(sc->intrs[i].tq, &sc->intrs[i].task);
2559 LOCK(&sc->dev_lock);
2561 /* Delete RX queue in card with flush param */
2564 /* Invalidate any pending cq and eq entries*/
2565 for_all_evnt_queues(sc, eq, i)
2567 for_all_rq_queues(sc, rq, i)
2568 oce_drain_rq_cq(rq);
2569 for_all_wq_queues(sc, wq, i)
2570 oce_drain_wq_cq(wq);
2572 /* But still we need to get MCC aync events.
2573 So enable intrs and also arm first EQ
2575 oce_hw_intr_enable(sc);
2576 oce_arm_eq(sc, sc->eq[0]->eq_id, 0, TRUE, FALSE);
2583 oce_if_activate(POCE_SOFTC sc)
2590 sc->ifp->if_drv_flags |= IFF_DRV_RUNNING;
2592 oce_hw_intr_disable(sc);
2596 for_all_rq_queues(sc, rq, i) {
2597 rc = oce_start_rq(rq);
2599 device_printf(sc->dev, "Unable to start RX\n");
2602 for_all_wq_queues(sc, wq, i) {
2603 rc = oce_start_wq(wq);
2605 device_printf(sc->dev, "Unable to start TX\n");
2609 for_all_evnt_queues(sc, eq, i)
2610 oce_arm_eq(sc, eq->eq_id, 0, TRUE, FALSE);
2612 oce_hw_intr_enable(sc);
2617 process_link_state(POCE_SOFTC sc, struct oce_async_cqe_link_state *acqe)
2619 /* Update Link status */
2620 if ((acqe->u0.s.link_status & ~ASYNC_EVENT_LOGICAL) ==
2621 ASYNC_EVENT_LINK_UP) {
2622 sc->link_status = ASYNC_EVENT_LINK_UP;
2623 if_link_state_change(sc->ifp, LINK_STATE_UP);
2625 sc->link_status = ASYNC_EVENT_LINK_DOWN;
2626 if_link_state_change(sc->ifp, LINK_STATE_DOWN);
2631 static void oce_async_grp5_osbmc_process(POCE_SOFTC sc,
2632 struct oce_async_evt_grp5_os2bmc *evt)
2634 DW_SWAP(evt, sizeof(struct oce_async_evt_grp5_os2bmc));
2635 if (evt->u.s.mgmt_enable)
2636 sc->flags |= OCE_FLAGS_OS2BMC;
2640 sc->bmc_filt_mask = evt->u.s.arp_filter;
2641 sc->bmc_filt_mask |= (evt->u.s.dhcp_client_filt << 1);
2642 sc->bmc_filt_mask |= (evt->u.s.dhcp_server_filt << 2);
2643 sc->bmc_filt_mask |= (evt->u.s.net_bios_filt << 3);
2644 sc->bmc_filt_mask |= (evt->u.s.bcast_filt << 4);
2645 sc->bmc_filt_mask |= (evt->u.s.ipv6_nbr_filt << 5);
2646 sc->bmc_filt_mask |= (evt->u.s.ipv6_ra_filt << 6);
2647 sc->bmc_filt_mask |= (evt->u.s.ipv6_ras_filt << 7);
2648 sc->bmc_filt_mask |= (evt->u.s.mcast_filt << 8);
2652 static void oce_process_grp5_events(POCE_SOFTC sc, struct oce_mq_cqe *cqe)
2654 struct oce_async_event_grp5_pvid_state *gcqe;
2655 struct oce_async_evt_grp5_os2bmc *bmccqe;
2657 switch (cqe->u0.s.async_type) {
2658 case ASYNC_EVENT_PVID_STATE:
2660 gcqe = (struct oce_async_event_grp5_pvid_state *)cqe;
2662 sc->pvid = gcqe->tag & VLAN_VID_MASK;
2666 case ASYNC_EVENT_OS2BMC:
2667 bmccqe = (struct oce_async_evt_grp5_os2bmc *)cqe;
2668 oce_async_grp5_osbmc_process(sc, bmccqe);
2675 /* Handle the Completion Queue for the Mailbox/Async notifications */
2677 oce_mq_handler(void *arg)
2679 struct oce_mq *mq = (struct oce_mq *)arg;
2680 POCE_SOFTC sc = mq->parent;
2681 struct oce_cq *cq = mq->cq;
2682 int num_cqes = 0, evt_type = 0, optype = 0;
2683 struct oce_mq_cqe *cqe;
2684 struct oce_async_cqe_link_state *acqe;
2685 struct oce_async_event_qnq *dbgcqe;
2688 bus_dmamap_sync(cq->ring->dma.tag,
2689 cq->ring->dma.map, BUS_DMASYNC_POSTWRITE);
2690 cqe = RING_GET_CONSUMER_ITEM_VA(cq->ring, struct oce_mq_cqe);
2692 while (cqe->u0.dw[3]) {
2693 DW_SWAP((uint32_t *) cqe, sizeof(oce_mq_cqe));
2694 if (cqe->u0.s.async_event) {
2695 evt_type = cqe->u0.s.event_type;
2696 optype = cqe->u0.s.async_type;
2697 if (evt_type == ASYNC_EVENT_CODE_LINK_STATE) {
2698 /* Link status evt */
2699 acqe = (struct oce_async_cqe_link_state *)cqe;
2700 process_link_state(sc, acqe);
2701 } else if (evt_type == ASYNC_EVENT_GRP5) {
2702 oce_process_grp5_events(sc, cqe);
2703 } else if (evt_type == ASYNC_EVENT_CODE_DEBUG &&
2704 optype == ASYNC_EVENT_DEBUG_QNQ) {
2705 dbgcqe = (struct oce_async_event_qnq *)cqe;
2707 sc->qnqid = dbgcqe->vlan_tag;
2708 sc->qnq_debug_event = TRUE;
2712 RING_GET(cq->ring, 1);
2713 bus_dmamap_sync(cq->ring->dma.tag,
2714 cq->ring->dma.map, BUS_DMASYNC_POSTWRITE);
2715 cqe = RING_GET_CONSUMER_ITEM_VA(cq->ring, struct oce_mq_cqe);
2720 oce_arm_cq(sc, cq->cq_id, num_cqes, FALSE);
2727 setup_max_queues_want(POCE_SOFTC sc)
2729 /* Check if it is FLEX machine. Is so dont use RSS */
2730 if ((sc->function_mode & FNM_FLEX10_MODE) ||
2731 (sc->function_mode & FNM_UMC_MODE) ||
2732 (sc->function_mode & FNM_VNIC_MODE) ||
2733 (!is_rss_enabled(sc)) ||
2738 sc->nrqs = MIN(OCE_NCPUS, sc->nrssqs) + 1;
2739 sc->nwqs = MIN(OCE_NCPUS, sc->nrssqs);
2742 if (IS_BE2(sc) && is_rss_enabled(sc))
2743 sc->nrqs = MIN(OCE_NCPUS, sc->nrssqs) + 1;
2748 update_queues_got(POCE_SOFTC sc)
2750 if (is_rss_enabled(sc)) {
2751 sc->nrqs = sc->intr_count + 1;
2752 sc->nwqs = sc->intr_count;
2763 oce_check_ipv6_ext_hdr(struct mbuf *m)
2765 struct ether_header *eh = mtod(m, struct ether_header *);
2766 caddr_t m_datatemp = m->m_data;
2768 if (eh->ether_type == htons(ETHERTYPE_IPV6)) {
2769 m->m_data += sizeof(struct ether_header);
2770 struct ip6_hdr *ip6 = mtod(m, struct ip6_hdr *);
2772 if((ip6->ip6_nxt != IPPROTO_TCP) && \
2773 (ip6->ip6_nxt != IPPROTO_UDP)){
2774 struct ip6_ext *ip6e = NULL;
2775 m->m_data += sizeof(struct ip6_hdr);
2777 ip6e = (struct ip6_ext *) mtod(m, struct ip6_ext *);
2778 if(ip6e->ip6e_len == 0xff) {
2779 m->m_data = m_datatemp;
2783 m->m_data = m_datatemp;
2789 is_be3_a1(POCE_SOFTC sc)
2791 if((sc->flags & OCE_FLAGS_BE3) && ((sc->asic_revision & 0xFF) < 2)) {
2797 static struct mbuf *
2798 oce_insert_vlan_tag(POCE_SOFTC sc, struct mbuf *m, boolean_t *complete)
2800 uint16_t vlan_tag = 0;
2805 /* Embed vlan tag in the packet if it is not part of it */
2806 if(m->m_flags & M_VLANTAG) {
2807 vlan_tag = EVL_VLANOFTAG(m->m_pkthdr.ether_vtag);
2808 m->m_flags &= ~M_VLANTAG;
2811 /* if UMC, ignore vlan tag insertion and instead insert pvid */
2814 vlan_tag = sc->pvid;
2820 m = ether_vlanencap(m, vlan_tag);
2824 m = ether_vlanencap(m, sc->qnqid);
2833 oce_tx_asic_stall_verify(POCE_SOFTC sc, struct mbuf *m)
2835 if(is_be3_a1(sc) && IS_QNQ_OR_UMC(sc) && \
2836 oce_check_ipv6_ext_hdr(m)) {
2843 oce_get_config(POCE_SOFTC sc)
2846 uint32_t max_rss = 0;
2848 if ((IS_BE(sc) || IS_SH(sc)) && (!sc->be3_native))
2849 max_rss = OCE_LEGACY_MODE_RSS;
2851 max_rss = OCE_MAX_RSS;
2854 rc = oce_get_profile_config(sc, max_rss);
2856 sc->nwqs = OCE_MAX_WQ;
2857 sc->nrssqs = max_rss;
2858 sc->nrqs = sc->nrssqs + 1;
2861 else { /* For BE3 don't rely on fw for determining the resources */
2862 sc->nrssqs = max_rss;
2863 sc->nrqs = sc->nrssqs + 1;
2864 sc->nwqs = OCE_MAX_WQ;
2865 sc->max_vlans = MAX_VLANFILTER_SIZE;
2870 oce_rdma_close(void)
2872 if (oce_rdma_if != NULL) {
2878 oce_get_mac_addr(POCE_SOFTC sc, uint8_t *macaddr)
2880 memcpy(macaddr, sc->macaddr.mac_addr, 6);
2884 oce_register_rdma(POCE_RDMA_INFO rdma_info, POCE_RDMA_IF rdma_if)
2887 struct oce_dev_info di;
2890 if ((rdma_info == NULL) || (rdma_if == NULL)) {
2894 if ((rdma_info->size != OCE_RDMA_INFO_SIZE) ||
2895 (rdma_if->size != OCE_RDMA_IF_SIZE)) {
2899 rdma_info->close = oce_rdma_close;
2900 rdma_info->mbox_post = oce_mbox_post;
2901 rdma_info->common_req_hdr_init = mbx_common_req_hdr_init;
2902 rdma_info->get_mac_addr = oce_get_mac_addr;
2904 oce_rdma_if = rdma_if;
2907 while (sc != NULL) {
2908 if (oce_rdma_if->announce != NULL) {
2909 memset(&di, 0, sizeof(di));
2913 di.db_bhandle = sc->db_bhandle;
2914 di.db_btag = sc->db_btag;
2915 di.db_page_size = 4096;
2916 if (sc->flags & OCE_FLAGS_USING_MSIX) {
2917 di.intr_mode = OCE_INTERRUPT_MODE_MSIX;
2918 } else if (sc->flags & OCE_FLAGS_USING_MSI) {
2919 di.intr_mode = OCE_INTERRUPT_MODE_MSI;
2921 di.intr_mode = OCE_INTERRUPT_MODE_INTX;
2923 di.dev_family = OCE_GEN2_FAMILY; // fixme: must detect skyhawk
2924 if (di.intr_mode != OCE_INTERRUPT_MODE_INTX) {
2925 di.msix.num_vectors = sc->intr_count + sc->roce_intr_count;
2926 di.msix.start_vector = sc->intr_count;
2927 for (i=0; i<di.msix.num_vectors; i++) {
2928 di.msix.vector_list[i] = sc->intrs[i].vector;
2932 memcpy(di.mac_addr, sc->macaddr.mac_addr, 6);
2933 di.vendor_id = pci_get_vendor(sc->dev);
2934 di.dev_id = pci_get_device(sc->dev);
2936 if (sc->rdma_flags & OCE_RDMA_FLAG_SUPPORTED) {
2937 di.flags |= OCE_RDMA_INFO_RDMA_SUPPORTED;
2940 rdma_if->announce(&di);
2949 oce_read_env_variables( POCE_SOFTC sc )
2954 /* read if user wants to enable hwlro or swlro */
2955 //value = getenv("oce_enable_hwlro");
2956 if(value && IS_SH(sc)) {
2957 sc->enable_hwlro = strtol(value, NULL, 10);
2958 if(sc->enable_hwlro) {
2959 rc = oce_mbox_nic_query_lro_capabilities(sc, NULL, NULL);
2961 device_printf(sc->dev, "no hardware lro support\n");
2962 device_printf(sc->dev, "software lro enabled\n");
2963 sc->enable_hwlro = 0;
2965 device_printf(sc->dev, "hardware lro enabled\n");
2966 oce_max_rsp_handled = 32;
2969 device_printf(sc->dev, "software lro enabled\n");
2972 sc->enable_hwlro = 0;
2975 /* read mbuf size */
2976 //value = getenv("oce_rq_buf_size");
2977 if(value && IS_SH(sc)) {
2978 oce_rq_buf_size = strtol(value, NULL, 10);
2979 switch(oce_rq_buf_size) {
2987 device_printf(sc->dev, " Supported oce_rq_buf_size values are 2K, 4K, 9K, 16K \n");
2988 oce_rq_buf_size = 2048;