sys/dev/oce/oce_if.h

   1 /*-
   2  * SPDX-License-Identifier: BSD-3-Clause
   3  *
   4  * Copyright (C) 2013 Emulex
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright notice,
  11  *    this list of conditions and the following disclaimer.
  12  *
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  *
  17  * 3. Neither the name of the Emulex Corporation nor the names of its
  18  *    contributors may be used to endorse or promote products derived from
  19  *    this software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31  * POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * Contact Information:
  34  * freebsd-drivers@emulex.com
  35  *
  36  * Emulex
  37  * 3333 Susan Street
  38  * Costa Mesa, CA 92626
  39  */
  40
  41 /* $FreeBSD$ */
  42
  43 #include <sys/param.h>
  44 #include <sys/endian.h>
  45 #include <sys/eventhandler.h>
  46 #include <sys/malloc.h>
  47 #include <sys/module.h>
  48 #include <sys/kernel.h>
  49 #include <sys/bus.h>
  50 #include <sys/mbuf.h>
  51 #include <sys/rman.h>
  52 #include <sys/socket.h>
  53 #include <sys/sockio.h>
  54 #include <sys/sockopt.h>
  55 #include <sys/queue.h>
  56 #include <sys/taskqueue.h>
  57 #include <sys/lock.h>
  58 #include <sys/mutex.h>
  59 #include <sys/sysctl.h>
  60 #include <sys/random.h>
  61 #include <sys/firmware.h>
  62 #include <sys/systm.h>
  63 #include <sys/proc.h>
  64
  65 #include <dev/pci/pcireg.h>
  66 #include <dev/pci/pcivar.h>
  67
  68 #include <net/bpf.h>
  69 #include <net/ethernet.h>
  70 #include <net/if.h>
  71 #include <net/if_var.h>
  72 #include <net/if_types.h>
  73 #include <net/if_media.h>
  74 #include <net/if_vlan_var.h>
  75 #include <net/if_dl.h>
  76
  77 #include <netinet/in.h>
  78 #include <netinet/in_systm.h>
  79 #include <netinet/in_var.h>
  80 #include <netinet/if_ether.h>
  81 #include <netinet/ip.h>
  82 #include <netinet/ip6.h>
  83 #include <netinet6/in6_var.h>
  84 #include <netinet6/ip6_mroute.h>
  85
  86 #include <netinet/udp.h>
  87 #include <netinet/tcp.h>
  88 #include <netinet/sctp.h>
  89 #include <netinet/tcp_lro.h>
  90 #include <netinet/icmp6.h>
  91
  92 #include <machine/bus.h>
  93
  94 #include "oce_hw.h"
  95
  96 /* OCE device driver module component revision informaiton */
  97 #define COMPONENT_REVISION "11.0.50.0"
  98
  99 /* OCE devices supported by this driver */
 100 #define PCI_VENDOR_EMULEX               0x10df  /* Emulex */
 101 #define PCI_VENDOR_SERVERENGINES        0x19a2  /* ServerEngines (BE) */
 102 #define PCI_PRODUCT_BE2                 0x0700  /* BE2 network adapter */
 103 #define PCI_PRODUCT_BE3                 0x0710  /* BE3 network adapter */
 104 #define PCI_PRODUCT_XE201               0xe220  /* XE201 network adapter */
 105 #define PCI_PRODUCT_XE201_VF            0xe228  /* XE201 with VF in Lancer */
 106 #define PCI_PRODUCT_SH                  0x0720  /* Skyhawk network adapter */
 107
 108 #define IS_BE(sc)       (((sc->flags & OCE_FLAGS_BE3) | \
 109                          (sc->flags & OCE_FLAGS_BE2))? 1:0)
 110 #define IS_BE3(sc)      (sc->flags & OCE_FLAGS_BE3)
 111 #define IS_BE2(sc)      (sc->flags & OCE_FLAGS_BE2)
 112 #define IS_XE201(sc)    ((sc->flags & OCE_FLAGS_XE201) ? 1:0)
 113 #define HAS_A0_CHIP(sc) ((sc->flags & OCE_FLAGS_HAS_A0_CHIP) ? 1:0)
 114 #define IS_SH(sc)       ((sc->flags & OCE_FLAGS_SH) ? 1 : 0)
 115
 116 #define is_be_mode_mc(sc)       ((sc->function_mode & FNM_FLEX10_MODE) ||       \
 117                                 (sc->function_mode & FNM_UMC_MODE)    ||        \
 118                                 (sc->function_mode & FNM_VNIC_MODE))
 119 #define OCE_FUNCTION_CAPS_SUPER_NIC     0x40
 120 #define IS_PROFILE_SUPER_NIC(sc) (sc->function_caps & OCE_FUNCTION_CAPS_SUPER_NIC)
 121
 122
 123 /* proportion Service Level Interface queues */
 124 #define OCE_MAX_UNITS                   2
 125 #define OCE_MAX_PPORT                   OCE_MAX_UNITS
 126 #define OCE_MAX_VPORT                   OCE_MAX_UNITS
 127
 128 extern int mp_ncpus;                    /* system's total active cpu cores */
 129 #define OCE_NCPUS                       mp_ncpus
 130
 131 /* This should be powers of 2. Like 2,4,8 & 16 */
 132 #define OCE_MAX_RSS                     8
 133 #define OCE_LEGACY_MODE_RSS             4 /* For BE3 Legacy mode*/
 134 #define is_rss_enabled(sc)              ((sc->function_caps & FNC_RSS) && !is_be_mode_mc(sc))
 135
 136 #define OCE_MIN_RQ                      1
 137 #define OCE_MIN_WQ                      1
 138
 139 #define OCE_MAX_RQ                      OCE_MAX_RSS + 1 /* one default queue */
 140 #define OCE_MAX_WQ                      8
 141
 142 #define OCE_MAX_EQ                      32
 143 #define OCE_MAX_CQ                      OCE_MAX_RQ + OCE_MAX_WQ + 1 /* one MCC queue */
 144 #define OCE_MAX_CQ_EQ                   8 /* Max CQ that can attached to an EQ */
 145
 146 #define OCE_DEFAULT_WQ_EQD              16
 147 #define OCE_MAX_PACKET_Q                16
 148 #define OCE_LSO_MAX_SIZE                (64 * 1024)
 149 #define LONG_TIMEOUT                    30
 150 #define OCE_MAX_JUMBO_FRAME_SIZE        9018
 151 #define OCE_MAX_MTU                     (OCE_MAX_JUMBO_FRAME_SIZE - \
 152                                                 ETHER_VLAN_ENCAP_LEN - \
 153                                                 ETHER_HDR_LEN)
 154
 155 #define OCE_RDMA_VECTORS                2
 156
 157 #define OCE_MAX_TX_ELEMENTS             29
 158 #define OCE_MAX_TX_DESC                 1024
 159 #define OCE_MAX_TX_SIZE                 65535
 160 #define OCE_MAX_TSO_SIZE                (65535 - ETHER_HDR_LEN)
 161 #define OCE_MAX_RX_SIZE                 4096
 162 #define OCE_MAX_RQ_POSTS                255
 163 #define OCE_HWLRO_MAX_RQ_POSTS          64
 164 #define OCE_DEFAULT_PROMISCUOUS         0
 165
 166
 167 #define RSS_ENABLE_IPV4                 0x1
 168 #define RSS_ENABLE_TCP_IPV4             0x2
 169 #define RSS_ENABLE_IPV6                 0x4
 170 #define RSS_ENABLE_TCP_IPV6             0x8
 171
 172 #define INDIRECTION_TABLE_ENTRIES       128
 173
 174 /* flow control definitions */
 175 #define OCE_FC_NONE                     0x00000000
 176 #define OCE_FC_TX                       0x00000001
 177 #define OCE_FC_RX                       0x00000002
 178 #define OCE_DEFAULT_FLOW_CONTROL        (OCE_FC_TX | OCE_FC_RX)
 179
 180
 181 /* Interface capabilities to give device when creating interface */
 182 #define  OCE_CAPAB_FLAGS                (MBX_RX_IFACE_FLAGS_BROADCAST    | \
 183                                         MBX_RX_IFACE_FLAGS_UNTAGGED      | \
 184                                         MBX_RX_IFACE_FLAGS_PROMISCUOUS      | \
 185                                         MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS |   \
 186                                         MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS   | \
 187                                         MBX_RX_IFACE_FLAGS_RSS | \
 188                                         MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR)
 189
 190 /* Interface capabilities to enable by default (others set dynamically) */
 191 #define  OCE_CAPAB_ENABLE               (MBX_RX_IFACE_FLAGS_BROADCAST | \
 192                                         MBX_RX_IFACE_FLAGS_UNTAGGED   | \
 193                                         MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR)
 194
 195 #define OCE_IF_HWASSIST                 (CSUM_IP | CSUM_TCP | CSUM_UDP)
 196 #define OCE_IF_CAPABILITIES             (IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \
 197                                         IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | \
 198                                         IFCAP_JUMBO_MTU | IFCAP_VLAN_MTU)
 199 #define OCE_IF_HWASSIST_NONE            0
 200 #define OCE_IF_CAPABILITIES_NONE        0
 201
 202
 203 #define ETH_ADDR_LEN                    6
 204 #define MAX_VLANFILTER_SIZE             64
 205 #define MAX_VLANS                       4096
 206
 207 #define upper_32_bits(n)                ((uint32_t)(((n) >> 16) >> 16))
 208 #define BSWAP_8(x)                      ((x) & 0xff)
 209 #define BSWAP_16(x)                     ((BSWAP_8(x) << 8) | BSWAP_8((x) >> 8))
 210 #define BSWAP_32(x)                     ((BSWAP_16(x) << 16) | \
 211                                          BSWAP_16((x) >> 16))
 212 #define BSWAP_64(x)                     ((BSWAP_32(x) << 32) | \
 213                                         BSWAP_32((x) >> 32))
 214
 215 #define for_all_wq_queues(sc, wq, i)    \
 216                 for (i = 0, wq = sc->wq[0]; i < sc->nwqs; i++, wq = sc->wq[i])
 217 #define for_all_rq_queues(sc, rq, i)    \
 218                 for (i = 0, rq = sc->rq[0]; i < sc->nrqs; i++, rq = sc->rq[i])
 219 #define for_all_rss_queues(sc, rq, i)   \
 220                 for (i = 0, rq = sc->rq[i + 1]; i < (sc->nrqs - 1); \
 221                      i++, rq = sc->rq[i + 1])
 222 #define for_all_evnt_queues(sc, eq, i)  \
 223                 for (i = 0, eq = sc->eq[0]; i < sc->neqs; i++, eq = sc->eq[i])
 224 #define for_all_cq_queues(sc, cq, i)    \
 225                 for (i = 0, cq = sc->cq[0]; i < sc->ncqs; i++, cq = sc->cq[i])
 226
 227
 228 /* Flash specific */
 229 #define IOCTL_COOKIE                    "SERVERENGINES CORP"
 230 #define MAX_FLASH_COMP                  32
 231
 232 #define IMG_ISCSI                       160
 233 #define IMG_REDBOOT                     224
 234 #define IMG_BIOS                        34
 235 #define IMG_PXEBIOS                     32
 236 #define IMG_FCOEBIOS                    33
 237 #define IMG_ISCSI_BAK                   176
 238 #define IMG_FCOE                        162
 239 #define IMG_FCOE_BAK                    178
 240 #define IMG_NCSI                        16
 241 #define IMG_PHY                         192
 242 #define FLASHROM_OPER_FLASH             1
 243 #define FLASHROM_OPER_SAVE              2
 244 #define FLASHROM_OPER_REPORT            4
 245 #define FLASHROM_OPER_FLASH_PHY         9
 246 #define FLASHROM_OPER_SAVE_PHY          10
 247 #define TN_8022                         13
 248
 249 enum {
 250         PHY_TYPE_CX4_10GB = 0,
 251         PHY_TYPE_XFP_10GB,
 252         PHY_TYPE_SFP_1GB,
 253         PHY_TYPE_SFP_PLUS_10GB,
 254         PHY_TYPE_KR_10GB,
 255         PHY_TYPE_KX4_10GB,
 256         PHY_TYPE_BASET_10GB,
 257         PHY_TYPE_BASET_1GB,
 258         PHY_TYPE_BASEX_1GB,
 259         PHY_TYPE_SGMII,
 260         PHY_TYPE_DISABLED = 255
 261 };
 262
 263 /**
 264  * @brief Define and hold all necessary info for a single interrupt
 265  */
 266 #define OCE_MAX_MSI                     32 /* Message Signaled Interrupts */
 267 #define OCE_MAX_MSIX                    2048 /* PCI Express MSI Interrrupts */
 268
 269 typedef struct oce_intr_info {
 270         void *tag;              /* cookie returned by bus_setup_intr */
 271         struct resource *intr_res;      /* PCI resource container */
 272         int irq_rr;             /* resource id for the interrupt */
 273         struct oce_softc *sc;   /* pointer to the parent soft c */
 274         struct oce_eq *eq;      /* pointer to the connected EQ */
 275         struct taskqueue *tq;   /* Associated task queue */
 276         struct task task;       /* task queue task */
 277         char task_name[32];     /* task name */
 278         int vector;             /* interrupt vector number */
 279 } OCE_INTR_INFO, *POCE_INTR_INFO;
 280
 281
 282 /* Ring related */
 283 #define GET_Q_NEXT(_START, _STEP, _END) \
 284         (((_START) + (_STEP)) < (_END) ? ((_START) + (_STEP)) \
 285         : (((_START) + (_STEP)) - (_END)))
 286
 287 #define DBUF_PA(obj)                    ((obj)->addr)
 288 #define DBUF_VA(obj)                    ((obj)->ptr)
 289 #define DBUF_TAG(obj)                   ((obj)->tag)
 290 #define DBUF_MAP(obj)                   ((obj)->map)
 291 #define DBUF_SYNC(obj, flags)           \
 292                 (void) bus_dmamap_sync(DBUF_TAG(obj), DBUF_MAP(obj), (flags))
 293
 294 #define RING_NUM_PENDING(ring)          ring->num_used
 295 #define RING_FULL(ring)                 (ring->num_used == ring->num_items)
 296 #define RING_EMPTY(ring)                (ring->num_used == 0)
 297 #define RING_NUM_FREE(ring)             \
 298                 (uint32_t)(ring->num_items - ring->num_used)
 299 #define RING_GET(ring, n)               \
 300                 ring->cidx = GET_Q_NEXT(ring->cidx, n, ring->num_items)
 301 #define RING_PUT(ring, n)               \
 302                 ring->pidx = GET_Q_NEXT(ring->pidx, n, ring->num_items)
 303
 304 #define RING_GET_CONSUMER_ITEM_VA(ring, type)   \
 305         (void*)((type *)DBUF_VA(&ring->dma) + ring->cidx)
 306 #define RING_GET_CONSUMER_ITEM_PA(ring, type)           \
 307         (uint64_t)(((type *)DBUF_PA(ring->dbuf)) + ring->cidx)
 308 #define RING_GET_PRODUCER_ITEM_VA(ring, type)           \
 309         (void *)(((type *)DBUF_VA(&ring->dma)) + ring->pidx)
 310 #define RING_GET_PRODUCER_ITEM_PA(ring, type)           \
 311         (uint64_t)(((type *)DBUF_PA(ring->dbuf)) + ring->pidx)
 312
 313 #define OCE_DMAPTR(o, c)                ((c *)(o)->ptr)
 314
 315 struct oce_packet_desc {
 316         struct mbuf *mbuf;
 317         bus_dmamap_t map;
 318         int nsegs;
 319         uint32_t wqe_idx;
 320 };
 321
 322 typedef struct oce_dma_mem {
 323         bus_dma_tag_t tag;
 324         bus_dmamap_t map;
 325         void *ptr;
 326         bus_addr_t paddr;
 327 } OCE_DMA_MEM, *POCE_DMA_MEM;
 328
 329 typedef struct oce_ring_buffer_s {
 330         uint16_t cidx;  /* Get ptr */
 331         uint16_t pidx;  /* Put Ptr */
 332         size_t item_size;
 333         size_t num_items;
 334         uint32_t num_used;
 335         OCE_DMA_MEM dma;
 336 } oce_ring_buffer_t;
 337
 338 /* Stats */
 339 #define OCE_UNICAST_PACKET      0
 340 #define OCE_MULTICAST_PACKET    1
 341 #define OCE_BROADCAST_PACKET    2
 342 #define OCE_RSVD_PACKET         3
 343
 344 struct oce_rx_stats {
 345         /* Total Receive Stats*/
 346         uint64_t t_rx_pkts;
 347         uint64_t t_rx_bytes;
 348         uint32_t t_rx_frags;
 349         uint32_t t_rx_mcast_pkts;
 350         uint32_t t_rx_ucast_pkts;
 351         uint32_t t_rxcp_errs;
 352 };
 353 struct oce_tx_stats {
 354         /*Total Transmit Stats */
 355         uint64_t t_tx_pkts;
 356         uint64_t t_tx_bytes;
 357         uint32_t t_tx_reqs;
 358         uint32_t t_tx_stops;
 359         uint32_t t_tx_wrbs;
 360         uint32_t t_tx_compl;
 361         uint32_t t_ipv6_ext_hdr_tx_drop;
 362 };
 363
 364 struct oce_be_stats {
 365         uint8_t  be_on_die_temperature;
 366         uint32_t be_tx_events;
 367         uint32_t eth_red_drops;
 368         uint32_t rx_drops_no_pbuf;
 369         uint32_t rx_drops_no_txpb;
 370         uint32_t rx_drops_no_erx_descr;
 371         uint32_t rx_drops_no_tpre_descr;
 372         uint32_t rx_drops_too_many_frags;
 373         uint32_t rx_drops_invalid_ring;
 374         uint32_t forwarded_packets;
 375         uint32_t rx_drops_mtu;
 376         uint32_t rx_crc_errors;
 377         uint32_t rx_alignment_symbol_errors;
 378         uint32_t rx_pause_frames;
 379         uint32_t rx_priority_pause_frames;
 380         uint32_t rx_control_frames;
 381         uint32_t rx_in_range_errors;
 382         uint32_t rx_out_range_errors;
 383         uint32_t rx_frame_too_long;
 384         uint32_t rx_address_match_errors;
 385         uint32_t rx_dropped_too_small;
 386         uint32_t rx_dropped_too_short;
 387         uint32_t rx_dropped_header_too_small;
 388         uint32_t rx_dropped_tcp_length;
 389         uint32_t rx_dropped_runt;
 390         uint32_t rx_ip_checksum_errs;
 391         uint32_t rx_tcp_checksum_errs;
 392         uint32_t rx_udp_checksum_errs;
 393         uint32_t rx_switched_unicast_packets;
 394         uint32_t rx_switched_multicast_packets;
 395         uint32_t rx_switched_broadcast_packets;
 396         uint32_t tx_pauseframes;
 397         uint32_t tx_priority_pauseframes;
 398         uint32_t tx_controlframes;
 399         uint32_t rxpp_fifo_overflow_drop;
 400         uint32_t rx_input_fifo_overflow_drop;
 401         uint32_t pmem_fifo_overflow_drop;
 402         uint32_t jabber_events;
 403 };
 404
 405 struct oce_xe201_stats {
 406         uint64_t tx_pkts;
 407         uint64_t tx_unicast_pkts;
 408         uint64_t tx_multicast_pkts;
 409         uint64_t tx_broadcast_pkts;
 410         uint64_t tx_bytes;
 411         uint64_t tx_unicast_bytes;
 412         uint64_t tx_multicast_bytes;
 413         uint64_t tx_broadcast_bytes;
 414         uint64_t tx_discards;
 415         uint64_t tx_errors;
 416         uint64_t tx_pause_frames;
 417         uint64_t tx_pause_on_frames;
 418         uint64_t tx_pause_off_frames;
 419         uint64_t tx_internal_mac_errors;
 420         uint64_t tx_control_frames;
 421         uint64_t tx_pkts_64_bytes;
 422         uint64_t tx_pkts_65_to_127_bytes;
 423         uint64_t tx_pkts_128_to_255_bytes;
 424         uint64_t tx_pkts_256_to_511_bytes;
 425         uint64_t tx_pkts_512_to_1023_bytes;
 426         uint64_t tx_pkts_1024_to_1518_bytes;
 427         uint64_t tx_pkts_1519_to_2047_bytes;
 428         uint64_t tx_pkts_2048_to_4095_bytes;
 429         uint64_t tx_pkts_4096_to_8191_bytes;
 430         uint64_t tx_pkts_8192_to_9216_bytes;
 431         uint64_t tx_lso_pkts;
 432         uint64_t rx_pkts;
 433         uint64_t rx_unicast_pkts;
 434         uint64_t rx_multicast_pkts;
 435         uint64_t rx_broadcast_pkts;
 436         uint64_t rx_bytes;
 437         uint64_t rx_unicast_bytes;
 438         uint64_t rx_multicast_bytes;
 439         uint64_t rx_broadcast_bytes;
 440         uint32_t rx_unknown_protos;
 441         uint64_t rx_discards;
 442         uint64_t rx_errors;
 443         uint64_t rx_crc_errors;
 444         uint64_t rx_alignment_errors;
 445         uint64_t rx_symbol_errors;
 446         uint64_t rx_pause_frames;
 447         uint64_t rx_pause_on_frames;
 448         uint64_t rx_pause_off_frames;
 449         uint64_t rx_frames_too_long;
 450         uint64_t rx_internal_mac_errors;
 451         uint32_t rx_undersize_pkts;
 452         uint32_t rx_oversize_pkts;
 453         uint32_t rx_fragment_pkts;
 454         uint32_t rx_jabbers;
 455         uint64_t rx_control_frames;
 456         uint64_t rx_control_frames_unknown_opcode;
 457         uint32_t rx_in_range_errors;
 458         uint32_t rx_out_of_range_errors;
 459         uint32_t rx_address_match_errors;
 460         uint32_t rx_vlan_mismatch_errors;
 461         uint32_t rx_dropped_too_small;
 462         uint32_t rx_dropped_too_short;
 463         uint32_t rx_dropped_header_too_small;
 464         uint32_t rx_dropped_invalid_tcp_length;
 465         uint32_t rx_dropped_runt;
 466         uint32_t rx_ip_checksum_errors;
 467         uint32_t rx_tcp_checksum_errors;
 468         uint32_t rx_udp_checksum_errors;
 469         uint32_t rx_non_rss_pkts;
 470         uint64_t rx_ipv4_pkts;
 471         uint64_t rx_ipv6_pkts;
 472         uint64_t rx_ipv4_bytes;
 473         uint64_t rx_ipv6_bytes;
 474         uint64_t rx_nic_pkts;
 475         uint64_t rx_tcp_pkts;
 476         uint64_t rx_iscsi_pkts;
 477         uint64_t rx_management_pkts;
 478         uint64_t rx_switched_unicast_pkts;
 479         uint64_t rx_switched_multicast_pkts;
 480         uint64_t rx_switched_broadcast_pkts;
 481         uint64_t num_forwards;
 482         uint32_t rx_fifo_overflow;
 483         uint32_t rx_input_fifo_overflow;
 484         uint64_t rx_drops_too_many_frags;
 485         uint32_t rx_drops_invalid_queue;
 486         uint64_t rx_drops_mtu;
 487         uint64_t rx_pkts_64_bytes;
 488         uint64_t rx_pkts_65_to_127_bytes;
 489         uint64_t rx_pkts_128_to_255_bytes;
 490         uint64_t rx_pkts_256_to_511_bytes;
 491         uint64_t rx_pkts_512_to_1023_bytes;
 492         uint64_t rx_pkts_1024_to_1518_bytes;
 493         uint64_t rx_pkts_1519_to_2047_bytes;
 494         uint64_t rx_pkts_2048_to_4095_bytes;
 495         uint64_t rx_pkts_4096_to_8191_bytes;
 496         uint64_t rx_pkts_8192_to_9216_bytes;
 497 };
 498
 499 struct oce_drv_stats {
 500         struct oce_rx_stats rx;
 501         struct oce_tx_stats tx;
 502         union {
 503                 struct oce_be_stats be;
 504                 struct oce_xe201_stats xe201;
 505         } u0;
 506 };
 507
 508 #define INTR_RATE_HWM                   15000
 509 #define INTR_RATE_LWM                   10000
 510
 511 #define OCE_MAX_EQD 128u
 512 #define OCE_MIN_EQD 0u
 513
 514 struct oce_set_eqd {
 515         uint32_t eq_id;
 516         uint32_t phase;
 517         uint32_t delay_multiplier;
 518 };
 519
 520 struct oce_aic_obj {             /* Adaptive interrupt coalescing (AIC) info */
 521         boolean_t enable;
 522         uint32_t  min_eqd;            /* in usecs */
 523         uint32_t  max_eqd;            /* in usecs */
 524         uint32_t  cur_eqd;            /* in usecs */
 525         uint32_t  et_eqd;             /* configured value when aic is off */
 526         uint64_t  ticks;
 527         uint64_t  prev_rxpkts;
 528         uint64_t  prev_txreqs;
 529 };
 530
 531 #define MAX_LOCK_DESC_LEN                       32
 532 struct oce_lock {
 533         struct mtx mutex;
 534         char name[MAX_LOCK_DESC_LEN+1];
 535 };
 536 #define OCE_LOCK                                struct oce_lock
 537
 538 #define LOCK_CREATE(lock, desc)                 { \
 539         strncpy((lock)->name, (desc), MAX_LOCK_DESC_LEN); \
 540         (lock)->name[MAX_LOCK_DESC_LEN] = '\0'; \
 541         mtx_init(&(lock)->mutex, (lock)->name, NULL, MTX_DEF); \
 542 }
 543 #define LOCK_DESTROY(lock)                      \
 544                 if (mtx_initialized(&(lock)->mutex))\
 545                         mtx_destroy(&(lock)->mutex)
 546 #define TRY_LOCK(lock)                          mtx_trylock(&(lock)->mutex)
 547 #define LOCK(lock)                              mtx_lock(&(lock)->mutex)
 548 #define LOCKED(lock)                            mtx_owned(&(lock)->mutex)
 549 #define UNLOCK(lock)                            mtx_unlock(&(lock)->mutex)
 550
 551 #define DEFAULT_MQ_MBOX_TIMEOUT                 (5 * 1000 * 1000)
 552 #define MBX_READY_TIMEOUT                       (1 * 1000 * 1000)
 553 #define DEFAULT_DRAIN_TIME                      200
 554 #define MBX_TIMEOUT_SEC                         5
 555 #define STAT_TIMEOUT                            2000000
 556
 557 /* size of the packet descriptor array in a transmit queue */
 558 #define OCE_TX_RING_SIZE                        2048
 559 #define OCE_RX_RING_SIZE                        1024
 560 #define OCE_WQ_PACKET_ARRAY_SIZE                (OCE_TX_RING_SIZE/2)
 561 #define OCE_RQ_PACKET_ARRAY_SIZE                (OCE_RX_RING_SIZE)
 562
 563 struct oce_dev;
 564
 565 enum eq_len {
 566         EQ_LEN_256  = 256,
 567         EQ_LEN_512  = 512,
 568         EQ_LEN_1024 = 1024,
 569         EQ_LEN_2048 = 2048,
 570         EQ_LEN_4096 = 4096
 571 };
 572
 573 enum eqe_size {
 574         EQE_SIZE_4  = 4,
 575         EQE_SIZE_16 = 16
 576 };
 577
 578 enum qtype {
 579         QTYPE_EQ,
 580         QTYPE_MQ,
 581         QTYPE_WQ,
 582         QTYPE_RQ,
 583         QTYPE_CQ,
 584         QTYPE_RSS
 585 };
 586
 587 typedef enum qstate_e {
 588         QDELETED = 0x0,
 589         QCREATED = 0x1
 590 } qstate_t;
 591
 592 struct eq_config {
 593         enum eq_len q_len;
 594         enum eqe_size item_size;
 595         uint32_t q_vector_num;
 596         uint8_t min_eqd;
 597         uint8_t max_eqd;
 598         uint8_t cur_eqd;
 599         uint8_t pad;
 600 };
 601
 602 struct oce_eq {
 603         uint32_t eq_id;
 604         void *parent;
 605         void *cb_context;
 606         oce_ring_buffer_t *ring;
 607         uint32_t ref_count;
 608         qstate_t qstate;
 609         struct oce_cq *cq[OCE_MAX_CQ_EQ];
 610         int cq_valid;
 611         struct eq_config eq_cfg;
 612         int vector;
 613         uint64_t intr;
 614 };
 615
 616 enum cq_len {
 617         CQ_LEN_256  = 256,
 618         CQ_LEN_512  = 512,
 619         CQ_LEN_1024 = 1024,
 620         CQ_LEN_2048 = 2048
 621 };
 622
 623 struct cq_config {
 624         enum cq_len q_len;
 625         uint32_t item_size;
 626         boolean_t is_eventable;
 627         boolean_t sol_eventable;
 628         boolean_t nodelay;
 629         uint16_t dma_coalescing;
 630 };
 631
 632 typedef uint16_t(*cq_handler_t) (void *arg1);
 633
 634 struct oce_cq {
 635         uint32_t cq_id;
 636         void *parent;
 637         struct oce_eq *eq;
 638         cq_handler_t cq_handler;
 639         void *cb_arg;
 640         oce_ring_buffer_t *ring;
 641         qstate_t qstate;
 642         struct cq_config cq_cfg;
 643         uint32_t ref_count;
 644 };
 645
 646
 647 struct mq_config {
 648         uint32_t eqd;
 649         uint8_t q_len;
 650         uint8_t pad[3];
 651 };
 652
 653
 654 struct oce_mq {
 655         void *parent;
 656         oce_ring_buffer_t *ring;
 657         uint32_t mq_id;
 658         struct oce_cq *cq;
 659         struct oce_cq *async_cq;
 660         uint32_t mq_free;
 661         qstate_t qstate;
 662         struct mq_config cfg;
 663 };
 664
 665 struct oce_mbx_ctx {
 666         struct oce_mbx *mbx;
 667         void (*cb) (void *ctx);
 668         void *cb_ctx;
 669 };
 670
 671 struct wq_config {
 672         uint8_t wq_type;
 673         uint16_t buf_size;
 674         uint8_t pad[1];
 675         uint32_t q_len;
 676         uint16_t pd_id;
 677         uint16_t pci_fn_num;
 678         uint32_t eqd;   /* interrupt delay */
 679         uint32_t nbufs;
 680         uint32_t nhdl;
 681 };
 682
 683 struct oce_tx_queue_stats {
 684         uint64_t tx_pkts;
 685         uint64_t tx_bytes;
 686         uint32_t tx_reqs;
 687         uint32_t tx_stops; /* number of times TX Q was stopped */
 688         uint32_t tx_wrbs;
 689         uint32_t tx_compl;
 690         uint32_t tx_rate;
 691         uint32_t ipv6_ext_hdr_tx_drop;
 692 };
 693
 694 struct oce_wq {
 695         OCE_LOCK tx_lock;
 696         OCE_LOCK tx_compl_lock;
 697         void *parent;
 698         oce_ring_buffer_t *ring;
 699         struct oce_cq *cq;
 700         bus_dma_tag_t tag;
 701         struct oce_packet_desc pckts[OCE_WQ_PACKET_ARRAY_SIZE];
 702         uint32_t pkt_desc_tail;
 703         uint32_t pkt_desc_head;
 704         uint32_t wqm_used;
 705         boolean_t resched;
 706         uint32_t wq_free;
 707         uint32_t tx_deferd;
 708         uint32_t pkt_drops;
 709         qstate_t qstate;
 710         uint16_t wq_id;
 711         struct wq_config cfg;
 712         int queue_index;
 713         struct oce_tx_queue_stats tx_stats;
 714         struct buf_ring *br;
 715         struct task txtask;
 716         uint32_t db_offset;
 717 };
 718
 719 struct rq_config {
 720         uint32_t q_len;
 721         uint32_t frag_size;
 722         uint32_t mtu;
 723         uint32_t if_id;
 724         uint32_t is_rss_queue;
 725         uint32_t eqd;
 726         uint32_t nbufs;
 727 };
 728
 729 struct oce_rx_queue_stats {
 730         uint32_t rx_post_fail;
 731         uint32_t rx_ucast_pkts;
 732         uint32_t rx_compl;
 733         uint64_t rx_bytes;
 734         uint64_t rx_bytes_prev;
 735         uint64_t rx_pkts;
 736         uint32_t rx_rate;
 737         uint32_t rx_mcast_pkts;
 738         uint32_t rxcp_err;
 739         uint32_t rx_frags;
 740         uint32_t prev_rx_frags;
 741         uint32_t rx_fps;
 742         uint32_t rx_drops_no_frags;  /* HW has no fetched frags */
 743 };
 744
 745
 746 struct oce_rq {
 747         struct rq_config cfg;
 748         uint32_t rq_id;
 749         int queue_index;
 750         uint32_t rss_cpuid;
 751         void *parent;
 752         oce_ring_buffer_t *ring;
 753         struct oce_cq *cq;
 754         void *pad1;
 755         bus_dma_tag_t tag;
 756         struct oce_packet_desc pckts[OCE_RQ_PACKET_ARRAY_SIZE];
 757         uint32_t pending;
 758 #ifdef notdef
 759         struct mbuf *head;
 760         struct mbuf *tail;
 761         int fragsleft;
 762 #endif
 763         qstate_t qstate;
 764         OCE_LOCK rx_lock;
 765         struct oce_rx_queue_stats rx_stats;
 766         struct lro_ctrl lro;
 767         int lro_pkts_queued;
 768         int islro;
 769         struct nic_hwlro_cqe_part1 *cqe_firstpart;
 770
 771 };
 772
 773 struct link_status {
 774         uint8_t phys_port_speed;
 775         uint8_t logical_link_status;
 776         uint16_t qos_link_speed;
 777 };
 778
 779
 780
 781 #define OCE_FLAGS_PCIX                  0x00000001
 782 #define OCE_FLAGS_PCIE                  0x00000002
 783 #define OCE_FLAGS_MSI_CAPABLE           0x00000004
 784 #define OCE_FLAGS_MSIX_CAPABLE          0x00000008
 785 #define OCE_FLAGS_USING_MSI             0x00000010
 786 #define OCE_FLAGS_USING_MSIX            0x00000020
 787 #define OCE_FLAGS_FUNCRESET_RQD         0x00000040
 788 #define OCE_FLAGS_VIRTUAL_PORT          0x00000080
 789 #define OCE_FLAGS_MBOX_ENDIAN_RQD       0x00000100
 790 #define OCE_FLAGS_BE3                   0x00000200
 791 #define OCE_FLAGS_XE201                 0x00000400
 792 #define OCE_FLAGS_BE2                   0x00000800
 793 #define OCE_FLAGS_SH                    0x00001000
 794 #define OCE_FLAGS_OS2BMC                0x00002000
 795
 796 #define OCE_DEV_BE2_CFG_BAR             1
 797 #define OCE_DEV_CFG_BAR                 0
 798 #define OCE_PCI_CSR_BAR                 2
 799 #define OCE_PCI_DB_BAR                  4
 800
 801 typedef struct oce_softc {
 802         device_t dev;
 803         OCE_LOCK dev_lock;
 804
 805         uint32_t flags;
 806
 807         uint32_t pcie_link_speed;
 808         uint32_t pcie_link_width;
 809
 810         uint8_t fn; /* PCI function number */
 811
 812         struct resource *devcfg_res;
 813         bus_space_tag_t devcfg_btag;
 814         bus_space_handle_t devcfg_bhandle;
 815         void *devcfg_vhandle;
 816
 817         struct resource *csr_res;
 818         bus_space_tag_t csr_btag;
 819         bus_space_handle_t csr_bhandle;
 820         void *csr_vhandle;
 821
 822         struct resource *db_res;
 823         bus_space_tag_t db_btag;
 824         bus_space_handle_t db_bhandle;
 825         void *db_vhandle;
 826
 827         OCE_INTR_INFO intrs[OCE_MAX_EQ];
 828         int intr_count;
 829         int roce_intr_count;
 830
 831         struct ifnet *ifp;
 832
 833         struct ifmedia media;
 834         uint8_t link_status;
 835         uint8_t link_speed;
 836         uint8_t duplex;
 837         uint32_t qos_link_speed;
 838         uint32_t speed;
 839         uint32_t enable_hwlro;
 840
 841         char fw_version[32];
 842         struct mac_address_format macaddr;
 843
 844         OCE_DMA_MEM bsmbx;
 845         OCE_LOCK bmbx_lock;
 846
 847         uint32_t config_number;
 848         uint32_t asic_revision;
 849         uint32_t port_id;
 850         uint32_t function_mode;
 851         uint32_t function_caps;
 852         uint32_t max_tx_rings;
 853         uint32_t max_rx_rings;
 854
 855         struct oce_wq *wq[OCE_MAX_WQ];  /* TX work queues */
 856         struct oce_rq *rq[OCE_MAX_RQ];  /* RX work queues */
 857         struct oce_cq *cq[OCE_MAX_CQ];  /* Completion queues */
 858         struct oce_eq *eq[OCE_MAX_EQ];  /* Event queues */
 859         struct oce_mq *mq;              /* Mailbox queue */
 860
 861         uint32_t neqs;
 862         uint32_t ncqs;
 863         uint32_t nrqs;
 864         uint32_t nwqs;
 865         uint32_t nrssqs;
 866
 867         uint32_t tx_ring_size;
 868         uint32_t rx_ring_size;
 869         uint32_t rq_frag_size;
 870
 871         uint32_t if_id;         /* interface ID */
 872         uint32_t nifs;          /* number of adapter interfaces, 0 or 1 */
 873         uint32_t pmac_id;       /* PMAC id */
 874
 875         uint32_t if_cap_flags;
 876
 877         uint32_t flow_control;
 878         uint8_t  promisc;
 879
 880         struct oce_aic_obj aic_obj[OCE_MAX_EQ];
 881
 882         /*Vlan Filtering related */
 883         eventhandler_tag vlan_attach;
 884         eventhandler_tag vlan_detach;
 885         uint16_t vlans_added;
 886         uint8_t vlan_tag[MAX_VLANS];
 887         /*stats */
 888         OCE_DMA_MEM stats_mem;
 889         struct oce_drv_stats oce_stats_info;
 890         struct callout  timer;
 891         int8_t be3_native;
 892         uint8_t hw_error;
 893         uint16_t qnq_debug_event;
 894         uint16_t qnqid;
 895         uint32_t pvid;
 896         uint32_t max_vlans;
 897         uint32_t bmc_filt_mask;
 898
 899         void *rdma_context;
 900         uint32_t rdma_flags;
 901         struct oce_softc *next;
 902
 903 } OCE_SOFTC, *POCE_SOFTC;
 904
 905 #define OCE_RDMA_FLAG_SUPPORTED         0x00000001
 906
 907
 908 /**************************************************
 909  * BUS memory read/write macros
 910  * BE3: accesses three BAR spaces (CFG, CSR, DB)
 911  * Lancer: accesses one BAR space (CFG)
 912  **************************************************/
 913 #define OCE_READ_CSR_MPU(sc, space, o) \
 914         ((IS_BE(sc)) ? (bus_space_read_4((sc)->space##_btag, \
 915                                         (sc)->space##_bhandle,o)) \
 916                                 : (bus_space_read_4((sc)->devcfg_btag, \
 917                                         (sc)->devcfg_bhandle,o)))
 918 #define OCE_READ_REG32(sc, space, o) \
 919         ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_4((sc)->space##_btag, \
 920                                         (sc)->space##_bhandle,o)) \
 921                                 : (bus_space_read_4((sc)->devcfg_btag, \
 922                                         (sc)->devcfg_bhandle,o)))
 923 #define OCE_READ_REG16(sc, space, o) \
 924         ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_2((sc)->space##_btag, \
 925                                         (sc)->space##_bhandle,o)) \
 926                                 : (bus_space_read_2((sc)->devcfg_btag, \
 927                                         (sc)->devcfg_bhandle,o)))
 928 #define OCE_READ_REG8(sc, space, o) \
 929         ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_1((sc)->space##_btag, \
 930                                         (sc)->space##_bhandle,o)) \
 931                                 : (bus_space_read_1((sc)->devcfg_btag, \
 932                                         (sc)->devcfg_bhandle,o)))
 933
 934 #define OCE_WRITE_CSR_MPU(sc, space, o, v) \
 935         ((IS_BE(sc)) ? (bus_space_write_4((sc)->space##_btag, \
 936                                        (sc)->space##_bhandle,o,v)) \
 937                                 : (bus_space_write_4((sc)->devcfg_btag, \
 938                                         (sc)->devcfg_bhandle,o,v)))
 939 #define OCE_WRITE_REG32(sc, space, o, v) \
 940         ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_4((sc)->space##_btag, \
 941                                        (sc)->space##_bhandle,o,v)) \
 942                                 : (bus_space_write_4((sc)->devcfg_btag, \
 943                                         (sc)->devcfg_bhandle,o,v)))
 944 #define OCE_WRITE_REG16(sc, space, o, v) \
 945         ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_2((sc)->space##_btag, \
 946                                        (sc)->space##_bhandle,o,v)) \
 947                                 : (bus_space_write_2((sc)->devcfg_btag, \
 948                                         (sc)->devcfg_bhandle,o,v)))
 949 #define OCE_WRITE_REG8(sc, space, o, v) \
 950         ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_1((sc)->space##_btag, \
 951                                        (sc)->space##_bhandle,o,v)) \
 952                                 : (bus_space_write_1((sc)->devcfg_btag, \
 953                                         (sc)->devcfg_bhandle,o,v)))
 954
 955 void oce_rx_flush_lro(struct oce_rq *rq);
 956 /***********************************************************
 957  * DMA memory functions
 958  ***********************************************************/
 959 #define oce_dma_sync(d, f)              bus_dmamap_sync((d)->tag, (d)->map, f)
 960 int oce_dma_alloc(POCE_SOFTC sc, bus_size_t size, POCE_DMA_MEM dma, int flags);
 961 void oce_dma_free(POCE_SOFTC sc, POCE_DMA_MEM dma);
 962 void oce_dma_map_addr(void *arg, bus_dma_segment_t * segs, int nseg, int error);
 963 void oce_destroy_ring_buffer(POCE_SOFTC sc, oce_ring_buffer_t *ring);
 964 oce_ring_buffer_t *oce_create_ring_buffer(POCE_SOFTC sc,
 965                                           uint32_t q_len, uint32_t num_entries);
 966 /************************************************************
 967  * oce_hw_xxx functions
 968  ************************************************************/
 969 int oce_clear_rx_buf(struct oce_rq *rq);
 970 int oce_hw_pci_alloc(POCE_SOFTC sc);
 971 int oce_hw_init(POCE_SOFTC sc);
 972 int oce_hw_start(POCE_SOFTC sc);
 973 int oce_create_nw_interface(POCE_SOFTC sc);
 974 int oce_pci_soft_reset(POCE_SOFTC sc);
 975 int oce_hw_update_multicast(POCE_SOFTC sc);
 976 void oce_delete_nw_interface(POCE_SOFTC sc);
 977 void oce_hw_shutdown(POCE_SOFTC sc);
 978 void oce_hw_intr_enable(POCE_SOFTC sc);
 979 void oce_hw_intr_disable(POCE_SOFTC sc);
 980 void oce_hw_pci_free(POCE_SOFTC sc);
 981
 982 /***********************************************************
 983  * oce_queue_xxx functions
 984  ***********************************************************/
 985 int oce_queue_init_all(POCE_SOFTC sc);
 986 int oce_start_rq(struct oce_rq *rq);
 987 int oce_start_wq(struct oce_wq *wq);
 988 int oce_start_mq(struct oce_mq *mq);
 989 int oce_start_rx(POCE_SOFTC sc);
 990 void oce_arm_eq(POCE_SOFTC sc,
 991                 int16_t qid, int npopped, uint32_t rearm, uint32_t clearint);
 992 void oce_queue_release_all(POCE_SOFTC sc);
 993 void oce_arm_cq(POCE_SOFTC sc, int16_t qid, int npopped, uint32_t rearm);
 994 void oce_drain_eq(struct oce_eq *eq);
 995 void oce_drain_mq_cq(void *arg);
 996 void oce_drain_rq_cq(struct oce_rq *rq);
 997 void oce_drain_wq_cq(struct oce_wq *wq);
 998
 999 uint32_t oce_page_list(oce_ring_buffer_t *ring, struct phys_addr *pa_list);
1000
1001 /***********************************************************
1002  * cleanup  functions
1003  ***********************************************************/
1004 void oce_stop_rx(POCE_SOFTC sc);
1005 void oce_discard_rx_comp(struct oce_rq *rq, int num_frags);
1006 void oce_rx_cq_clean(struct oce_rq *rq);
1007 void oce_rx_cq_clean_hwlro(struct oce_rq *rq);
1008 void oce_intr_free(POCE_SOFTC sc);
1009 void oce_free_posted_rxbuf(struct oce_rq *rq);
1010 #if defined(INET6) || defined(INET)
1011 void oce_free_lro(POCE_SOFTC sc);
1012 #endif
1013
1014
1015 /************************************************************
1016  * Mailbox functions
1017  ************************************************************/
1018 int oce_fw_clean(POCE_SOFTC sc);
1019 int oce_wait_ready(POCE_SOFTC sc);
1020 int oce_reset_fun(POCE_SOFTC sc);
1021 int oce_mbox_init(POCE_SOFTC sc);
1022 int oce_mbox_dispatch(POCE_SOFTC sc, uint32_t tmo_sec);
1023 int oce_get_fw_version(POCE_SOFTC sc);
1024 int oce_first_mcc_cmd(POCE_SOFTC sc);
1025
1026 int oce_read_mac_addr(POCE_SOFTC sc, uint32_t if_id, uint8_t perm,
1027                         uint8_t type, struct mac_address_format *mac);
1028 int oce_get_fw_config(POCE_SOFTC sc);
1029 int oce_if_create(POCE_SOFTC sc, uint32_t cap_flags, uint32_t en_flags,
1030                 uint16_t vlan_tag, uint8_t *mac_addr, uint32_t *if_id);
1031 int oce_if_del(POCE_SOFTC sc, uint32_t if_id);
1032 int oce_config_vlan(POCE_SOFTC sc, uint32_t if_id,
1033                 struct normal_vlan *vtag_arr, uint8_t vtag_cnt,
1034                 uint32_t untagged, uint32_t enable_promisc);
1035 int oce_set_flow_control(POCE_SOFTC sc, uint32_t flow_control);
1036 int oce_config_nic_rss(POCE_SOFTC sc, uint32_t if_id, uint16_t enable_rss);
1037 int oce_rxf_set_promiscuous(POCE_SOFTC sc, uint8_t enable);
1038 int oce_set_common_iface_rx_filter(POCE_SOFTC sc, POCE_DMA_MEM sgl);
1039 int oce_get_link_status(POCE_SOFTC sc, struct link_status *link);
1040 int oce_mbox_get_nic_stats_v0(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem);
1041 int oce_mbox_get_nic_stats_v1(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem);
1042 int oce_mbox_get_nic_stats_v2(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem);
1043 int oce_mbox_get_pport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1044                                 uint32_t reset_stats);
1045 int oce_mbox_get_vport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1046                                 uint32_t req_size, uint32_t reset_stats);
1047 int oce_update_multicast(POCE_SOFTC sc, POCE_DMA_MEM pdma_mem);
1048 int oce_pass_through_mbox(POCE_SOFTC sc, POCE_DMA_MEM dma_mem, uint32_t req_size);
1049 int oce_mbox_macaddr_del(POCE_SOFTC sc, uint32_t if_id, uint32_t pmac_id);
1050 int oce_mbox_macaddr_add(POCE_SOFTC sc, uint8_t *mac_addr,
1051                 uint32_t if_id, uint32_t *pmac_id);
1052 int oce_mbox_cmd_test_loopback(POCE_SOFTC sc, uint32_t port_num,
1053         uint32_t loopback_type, uint32_t pkt_size, uint32_t num_pkts,
1054         uint64_t pattern);
1055
1056 int oce_mbox_cmd_set_loopback(POCE_SOFTC sc, uint8_t port_num,
1057         uint8_t loopback_type, uint8_t enable);
1058
1059 int oce_mbox_check_native_mode(POCE_SOFTC sc);
1060 int oce_mbox_post(POCE_SOFTC sc,
1061                   struct oce_mbx *mbx, struct oce_mbx_ctx *mbxctx);
1062 int oce_mbox_write_flashrom(POCE_SOFTC sc, uint32_t optype,uint32_t opcode,
1063                                 POCE_DMA_MEM pdma_mem, uint32_t num_bytes);
1064 int oce_mbox_lancer_write_flashrom(POCE_SOFTC sc, uint32_t data_size,
1065                         uint32_t data_offset,POCE_DMA_MEM pdma_mem,
1066                         uint32_t *written_data, uint32_t *additional_status);
1067
1068 int oce_mbox_get_flashrom_crc(POCE_SOFTC sc, uint8_t *flash_crc,
1069                                 uint32_t offset, uint32_t optype);
1070 int oce_mbox_get_phy_info(POCE_SOFTC sc, struct oce_phy_info *phy_info);
1071 int oce_mbox_create_rq(struct oce_rq *rq);
1072 int oce_mbox_create_wq(struct oce_wq *wq);
1073 int oce_mbox_create_eq(struct oce_eq *eq);
1074 int oce_mbox_cq_create(struct oce_cq *cq, uint32_t ncoalesce,
1075                          uint32_t is_eventable);
1076 int oce_mbox_read_transrecv_data(POCE_SOFTC sc, uint32_t page_num);
1077 void oce_mbox_eqd_modify_periodic(POCE_SOFTC sc, struct oce_set_eqd *set_eqd,
1078                                         int num);
1079 int oce_get_profile_config(POCE_SOFTC sc, uint32_t max_rss);
1080 int oce_get_func_config(POCE_SOFTC sc);
1081 void mbx_common_req_hdr_init(struct mbx_hdr *hdr,
1082                              uint8_t dom,
1083                              uint8_t port,
1084                              uint8_t subsys,
1085                              uint8_t opcode,
1086                              uint32_t timeout, uint32_t pyld_len,
1087                              uint8_t version);
1088
1089
1090 uint16_t oce_mq_handler(void *arg);
1091
1092 /************************************************************
1093  * Transmit functions
1094  ************************************************************/
1095 uint16_t oce_wq_handler(void *arg);
1096 void     oce_start(struct ifnet *ifp);
1097 void     oce_tx_task(void *arg, int npending);
1098
1099 /************************************************************
1100  * Receive functions
1101  ************************************************************/
1102 int      oce_alloc_rx_bufs(struct oce_rq *rq, int count);
1103 uint16_t oce_rq_handler(void *arg);
1104
1105
1106 /* Sysctl functions */
1107 void oce_add_sysctls(POCE_SOFTC sc);
1108 void oce_refresh_queue_stats(POCE_SOFTC sc);
1109 int  oce_refresh_nic_stats(POCE_SOFTC sc);
1110 int  oce_stats_init(POCE_SOFTC sc);
1111 void oce_stats_free(POCE_SOFTC sc);
1112
1113 /* hw lro functions */
1114 int oce_mbox_nic_query_lro_capabilities(POCE_SOFTC sc, uint32_t *lro_rq_cnt, uint32_t *lro_flags);
1115 int oce_mbox_nic_set_iface_lro_config(POCE_SOFTC sc, int enable);
1116 int oce_mbox_create_rq_v2(struct oce_rq *rq);
1117
1118 /* Capabilities */
1119 #define OCE_MODCAP_RSS                  1
1120 #define OCE_MAX_RSP_HANDLED             64
1121 extern uint32_t oce_max_rsp_handled;    /* max responses */
1122 extern uint32_t oce_rq_buf_size;
1123
1124 #define OCE_MAC_LOOPBACK                0x0
1125 #define OCE_PHY_LOOPBACK                0x1
1126 #define OCE_ONE_PORT_EXT_LOOPBACK       0x2
1127 #define OCE_NO_LOOPBACK                 0xff
1128
1129 #undef IFM_40G_SR4
1130 #define IFM_40G_SR4                     28
1131
1132 #define atomic_inc_32(x)                atomic_add_32(x, 1)
1133 #define atomic_dec_32(x)                atomic_subtract_32(x, 1)
1134
1135 #define LE_64(x)                        htole64(x)
1136 #define LE_32(x)                        htole32(x)
1137 #define LE_16(x)                        htole16(x)
1138 #define HOST_64(x)                      le64toh(x)
1139 #define HOST_32(x)                      le32toh(x)
1140 #define HOST_16(x)                      le16toh(x)
1141 #define DW_SWAP(x, l)
1142 #define IS_ALIGNED(x,a)                 ((x % a) == 0)
1143 #define ADDR_HI(x)                      ((uint32_t)((uint64_t)(x) >> 32))
1144 #define ADDR_LO(x)                      ((uint32_t)((uint64_t)(x) & 0xffffffff));
1145
1146 #define IF_LRO_ENABLED(sc)  (((sc)->ifp->if_capenable & IFCAP_LRO) ? 1:0)
1147 #define IF_LSO_ENABLED(sc)  (((sc)->ifp->if_capenable & IFCAP_TSO4) ? 1:0)
1148 #define IF_CSUM_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_HWCSUM) ? 1:0)
1149
1150 #define OCE_LOG2(x)                     (oce_highbit(x))
1151 static inline uint32_t oce_highbit(uint32_t x)
1152 {
1153         int i;
1154         int c;
1155         int b;
1156
1157         c = 0;
1158         b = 0;
1159
1160         for (i = 0; i < 32; i++) {
1161                 if ((1 << i) & x) {
1162                         c++;
1163                         b = i;
1164                 }
1165         }
1166
1167         if (c == 1)
1168                 return b;
1169
1170         return 0;
1171 }
1172
1173 static inline int MPU_EP_SEMAPHORE(POCE_SOFTC sc)
1174 {
1175         if (IS_BE(sc))
1176                 return MPU_EP_SEMAPHORE_BE3;
1177         else if (IS_SH(sc))
1178                 return MPU_EP_SEMAPHORE_SH;
1179         else
1180                 return MPU_EP_SEMAPHORE_XE201;
1181 }
1182
1183 #define TRANSCEIVER_DATA_NUM_ELE 64
1184 #define TRANSCEIVER_DATA_SIZE 256
1185 #define TRANSCEIVER_A0_SIZE 128
1186 #define TRANSCEIVER_A2_SIZE 128
1187 #define PAGE_NUM_A0 0xa0
1188 #define PAGE_NUM_A2 0xa2
1189 #define IS_QNQ_OR_UMC(sc) ((sc->pvid && (sc->function_mode & FNM_UMC_MODE ))\
1190                      || (sc->qnqid && (sc->function_mode & FNM_FLEX10_MODE)))
1191 extern uint8_t sfp_vpd_dump_buffer[TRANSCEIVER_DATA_SIZE];
1192
1193 struct oce_rdma_info;
1194 extern struct oce_rdma_if *oce_rdma_if;
1195
1196
1197
1198 /* OS2BMC related */
1199
1200 #define DHCP_CLIENT_PORT        68
1201 #define DHCP_SERVER_PORT        67
1202 #define NET_BIOS_PORT1          137
1203 #define NET_BIOS_PORT2          138
1204 #define DHCPV6_RAS_PORT         547
1205
1206 #define BMC_FILT_BROADCAST_ARP                          ((uint32_t)(1))
1207 #define BMC_FILT_BROADCAST_DHCP_CLIENT                  ((uint32_t)(1 << 1))
1208 #define BMC_FILT_BROADCAST_DHCP_SERVER                  ((uint32_t)(1 << 2))
1209 #define BMC_FILT_BROADCAST_NET_BIOS                     ((uint32_t)(1 << 3))
1210 #define BMC_FILT_BROADCAST                              ((uint32_t)(1 << 4))
1211 #define BMC_FILT_MULTICAST_IPV6_NEIGH_ADVER             ((uint32_t)(1 << 5))
1212 #define BMC_FILT_MULTICAST_IPV6_RA                      ((uint32_t)(1 << 6))
1213 #define BMC_FILT_MULTICAST_IPV6_RAS                     ((uint32_t)(1 << 7))
1214 #define BMC_FILT_MULTICAST                              ((uint32_t)(1 << 8))
1215
1216 #define ND_ROUTER_ADVERT        134
1217 #define ND_NEIGHBOR_ADVERT      136
1218
1219 #define is_mc_allowed_on_bmc(sc, eh)       \
1220         (!is_multicast_filt_enabled(sc) && \
1221         ETHER_IS_MULTICAST(eh->ether_dhost) && \
1222         !ETHER_IS_BROADCAST(eh->ether_dhost))
1223
1224 #define is_bc_allowed_on_bmc(sc, eh)       \
1225         (!is_broadcast_filt_enabled(sc) && \
1226         ETHER_IS_BROADCAST(eh->ether_dhost))
1227
1228 #define is_arp_allowed_on_bmc(sc, et)     \
1229         (is_arp(et) && is_arp_filt_enabled(sc))
1230
1231 #define is_arp(et)     (et == ETHERTYPE_ARP)
1232
1233 #define is_arp_filt_enabled(sc)    \
1234         (sc->bmc_filt_mask & (BMC_FILT_BROADCAST_ARP))
1235
1236 #define is_dhcp_client_filt_enabled(sc)    \
1237         (sc->bmc_filt_mask & BMC_FILT_BROADCAST_DHCP_CLIENT)
1238
1239 #define is_dhcp_srvr_filt_enabled(sc)      \
1240         (sc->bmc_filt_mask & BMC_FILT_BROADCAST_DHCP_SERVER)
1241
1242 #define is_nbios_filt_enabled(sc)  \
1243         (sc->bmc_filt_mask & BMC_FILT_BROADCAST_NET_BIOS)
1244
1245 #define is_ipv6_na_filt_enabled(sc)        \
1246         (sc->bmc_filt_mask &       \
1247         BMC_FILT_MULTICAST_IPV6_NEIGH_ADVER)
1248
1249 #define is_ipv6_ra_filt_enabled(sc)        \
1250         (sc->bmc_filt_mask & BMC_FILT_MULTICAST_IPV6_RA)
1251
1252 #define is_ipv6_ras_filt_enabled(sc)       \
1253         (sc->bmc_filt_mask & BMC_FILT_MULTICAST_IPV6_RAS)
1254
1255 #define is_broadcast_filt_enabled(sc)      \
1256         (sc->bmc_filt_mask & BMC_FILT_BROADCAST)
1257
1258 #define is_multicast_filt_enabled(sc)      \
1259         (sc->bmc_filt_mask & BMC_FILT_MULTICAST)
1260
1261 #define is_os2bmc_enabled(sc) (sc->flags & OCE_FLAGS_OS2BMC)
1262
1263 #define LRO_FLAGS_HASH_MODE 0x00000001
1264 #define LRO_FLAGS_RSS_MODE 0x00000004
1265 #define LRO_FLAGS_CLSC_IPV4 0x00000010
1266 #define LRO_FLAGS_CLSC_IPV6 0x00000020
1267 #define NIC_RQ_FLAGS_RSS 0x0001
1268 #define NIC_RQ_FLAGS_LRO 0x0020
1269