2 * Copyright (C) 2013 Emulex
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of the Emulex Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
31 * Contact Information:
32 * freebsd-drivers@emulex.com
36 * Costa Mesa, CA 92626
41 #include <sys/param.h>
42 #include <sys/endian.h>
43 #include <sys/eventhandler.h>
44 #include <sys/malloc.h>
45 #include <sys/module.h>
46 #include <sys/kernel.h>
50 #include <sys/socket.h>
51 #include <sys/sockio.h>
52 #include <sys/sockopt.h>
53 #include <sys/queue.h>
54 #include <sys/taskqueue.h>
56 #include <sys/mutex.h>
57 #include <sys/sysctl.h>
58 #include <sys/random.h>
59 #include <sys/firmware.h>
60 #include <sys/systm.h>
63 #include <dev/pci/pcireg.h>
64 #include <dev/pci/pcivar.h>
67 #include <net/ethernet.h>
69 #include <net/if_var.h>
70 #include <net/if_types.h>
71 #include <net/if_media.h>
72 #include <net/if_vlan_var.h>
73 #include <net/if_dl.h>
75 #include <netinet/in.h>
76 #include <netinet/in_systm.h>
77 #include <netinet/in_var.h>
78 #include <netinet/if_ether.h>
79 #include <netinet/ip.h>
80 #include <netinet/ip6.h>
81 #include <netinet6/in6_var.h>
82 #include <netinet6/ip6_mroute.h>
84 #include <netinet/udp.h>
85 #include <netinet/tcp.h>
86 #include <netinet/sctp.h>
87 #include <netinet/tcp_lro.h>
88 #include <netinet/icmp6.h>
90 #include <machine/bus.h>
94 /* OCE device driver module component revision informaiton */
95 #define COMPONENT_REVISION "11.0.50.0"
97 /* OCE devices supported by this driver */
98 #define PCI_VENDOR_EMULEX 0x10df /* Emulex */
99 #define PCI_VENDOR_SERVERENGINES 0x19a2 /* ServerEngines (BE) */
100 #define PCI_PRODUCT_BE2 0x0700 /* BE2 network adapter */
101 #define PCI_PRODUCT_BE3 0x0710 /* BE3 network adapter */
102 #define PCI_PRODUCT_XE201 0xe220 /* XE201 network adapter */
103 #define PCI_PRODUCT_XE201_VF 0xe228 /* XE201 with VF in Lancer */
104 #define PCI_PRODUCT_SH 0x0720 /* Skyhawk network adapter */
106 #define IS_BE(sc) (((sc->flags & OCE_FLAGS_BE3) | \
107 (sc->flags & OCE_FLAGS_BE2))? 1:0)
108 #define IS_BE3(sc) (sc->flags & OCE_FLAGS_BE3)
109 #define IS_BE2(sc) (sc->flags & OCE_FLAGS_BE2)
110 #define IS_XE201(sc) ((sc->flags & OCE_FLAGS_XE201) ? 1:0)
111 #define HAS_A0_CHIP(sc) ((sc->flags & OCE_FLAGS_HAS_A0_CHIP) ? 1:0)
112 #define IS_SH(sc) ((sc->flags & OCE_FLAGS_SH) ? 1 : 0)
114 #define is_be_mode_mc(sc) ((sc->function_mode & FNM_FLEX10_MODE) || \
115 (sc->function_mode & FNM_UMC_MODE) || \
116 (sc->function_mode & FNM_VNIC_MODE))
117 #define OCE_FUNCTION_CAPS_SUPER_NIC 0x40
118 #define IS_PROFILE_SUPER_NIC(sc) (sc->function_caps & OCE_FUNCTION_CAPS_SUPER_NIC)
121 /* proportion Service Level Interface queues */
122 #define OCE_MAX_UNITS 2
123 #define OCE_MAX_PPORT OCE_MAX_UNITS
124 #define OCE_MAX_VPORT OCE_MAX_UNITS
126 extern int mp_ncpus; /* system's total active cpu cores */
127 #define OCE_NCPUS mp_ncpus
129 /* This should be powers of 2. Like 2,4,8 & 16 */
130 #define OCE_MAX_RSS 8
131 #define OCE_LEGACY_MODE_RSS 4 /* For BE3 Legacy mode*/
132 #define is_rss_enabled(sc) ((sc->function_caps & FNC_RSS) && !is_be_mode_mc(sc))
137 #define OCE_MAX_RQ OCE_MAX_RSS + 1 /* one default queue */
140 #define OCE_MAX_EQ 32
141 #define OCE_MAX_CQ OCE_MAX_RQ + OCE_MAX_WQ + 1 /* one MCC queue */
142 #define OCE_MAX_CQ_EQ 8 /* Max CQ that can attached to an EQ */
144 #define OCE_DEFAULT_WQ_EQD 16
145 #define OCE_MAX_PACKET_Q 16
146 #define OCE_LSO_MAX_SIZE (64 * 1024)
147 #define LONG_TIMEOUT 30
148 #define OCE_MAX_JUMBO_FRAME_SIZE 9018
149 #define OCE_MAX_MTU (OCE_MAX_JUMBO_FRAME_SIZE - \
150 ETHER_VLAN_ENCAP_LEN - \
153 #define OCE_RDMA_VECTORS 2
155 #define OCE_MAX_TX_ELEMENTS 29
156 #define OCE_MAX_TX_DESC 1024
157 #define OCE_MAX_TX_SIZE 65535
158 #define OCE_MAX_TSO_SIZE (65535 - ETHER_HDR_LEN)
159 #define OCE_MAX_RX_SIZE 4096
160 #define OCE_MAX_RQ_POSTS 255
161 #define OCE_HWLRO_MAX_RQ_POSTS 64
162 #define OCE_DEFAULT_PROMISCUOUS 0
165 #define RSS_ENABLE_IPV4 0x1
166 #define RSS_ENABLE_TCP_IPV4 0x2
167 #define RSS_ENABLE_IPV6 0x4
168 #define RSS_ENABLE_TCP_IPV6 0x8
170 #define INDIRECTION_TABLE_ENTRIES 128
172 /* flow control definitions */
173 #define OCE_FC_NONE 0x00000000
174 #define OCE_FC_TX 0x00000001
175 #define OCE_FC_RX 0x00000002
176 #define OCE_DEFAULT_FLOW_CONTROL (OCE_FC_TX | OCE_FC_RX)
179 /* Interface capabilities to give device when creating interface */
180 #define OCE_CAPAB_FLAGS (MBX_RX_IFACE_FLAGS_BROADCAST | \
181 MBX_RX_IFACE_FLAGS_UNTAGGED | \
182 MBX_RX_IFACE_FLAGS_PROMISCUOUS | \
183 MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS | \
184 MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS | \
185 MBX_RX_IFACE_FLAGS_RSS | \
186 MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR)
188 /* Interface capabilities to enable by default (others set dynamically) */
189 #define OCE_CAPAB_ENABLE (MBX_RX_IFACE_FLAGS_BROADCAST | \
190 MBX_RX_IFACE_FLAGS_UNTAGGED | \
191 MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR)
193 #define OCE_IF_HWASSIST (CSUM_IP | CSUM_TCP | CSUM_UDP)
194 #define OCE_IF_CAPABILITIES (IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \
195 IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | \
196 IFCAP_JUMBO_MTU | IFCAP_VLAN_MTU)
197 #define OCE_IF_HWASSIST_NONE 0
198 #define OCE_IF_CAPABILITIES_NONE 0
201 #define ETH_ADDR_LEN 6
202 #define MAX_VLANFILTER_SIZE 64
203 #define MAX_VLANS 4096
205 #define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16))
206 #define BSWAP_8(x) ((x) & 0xff)
207 #define BSWAP_16(x) ((BSWAP_8(x) << 8) | BSWAP_8((x) >> 8))
208 #define BSWAP_32(x) ((BSWAP_16(x) << 16) | \
210 #define BSWAP_64(x) ((BSWAP_32(x) << 32) | \
213 #define for_all_wq_queues(sc, wq, i) \
214 for (i = 0, wq = sc->wq[0]; i < sc->nwqs; i++, wq = sc->wq[i])
215 #define for_all_rq_queues(sc, rq, i) \
216 for (i = 0, rq = sc->rq[0]; i < sc->nrqs; i++, rq = sc->rq[i])
217 #define for_all_rss_queues(sc, rq, i) \
218 for (i = 0, rq = sc->rq[i + 1]; i < (sc->nrqs - 1); \
219 i++, rq = sc->rq[i + 1])
220 #define for_all_evnt_queues(sc, eq, i) \
221 for (i = 0, eq = sc->eq[0]; i < sc->neqs; i++, eq = sc->eq[i])
222 #define for_all_cq_queues(sc, cq, i) \
223 for (i = 0, cq = sc->cq[0]; i < sc->ncqs; i++, cq = sc->cq[i])
227 #define IOCTL_COOKIE "SERVERENGINES CORP"
228 #define MAX_FLASH_COMP 32
230 #define IMG_ISCSI 160
231 #define IMG_REDBOOT 224
233 #define IMG_PXEBIOS 32
234 #define IMG_FCOEBIOS 33
235 #define IMG_ISCSI_BAK 176
237 #define IMG_FCOE_BAK 178
240 #define FLASHROM_OPER_FLASH 1
241 #define FLASHROM_OPER_SAVE 2
242 #define FLASHROM_OPER_REPORT 4
243 #define FLASHROM_OPER_FLASH_PHY 9
244 #define FLASHROM_OPER_SAVE_PHY 10
248 PHY_TYPE_CX4_10GB = 0,
251 PHY_TYPE_SFP_PLUS_10GB,
258 PHY_TYPE_DISABLED = 255
262 * @brief Define and hold all necessary info for a single interrupt
264 #define OCE_MAX_MSI 32 /* Message Signaled Interrupts */
265 #define OCE_MAX_MSIX 2048 /* PCI Express MSI Interrrupts */
267 typedef struct oce_intr_info {
268 void *tag; /* cookie returned by bus_setup_intr */
269 struct resource *intr_res; /* PCI resource container */
270 int irq_rr; /* resource id for the interrupt */
271 struct oce_softc *sc; /* pointer to the parent soft c */
272 struct oce_eq *eq; /* pointer to the connected EQ */
273 struct taskqueue *tq; /* Associated task queue */
274 struct task task; /* task queue task */
275 char task_name[32]; /* task name */
276 int vector; /* interrupt vector number */
277 } OCE_INTR_INFO, *POCE_INTR_INFO;
281 #define GET_Q_NEXT(_START, _STEP, _END) \
282 (((_START) + (_STEP)) < (_END) ? ((_START) + (_STEP)) \
283 : (((_START) + (_STEP)) - (_END)))
285 #define DBUF_PA(obj) ((obj)->addr)
286 #define DBUF_VA(obj) ((obj)->ptr)
287 #define DBUF_TAG(obj) ((obj)->tag)
288 #define DBUF_MAP(obj) ((obj)->map)
289 #define DBUF_SYNC(obj, flags) \
290 (void) bus_dmamap_sync(DBUF_TAG(obj), DBUF_MAP(obj), (flags))
292 #define RING_NUM_PENDING(ring) ring->num_used
293 #define RING_FULL(ring) (ring->num_used == ring->num_items)
294 #define RING_EMPTY(ring) (ring->num_used == 0)
295 #define RING_NUM_FREE(ring) \
296 (uint32_t)(ring->num_items - ring->num_used)
297 #define RING_GET(ring, n) \
298 ring->cidx = GET_Q_NEXT(ring->cidx, n, ring->num_items)
299 #define RING_PUT(ring, n) \
300 ring->pidx = GET_Q_NEXT(ring->pidx, n, ring->num_items)
302 #define RING_GET_CONSUMER_ITEM_VA(ring, type) \
303 (void*)((type *)DBUF_VA(&ring->dma) + ring->cidx)
304 #define RING_GET_CONSUMER_ITEM_PA(ring, type) \
305 (uint64_t)(((type *)DBUF_PA(ring->dbuf)) + ring->cidx)
306 #define RING_GET_PRODUCER_ITEM_VA(ring, type) \
307 (void *)(((type *)DBUF_VA(&ring->dma)) + ring->pidx)
308 #define RING_GET_PRODUCER_ITEM_PA(ring, type) \
309 (uint64_t)(((type *)DBUF_PA(ring->dbuf)) + ring->pidx)
311 #define OCE_DMAPTR(o, c) ((c *)(o)->ptr)
313 struct oce_packet_desc {
320 typedef struct oce_dma_mem {
325 } OCE_DMA_MEM, *POCE_DMA_MEM;
327 typedef struct oce_ring_buffer_s {
328 uint16_t cidx; /* Get ptr */
329 uint16_t pidx; /* Put Ptr */
337 #define OCE_UNICAST_PACKET 0
338 #define OCE_MULTICAST_PACKET 1
339 #define OCE_BROADCAST_PACKET 2
340 #define OCE_RSVD_PACKET 3
342 struct oce_rx_stats {
343 /* Total Receive Stats*/
347 uint32_t t_rx_mcast_pkts;
348 uint32_t t_rx_ucast_pkts;
349 uint32_t t_rxcp_errs;
351 struct oce_tx_stats {
352 /*Total Transmit Stats */
359 uint32_t t_ipv6_ext_hdr_tx_drop;
362 struct oce_be_stats {
363 uint8_t be_on_die_temperature;
364 uint32_t be_tx_events;
365 uint32_t eth_red_drops;
366 uint32_t rx_drops_no_pbuf;
367 uint32_t rx_drops_no_txpb;
368 uint32_t rx_drops_no_erx_descr;
369 uint32_t rx_drops_no_tpre_descr;
370 uint32_t rx_drops_too_many_frags;
371 uint32_t rx_drops_invalid_ring;
372 uint32_t forwarded_packets;
373 uint32_t rx_drops_mtu;
374 uint32_t rx_crc_errors;
375 uint32_t rx_alignment_symbol_errors;
376 uint32_t rx_pause_frames;
377 uint32_t rx_priority_pause_frames;
378 uint32_t rx_control_frames;
379 uint32_t rx_in_range_errors;
380 uint32_t rx_out_range_errors;
381 uint32_t rx_frame_too_long;
382 uint32_t rx_address_match_errors;
383 uint32_t rx_dropped_too_small;
384 uint32_t rx_dropped_too_short;
385 uint32_t rx_dropped_header_too_small;
386 uint32_t rx_dropped_tcp_length;
387 uint32_t rx_dropped_runt;
388 uint32_t rx_ip_checksum_errs;
389 uint32_t rx_tcp_checksum_errs;
390 uint32_t rx_udp_checksum_errs;
391 uint32_t rx_switched_unicast_packets;
392 uint32_t rx_switched_multicast_packets;
393 uint32_t rx_switched_broadcast_packets;
394 uint32_t tx_pauseframes;
395 uint32_t tx_priority_pauseframes;
396 uint32_t tx_controlframes;
397 uint32_t rxpp_fifo_overflow_drop;
398 uint32_t rx_input_fifo_overflow_drop;
399 uint32_t pmem_fifo_overflow_drop;
400 uint32_t jabber_events;
403 struct oce_xe201_stats {
405 uint64_t tx_unicast_pkts;
406 uint64_t tx_multicast_pkts;
407 uint64_t tx_broadcast_pkts;
409 uint64_t tx_unicast_bytes;
410 uint64_t tx_multicast_bytes;
411 uint64_t tx_broadcast_bytes;
412 uint64_t tx_discards;
414 uint64_t tx_pause_frames;
415 uint64_t tx_pause_on_frames;
416 uint64_t tx_pause_off_frames;
417 uint64_t tx_internal_mac_errors;
418 uint64_t tx_control_frames;
419 uint64_t tx_pkts_64_bytes;
420 uint64_t tx_pkts_65_to_127_bytes;
421 uint64_t tx_pkts_128_to_255_bytes;
422 uint64_t tx_pkts_256_to_511_bytes;
423 uint64_t tx_pkts_512_to_1023_bytes;
424 uint64_t tx_pkts_1024_to_1518_bytes;
425 uint64_t tx_pkts_1519_to_2047_bytes;
426 uint64_t tx_pkts_2048_to_4095_bytes;
427 uint64_t tx_pkts_4096_to_8191_bytes;
428 uint64_t tx_pkts_8192_to_9216_bytes;
429 uint64_t tx_lso_pkts;
431 uint64_t rx_unicast_pkts;
432 uint64_t rx_multicast_pkts;
433 uint64_t rx_broadcast_pkts;
435 uint64_t rx_unicast_bytes;
436 uint64_t rx_multicast_bytes;
437 uint64_t rx_broadcast_bytes;
438 uint32_t rx_unknown_protos;
439 uint64_t rx_discards;
441 uint64_t rx_crc_errors;
442 uint64_t rx_alignment_errors;
443 uint64_t rx_symbol_errors;
444 uint64_t rx_pause_frames;
445 uint64_t rx_pause_on_frames;
446 uint64_t rx_pause_off_frames;
447 uint64_t rx_frames_too_long;
448 uint64_t rx_internal_mac_errors;
449 uint32_t rx_undersize_pkts;
450 uint32_t rx_oversize_pkts;
451 uint32_t rx_fragment_pkts;
453 uint64_t rx_control_frames;
454 uint64_t rx_control_frames_unknown_opcode;
455 uint32_t rx_in_range_errors;
456 uint32_t rx_out_of_range_errors;
457 uint32_t rx_address_match_errors;
458 uint32_t rx_vlan_mismatch_errors;
459 uint32_t rx_dropped_too_small;
460 uint32_t rx_dropped_too_short;
461 uint32_t rx_dropped_header_too_small;
462 uint32_t rx_dropped_invalid_tcp_length;
463 uint32_t rx_dropped_runt;
464 uint32_t rx_ip_checksum_errors;
465 uint32_t rx_tcp_checksum_errors;
466 uint32_t rx_udp_checksum_errors;
467 uint32_t rx_non_rss_pkts;
468 uint64_t rx_ipv4_pkts;
469 uint64_t rx_ipv6_pkts;
470 uint64_t rx_ipv4_bytes;
471 uint64_t rx_ipv6_bytes;
472 uint64_t rx_nic_pkts;
473 uint64_t rx_tcp_pkts;
474 uint64_t rx_iscsi_pkts;
475 uint64_t rx_management_pkts;
476 uint64_t rx_switched_unicast_pkts;
477 uint64_t rx_switched_multicast_pkts;
478 uint64_t rx_switched_broadcast_pkts;
479 uint64_t num_forwards;
480 uint32_t rx_fifo_overflow;
481 uint32_t rx_input_fifo_overflow;
482 uint64_t rx_drops_too_many_frags;
483 uint32_t rx_drops_invalid_queue;
484 uint64_t rx_drops_mtu;
485 uint64_t rx_pkts_64_bytes;
486 uint64_t rx_pkts_65_to_127_bytes;
487 uint64_t rx_pkts_128_to_255_bytes;
488 uint64_t rx_pkts_256_to_511_bytes;
489 uint64_t rx_pkts_512_to_1023_bytes;
490 uint64_t rx_pkts_1024_to_1518_bytes;
491 uint64_t rx_pkts_1519_to_2047_bytes;
492 uint64_t rx_pkts_2048_to_4095_bytes;
493 uint64_t rx_pkts_4096_to_8191_bytes;
494 uint64_t rx_pkts_8192_to_9216_bytes;
497 struct oce_drv_stats {
498 struct oce_rx_stats rx;
499 struct oce_tx_stats tx;
501 struct oce_be_stats be;
502 struct oce_xe201_stats xe201;
506 #define INTR_RATE_HWM 15000
507 #define INTR_RATE_LWM 10000
509 #define OCE_MAX_EQD 128u
510 #define OCE_MIN_EQD 0u
515 uint32_t delay_multiplier;
518 struct oce_aic_obj { /* Adaptive interrupt coalescing (AIC) info */
520 uint32_t min_eqd; /* in usecs */
521 uint32_t max_eqd; /* in usecs */
522 uint32_t cur_eqd; /* in usecs */
523 uint32_t et_eqd; /* configured value when aic is off */
525 uint64_t prev_rxpkts;
526 uint64_t prev_txreqs;
529 #define MAX_LOCK_DESC_LEN 32
532 char name[MAX_LOCK_DESC_LEN+1];
534 #define OCE_LOCK struct oce_lock
536 #define LOCK_CREATE(lock, desc) { \
537 strncpy((lock)->name, (desc), MAX_LOCK_DESC_LEN); \
538 (lock)->name[MAX_LOCK_DESC_LEN] = '\0'; \
539 mtx_init(&(lock)->mutex, (lock)->name, NULL, MTX_DEF); \
541 #define LOCK_DESTROY(lock) \
542 if (mtx_initialized(&(lock)->mutex))\
543 mtx_destroy(&(lock)->mutex)
544 #define TRY_LOCK(lock) mtx_trylock(&(lock)->mutex)
545 #define LOCK(lock) mtx_lock(&(lock)->mutex)
546 #define LOCKED(lock) mtx_owned(&(lock)->mutex)
547 #define UNLOCK(lock) mtx_unlock(&(lock)->mutex)
549 #define DEFAULT_MQ_MBOX_TIMEOUT (5 * 1000 * 1000)
550 #define MBX_READY_TIMEOUT (1 * 1000 * 1000)
551 #define DEFAULT_DRAIN_TIME 200
552 #define MBX_TIMEOUT_SEC 5
553 #define STAT_TIMEOUT 2000000
555 /* size of the packet descriptor array in a transmit queue */
556 #define OCE_TX_RING_SIZE 2048
557 #define OCE_RX_RING_SIZE 1024
558 #define OCE_WQ_PACKET_ARRAY_SIZE (OCE_TX_RING_SIZE/2)
559 #define OCE_RQ_PACKET_ARRAY_SIZE (OCE_RX_RING_SIZE)
585 typedef enum qstate_e {
592 enum eqe_size item_size;
593 uint32_t q_vector_num;
604 oce_ring_buffer_t *ring;
607 struct oce_cq *cq[OCE_MAX_CQ_EQ];
609 struct eq_config eq_cfg;
624 boolean_t is_eventable;
625 boolean_t sol_eventable;
627 uint16_t dma_coalescing;
630 typedef uint16_t(*cq_handler_t) (void *arg1);
636 cq_handler_t cq_handler;
638 oce_ring_buffer_t *ring;
640 struct cq_config cq_cfg;
654 oce_ring_buffer_t *ring;
657 struct oce_cq *async_cq;
660 struct mq_config cfg;
665 void (*cb) (void *ctx);
676 uint32_t eqd; /* interrupt delay */
681 struct oce_tx_queue_stats {
685 uint32_t tx_stops; /* number of times TX Q was stopped */
689 uint32_t ipv6_ext_hdr_tx_drop;
694 OCE_LOCK tx_compl_lock;
696 oce_ring_buffer_t *ring;
699 struct oce_packet_desc pckts[OCE_WQ_PACKET_ARRAY_SIZE];
700 uint32_t pkt_desc_tail;
701 uint32_t pkt_desc_head;
709 struct wq_config cfg;
711 struct oce_tx_queue_stats tx_stats;
722 uint32_t is_rss_queue;
727 struct oce_rx_queue_stats {
728 uint32_t rx_post_fail;
729 uint32_t rx_ucast_pkts;
732 uint64_t rx_bytes_prev;
735 uint32_t rx_mcast_pkts;
738 uint32_t prev_rx_frags;
740 uint32_t rx_drops_no_frags; /* HW has no fetched frags */
745 struct rq_config cfg;
750 oce_ring_buffer_t *ring;
754 struct oce_packet_desc pckts[OCE_RQ_PACKET_ARRAY_SIZE];
763 struct oce_rx_queue_stats rx_stats;
767 struct nic_hwlro_cqe_part1 *cqe_firstpart;
772 uint8_t phys_port_speed;
773 uint8_t logical_link_status;
774 uint16_t qos_link_speed;
779 #define OCE_FLAGS_PCIX 0x00000001
780 #define OCE_FLAGS_PCIE 0x00000002
781 #define OCE_FLAGS_MSI_CAPABLE 0x00000004
782 #define OCE_FLAGS_MSIX_CAPABLE 0x00000008
783 #define OCE_FLAGS_USING_MSI 0x00000010
784 #define OCE_FLAGS_USING_MSIX 0x00000020
785 #define OCE_FLAGS_FUNCRESET_RQD 0x00000040
786 #define OCE_FLAGS_VIRTUAL_PORT 0x00000080
787 #define OCE_FLAGS_MBOX_ENDIAN_RQD 0x00000100
788 #define OCE_FLAGS_BE3 0x00000200
789 #define OCE_FLAGS_XE201 0x00000400
790 #define OCE_FLAGS_BE2 0x00000800
791 #define OCE_FLAGS_SH 0x00001000
792 #define OCE_FLAGS_OS2BMC 0x00002000
794 #define OCE_DEV_BE2_CFG_BAR 1
795 #define OCE_DEV_CFG_BAR 0
796 #define OCE_PCI_CSR_BAR 2
797 #define OCE_PCI_DB_BAR 4
799 typedef struct oce_softc {
805 uint32_t pcie_link_speed;
806 uint32_t pcie_link_width;
808 uint8_t fn; /* PCI function number */
810 struct resource *devcfg_res;
811 bus_space_tag_t devcfg_btag;
812 bus_space_handle_t devcfg_bhandle;
813 void *devcfg_vhandle;
815 struct resource *csr_res;
816 bus_space_tag_t csr_btag;
817 bus_space_handle_t csr_bhandle;
820 struct resource *db_res;
821 bus_space_tag_t db_btag;
822 bus_space_handle_t db_bhandle;
825 OCE_INTR_INFO intrs[OCE_MAX_EQ];
831 struct ifmedia media;
835 uint32_t qos_link_speed;
837 uint32_t enable_hwlro;
840 struct mac_address_format macaddr;
845 uint32_t config_number;
846 uint32_t asic_revision;
848 uint32_t function_mode;
849 uint32_t function_caps;
850 uint32_t max_tx_rings;
851 uint32_t max_rx_rings;
853 struct oce_wq *wq[OCE_MAX_WQ]; /* TX work queues */
854 struct oce_rq *rq[OCE_MAX_RQ]; /* RX work queues */
855 struct oce_cq *cq[OCE_MAX_CQ]; /* Completion queues */
856 struct oce_eq *eq[OCE_MAX_EQ]; /* Event queues */
857 struct oce_mq *mq; /* Mailbox queue */
865 uint32_t tx_ring_size;
866 uint32_t rx_ring_size;
867 uint32_t rq_frag_size;
869 uint32_t if_id; /* interface ID */
870 uint32_t nifs; /* number of adapter interfaces, 0 or 1 */
871 uint32_t pmac_id; /* PMAC id */
873 uint32_t if_cap_flags;
875 uint32_t flow_control;
878 struct oce_aic_obj aic_obj[OCE_MAX_EQ];
880 /*Vlan Filtering related */
881 eventhandler_tag vlan_attach;
882 eventhandler_tag vlan_detach;
883 uint16_t vlans_added;
884 uint8_t vlan_tag[MAX_VLANS];
886 OCE_DMA_MEM stats_mem;
887 struct oce_drv_stats oce_stats_info;
888 struct callout timer;
891 uint16_t qnq_debug_event;
895 uint32_t bmc_filt_mask;
899 struct oce_softc *next;
901 } OCE_SOFTC, *POCE_SOFTC;
903 #define OCE_RDMA_FLAG_SUPPORTED 0x00000001
906 /**************************************************
907 * BUS memory read/write macros
908 * BE3: accesses three BAR spaces (CFG, CSR, DB)
909 * Lancer: accesses one BAR space (CFG)
910 **************************************************/
911 #define OCE_READ_CSR_MPU(sc, space, o) \
912 ((IS_BE(sc)) ? (bus_space_read_4((sc)->space##_btag, \
913 (sc)->space##_bhandle,o)) \
914 : (bus_space_read_4((sc)->devcfg_btag, \
915 (sc)->devcfg_bhandle,o)))
916 #define OCE_READ_REG32(sc, space, o) \
917 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_4((sc)->space##_btag, \
918 (sc)->space##_bhandle,o)) \
919 : (bus_space_read_4((sc)->devcfg_btag, \
920 (sc)->devcfg_bhandle,o)))
921 #define OCE_READ_REG16(sc, space, o) \
922 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_2((sc)->space##_btag, \
923 (sc)->space##_bhandle,o)) \
924 : (bus_space_read_2((sc)->devcfg_btag, \
925 (sc)->devcfg_bhandle,o)))
926 #define OCE_READ_REG8(sc, space, o) \
927 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_1((sc)->space##_btag, \
928 (sc)->space##_bhandle,o)) \
929 : (bus_space_read_1((sc)->devcfg_btag, \
930 (sc)->devcfg_bhandle,o)))
932 #define OCE_WRITE_CSR_MPU(sc, space, o, v) \
933 ((IS_BE(sc)) ? (bus_space_write_4((sc)->space##_btag, \
934 (sc)->space##_bhandle,o,v)) \
935 : (bus_space_write_4((sc)->devcfg_btag, \
936 (sc)->devcfg_bhandle,o,v)))
937 #define OCE_WRITE_REG32(sc, space, o, v) \
938 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_4((sc)->space##_btag, \
939 (sc)->space##_bhandle,o,v)) \
940 : (bus_space_write_4((sc)->devcfg_btag, \
941 (sc)->devcfg_bhandle,o,v)))
942 #define OCE_WRITE_REG16(sc, space, o, v) \
943 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_2((sc)->space##_btag, \
944 (sc)->space##_bhandle,o,v)) \
945 : (bus_space_write_2((sc)->devcfg_btag, \
946 (sc)->devcfg_bhandle,o,v)))
947 #define OCE_WRITE_REG8(sc, space, o, v) \
948 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_1((sc)->space##_btag, \
949 (sc)->space##_bhandle,o,v)) \
950 : (bus_space_write_1((sc)->devcfg_btag, \
951 (sc)->devcfg_bhandle,o,v)))
953 void oce_rx_flush_lro(struct oce_rq *rq);
954 /***********************************************************
955 * DMA memory functions
956 ***********************************************************/
957 #define oce_dma_sync(d, f) bus_dmamap_sync((d)->tag, (d)->map, f)
958 int oce_dma_alloc(POCE_SOFTC sc, bus_size_t size, POCE_DMA_MEM dma, int flags);
959 void oce_dma_free(POCE_SOFTC sc, POCE_DMA_MEM dma);
960 void oce_dma_map_addr(void *arg, bus_dma_segment_t * segs, int nseg, int error);
961 void oce_destroy_ring_buffer(POCE_SOFTC sc, oce_ring_buffer_t *ring);
962 oce_ring_buffer_t *oce_create_ring_buffer(POCE_SOFTC sc,
963 uint32_t q_len, uint32_t num_entries);
964 /************************************************************
965 * oce_hw_xxx functions
966 ************************************************************/
967 int oce_clear_rx_buf(struct oce_rq *rq);
968 int oce_hw_pci_alloc(POCE_SOFTC sc);
969 int oce_hw_init(POCE_SOFTC sc);
970 int oce_hw_start(POCE_SOFTC sc);
971 int oce_create_nw_interface(POCE_SOFTC sc);
972 int oce_pci_soft_reset(POCE_SOFTC sc);
973 int oce_hw_update_multicast(POCE_SOFTC sc);
974 void oce_delete_nw_interface(POCE_SOFTC sc);
975 void oce_hw_shutdown(POCE_SOFTC sc);
976 void oce_hw_intr_enable(POCE_SOFTC sc);
977 void oce_hw_intr_disable(POCE_SOFTC sc);
978 void oce_hw_pci_free(POCE_SOFTC sc);
980 /***********************************************************
981 * oce_queue_xxx functions
982 ***********************************************************/
983 int oce_queue_init_all(POCE_SOFTC sc);
984 int oce_start_rq(struct oce_rq *rq);
985 int oce_start_wq(struct oce_wq *wq);
986 int oce_start_mq(struct oce_mq *mq);
987 int oce_start_rx(POCE_SOFTC sc);
988 void oce_arm_eq(POCE_SOFTC sc,
989 int16_t qid, int npopped, uint32_t rearm, uint32_t clearint);
990 void oce_queue_release_all(POCE_SOFTC sc);
991 void oce_arm_cq(POCE_SOFTC sc, int16_t qid, int npopped, uint32_t rearm);
992 void oce_drain_eq(struct oce_eq *eq);
993 void oce_drain_mq_cq(void *arg);
994 void oce_drain_rq_cq(struct oce_rq *rq);
995 void oce_drain_wq_cq(struct oce_wq *wq);
997 uint32_t oce_page_list(oce_ring_buffer_t *ring, struct phys_addr *pa_list);
999 /***********************************************************
1001 ***********************************************************/
1002 void oce_stop_rx(POCE_SOFTC sc);
1003 void oce_discard_rx_comp(struct oce_rq *rq, int num_frags);
1004 void oce_rx_cq_clean(struct oce_rq *rq);
1005 void oce_rx_cq_clean_hwlro(struct oce_rq *rq);
1006 void oce_intr_free(POCE_SOFTC sc);
1007 void oce_free_posted_rxbuf(struct oce_rq *rq);
1008 #if defined(INET6) || defined(INET)
1009 void oce_free_lro(POCE_SOFTC sc);
1013 /************************************************************
1015 ************************************************************/
1016 int oce_fw_clean(POCE_SOFTC sc);
1017 int oce_reset_fun(POCE_SOFTC sc);
1018 int oce_mbox_init(POCE_SOFTC sc);
1019 int oce_mbox_dispatch(POCE_SOFTC sc, uint32_t tmo_sec);
1020 int oce_get_fw_version(POCE_SOFTC sc);
1021 int oce_first_mcc_cmd(POCE_SOFTC sc);
1023 int oce_read_mac_addr(POCE_SOFTC sc, uint32_t if_id, uint8_t perm,
1024 uint8_t type, struct mac_address_format *mac);
1025 int oce_get_fw_config(POCE_SOFTC sc);
1026 int oce_if_create(POCE_SOFTC sc, uint32_t cap_flags, uint32_t en_flags,
1027 uint16_t vlan_tag, uint8_t *mac_addr, uint32_t *if_id);
1028 int oce_if_del(POCE_SOFTC sc, uint32_t if_id);
1029 int oce_config_vlan(POCE_SOFTC sc, uint32_t if_id,
1030 struct normal_vlan *vtag_arr, uint8_t vtag_cnt,
1031 uint32_t untagged, uint32_t enable_promisc);
1032 int oce_set_flow_control(POCE_SOFTC sc, uint32_t flow_control);
1033 int oce_config_nic_rss(POCE_SOFTC sc, uint32_t if_id, uint16_t enable_rss);
1034 int oce_rxf_set_promiscuous(POCE_SOFTC sc, uint8_t enable);
1035 int oce_set_common_iface_rx_filter(POCE_SOFTC sc, POCE_DMA_MEM sgl);
1036 int oce_get_link_status(POCE_SOFTC sc, struct link_status *link);
1037 int oce_mbox_get_nic_stats_v0(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem);
1038 int oce_mbox_get_nic_stats_v1(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem);
1039 int oce_mbox_get_nic_stats_v2(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem);
1040 int oce_mbox_get_pport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1041 uint32_t reset_stats);
1042 int oce_mbox_get_vport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1043 uint32_t req_size, uint32_t reset_stats);
1044 int oce_update_multicast(POCE_SOFTC sc, POCE_DMA_MEM pdma_mem);
1045 int oce_pass_through_mbox(POCE_SOFTC sc, POCE_DMA_MEM dma_mem, uint32_t req_size);
1046 int oce_mbox_macaddr_del(POCE_SOFTC sc, uint32_t if_id, uint32_t pmac_id);
1047 int oce_mbox_macaddr_add(POCE_SOFTC sc, uint8_t *mac_addr,
1048 uint32_t if_id, uint32_t *pmac_id);
1049 int oce_mbox_cmd_test_loopback(POCE_SOFTC sc, uint32_t port_num,
1050 uint32_t loopback_type, uint32_t pkt_size, uint32_t num_pkts,
1053 int oce_mbox_cmd_set_loopback(POCE_SOFTC sc, uint8_t port_num,
1054 uint8_t loopback_type, uint8_t enable);
1056 int oce_mbox_check_native_mode(POCE_SOFTC sc);
1057 int oce_mbox_post(POCE_SOFTC sc,
1058 struct oce_mbx *mbx, struct oce_mbx_ctx *mbxctx);
1059 int oce_mbox_write_flashrom(POCE_SOFTC sc, uint32_t optype,uint32_t opcode,
1060 POCE_DMA_MEM pdma_mem, uint32_t num_bytes);
1061 int oce_mbox_lancer_write_flashrom(POCE_SOFTC sc, uint32_t data_size,
1062 uint32_t data_offset,POCE_DMA_MEM pdma_mem,
1063 uint32_t *written_data, uint32_t *additional_status);
1065 int oce_mbox_get_flashrom_crc(POCE_SOFTC sc, uint8_t *flash_crc,
1066 uint32_t offset, uint32_t optype);
1067 int oce_mbox_get_phy_info(POCE_SOFTC sc, struct oce_phy_info *phy_info);
1068 int oce_mbox_create_rq(struct oce_rq *rq);
1069 int oce_mbox_create_wq(struct oce_wq *wq);
1070 int oce_mbox_create_eq(struct oce_eq *eq);
1071 int oce_mbox_cq_create(struct oce_cq *cq, uint32_t ncoalesce,
1072 uint32_t is_eventable);
1073 int oce_mbox_read_transrecv_data(POCE_SOFTC sc, uint32_t page_num);
1074 void oce_mbox_eqd_modify_periodic(POCE_SOFTC sc, struct oce_set_eqd *set_eqd,
1076 int oce_get_profile_config(POCE_SOFTC sc, uint32_t max_rss);
1077 int oce_get_func_config(POCE_SOFTC sc);
1078 void mbx_common_req_hdr_init(struct mbx_hdr *hdr,
1083 uint32_t timeout, uint32_t pyld_len,
1087 uint16_t oce_mq_handler(void *arg);
1089 /************************************************************
1090 * Transmit functions
1091 ************************************************************/
1092 uint16_t oce_wq_handler(void *arg);
1093 void oce_start(struct ifnet *ifp);
1094 void oce_tx_task(void *arg, int npending);
1096 /************************************************************
1098 ************************************************************/
1099 int oce_alloc_rx_bufs(struct oce_rq *rq, int count);
1100 uint16_t oce_rq_handler(void *arg);
1103 /* Sysctl functions */
1104 void oce_add_sysctls(POCE_SOFTC sc);
1105 void oce_refresh_queue_stats(POCE_SOFTC sc);
1106 int oce_refresh_nic_stats(POCE_SOFTC sc);
1107 int oce_stats_init(POCE_SOFTC sc);
1108 void oce_stats_free(POCE_SOFTC sc);
1110 /* hw lro functions */
1111 int oce_mbox_nic_query_lro_capabilities(POCE_SOFTC sc, uint32_t *lro_rq_cnt, uint32_t *lro_flags);
1112 int oce_mbox_nic_set_iface_lro_config(POCE_SOFTC sc, int enable);
1113 int oce_mbox_create_rq_v2(struct oce_rq *rq);
1116 #define OCE_MODCAP_RSS 1
1117 #define OCE_MAX_RSP_HANDLED 64
1118 extern uint32_t oce_max_rsp_handled; /* max responses */
1119 extern uint32_t oce_rq_buf_size;
1121 #define OCE_MAC_LOOPBACK 0x0
1122 #define OCE_PHY_LOOPBACK 0x1
1123 #define OCE_ONE_PORT_EXT_LOOPBACK 0x2
1124 #define OCE_NO_LOOPBACK 0xff
1127 #define IFM_40G_SR4 28
1129 #define atomic_inc_32(x) atomic_add_32(x, 1)
1130 #define atomic_dec_32(x) atomic_subtract_32(x, 1)
1132 #define LE_64(x) htole64(x)
1133 #define LE_32(x) htole32(x)
1134 #define LE_16(x) htole16(x)
1135 #define HOST_64(x) le64toh(x)
1136 #define HOST_32(x) le32toh(x)
1137 #define HOST_16(x) le16toh(x)
1138 #define DW_SWAP(x, l)
1139 #define IS_ALIGNED(x,a) ((x % a) == 0)
1140 #define ADDR_HI(x) ((uint32_t)((uint64_t)(x) >> 32))
1141 #define ADDR_LO(x) ((uint32_t)((uint64_t)(x) & 0xffffffff));
1143 #define IF_LRO_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_LRO) ? 1:0)
1144 #define IF_LSO_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_TSO4) ? 1:0)
1145 #define IF_CSUM_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_HWCSUM) ? 1:0)
1147 #define OCE_LOG2(x) (oce_highbit(x))
1148 static inline uint32_t oce_highbit(uint32_t x)
1157 for (i = 0; i < 32; i++) {
1170 static inline int MPU_EP_SEMAPHORE(POCE_SOFTC sc)
1173 return MPU_EP_SEMAPHORE_BE3;
1175 return MPU_EP_SEMAPHORE_SH;
1177 return MPU_EP_SEMAPHORE_XE201;
1180 #define TRANSCEIVER_DATA_NUM_ELE 64
1181 #define TRANSCEIVER_DATA_SIZE 256
1182 #define TRANSCEIVER_A0_SIZE 128
1183 #define TRANSCEIVER_A2_SIZE 128
1184 #define PAGE_NUM_A0 0xa0
1185 #define PAGE_NUM_A2 0xa2
1186 #define IS_QNQ_OR_UMC(sc) ((sc->pvid && (sc->function_mode & FNM_UMC_MODE ))\
1187 || (sc->qnqid && (sc->function_mode & FNM_FLEX10_MODE)))
1189 struct oce_rdma_info;
1190 extern struct oce_rdma_if *oce_rdma_if;
1194 /* OS2BMC related */
1196 #define DHCP_CLIENT_PORT 68
1197 #define DHCP_SERVER_PORT 67
1198 #define NET_BIOS_PORT1 137
1199 #define NET_BIOS_PORT2 138
1200 #define DHCPV6_RAS_PORT 547
1202 #define BMC_FILT_BROADCAST_ARP ((uint32_t)(1))
1203 #define BMC_FILT_BROADCAST_DHCP_CLIENT ((uint32_t)(1 << 1))
1204 #define BMC_FILT_BROADCAST_DHCP_SERVER ((uint32_t)(1 << 2))
1205 #define BMC_FILT_BROADCAST_NET_BIOS ((uint32_t)(1 << 3))
1206 #define BMC_FILT_BROADCAST ((uint32_t)(1 << 4))
1207 #define BMC_FILT_MULTICAST_IPV6_NEIGH_ADVER ((uint32_t)(1 << 5))
1208 #define BMC_FILT_MULTICAST_IPV6_RA ((uint32_t)(1 << 6))
1209 #define BMC_FILT_MULTICAST_IPV6_RAS ((uint32_t)(1 << 7))
1210 #define BMC_FILT_MULTICAST ((uint32_t)(1 << 8))
1212 #define ND_ROUTER_ADVERT 134
1213 #define ND_NEIGHBOR_ADVERT 136
1215 #define is_mc_allowed_on_bmc(sc, eh) \
1216 (!is_multicast_filt_enabled(sc) && \
1217 ETHER_IS_MULTICAST(eh->ether_dhost) && \
1218 !ETHER_IS_BROADCAST(eh->ether_dhost))
1220 #define is_bc_allowed_on_bmc(sc, eh) \
1221 (!is_broadcast_filt_enabled(sc) && \
1222 ETHER_IS_BROADCAST(eh->ether_dhost))
1224 #define is_arp_allowed_on_bmc(sc, et) \
1225 (is_arp(et) && is_arp_filt_enabled(sc))
1227 #define is_arp(et) (et == ETHERTYPE_ARP)
1229 #define is_arp_filt_enabled(sc) \
1230 (sc->bmc_filt_mask & (BMC_FILT_BROADCAST_ARP))
1232 #define is_dhcp_client_filt_enabled(sc) \
1233 (sc->bmc_filt_mask & BMC_FILT_BROADCAST_DHCP_CLIENT)
1235 #define is_dhcp_srvr_filt_enabled(sc) \
1236 (sc->bmc_filt_mask & BMC_FILT_BROADCAST_DHCP_SERVER)
1238 #define is_nbios_filt_enabled(sc) \
1239 (sc->bmc_filt_mask & BMC_FILT_BROADCAST_NET_BIOS)
1241 #define is_ipv6_na_filt_enabled(sc) \
1242 (sc->bmc_filt_mask & \
1243 BMC_FILT_MULTICAST_IPV6_NEIGH_ADVER)
1245 #define is_ipv6_ra_filt_enabled(sc) \
1246 (sc->bmc_filt_mask & BMC_FILT_MULTICAST_IPV6_RA)
1248 #define is_ipv6_ras_filt_enabled(sc) \
1249 (sc->bmc_filt_mask & BMC_FILT_MULTICAST_IPV6_RAS)
1251 #define is_broadcast_filt_enabled(sc) \
1252 (sc->bmc_filt_mask & BMC_FILT_BROADCAST)
1254 #define is_multicast_filt_enabled(sc) \
1255 (sc->bmc_filt_mask & BMC_FILT_MULTICAST)
1257 #define is_os2bmc_enabled(sc) (sc->flags & OCE_FLAGS_OS2BMC)
1259 #define LRO_FLAGS_HASH_MODE 0x00000001
1260 #define LRO_FLAGS_RSS_MODE 0x00000004
1261 #define LRO_FLAGS_CLSC_IPV4 0x00000010
1262 #define LRO_FLAGS_CLSC_IPV6 0x00000020
1263 #define NIC_RQ_FLAGS_RSS 0x0001
1264 #define NIC_RQ_FLAGS_LRO 0x0020