2 * Copyright (C) 2013 Emulex
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of the Emulex Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
31 * Contact Information:
32 * freebsd-drivers@emulex.com
36 * Costa Mesa, CA 92626
41 #include <sys/param.h>
42 #include <sys/endian.h>
43 #include <sys/eventhandler.h>
44 #include <sys/module.h>
45 #include <sys/kernel.h>
49 #include <sys/socket.h>
50 #include <sys/sockio.h>
51 #include <sys/sockopt.h>
52 #include <sys/queue.h>
53 #include <sys/taskqueue.h>
55 #include <sys/mutex.h>
56 #include <sys/sysctl.h>
57 #include <sys/random.h>
58 #include <sys/firmware.h>
59 #include <sys/systm.h>
62 #include <dev/pci/pcireg.h>
63 #include <dev/pci/pcivar.h>
66 #include <net/ethernet.h>
68 #include <net/if_var.h>
69 #include <net/if_types.h>
70 #include <net/if_media.h>
71 #include <net/if_vlan_var.h>
72 #include <net/if_dl.h>
74 #include <netinet/in.h>
75 #include <netinet/in_systm.h>
76 #include <netinet/in_var.h>
77 #include <netinet/if_ether.h>
78 #include <netinet/ip.h>
79 #include <netinet/ip6.h>
80 #include <netinet6/in6_var.h>
81 #include <netinet6/ip6_mroute.h>
83 #include <netinet/udp.h>
84 #include <netinet/tcp.h>
85 #include <netinet/sctp.h>
86 #include <netinet/tcp_lro.h>
88 #include <machine/bus.h>
92 /* OCE device driver module component revision informaiton */
93 #define COMPONENT_REVISION "10.0.664.0"
95 /* OCE devices supported by this driver */
96 #define PCI_VENDOR_EMULEX 0x10df /* Emulex */
97 #define PCI_VENDOR_SERVERENGINES 0x19a2 /* ServerEngines (BE) */
98 #define PCI_PRODUCT_BE2 0x0700 /* BE2 network adapter */
99 #define PCI_PRODUCT_BE3 0x0710 /* BE3 network adapter */
100 #define PCI_PRODUCT_XE201 0xe220 /* XE201 network adapter */
101 #define PCI_PRODUCT_XE201_VF 0xe228 /* XE201 with VF in Lancer */
102 #define PCI_PRODUCT_SH 0x0720 /* Skyhawk network adapter */
104 #define IS_BE(sc) (((sc->flags & OCE_FLAGS_BE3) | \
105 (sc->flags & OCE_FLAGS_BE2))? 1:0)
106 #define IS_BE3(sc) (sc->flags & OCE_FLAGS_BE3)
107 #define IS_BE2(sc) (sc->flags & OCE_FLAGS_BE2)
108 #define IS_XE201(sc) ((sc->flags & OCE_FLAGS_XE201) ? 1:0)
109 #define HAS_A0_CHIP(sc) ((sc->flags & OCE_FLAGS_HAS_A0_CHIP) ? 1:0)
110 #define IS_SH(sc) ((sc->flags & OCE_FLAGS_SH) ? 1 : 0)
112 #define is_be_mode_mc(sc) ((sc->function_mode & FNM_FLEX10_MODE) || \
113 (sc->function_mode & FNM_UMC_MODE) || \
114 (sc->function_mode & FNM_VNIC_MODE))
115 #define OCE_FUNCTION_CAPS_SUPER_NIC 0x40
116 #define IS_PROFILE_SUPER_NIC(sc) (sc->function_caps & OCE_FUNCTION_CAPS_SUPER_NIC)
119 /* proportion Service Level Interface queues */
120 #define OCE_MAX_UNITS 2
121 #define OCE_MAX_PPORT OCE_MAX_UNITS
122 #define OCE_MAX_VPORT OCE_MAX_UNITS
124 extern int mp_ncpus; /* system's total active cpu cores */
125 #define OCE_NCPUS mp_ncpus
127 /* This should be powers of 2. Like 2,4,8 & 16 */
128 #define OCE_MAX_RSS 8
129 #define OCE_LEGACY_MODE_RSS 4 /* For BE3 Legacy mode*/
130 #define is_rss_enabled(sc) ((sc->function_caps & FNC_RSS) && !is_be_mode_mc(sc))
135 #define OCE_MAX_RQ OCE_MAX_RSS + 1 /* one default queue */
138 #define OCE_MAX_EQ 32
139 #define OCE_MAX_CQ OCE_MAX_RQ + OCE_MAX_WQ + 1 /* one MCC queue */
140 #define OCE_MAX_CQ_EQ 8 /* Max CQ that can attached to an EQ */
142 #define OCE_DEFAULT_WQ_EQD 16
143 #define OCE_MAX_PACKET_Q 16
144 #define OCE_RQ_BUF_SIZE 2048
145 #define OCE_LSO_MAX_SIZE (64 * 1024)
146 #define LONG_TIMEOUT 30
147 #define OCE_MAX_JUMBO_FRAME_SIZE 9018
148 #define OCE_MAX_MTU (OCE_MAX_JUMBO_FRAME_SIZE - \
149 ETHER_VLAN_ENCAP_LEN - \
152 #define OCE_MAX_TX_ELEMENTS 29
153 #define OCE_MAX_TX_DESC 1024
154 #define OCE_MAX_TX_SIZE 65535
155 #define OCE_MAX_RX_SIZE 4096
156 #define OCE_MAX_RQ_POSTS 255
157 #define OCE_DEFAULT_PROMISCUOUS 0
160 #define RSS_ENABLE_IPV4 0x1
161 #define RSS_ENABLE_TCP_IPV4 0x2
162 #define RSS_ENABLE_IPV6 0x4
163 #define RSS_ENABLE_TCP_IPV6 0x8
165 #define INDIRECTION_TABLE_ENTRIES 128
167 /* flow control definitions */
168 #define OCE_FC_NONE 0x00000000
169 #define OCE_FC_TX 0x00000001
170 #define OCE_FC_RX 0x00000002
171 #define OCE_DEFAULT_FLOW_CONTROL (OCE_FC_TX | OCE_FC_RX)
174 /* Interface capabilities to give device when creating interface */
175 #define OCE_CAPAB_FLAGS (MBX_RX_IFACE_FLAGS_BROADCAST | \
176 MBX_RX_IFACE_FLAGS_UNTAGGED | \
177 MBX_RX_IFACE_FLAGS_PROMISCUOUS | \
178 MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS | \
179 MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS | \
180 MBX_RX_IFACE_FLAGS_RSS | \
181 MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR)
183 /* Interface capabilities to enable by default (others set dynamically) */
184 #define OCE_CAPAB_ENABLE (MBX_RX_IFACE_FLAGS_BROADCAST | \
185 MBX_RX_IFACE_FLAGS_UNTAGGED | \
186 MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR)
188 #define OCE_IF_HWASSIST (CSUM_IP | CSUM_TCP | CSUM_UDP)
189 #define OCE_IF_CAPABILITIES (IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \
190 IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | \
191 IFCAP_JUMBO_MTU | IFCAP_VLAN_MTU)
192 #define OCE_IF_HWASSIST_NONE 0
193 #define OCE_IF_CAPABILITIES_NONE 0
196 #define ETH_ADDR_LEN 6
197 #define MAX_VLANFILTER_SIZE 64
198 #define MAX_VLANS 4096
200 #define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16))
201 #define BSWAP_8(x) ((x) & 0xff)
202 #define BSWAP_16(x) ((BSWAP_8(x) << 8) | BSWAP_8((x) >> 8))
203 #define BSWAP_32(x) ((BSWAP_16(x) << 16) | \
205 #define BSWAP_64(x) ((BSWAP_32(x) << 32) | \
208 #define for_all_wq_queues(sc, wq, i) \
209 for (i = 0, wq = sc->wq[0]; i < sc->nwqs; i++, wq = sc->wq[i])
210 #define for_all_rq_queues(sc, rq, i) \
211 for (i = 0, rq = sc->rq[0]; i < sc->nrqs; i++, rq = sc->rq[i])
212 #define for_all_rss_queues(sc, rq, i) \
213 for (i = 0, rq = sc->rq[i + 1]; i < (sc->nrqs - 1); \
214 i++, rq = sc->rq[i + 1])
215 #define for_all_evnt_queues(sc, eq, i) \
216 for (i = 0, eq = sc->eq[0]; i < sc->neqs; i++, eq = sc->eq[i])
217 #define for_all_cq_queues(sc, cq, i) \
218 for (i = 0, cq = sc->cq[0]; i < sc->ncqs; i++, cq = sc->cq[i])
222 #define IOCTL_COOKIE "SERVERENGINES CORP"
223 #define MAX_FLASH_COMP 32
225 #define IMG_ISCSI 160
226 #define IMG_REDBOOT 224
228 #define IMG_PXEBIOS 32
229 #define IMG_FCOEBIOS 33
230 #define IMG_ISCSI_BAK 176
232 #define IMG_FCOE_BAK 178
235 #define FLASHROM_OPER_FLASH 1
236 #define FLASHROM_OPER_SAVE 2
237 #define FLASHROM_OPER_REPORT 4
238 #define FLASHROM_OPER_FLASH_PHY 9
239 #define FLASHROM_OPER_SAVE_PHY 10
243 PHY_TYPE_CX4_10GB = 0,
246 PHY_TYPE_SFP_PLUS_10GB,
253 PHY_TYPE_DISABLED = 255
257 * @brief Define and hold all necessary info for a single interrupt
259 #define OCE_MAX_MSI 32 /* Message Signaled Interrupts */
260 #define OCE_MAX_MSIX 2048 /* PCI Express MSI Interrrupts */
262 typedef struct oce_intr_info {
263 void *tag; /* cookie returned by bus_setup_intr */
264 struct resource *intr_res; /* PCI resource container */
265 int irq_rr; /* resource id for the interrupt */
266 struct oce_softc *sc; /* pointer to the parent soft c */
267 struct oce_eq *eq; /* pointer to the connected EQ */
268 struct taskqueue *tq; /* Associated task queue */
269 struct task task; /* task queue task */
270 char task_name[32]; /* task name */
271 int vector; /* interrupt vector number */
272 } OCE_INTR_INFO, *POCE_INTR_INFO;
276 #define GET_Q_NEXT(_START, _STEP, _END) \
277 (((_START) + (_STEP)) < (_END) ? ((_START) + (_STEP)) \
278 : (((_START) + (_STEP)) - (_END)))
280 #define DBUF_PA(obj) ((obj)->addr)
281 #define DBUF_VA(obj) ((obj)->ptr)
282 #define DBUF_TAG(obj) ((obj)->tag)
283 #define DBUF_MAP(obj) ((obj)->map)
284 #define DBUF_SYNC(obj, flags) \
285 (void) bus_dmamap_sync(DBUF_TAG(obj), DBUF_MAP(obj), (flags))
287 #define RING_NUM_PENDING(ring) ring->num_used
288 #define RING_FULL(ring) (ring->num_used == ring->num_items)
289 #define RING_EMPTY(ring) (ring->num_used == 0)
290 #define RING_NUM_FREE(ring) \
291 (uint32_t)(ring->num_items - ring->num_used)
292 #define RING_GET(ring, n) \
293 ring->cidx = GET_Q_NEXT(ring->cidx, n, ring->num_items)
294 #define RING_PUT(ring, n) \
295 ring->pidx = GET_Q_NEXT(ring->pidx, n, ring->num_items)
297 #define RING_GET_CONSUMER_ITEM_VA(ring, type) \
298 (void*)((type *)DBUF_VA(&ring->dma) + ring->cidx)
299 #define RING_GET_CONSUMER_ITEM_PA(ring, type) \
300 (uint64_t)(((type *)DBUF_PA(ring->dbuf)) + ring->cidx)
301 #define RING_GET_PRODUCER_ITEM_VA(ring, type) \
302 (void *)(((type *)DBUF_VA(&ring->dma)) + ring->pidx)
303 #define RING_GET_PRODUCER_ITEM_PA(ring, type) \
304 (uint64_t)(((type *)DBUF_PA(ring->dbuf)) + ring->pidx)
306 #define OCE_DMAPTR(o, c) ((c *)(o)->ptr)
308 struct oce_packet_desc {
315 typedef struct oce_dma_mem {
320 } OCE_DMA_MEM, *POCE_DMA_MEM;
322 typedef struct oce_ring_buffer_s {
323 uint16_t cidx; /* Get ptr */
324 uint16_t pidx; /* Put Ptr */
332 #define OCE_UNICAST_PACKET 0
333 #define OCE_MULTICAST_PACKET 1
334 #define OCE_BROADCAST_PACKET 2
335 #define OCE_RSVD_PACKET 3
337 struct oce_rx_stats {
338 /* Total Receive Stats*/
342 uint32_t t_rx_mcast_pkts;
343 uint32_t t_rx_ucast_pkts;
344 uint32_t t_rxcp_errs;
346 struct oce_tx_stats {
347 /*Total Transmit Stats */
354 uint32_t t_ipv6_ext_hdr_tx_drop;
357 struct oce_be_stats {
358 uint8_t be_on_die_temperature;
359 uint32_t be_tx_events;
360 uint32_t eth_red_drops;
361 uint32_t rx_drops_no_pbuf;
362 uint32_t rx_drops_no_txpb;
363 uint32_t rx_drops_no_erx_descr;
364 uint32_t rx_drops_no_tpre_descr;
365 uint32_t rx_drops_too_many_frags;
366 uint32_t rx_drops_invalid_ring;
367 uint32_t forwarded_packets;
368 uint32_t rx_drops_mtu;
369 uint32_t rx_crc_errors;
370 uint32_t rx_alignment_symbol_errors;
371 uint32_t rx_pause_frames;
372 uint32_t rx_priority_pause_frames;
373 uint32_t rx_control_frames;
374 uint32_t rx_in_range_errors;
375 uint32_t rx_out_range_errors;
376 uint32_t rx_frame_too_long;
377 uint32_t rx_address_match_errors;
378 uint32_t rx_dropped_too_small;
379 uint32_t rx_dropped_too_short;
380 uint32_t rx_dropped_header_too_small;
381 uint32_t rx_dropped_tcp_length;
382 uint32_t rx_dropped_runt;
383 uint32_t rx_ip_checksum_errs;
384 uint32_t rx_tcp_checksum_errs;
385 uint32_t rx_udp_checksum_errs;
386 uint32_t rx_switched_unicast_packets;
387 uint32_t rx_switched_multicast_packets;
388 uint32_t rx_switched_broadcast_packets;
389 uint32_t tx_pauseframes;
390 uint32_t tx_priority_pauseframes;
391 uint32_t tx_controlframes;
392 uint32_t rxpp_fifo_overflow_drop;
393 uint32_t rx_input_fifo_overflow_drop;
394 uint32_t pmem_fifo_overflow_drop;
395 uint32_t jabber_events;
398 struct oce_xe201_stats {
400 uint64_t tx_unicast_pkts;
401 uint64_t tx_multicast_pkts;
402 uint64_t tx_broadcast_pkts;
404 uint64_t tx_unicast_bytes;
405 uint64_t tx_multicast_bytes;
406 uint64_t tx_broadcast_bytes;
407 uint64_t tx_discards;
409 uint64_t tx_pause_frames;
410 uint64_t tx_pause_on_frames;
411 uint64_t tx_pause_off_frames;
412 uint64_t tx_internal_mac_errors;
413 uint64_t tx_control_frames;
414 uint64_t tx_pkts_64_bytes;
415 uint64_t tx_pkts_65_to_127_bytes;
416 uint64_t tx_pkts_128_to_255_bytes;
417 uint64_t tx_pkts_256_to_511_bytes;
418 uint64_t tx_pkts_512_to_1023_bytes;
419 uint64_t tx_pkts_1024_to_1518_bytes;
420 uint64_t tx_pkts_1519_to_2047_bytes;
421 uint64_t tx_pkts_2048_to_4095_bytes;
422 uint64_t tx_pkts_4096_to_8191_bytes;
423 uint64_t tx_pkts_8192_to_9216_bytes;
424 uint64_t tx_lso_pkts;
426 uint64_t rx_unicast_pkts;
427 uint64_t rx_multicast_pkts;
428 uint64_t rx_broadcast_pkts;
430 uint64_t rx_unicast_bytes;
431 uint64_t rx_multicast_bytes;
432 uint64_t rx_broadcast_bytes;
433 uint32_t rx_unknown_protos;
434 uint64_t rx_discards;
436 uint64_t rx_crc_errors;
437 uint64_t rx_alignment_errors;
438 uint64_t rx_symbol_errors;
439 uint64_t rx_pause_frames;
440 uint64_t rx_pause_on_frames;
441 uint64_t rx_pause_off_frames;
442 uint64_t rx_frames_too_long;
443 uint64_t rx_internal_mac_errors;
444 uint32_t rx_undersize_pkts;
445 uint32_t rx_oversize_pkts;
446 uint32_t rx_fragment_pkts;
448 uint64_t rx_control_frames;
449 uint64_t rx_control_frames_unknown_opcode;
450 uint32_t rx_in_range_errors;
451 uint32_t rx_out_of_range_errors;
452 uint32_t rx_address_match_errors;
453 uint32_t rx_vlan_mismatch_errors;
454 uint32_t rx_dropped_too_small;
455 uint32_t rx_dropped_too_short;
456 uint32_t rx_dropped_header_too_small;
457 uint32_t rx_dropped_invalid_tcp_length;
458 uint32_t rx_dropped_runt;
459 uint32_t rx_ip_checksum_errors;
460 uint32_t rx_tcp_checksum_errors;
461 uint32_t rx_udp_checksum_errors;
462 uint32_t rx_non_rss_pkts;
463 uint64_t rx_ipv4_pkts;
464 uint64_t rx_ipv6_pkts;
465 uint64_t rx_ipv4_bytes;
466 uint64_t rx_ipv6_bytes;
467 uint64_t rx_nic_pkts;
468 uint64_t rx_tcp_pkts;
469 uint64_t rx_iscsi_pkts;
470 uint64_t rx_management_pkts;
471 uint64_t rx_switched_unicast_pkts;
472 uint64_t rx_switched_multicast_pkts;
473 uint64_t rx_switched_broadcast_pkts;
474 uint64_t num_forwards;
475 uint32_t rx_fifo_overflow;
476 uint32_t rx_input_fifo_overflow;
477 uint64_t rx_drops_too_many_frags;
478 uint32_t rx_drops_invalid_queue;
479 uint64_t rx_drops_mtu;
480 uint64_t rx_pkts_64_bytes;
481 uint64_t rx_pkts_65_to_127_bytes;
482 uint64_t rx_pkts_128_to_255_bytes;
483 uint64_t rx_pkts_256_to_511_bytes;
484 uint64_t rx_pkts_512_to_1023_bytes;
485 uint64_t rx_pkts_1024_to_1518_bytes;
486 uint64_t rx_pkts_1519_to_2047_bytes;
487 uint64_t rx_pkts_2048_to_4095_bytes;
488 uint64_t rx_pkts_4096_to_8191_bytes;
489 uint64_t rx_pkts_8192_to_9216_bytes;
492 struct oce_drv_stats {
493 struct oce_rx_stats rx;
494 struct oce_tx_stats tx;
496 struct oce_be_stats be;
497 struct oce_xe201_stats xe201;
501 #define INTR_RATE_HWM 15000
502 #define INTR_RATE_LWM 10000
504 #define OCE_MAX_EQD 128u
505 #define OCE_MIN_EQD 50u
510 uint32_t delay_multiplier;
513 struct oce_aic_obj { /* Adaptive interrupt coalescing (AIC) info */
515 uint32_t min_eqd; /* in usecs */
516 uint32_t max_eqd; /* in usecs */
517 uint32_t cur_eqd; /* in usecs */
518 uint32_t et_eqd; /* configured value when aic is off */
523 #define MAX_LOCK_DESC_LEN 32
526 char name[MAX_LOCK_DESC_LEN+1];
528 #define OCE_LOCK struct oce_lock
530 #define LOCK_CREATE(lock, desc) { \
531 strncpy((lock)->name, (desc), MAX_LOCK_DESC_LEN); \
532 (lock)->name[MAX_LOCK_DESC_LEN] = '\0'; \
533 mtx_init(&(lock)->mutex, (lock)->name, NULL, MTX_DEF); \
535 #define LOCK_DESTROY(lock) \
536 if (mtx_initialized(&(lock)->mutex))\
537 mtx_destroy(&(lock)->mutex)
538 #define TRY_LOCK(lock) mtx_trylock(&(lock)->mutex)
539 #define LOCK(lock) mtx_lock(&(lock)->mutex)
540 #define LOCKED(lock) mtx_owned(&(lock)->mutex)
541 #define UNLOCK(lock) mtx_unlock(&(lock)->mutex)
543 #define DEFAULT_MQ_MBOX_TIMEOUT (5 * 1000 * 1000)
544 #define MBX_READY_TIMEOUT (1 * 1000 * 1000)
545 #define DEFAULT_DRAIN_TIME 200
546 #define MBX_TIMEOUT_SEC 5
547 #define STAT_TIMEOUT 2000000
549 /* size of the packet descriptor array in a transmit queue */
550 #define OCE_TX_RING_SIZE 2048
551 #define OCE_RX_RING_SIZE 1024
552 #define OCE_WQ_PACKET_ARRAY_SIZE (OCE_TX_RING_SIZE/2)
553 #define OCE_RQ_PACKET_ARRAY_SIZE (OCE_RX_RING_SIZE)
579 typedef enum qstate_e {
586 enum eqe_size item_size;
587 uint32_t q_vector_num;
598 oce_ring_buffer_t *ring;
601 struct oce_cq *cq[OCE_MAX_CQ_EQ];
603 struct eq_config eq_cfg;
617 boolean_t is_eventable;
618 boolean_t sol_eventable;
620 uint16_t dma_coalescing;
623 typedef uint16_t(*cq_handler_t) (void *arg1);
629 cq_handler_t cq_handler;
631 oce_ring_buffer_t *ring;
633 struct cq_config cq_cfg;
647 oce_ring_buffer_t *ring;
650 struct oce_cq *async_cq;
653 struct mq_config cfg;
658 void (*cb) (void *ctx);
669 uint32_t eqd; /* interrupt delay */
674 struct oce_tx_queue_stats {
678 uint32_t tx_stops; /* number of times TX Q was stopped */
682 uint32_t ipv6_ext_hdr_tx_drop;
688 oce_ring_buffer_t *ring;
691 struct oce_packet_desc pckts[OCE_WQ_PACKET_ARRAY_SIZE];
692 uint32_t pkt_desc_tail;
693 uint32_t pkt_desc_head;
701 struct wq_config cfg;
703 struct oce_tx_queue_stats tx_stats;
714 uint32_t is_rss_queue;
719 struct oce_rx_queue_stats {
720 uint32_t rx_post_fail;
721 uint32_t rx_ucast_pkts;
724 uint64_t rx_bytes_prev;
727 uint32_t rx_mcast_pkts;
730 uint32_t prev_rx_frags;
736 struct rq_config cfg;
741 oce_ring_buffer_t *ring;
745 struct oce_packet_desc pckts[OCE_RQ_PACKET_ARRAY_SIZE];
747 uint32_t packets_out;
756 struct oce_rx_queue_stats rx_stats;
763 uint8_t phys_port_speed;
764 uint8_t logical_link_status;
765 uint16_t qos_link_speed;
770 #define OCE_FLAGS_PCIX 0x00000001
771 #define OCE_FLAGS_PCIE 0x00000002
772 #define OCE_FLAGS_MSI_CAPABLE 0x00000004
773 #define OCE_FLAGS_MSIX_CAPABLE 0x00000008
774 #define OCE_FLAGS_USING_MSI 0x00000010
775 #define OCE_FLAGS_USING_MSIX 0x00000020
776 #define OCE_FLAGS_FUNCRESET_RQD 0x00000040
777 #define OCE_FLAGS_VIRTUAL_PORT 0x00000080
778 #define OCE_FLAGS_MBOX_ENDIAN_RQD 0x00000100
779 #define OCE_FLAGS_BE3 0x00000200
780 #define OCE_FLAGS_XE201 0x00000400
781 #define OCE_FLAGS_BE2 0x00000800
782 #define OCE_FLAGS_SH 0x00001000
784 #define OCE_DEV_BE2_CFG_BAR 1
785 #define OCE_DEV_CFG_BAR 0
786 #define OCE_PCI_CSR_BAR 2
787 #define OCE_PCI_DB_BAR 4
789 typedef struct oce_softc {
795 uint32_t pcie_link_speed;
796 uint32_t pcie_link_width;
798 uint8_t fn; /* PCI function number */
800 struct resource *devcfg_res;
801 bus_space_tag_t devcfg_btag;
802 bus_space_handle_t devcfg_bhandle;
803 void *devcfg_vhandle;
805 struct resource *csr_res;
806 bus_space_tag_t csr_btag;
807 bus_space_handle_t csr_bhandle;
810 struct resource *db_res;
811 bus_space_tag_t db_btag;
812 bus_space_handle_t db_bhandle;
815 OCE_INTR_INFO intrs[OCE_MAX_EQ];
820 struct ifmedia media;
824 uint32_t qos_link_speed;
828 struct mac_address_format macaddr;
833 uint32_t config_number;
834 uint32_t asic_revision;
836 uint32_t function_mode;
837 uint32_t function_caps;
838 uint32_t max_tx_rings;
839 uint32_t max_rx_rings;
841 struct oce_wq *wq[OCE_MAX_WQ]; /* TX work queues */
842 struct oce_rq *rq[OCE_MAX_RQ]; /* RX work queues */
843 struct oce_cq *cq[OCE_MAX_CQ]; /* Completion queues */
844 struct oce_eq *eq[OCE_MAX_EQ]; /* Event queues */
845 struct oce_mq *mq; /* Mailbox queue */
853 uint32_t tx_ring_size;
854 uint32_t rx_ring_size;
855 uint32_t rq_frag_size;
857 uint32_t if_id; /* interface ID */
858 uint32_t nifs; /* number of adapter interfaces, 0 or 1 */
859 uint32_t pmac_id; /* PMAC id */
861 uint32_t if_cap_flags;
863 uint32_t flow_control;
866 struct oce_aic_obj aic_obj[OCE_MAX_EQ];
868 /*Vlan Filtering related */
869 eventhandler_tag vlan_attach;
870 eventhandler_tag vlan_detach;
871 uint16_t vlans_added;
872 uint8_t vlan_tag[MAX_VLANS];
874 OCE_DMA_MEM stats_mem;
875 struct oce_drv_stats oce_stats_info;
876 struct callout timer;
879 uint16_t qnq_debug_event;
884 } OCE_SOFTC, *POCE_SOFTC;
888 /**************************************************
889 * BUS memory read/write macros
890 * BE3: accesses three BAR spaces (CFG, CSR, DB)
891 * Lancer: accesses one BAR space (CFG)
892 **************************************************/
893 #define OCE_READ_CSR_MPU(sc, space, o) \
894 ((IS_BE(sc)) ? (bus_space_read_4((sc)->space##_btag, \
895 (sc)->space##_bhandle,o)) \
896 : (bus_space_read_4((sc)->devcfg_btag, \
897 (sc)->devcfg_bhandle,o)))
898 #define OCE_READ_REG32(sc, space, o) \
899 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_4((sc)->space##_btag, \
900 (sc)->space##_bhandle,o)) \
901 : (bus_space_read_4((sc)->devcfg_btag, \
902 (sc)->devcfg_bhandle,o)))
903 #define OCE_READ_REG16(sc, space, o) \
904 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_2((sc)->space##_btag, \
905 (sc)->space##_bhandle,o)) \
906 : (bus_space_read_2((sc)->devcfg_btag, \
907 (sc)->devcfg_bhandle,o)))
908 #define OCE_READ_REG8(sc, space, o) \
909 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_1((sc)->space##_btag, \
910 (sc)->space##_bhandle,o)) \
911 : (bus_space_read_1((sc)->devcfg_btag, \
912 (sc)->devcfg_bhandle,o)))
914 #define OCE_WRITE_CSR_MPU(sc, space, o, v) \
915 ((IS_BE(sc)) ? (bus_space_write_4((sc)->space##_btag, \
916 (sc)->space##_bhandle,o,v)) \
917 : (bus_space_write_4((sc)->devcfg_btag, \
918 (sc)->devcfg_bhandle,o,v)))
919 #define OCE_WRITE_REG32(sc, space, o, v) \
920 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_4((sc)->space##_btag, \
921 (sc)->space##_bhandle,o,v)) \
922 : (bus_space_write_4((sc)->devcfg_btag, \
923 (sc)->devcfg_bhandle,o,v)))
924 #define OCE_WRITE_REG16(sc, space, o, v) \
925 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_2((sc)->space##_btag, \
926 (sc)->space##_bhandle,o,v)) \
927 : (bus_space_write_2((sc)->devcfg_btag, \
928 (sc)->devcfg_bhandle,o,v)))
929 #define OCE_WRITE_REG8(sc, space, o, v) \
930 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_1((sc)->space##_btag, \
931 (sc)->space##_bhandle,o,v)) \
932 : (bus_space_write_1((sc)->devcfg_btag, \
933 (sc)->devcfg_bhandle,o,v)))
936 /***********************************************************
937 * DMA memory functions
938 ***********************************************************/
939 #define oce_dma_sync(d, f) bus_dmamap_sync((d)->tag, (d)->map, f)
940 int oce_dma_alloc(POCE_SOFTC sc, bus_size_t size, POCE_DMA_MEM dma, int flags);
941 void oce_dma_free(POCE_SOFTC sc, POCE_DMA_MEM dma);
942 void oce_dma_map_addr(void *arg, bus_dma_segment_t * segs, int nseg, int error);
943 void oce_destroy_ring_buffer(POCE_SOFTC sc, oce_ring_buffer_t *ring);
944 oce_ring_buffer_t *oce_create_ring_buffer(POCE_SOFTC sc,
945 uint32_t q_len, uint32_t num_entries);
946 /************************************************************
947 * oce_hw_xxx functions
948 ************************************************************/
949 int oce_clear_rx_buf(struct oce_rq *rq);
950 int oce_hw_pci_alloc(POCE_SOFTC sc);
951 int oce_hw_init(POCE_SOFTC sc);
952 int oce_hw_start(POCE_SOFTC sc);
953 int oce_create_nw_interface(POCE_SOFTC sc);
954 int oce_pci_soft_reset(POCE_SOFTC sc);
955 int oce_hw_update_multicast(POCE_SOFTC sc);
956 void oce_delete_nw_interface(POCE_SOFTC sc);
957 void oce_hw_shutdown(POCE_SOFTC sc);
958 void oce_hw_intr_enable(POCE_SOFTC sc);
959 void oce_hw_intr_disable(POCE_SOFTC sc);
960 void oce_hw_pci_free(POCE_SOFTC sc);
962 /***********************************************************
963 * oce_queue_xxx functions
964 ***********************************************************/
965 int oce_queue_init_all(POCE_SOFTC sc);
966 int oce_start_rq(struct oce_rq *rq);
967 int oce_start_wq(struct oce_wq *wq);
968 int oce_start_mq(struct oce_mq *mq);
969 int oce_start_rx(POCE_SOFTC sc);
970 void oce_arm_eq(POCE_SOFTC sc,
971 int16_t qid, int npopped, uint32_t rearm, uint32_t clearint);
972 void oce_queue_release_all(POCE_SOFTC sc);
973 void oce_arm_cq(POCE_SOFTC sc, int16_t qid, int npopped, uint32_t rearm);
974 void oce_drain_eq(struct oce_eq *eq);
975 void oce_drain_mq_cq(void *arg);
976 void oce_drain_rq_cq(struct oce_rq *rq);
977 void oce_drain_wq_cq(struct oce_wq *wq);
979 uint32_t oce_page_list(oce_ring_buffer_t *ring, struct phys_addr *pa_list);
981 /***********************************************************
983 ***********************************************************/
984 void oce_stop_rx(POCE_SOFTC sc);
985 void oce_intr_free(POCE_SOFTC sc);
986 void oce_free_posted_rxbuf(struct oce_rq *rq);
987 #if defined(INET6) || defined(INET)
988 void oce_free_lro(POCE_SOFTC sc);
992 /************************************************************
994 ************************************************************/
995 int oce_fw_clean(POCE_SOFTC sc);
996 int oce_reset_fun(POCE_SOFTC sc);
997 int oce_mbox_init(POCE_SOFTC sc);
998 int oce_mbox_dispatch(POCE_SOFTC sc, uint32_t tmo_sec);
999 int oce_get_fw_version(POCE_SOFTC sc);
1000 int oce_first_mcc_cmd(POCE_SOFTC sc);
1002 int oce_read_mac_addr(POCE_SOFTC sc, uint32_t if_id, uint8_t perm,
1003 uint8_t type, struct mac_address_format *mac);
1004 int oce_get_fw_config(POCE_SOFTC sc);
1005 int oce_if_create(POCE_SOFTC sc, uint32_t cap_flags, uint32_t en_flags,
1006 uint16_t vlan_tag, uint8_t *mac_addr, uint32_t *if_id);
1007 int oce_if_del(POCE_SOFTC sc, uint32_t if_id);
1008 int oce_config_vlan(POCE_SOFTC sc, uint32_t if_id,
1009 struct normal_vlan *vtag_arr, uint8_t vtag_cnt,
1010 uint32_t untagged, uint32_t enable_promisc);
1011 int oce_set_flow_control(POCE_SOFTC sc, uint32_t flow_control);
1012 int oce_config_nic_rss(POCE_SOFTC sc, uint32_t if_id, uint16_t enable_rss);
1013 int oce_rxf_set_promiscuous(POCE_SOFTC sc, uint8_t enable);
1014 int oce_set_common_iface_rx_filter(POCE_SOFTC sc, POCE_DMA_MEM sgl);
1015 int oce_get_link_status(POCE_SOFTC sc, struct link_status *link);
1016 int oce_mbox_get_nic_stats_v0(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem);
1017 int oce_mbox_get_nic_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem);
1018 int oce_mbox_get_pport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1019 uint32_t reset_stats);
1020 int oce_mbox_get_vport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1021 uint32_t req_size, uint32_t reset_stats);
1022 int oce_update_multicast(POCE_SOFTC sc, POCE_DMA_MEM pdma_mem);
1023 int oce_pass_through_mbox(POCE_SOFTC sc, POCE_DMA_MEM dma_mem, uint32_t req_size);
1024 int oce_mbox_macaddr_del(POCE_SOFTC sc, uint32_t if_id, uint32_t pmac_id);
1025 int oce_mbox_macaddr_add(POCE_SOFTC sc, uint8_t *mac_addr,
1026 uint32_t if_id, uint32_t *pmac_id);
1027 int oce_mbox_cmd_test_loopback(POCE_SOFTC sc, uint32_t port_num,
1028 uint32_t loopback_type, uint32_t pkt_size, uint32_t num_pkts,
1031 int oce_mbox_cmd_set_loopback(POCE_SOFTC sc, uint8_t port_num,
1032 uint8_t loopback_type, uint8_t enable);
1034 int oce_mbox_check_native_mode(POCE_SOFTC sc);
1035 int oce_mbox_post(POCE_SOFTC sc,
1036 struct oce_mbx *mbx, struct oce_mbx_ctx *mbxctx);
1037 int oce_mbox_write_flashrom(POCE_SOFTC sc, uint32_t optype,uint32_t opcode,
1038 POCE_DMA_MEM pdma_mem, uint32_t num_bytes);
1039 int oce_mbox_lancer_write_flashrom(POCE_SOFTC sc, uint32_t data_size,
1040 uint32_t data_offset,POCE_DMA_MEM pdma_mem,
1041 uint32_t *written_data, uint32_t *additional_status);
1043 int oce_mbox_get_flashrom_crc(POCE_SOFTC sc, uint8_t *flash_crc,
1044 uint32_t offset, uint32_t optype);
1045 int oce_mbox_get_phy_info(POCE_SOFTC sc, struct oce_phy_info *phy_info);
1046 int oce_mbox_create_rq(struct oce_rq *rq);
1047 int oce_mbox_create_wq(struct oce_wq *wq);
1048 int oce_mbox_create_eq(struct oce_eq *eq);
1049 int oce_mbox_cq_create(struct oce_cq *cq, uint32_t ncoalesce,
1050 uint32_t is_eventable);
1051 int oce_mbox_read_transrecv_data(POCE_SOFTC sc, uint32_t page_num);
1052 void oce_mbox_eqd_modify_periodic(POCE_SOFTC sc, struct oce_set_eqd *set_eqd,
1054 int oce_get_profile_config(POCE_SOFTC sc, uint32_t max_rss);
1055 int oce_get_func_config(POCE_SOFTC sc);
1056 void mbx_common_req_hdr_init(struct mbx_hdr *hdr,
1061 uint32_t timeout, uint32_t pyld_len,
1065 uint16_t oce_mq_handler(void *arg);
1067 /************************************************************
1068 * Transmit functions
1069 ************************************************************/
1070 uint16_t oce_wq_handler(void *arg);
1071 void oce_start(struct ifnet *ifp);
1072 void oce_tx_task(void *arg, int npending);
1074 /************************************************************
1076 ************************************************************/
1077 int oce_alloc_rx_bufs(struct oce_rq *rq, int count);
1078 uint16_t oce_rq_handler(void *arg);
1081 /* Sysctl functions */
1082 void oce_add_sysctls(POCE_SOFTC sc);
1083 void oce_refresh_queue_stats(POCE_SOFTC sc);
1084 int oce_refresh_nic_stats(POCE_SOFTC sc);
1085 int oce_stats_init(POCE_SOFTC sc);
1086 void oce_stats_free(POCE_SOFTC sc);
1089 #define OCE_MODCAP_RSS 1
1090 #define OCE_MAX_RSP_HANDLED 64
1091 extern uint32_t oce_max_rsp_handled; /* max responses */
1093 #define OCE_MAC_LOOPBACK 0x0
1094 #define OCE_PHY_LOOPBACK 0x1
1095 #define OCE_ONE_PORT_EXT_LOOPBACK 0x2
1096 #define OCE_NO_LOOPBACK 0xff
1099 #define IFM_40G_SR4 28
1101 #define atomic_inc_32(x) atomic_add_32(x, 1)
1102 #define atomic_dec_32(x) atomic_subtract_32(x, 1)
1104 #define LE_64(x) htole64(x)
1105 #define LE_32(x) htole32(x)
1106 #define LE_16(x) htole16(x)
1107 #define HOST_64(x) le64toh(x)
1108 #define HOST_32(x) le32toh(x)
1109 #define HOST_16(x) le16toh(x)
1110 #define DW_SWAP(x, l)
1111 #define IS_ALIGNED(x,a) ((x % a) == 0)
1112 #define ADDR_HI(x) ((uint32_t)((uint64_t)(x) >> 32))
1113 #define ADDR_LO(x) ((uint32_t)((uint64_t)(x) & 0xffffffff));
1115 #define IF_LRO_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_LRO) ? 1:0)
1116 #define IF_LSO_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_TSO4) ? 1:0)
1117 #define IF_CSUM_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_HWCSUM) ? 1:0)
1119 #define OCE_LOG2(x) (oce_highbit(x))
1120 static inline uint32_t oce_highbit(uint32_t x)
1129 for (i = 0; i < 32; i++) {
1142 static inline int MPU_EP_SEMAPHORE(POCE_SOFTC sc)
1145 return MPU_EP_SEMAPHORE_BE3;
1147 return MPU_EP_SEMAPHORE_SH;
1149 return MPU_EP_SEMAPHORE_XE201;
1152 #define TRANSCEIVER_DATA_NUM_ELE 64
1153 #define TRANSCEIVER_DATA_SIZE 256
1154 #define TRANSCEIVER_A0_SIZE 128
1155 #define TRANSCEIVER_A2_SIZE 128
1156 #define PAGE_NUM_A0 0xa0
1157 #define PAGE_NUM_A2 0xa2
1158 #define IS_QNQ_OR_UMC(sc) ((sc->pvid && (sc->function_mode & FNM_UMC_MODE ))\
1159 || (sc->qnqid && (sc->function_mode & FNM_FLEX10_MODE)))