2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (C) 2013 Emulex
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of the Emulex Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
33 * Contact Information:
34 * freebsd-drivers@emulex.com
38 * Costa Mesa, CA 92626
46 oce_wait_ready(POCE_SOFTC sc)
48 #define SLIPORT_READY_TIMEOUT 30000
49 uint32_t sliport_status, i;
54 for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
55 sliport_status = OCE_READ_REG32(sc, db, SLIPORT_STATUS_OFFSET);
56 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
59 if (sliport_status & SLIPORT_STATUS_ERR_MASK &&
60 !(sliport_status & SLIPORT_STATUS_RN_MASK)) {
61 device_printf(sc->dev, "Error detected in the card\n");
68 device_printf(sc->dev, "Firmware wait timed out\n");
74 * @brief Reset (firmware) common function
75 * @param sc software handle to the device
76 * @returns 0 on success, ETIMEDOUT on failure
79 oce_reset_fun(POCE_SOFTC sc)
83 struct ioctl_common_function_reset *fwcmd;
87 OCE_WRITE_REG32(sc, db, SLIPORT_CONTROL_OFFSET,
88 SLI_PORT_CONTROL_IP_MASK);
90 rc = oce_wait_ready(sc);
92 device_printf(sc->dev, "Firmware reset Failed\n");
98 mb = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx);
100 bzero(mbx, sizeof(struct oce_mbx));
102 fwcmd = (struct ioctl_common_function_reset *)&mbx->payload;
103 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
104 MBX_SUBSYSTEM_COMMON,
105 OPCODE_COMMON_FUNCTION_RESET,
106 10, /* MBX_TIMEOUT_SEC */
108 ioctl_common_function_reset),
111 mbx->u0.s.embedded = 1;
112 mbx->payload_length =
113 sizeof(struct ioctl_common_function_reset);
115 rc = oce_mbox_dispatch(sc, 2);
122 * @brief This funtions tells firmware we are
123 * done with commands.
124 * @param sc software handle to the device
125 * @returns 0 on success, ETIMEDOUT on failure
128 oce_fw_clean(POCE_SOFTC sc)
130 struct oce_bmbx *mbx;
134 mbx = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx);
135 ptr = (uint8_t *) &mbx->mbx;
137 /* Endian Signature */
147 ret = oce_mbox_dispatch(sc, 2);
154 * @brief Mailbox wait
155 * @param sc software handle to the device
156 * @param tmo_sec timeout in seconds
159 oce_mbox_wait(POCE_SOFTC sc, uint32_t tmo_sec)
162 pd_mpu_mbox_db_t mbox_db;
170 mbox_db.dw0 = OCE_READ_REG32(sc, db, PD_MPU_MBOX_DB);
172 if (mbox_db.bits.ready)
178 device_printf(sc->dev, "Mailbox timed out\n");
185 * @brief Mailbox dispatch
186 * @param sc software handle to the device
187 * @param tmo_sec timeout in seconds
190 oce_mbox_dispatch(POCE_SOFTC sc, uint32_t tmo_sec)
192 pd_mpu_mbox_db_t mbox_db;
196 oce_dma_sync(&sc->bsmbx, BUS_DMASYNC_PREWRITE);
197 pa = (uint32_t) ((uint64_t) sc->bsmbx.paddr >> 34);
198 bzero(&mbox_db, sizeof(pd_mpu_mbox_db_t));
199 mbox_db.bits.ready = 0;
201 mbox_db.bits.address = pa;
203 rc = oce_mbox_wait(sc, tmo_sec);
205 OCE_WRITE_REG32(sc, db, PD_MPU_MBOX_DB, mbox_db.dw0);
207 pa = (uint32_t) ((uint64_t) sc->bsmbx.paddr >> 4) & 0x3fffffff;
208 mbox_db.bits.ready = 0;
210 mbox_db.bits.address = pa;
212 rc = oce_mbox_wait(sc, tmo_sec);
215 OCE_WRITE_REG32(sc, db, PD_MPU_MBOX_DB, mbox_db.dw0);
217 rc = oce_mbox_wait(sc, tmo_sec);
219 oce_dma_sync(&sc->bsmbx, BUS_DMASYNC_POSTWRITE);
229 * @brief Mailbox common request header initialization
230 * @param hdr mailbox header
233 * @param subsys subsystem
234 * @param opcode opcode
235 * @param timeout timeout
236 * @param pyld_len payload length
239 mbx_common_req_hdr_init(struct mbx_hdr *hdr,
240 uint8_t dom, uint8_t port,
241 uint8_t subsys, uint8_t opcode,
242 uint32_t timeout, uint32_t pyld_len,
245 hdr->u0.req.opcode = opcode;
246 hdr->u0.req.subsystem = subsys;
247 hdr->u0.req.port_number = port;
248 hdr->u0.req.domain = dom;
250 hdr->u0.req.timeout = timeout;
251 hdr->u0.req.request_length = pyld_len - sizeof(struct mbx_hdr);
252 hdr->u0.req.version = version;
258 * @brief Function to initialize the hw with host endian information
259 * @param sc software handle to the device
260 * @returns 0 on success, ETIMEDOUT on failure
263 oce_mbox_init(POCE_SOFTC sc)
265 struct oce_bmbx *mbx;
269 if (sc->flags & OCE_FLAGS_MBOX_ENDIAN_RQD) {
270 mbx = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx);
271 ptr = (uint8_t *) &mbx->mbx;
273 /* Endian Signature */
283 ret = oce_mbox_dispatch(sc, 0);
291 * @brief Function to get the firmware version
292 * @param sc software handle to the device
293 * @returns 0 on success, EIO on failure
296 oce_get_fw_version(POCE_SOFTC sc)
299 struct mbx_get_common_fw_version *fwcmd;
302 bzero(&mbx, sizeof(struct oce_mbx));
304 fwcmd = (struct mbx_get_common_fw_version *)&mbx.payload;
305 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
306 MBX_SUBSYSTEM_COMMON,
307 OPCODE_COMMON_GET_FW_VERSION,
309 sizeof(struct mbx_get_common_fw_version),
312 mbx.u0.s.embedded = 1;
313 mbx.payload_length = sizeof(struct mbx_get_common_fw_version);
314 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
316 ret = oce_mbox_post(sc, &mbx, NULL);
318 ret = fwcmd->hdr.u0.rsp.status;
320 device_printf(sc->dev,
321 "%s failed - cmd status: %d addi status: %d\n",
323 fwcmd->hdr.u0.rsp.additional_status);
327 bcopy(fwcmd->params.rsp.fw_ver_str, sc->fw_version, 32);
334 * @brief Firmware will send gracious notifications during
335 * attach only after sending first mcc commnad. We
336 * use MCC queue only for getting async and mailbox
337 * for sending cmds. So to get gracious notifications
338 * atleast send one dummy command on mcc.
341 oce_first_mcc_cmd(POCE_SOFTC sc)
344 struct oce_mq *mq = sc->mq;
345 struct mbx_get_common_fw_version *fwcmd;
348 mbx = RING_GET_PRODUCER_ITEM_VA(mq->ring, struct oce_mbx);
349 bzero(mbx, sizeof(struct oce_mbx));
351 fwcmd = (struct mbx_get_common_fw_version *)&mbx->payload;
352 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
353 MBX_SUBSYSTEM_COMMON,
354 OPCODE_COMMON_GET_FW_VERSION,
356 sizeof(struct mbx_get_common_fw_version),
358 mbx->u0.s.embedded = 1;
359 mbx->payload_length = sizeof(struct mbx_get_common_fw_version);
360 bus_dmamap_sync(mq->ring->dma.tag, mq->ring->dma.map,
361 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
362 RING_PUT(mq->ring, 1);
363 reg_value = (1 << 16) | mq->mq_id;
364 OCE_WRITE_REG32(sc, db, PD_MQ_DB, reg_value);
370 * @brief Function to post a MBX to the mbox
371 * @param sc software handle to the device
372 * @param mbx pointer to the MBX to send
373 * @param mbxctx pointer to the mbx context structure
374 * @returns 0 on success, error on failure
377 oce_mbox_post(POCE_SOFTC sc, struct oce_mbx *mbx, struct oce_mbx_ctx *mbxctx)
379 struct oce_mbx *mb_mbx = NULL;
380 struct oce_mq_cqe *mb_cqe = NULL;
381 struct oce_bmbx *mb = NULL;
384 uint32_t cstatus = 0;
385 uint32_t xstatus = 0;
387 LOCK(&sc->bmbx_lock);
389 mb = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx);
396 /* copy mbx into mbox */
397 bcopy(mbx, mb_mbx, sizeof(struct oce_mbx));
400 rc = oce_mbox_dispatch(sc, tmo);
403 * the command completed successfully. Now get the
404 * completion queue entry
407 DW_SWAP(u32ptr(&mb_cqe->u0.dw[0]), sizeof(struct oce_mq_cqe));
409 /* copy mbox mbx back */
410 bcopy(mb_mbx, mbx, sizeof(struct oce_mbx));
412 /* pick up the mailbox status */
413 cstatus = mb_cqe->u0.s.completion_status;
414 xstatus = mb_cqe->u0.s.extended_status;
417 * store the mbx context in the cqe tag section so that
418 * the upper layer handling the cqe can associate the mbx
421 if (cstatus == 0 && mbxctx) {
423 mbxctx->mbx = mb_mbx;
424 bcopy(&mbxctx, mb_cqe->u0.s.mq_tag,
425 sizeof(struct oce_mbx_ctx *));
429 UNLOCK(&sc->bmbx_lock);
435 * @brief Function to read the mac address associated with an interface
436 * @param sc software handle to the device
437 * @param if_id interface id to read the address from
438 * @param perm set to 1 if reading the factory mac address.
439 * In this case if_id is ignored
440 * @param type type of the mac address, whether network or storage
441 * @param[out] mac [OUTPUT] pointer to a buffer containing the
442 * mac address when the command succeeds.
443 * @returns 0 on success, EIO on failure
446 oce_read_mac_addr(POCE_SOFTC sc, uint32_t if_id,
447 uint8_t perm, uint8_t type, struct mac_address_format *mac)
450 struct mbx_query_common_iface_mac *fwcmd;
453 bzero(&mbx, sizeof(struct oce_mbx));
455 fwcmd = (struct mbx_query_common_iface_mac *)&mbx.payload;
456 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
457 MBX_SUBSYSTEM_COMMON,
458 OPCODE_COMMON_QUERY_IFACE_MAC,
460 sizeof(struct mbx_query_common_iface_mac),
463 fwcmd->params.req.permanent = perm;
465 fwcmd->params.req.if_id = (uint16_t) if_id;
467 fwcmd->params.req.if_id = 0;
469 fwcmd->params.req.type = type;
471 mbx.u0.s.embedded = 1;
472 mbx.payload_length = sizeof(struct mbx_query_common_iface_mac);
473 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
475 ret = oce_mbox_post(sc, &mbx, NULL);
477 ret = fwcmd->hdr.u0.rsp.status;
479 device_printf(sc->dev,
480 "%s failed - cmd status: %d addi status: %d\n",
482 fwcmd->hdr.u0.rsp.additional_status);
486 /* copy the mac addres in the output parameter */
487 mac->size_of_struct = fwcmd->params.rsp.mac.size_of_struct;
488 bcopy(&fwcmd->params.rsp.mac.mac_addr[0], &mac->mac_addr[0],
489 mac->size_of_struct);
495 * @brief Function to query the fw attributes from the hw
496 * @param sc software handle to the device
497 * @returns 0 on success, EIO on failure
500 oce_get_fw_config(POCE_SOFTC sc)
503 struct mbx_common_query_fw_config *fwcmd;
506 bzero(&mbx, sizeof(struct oce_mbx));
508 fwcmd = (struct mbx_common_query_fw_config *)&mbx.payload;
509 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
510 MBX_SUBSYSTEM_COMMON,
511 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG,
513 sizeof(struct mbx_common_query_fw_config),
516 mbx.u0.s.embedded = 1;
517 mbx.payload_length = sizeof(struct mbx_common_query_fw_config);
518 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
520 ret = oce_mbox_post(sc, &mbx, NULL);
522 ret = fwcmd->hdr.u0.rsp.status;
524 device_printf(sc->dev,
525 "%s failed - cmd status: %d addi status: %d\n",
527 fwcmd->hdr.u0.rsp.additional_status);
531 DW_SWAP(u32ptr(fwcmd), sizeof(struct mbx_common_query_fw_config));
533 sc->config_number = HOST_32(fwcmd->params.rsp.config_number);
534 sc->asic_revision = HOST_32(fwcmd->params.rsp.asic_revision);
535 sc->port_id = HOST_32(fwcmd->params.rsp.port_id);
536 sc->function_mode = HOST_32(fwcmd->params.rsp.function_mode);
537 if ((sc->function_mode & (ULP_NIC_MODE | ULP_RDMA_MODE)) ==
538 (ULP_NIC_MODE | ULP_RDMA_MODE)) {
539 sc->rdma_flags = OCE_RDMA_FLAG_SUPPORTED;
541 sc->function_caps = HOST_32(fwcmd->params.rsp.function_caps);
543 if (fwcmd->params.rsp.ulp[0].ulp_mode & ULP_NIC_MODE) {
544 sc->max_tx_rings = HOST_32(fwcmd->params.rsp.ulp[0].nic_wq_tot);
545 sc->max_rx_rings = HOST_32(fwcmd->params.rsp.ulp[0].lro_rqid_tot);
547 sc->max_tx_rings = HOST_32(fwcmd->params.rsp.ulp[1].nic_wq_tot);
548 sc->max_rx_rings = HOST_32(fwcmd->params.rsp.ulp[1].lro_rqid_tot);
558 * @brief function to create a device interface
559 * @param sc software handle to the device
560 * @param cap_flags capability flags
561 * @param en_flags enable capability flags
562 * @param vlan_tag optional vlan tag to associate with the if
563 * @param mac_addr pointer to a buffer containing the mac address
564 * @param[out] if_id [OUTPUT] pointer to an integer to hold the ID of the
566 * @returns 0 on success, EIO on failure
569 oce_if_create(POCE_SOFTC sc,
577 struct mbx_create_common_iface *fwcmd;
580 bzero(&mbx, sizeof(struct oce_mbx));
582 fwcmd = (struct mbx_create_common_iface *)&mbx.payload;
583 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
584 MBX_SUBSYSTEM_COMMON,
585 OPCODE_COMMON_CREATE_IFACE,
587 sizeof(struct mbx_create_common_iface),
589 DW_SWAP(u32ptr(&fwcmd->hdr), sizeof(struct mbx_hdr));
591 fwcmd->params.req.version = 0;
592 fwcmd->params.req.cap_flags = LE_32(cap_flags);
593 fwcmd->params.req.enable_flags = LE_32(en_flags);
594 if (mac_addr != NULL) {
595 bcopy(mac_addr, &fwcmd->params.req.mac_addr[0], 6);
596 fwcmd->params.req.vlan_tag.u0.normal.vtag = LE_16(vlan_tag);
597 fwcmd->params.req.mac_invalid = 0;
599 fwcmd->params.req.mac_invalid = 1;
602 mbx.u0.s.embedded = 1;
603 mbx.payload_length = sizeof(struct mbx_create_common_iface);
604 DW_SWAP(u32ptr(&mbx), OCE_BMBX_RHDR_SZ);
606 rc = oce_mbox_post(sc, &mbx, NULL);
608 rc = fwcmd->hdr.u0.rsp.status;
610 device_printf(sc->dev,
611 "%s failed - cmd status: %d addi status: %d\n",
613 fwcmd->hdr.u0.rsp.additional_status);
617 *if_id = HOST_32(fwcmd->params.rsp.if_id);
619 if (mac_addr != NULL)
620 sc->pmac_id = HOST_32(fwcmd->params.rsp.pmac_id);
626 * @brief Function to delete an interface
627 * @param sc software handle to the device
628 * @param if_id ID of the interface to delete
629 * @returns 0 on success, EIO on failure
632 oce_if_del(POCE_SOFTC sc, uint32_t if_id)
635 struct mbx_destroy_common_iface *fwcmd;
638 bzero(&mbx, sizeof(struct oce_mbx));
640 fwcmd = (struct mbx_destroy_common_iface *)&mbx.payload;
641 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
642 MBX_SUBSYSTEM_COMMON,
643 OPCODE_COMMON_DESTROY_IFACE,
645 sizeof(struct mbx_destroy_common_iface),
648 fwcmd->params.req.if_id = if_id;
650 mbx.u0.s.embedded = 1;
651 mbx.payload_length = sizeof(struct mbx_destroy_common_iface);
652 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
654 rc = oce_mbox_post(sc, &mbx, NULL);
656 rc = fwcmd->hdr.u0.rsp.status;
658 device_printf(sc->dev,
659 "%s failed - cmd status: %d addi status: %d\n",
661 fwcmd->hdr.u0.rsp.additional_status);
666 * @brief Function to send the mbx command to configure vlan
667 * @param sc software handle to the device
668 * @param if_id interface identifier index
669 * @param vtag_arr array of vlan tags
670 * @param vtag_cnt number of elements in array
671 * @param untagged boolean TRUE/FLASE
672 * @param enable_promisc flag to enable/disable VLAN promiscuous mode
673 * @returns 0 on success, EIO on failure
676 oce_config_vlan(POCE_SOFTC sc,
678 struct normal_vlan *vtag_arr,
679 uint8_t vtag_cnt, uint32_t untagged, uint32_t enable_promisc)
682 struct mbx_common_config_vlan *fwcmd;
685 if (sc->vlans_added > sc->max_vlans)
688 bzero(&mbx, sizeof(struct oce_mbx));
689 fwcmd = (struct mbx_common_config_vlan *)&mbx.payload;
691 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
692 MBX_SUBSYSTEM_COMMON,
693 OPCODE_COMMON_CONFIG_IFACE_VLAN,
695 sizeof(struct mbx_common_config_vlan),
698 fwcmd->params.req.if_id = (uint8_t) if_id;
699 fwcmd->params.req.promisc = (uint8_t) enable_promisc;
700 fwcmd->params.req.untagged = (uint8_t) untagged;
701 fwcmd->params.req.num_vlans = vtag_cnt;
703 if (!enable_promisc) {
704 bcopy(vtag_arr, fwcmd->params.req.tags.normal_vlans,
705 vtag_cnt * sizeof(struct normal_vlan));
707 mbx.u0.s.embedded = 1;
708 mbx.payload_length = sizeof(struct mbx_common_config_vlan);
709 DW_SWAP(u32ptr(&mbx), (OCE_BMBX_RHDR_SZ + mbx.payload_length));
711 rc = oce_mbox_post(sc, &mbx, NULL);
713 rc = fwcmd->hdr.u0.rsp.status;
715 device_printf(sc->dev,
716 "%s failed - cmd status: %d addi status: %d\n",
718 fwcmd->hdr.u0.rsp.additional_status);
723 /* Enable Vlan Promis */
724 oce_rxf_set_promiscuous(sc, (1 << 1));
725 device_printf(sc->dev,"Enabling Vlan Promisc Mode\n");
732 * @brief Function to set flow control capability in the hardware
733 * @param sc software handle to the device
734 * @param flow_control flow control flags to set
735 * @returns 0 on success, EIO on failure
738 oce_set_flow_control(POCE_SOFTC sc, uint32_t flow_control)
741 struct mbx_common_get_set_flow_control *fwcmd =
742 (struct mbx_common_get_set_flow_control *)&mbx.payload;
745 bzero(&mbx, sizeof(struct oce_mbx));
747 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
748 MBX_SUBSYSTEM_COMMON,
749 OPCODE_COMMON_SET_FLOW_CONTROL,
751 sizeof(struct mbx_common_get_set_flow_control),
754 if (flow_control & OCE_FC_TX)
755 fwcmd->tx_flow_control = 1;
757 if (flow_control & OCE_FC_RX)
758 fwcmd->rx_flow_control = 1;
760 mbx.u0.s.embedded = 1;
761 mbx.payload_length = sizeof(struct mbx_common_get_set_flow_control);
762 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
764 rc = oce_mbox_post(sc, &mbx, NULL);
766 rc = fwcmd->hdr.u0.rsp.status;
768 device_printf(sc->dev,
769 "%s failed - cmd status: %d addi status: %d\n",
771 fwcmd->hdr.u0.rsp.additional_status);
776 * @brief Initialize the RSS CPU indirection table
778 * The table is used to choose the queue to place the incomming packets.
779 * Incomming packets are hashed. The lowest bits in the hash result
780 * are used as the index into the CPU indirection table.
781 * Each entry in the table contains the RSS CPU-ID returned by the NIC
782 * create. Based on the CPU ID, the receive completion is routed to
783 * the corresponding RSS CQs. (Non-RSS packets are always completed
784 * on the default (0) CQ).
786 * @param sc software handle to the device
787 * @param *fwcmd pointer to the rss mbox command
791 oce_rss_itbl_init(POCE_SOFTC sc, struct mbx_config_nic_rss *fwcmd)
793 int i = 0, j = 0, rc = 0;
794 uint8_t *tbl = fwcmd->params.req.cputable;
795 struct oce_rq *rq = NULL;
798 for (j = 0; j < INDIRECTION_TABLE_ENTRIES ; j += (sc->nrqs - 1)) {
799 for_all_rss_queues(sc, rq, i) {
800 if ((j + i) >= INDIRECTION_TABLE_ENTRIES)
802 tbl[j + i] = rq->rss_cpuid;
806 device_printf(sc->dev, "error: Invalid number of RSS RQ's\n");
811 /* fill log2 value indicating the size of the CPU table */
813 fwcmd->params.req.cpu_tbl_sz_log2 = LE_16(OCE_LOG2(INDIRECTION_TABLE_ENTRIES));
819 * @brief Function to set flow control capability in the hardware
820 * @param sc software handle to the device
821 * @param if_id interface id to read the address from
822 * @param enable_rss 0=disable, RSS_ENABLE_xxx flags otherwise
823 * @returns 0 on success, EIO on failure
826 oce_config_nic_rss(POCE_SOFTC sc, uint32_t if_id, uint16_t enable_rss)
830 struct mbx_config_nic_rss *fwcmd =
831 (struct mbx_config_nic_rss *)&mbx.payload;
834 bzero(&mbx, sizeof(struct oce_mbx));
836 if (IS_XE201(sc) || IS_SH(sc)) {
837 version = OCE_MBX_VER_V1;
838 fwcmd->params.req.enable_rss = RSS_ENABLE_UDP_IPV4 |
841 version = OCE_MBX_VER_V0;
843 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
847 sizeof(struct mbx_config_nic_rss),
850 fwcmd->params.req.enable_rss |= (RSS_ENABLE_IPV4 |
851 RSS_ENABLE_TCP_IPV4 |
853 RSS_ENABLE_TCP_IPV6);
855 if(!sc->enable_hwlro)
856 fwcmd->params.req.flush = OCE_FLUSH;
858 fwcmd->params.req.flush = 0;
860 fwcmd->params.req.if_id = LE_32(if_id);
862 read_random(fwcmd->params.req.hash, sizeof(fwcmd->params.req.hash));
864 rc = oce_rss_itbl_init(sc, fwcmd);
866 mbx.u0.s.embedded = 1;
867 mbx.payload_length = sizeof(struct mbx_config_nic_rss);
868 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
870 rc = oce_mbox_post(sc, &mbx, NULL);
872 rc = fwcmd->hdr.u0.rsp.status;
874 device_printf(sc->dev,
875 "%s failed - cmd status: %d addi status: %d\n",
877 fwcmd->hdr.u0.rsp.additional_status);
883 * @brief RXF function to enable/disable device promiscuous mode
884 * @param sc software handle to the device
885 * @param enable enable/disable flag
886 * @returns 0 on success, EIO on failure
888 * The NIC_CONFIG_PROMISCUOUS command deprecated for Lancer.
889 * This function uses the COMMON_SET_IFACE_RX_FILTER command instead.
892 oce_rxf_set_promiscuous(POCE_SOFTC sc, uint8_t enable)
894 struct mbx_set_common_iface_rx_filter *fwcmd;
895 int sz = sizeof(struct mbx_set_common_iface_rx_filter);
896 iface_rx_filter_ctx_t *req;
900 /* allocate mbx payload's dma scatter/gather memory */
901 rc = oce_dma_alloc(sc, sz, &sgl, 0);
905 fwcmd = OCE_DMAPTR(&sgl, struct mbx_set_common_iface_rx_filter);
907 req = &fwcmd->params.req;
908 req->iface_flags_mask = MBX_RX_IFACE_FLAGS_PROMISCUOUS |
909 MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS;
910 /* Bit 0 Mac promisc, Bit 1 Vlan promisc */
912 req->iface_flags = MBX_RX_IFACE_FLAGS_PROMISCUOUS;
915 req->iface_flags |= MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS;
917 req->if_id = sc->if_id;
919 rc = oce_set_common_iface_rx_filter(sc, &sgl);
920 oce_dma_free(sc, &sgl);
927 * @brief Function modify and select rx filter options
928 * @param sc software handle to the device
929 * @param sgl scatter/gather request/response
930 * @returns 0 on success, error code on failure
933 oce_set_common_iface_rx_filter(POCE_SOFTC sc, POCE_DMA_MEM sgl)
936 int mbx_sz = sizeof(struct mbx_set_common_iface_rx_filter);
937 struct mbx_set_common_iface_rx_filter *fwcmd;
940 bzero(&mbx, sizeof(struct oce_mbx));
941 fwcmd = OCE_DMAPTR(sgl, struct mbx_set_common_iface_rx_filter);
943 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
944 MBX_SUBSYSTEM_COMMON,
945 OPCODE_COMMON_SET_IFACE_RX_FILTER,
950 oce_dma_sync(sgl, BUS_DMASYNC_PREWRITE);
951 mbx.u0.s.embedded = 0;
952 mbx.u0.s.sge_count = 1;
953 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(sgl->paddr);
954 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(sgl->paddr);
955 mbx.payload.u0.u1.sgl[0].length = mbx_sz;
956 mbx.payload_length = mbx_sz;
957 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
959 rc = oce_mbox_post(sc, &mbx, NULL);
961 rc = fwcmd->hdr.u0.rsp.status;
963 device_printf(sc->dev,
964 "%s failed - cmd status: %d addi status: %d\n",
966 fwcmd->hdr.u0.rsp.additional_status);
971 * @brief Function to query the link status from the hardware
972 * @param sc software handle to the device
973 * @param[out] link pointer to the structure returning link attributes
974 * @returns 0 on success, EIO on failure
977 oce_get_link_status(POCE_SOFTC sc, struct link_status *link)
980 struct mbx_query_common_link_config *fwcmd;
983 bzero(&mbx, sizeof(struct oce_mbx));
985 IS_BE2(sc) ? (version = OCE_MBX_VER_V0) : (version = OCE_MBX_VER_V1);
987 fwcmd = (struct mbx_query_common_link_config *)&mbx.payload;
988 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
989 MBX_SUBSYSTEM_COMMON,
990 OPCODE_COMMON_QUERY_LINK_CONFIG,
992 sizeof(struct mbx_query_common_link_config),
995 mbx.u0.s.embedded = 1;
996 mbx.payload_length = sizeof(struct mbx_query_common_link_config);
997 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
999 rc = oce_mbox_post(sc, &mbx, NULL);
1002 rc = fwcmd->hdr.u0.rsp.status;
1004 device_printf(sc->dev,
1005 "%s failed - cmd status: %d addi status: %d\n",
1007 fwcmd->hdr.u0.rsp.additional_status);
1010 /* interpret response */
1011 link->qos_link_speed = HOST_16(fwcmd->params.rsp.qos_link_speed);
1012 link->phys_port_speed = fwcmd->params.rsp.physical_port_speed;
1013 link->logical_link_status = fwcmd->params.rsp.logical_link_status;
1020 * @brief Function to get NIC statistics
1021 * @param sc software handle to the device
1022 * @param *stats pointer to where to store statistics
1023 * @param reset_stats resets statistics of set
1024 * @returns 0 on success, EIO on failure
1025 * @note command depricated in Lancer
1027 #define OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, version) \
1029 oce_mbox_get_nic_stats_v##version(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem) \
1031 struct oce_mbx mbx; \
1032 struct mbx_get_nic_stats_v##version *fwcmd; \
1035 bzero(&mbx, sizeof(struct oce_mbx)); \
1036 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_nic_stats_v##version); \
1037 bzero(fwcmd, sizeof(*fwcmd)); \
1039 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, \
1040 MBX_SUBSYSTEM_NIC, \
1044 OCE_MBX_VER_V##version); \
1046 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */ \
1047 mbx.u0.s.sge_count = 1; /* using scatter gather instead */ \
1049 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE); \
1050 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr); \
1051 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr); \
1052 mbx.payload.u0.u1.sgl[0].length = sizeof(*fwcmd); \
1053 mbx.payload_length = sizeof(*fwcmd); \
1054 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); \
1056 rc = oce_mbox_post(sc, &mbx, NULL); \
1057 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE); \
1059 rc = fwcmd->hdr.u0.rsp.status; \
1061 device_printf(sc->dev, \
1062 "%s failed - cmd status: %d addi status: %d\n", \
1064 fwcmd->hdr.u0.rsp.additional_status); \
1068 OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, 0);
1069 OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, 1);
1070 OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, 2);
1074 * @brief Function to get pport (physical port) statistics
1075 * @param sc software handle to the device
1076 * @param *stats pointer to where to store statistics
1077 * @param reset_stats resets statistics of set
1078 * @returns 0 on success, EIO on failure
1081 oce_mbox_get_pport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1082 uint32_t reset_stats)
1085 struct mbx_get_pport_stats *fwcmd;
1088 bzero(&mbx, sizeof(struct oce_mbx));
1089 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_pport_stats);
1090 bzero(fwcmd, sizeof(struct mbx_get_pport_stats));
1092 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1094 NIC_GET_PPORT_STATS,
1096 sizeof(struct mbx_get_pport_stats),
1099 fwcmd->params.req.reset_stats = reset_stats;
1100 fwcmd->params.req.port_number = sc->port_id;
1102 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */
1103 mbx.u0.s.sge_count = 1; /* using scatter gather instead */
1105 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE);
1106 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr);
1107 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr);
1108 mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_pport_stats);
1110 mbx.payload_length = sizeof(struct mbx_get_pport_stats);
1111 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1113 rc = oce_mbox_post(sc, &mbx, NULL);
1114 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE);
1117 rc = fwcmd->hdr.u0.rsp.status;
1119 device_printf(sc->dev,
1120 "%s failed - cmd status: %d addi status: %d\n",
1122 fwcmd->hdr.u0.rsp.additional_status);
1128 * @brief Function to get vport (virtual port) statistics
1129 * @param sc software handle to the device
1130 * @param *stats pointer to where to store statistics
1131 * @param reset_stats resets statistics of set
1132 * @returns 0 on success, EIO on failure
1135 oce_mbox_get_vport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1136 uint32_t req_size, uint32_t reset_stats)
1139 struct mbx_get_vport_stats *fwcmd;
1142 bzero(&mbx, sizeof(struct oce_mbx));
1144 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_vport_stats);
1145 bzero(fwcmd, sizeof(struct mbx_get_vport_stats));
1147 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1149 NIC_GET_VPORT_STATS,
1151 sizeof(struct mbx_get_vport_stats),
1154 fwcmd->params.req.reset_stats = reset_stats;
1155 fwcmd->params.req.vport_number = sc->if_id;
1157 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */
1158 mbx.u0.s.sge_count = 1; /* using scatter gather instead */
1160 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE);
1161 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr);
1162 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr);
1163 mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_vport_stats);
1165 mbx.payload_length = sizeof(struct mbx_get_vport_stats);
1166 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1168 rc = oce_mbox_post(sc, &mbx, NULL);
1169 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE);
1172 rc = fwcmd->hdr.u0.rsp.status;
1174 device_printf(sc->dev,
1175 "%s failed - cmd status: %d addi status: %d\n",
1177 fwcmd->hdr.u0.rsp.additional_status);
1183 * @brief Function to update the muticast filter with
1185 * @param sc software handle to the device
1186 * @param dma_mem pointer to dma memory region
1187 * @returns 0 on success, EIO on failure
1190 oce_update_multicast(POCE_SOFTC sc, POCE_DMA_MEM pdma_mem)
1193 struct oce_mq_sge *sgl;
1194 struct mbx_set_common_iface_multicast *req = NULL;
1197 req = OCE_DMAPTR(pdma_mem, struct mbx_set_common_iface_multicast);
1198 mbx_common_req_hdr_init(&req->hdr, 0, 0,
1199 MBX_SUBSYSTEM_COMMON,
1200 OPCODE_COMMON_SET_IFACE_MULTICAST,
1202 sizeof(struct mbx_set_common_iface_multicast),
1205 bzero(&mbx, sizeof(struct oce_mbx));
1207 mbx.u0.s.embedded = 0; /*Non embeded*/
1208 mbx.payload_length = sizeof(struct mbx_set_common_iface_multicast);
1209 mbx.u0.s.sge_count = 1;
1210 sgl = &mbx.payload.u0.u1.sgl[0];
1211 sgl->pa_hi = htole32(upper_32_bits(pdma_mem->paddr));
1212 sgl->pa_lo = htole32((pdma_mem->paddr) & 0xFFFFFFFF);
1213 sgl->length = htole32(mbx.payload_length);
1215 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1217 rc = oce_mbox_post(sc, &mbx, NULL);
1219 rc = req->hdr.u0.rsp.status;
1221 device_printf(sc->dev,
1222 "%s failed - cmd status: %d addi status: %d\n",
1224 req->hdr.u0.rsp.additional_status);
1230 * @brief Function to send passthrough Ioctls
1231 * @param sc software handle to the device
1232 * @param dma_mem pointer to dma memory region
1233 * @param req_size size of dma_mem
1234 * @returns 0 on success, EIO on failure
1237 oce_pass_through_mbox(POCE_SOFTC sc, POCE_DMA_MEM dma_mem, uint32_t req_size)
1240 struct oce_mq_sge *sgl;
1243 bzero(&mbx, sizeof(struct oce_mbx));
1245 mbx.u0.s.embedded = 0; /*Non embeded*/
1246 mbx.payload_length = req_size;
1247 mbx.u0.s.sge_count = 1;
1248 sgl = &mbx.payload.u0.u1.sgl[0];
1249 sgl->pa_hi = htole32(upper_32_bits(dma_mem->paddr));
1250 sgl->pa_lo = htole32((dma_mem->paddr) & 0xFFFFFFFF);
1251 sgl->length = htole32(req_size);
1253 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1255 rc = oce_mbox_post(sc, &mbx, NULL);
1261 oce_mbox_macaddr_add(POCE_SOFTC sc, uint8_t *mac_addr,
1262 uint32_t if_id, uint32_t *pmac_id)
1265 struct mbx_add_common_iface_mac *fwcmd;
1268 bzero(&mbx, sizeof(struct oce_mbx));
1270 fwcmd = (struct mbx_add_common_iface_mac *)&mbx.payload;
1271 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1272 MBX_SUBSYSTEM_COMMON,
1273 OPCODE_COMMON_ADD_IFACE_MAC,
1275 sizeof(struct mbx_add_common_iface_mac),
1278 fwcmd->params.req.if_id = (uint16_t) if_id;
1279 bcopy(mac_addr, fwcmd->params.req.mac_address, 6);
1281 mbx.u0.s.embedded = 1;
1282 mbx.payload_length = sizeof(struct mbx_add_common_iface_mac);
1283 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1284 rc = oce_mbox_post(sc, &mbx, NULL);
1286 rc = fwcmd->hdr.u0.rsp.status;
1288 device_printf(sc->dev,
1289 "%s failed - cmd status: %d addi status: %d\n",
1291 fwcmd->hdr.u0.rsp.additional_status);
1294 *pmac_id = fwcmd->params.rsp.pmac_id;
1301 oce_mbox_macaddr_del(POCE_SOFTC sc, uint32_t if_id, uint32_t pmac_id)
1304 struct mbx_del_common_iface_mac *fwcmd;
1307 bzero(&mbx, sizeof(struct oce_mbx));
1309 fwcmd = (struct mbx_del_common_iface_mac *)&mbx.payload;
1310 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1311 MBX_SUBSYSTEM_COMMON,
1312 OPCODE_COMMON_DEL_IFACE_MAC,
1314 sizeof(struct mbx_del_common_iface_mac),
1317 fwcmd->params.req.if_id = (uint16_t)if_id;
1318 fwcmd->params.req.pmac_id = pmac_id;
1320 mbx.u0.s.embedded = 1;
1321 mbx.payload_length = sizeof(struct mbx_del_common_iface_mac);
1322 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1324 rc = oce_mbox_post(sc, &mbx, NULL);
1326 rc = fwcmd->hdr.u0.rsp.status;
1328 device_printf(sc->dev,
1329 "%s failed - cmd status: %d addi status: %d\n",
1331 fwcmd->hdr.u0.rsp.additional_status);
1338 oce_mbox_check_native_mode(POCE_SOFTC sc)
1341 struct mbx_common_set_function_cap *fwcmd;
1344 bzero(&mbx, sizeof(struct oce_mbx));
1346 fwcmd = (struct mbx_common_set_function_cap *)&mbx.payload;
1347 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1348 MBX_SUBSYSTEM_COMMON,
1349 OPCODE_COMMON_SET_FUNCTIONAL_CAPS,
1351 sizeof(struct mbx_common_set_function_cap),
1354 fwcmd->params.req.valid_capability_flags = CAP_SW_TIMESTAMPS |
1355 CAP_BE3_NATIVE_ERX_API;
1357 fwcmd->params.req.capability_flags = CAP_BE3_NATIVE_ERX_API;
1359 mbx.u0.s.embedded = 1;
1360 mbx.payload_length = sizeof(struct mbx_common_set_function_cap);
1361 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1363 rc = oce_mbox_post(sc, &mbx, NULL);
1365 rc = fwcmd->hdr.u0.rsp.status;
1367 device_printf(sc->dev,
1368 "%s failed - cmd status: %d addi status: %d\n",
1370 fwcmd->hdr.u0.rsp.additional_status);
1373 sc->be3_native = HOST_32(fwcmd->params.rsp.capability_flags)
1374 & CAP_BE3_NATIVE_ERX_API;
1383 oce_mbox_cmd_set_loopback(POCE_SOFTC sc, uint8_t port_num,
1384 uint8_t loopback_type, uint8_t enable)
1387 struct mbx_lowlevel_set_loopback_mode *fwcmd;
1391 bzero(&mbx, sizeof(struct oce_mbx));
1393 fwcmd = (struct mbx_lowlevel_set_loopback_mode *)&mbx.payload;
1394 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1395 MBX_SUBSYSTEM_LOWLEVEL,
1396 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
1398 sizeof(struct mbx_lowlevel_set_loopback_mode),
1401 fwcmd->params.req.src_port = port_num;
1402 fwcmd->params.req.dest_port = port_num;
1403 fwcmd->params.req.loopback_type = loopback_type;
1404 fwcmd->params.req.loopback_state = enable;
1406 mbx.u0.s.embedded = 1;
1407 mbx.payload_length = sizeof(struct mbx_lowlevel_set_loopback_mode);
1408 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1410 rc = oce_mbox_post(sc, &mbx, NULL);
1412 rc = fwcmd->hdr.u0.rsp.status;
1414 device_printf(sc->dev,
1415 "%s failed - cmd status: %d addi status: %d\n",
1417 fwcmd->hdr.u0.rsp.additional_status);
1424 oce_mbox_cmd_test_loopback(POCE_SOFTC sc, uint32_t port_num,
1425 uint32_t loopback_type, uint32_t pkt_size, uint32_t num_pkts,
1430 struct mbx_lowlevel_test_loopback_mode *fwcmd;
1434 bzero(&mbx, sizeof(struct oce_mbx));
1436 fwcmd = (struct mbx_lowlevel_test_loopback_mode *)&mbx.payload;
1437 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1438 MBX_SUBSYSTEM_LOWLEVEL,
1439 OPCODE_LOWLEVEL_TEST_LOOPBACK,
1441 sizeof(struct mbx_lowlevel_test_loopback_mode),
1444 fwcmd->params.req.pattern = pattern;
1445 fwcmd->params.req.src_port = port_num;
1446 fwcmd->params.req.dest_port = port_num;
1447 fwcmd->params.req.pkt_size = pkt_size;
1448 fwcmd->params.req.num_pkts = num_pkts;
1449 fwcmd->params.req.loopback_type = loopback_type;
1451 mbx.u0.s.embedded = 1;
1452 mbx.payload_length = sizeof(struct mbx_lowlevel_test_loopback_mode);
1453 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1455 rc = oce_mbox_post(sc, &mbx, NULL);
1457 rc = fwcmd->hdr.u0.rsp.status;
1459 device_printf(sc->dev,
1460 "%s failed - cmd status: %d addi status: %d\n",
1462 fwcmd->hdr.u0.rsp.additional_status);
1468 oce_mbox_write_flashrom(POCE_SOFTC sc, uint32_t optype,uint32_t opcode,
1469 POCE_DMA_MEM pdma_mem, uint32_t num_bytes)
1473 struct oce_mq_sge *sgl = NULL;
1474 struct mbx_common_read_write_flashrom *fwcmd = NULL;
1475 int rc = 0, payload_len = 0;
1477 bzero(&mbx, sizeof(struct oce_mbx));
1478 fwcmd = OCE_DMAPTR(pdma_mem, struct mbx_common_read_write_flashrom);
1479 payload_len = sizeof(struct mbx_common_read_write_flashrom) + 32*1024;
1481 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1482 MBX_SUBSYSTEM_COMMON,
1483 OPCODE_COMMON_WRITE_FLASHROM,
1488 fwcmd->flash_op_type = LE_32(optype);
1489 fwcmd->flash_op_code = LE_32(opcode);
1490 fwcmd->data_buffer_size = LE_32(num_bytes);
1492 mbx.u0.s.embedded = 0; /*Non embeded*/
1493 mbx.payload_length = payload_len;
1494 mbx.u0.s.sge_count = 1;
1496 sgl = &mbx.payload.u0.u1.sgl[0];
1497 sgl->pa_hi = upper_32_bits(pdma_mem->paddr);
1498 sgl->pa_lo = pdma_mem->paddr & 0xFFFFFFFF;
1499 sgl->length = payload_len;
1501 /* post the command */
1502 rc = oce_mbox_post(sc, &mbx, NULL);
1504 rc = fwcmd->hdr.u0.rsp.status;
1506 device_printf(sc->dev,
1507 "%s failed - cmd status: %d addi status: %d\n",
1509 fwcmd->hdr.u0.rsp.additional_status);
1516 oce_mbox_get_flashrom_crc(POCE_SOFTC sc, uint8_t *flash_crc,
1517 uint32_t offset, uint32_t optype)
1520 int rc = 0, payload_len = 0;
1522 struct mbx_common_read_write_flashrom *fwcmd;
1524 bzero(&mbx, sizeof(struct oce_mbx));
1526 fwcmd = (struct mbx_common_read_write_flashrom *)&mbx.payload;
1528 /* Firmware requires extra 4 bytes with this ioctl. Since there
1529 is enough room in the mbx payload it should be good enough
1530 Reference: Bug 14853
1532 payload_len = sizeof(struct mbx_common_read_write_flashrom) + 4;
1534 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1535 MBX_SUBSYSTEM_COMMON,
1536 OPCODE_COMMON_READ_FLASHROM,
1541 fwcmd->flash_op_type = optype;
1542 fwcmd->flash_op_code = FLASHROM_OPER_REPORT;
1543 fwcmd->data_offset = offset;
1544 fwcmd->data_buffer_size = 0x4;
1546 mbx.u0.s.embedded = 1;
1547 mbx.payload_length = payload_len;
1549 /* post the command */
1550 rc = oce_mbox_post(sc, &mbx, NULL);
1552 rc = fwcmd->hdr.u0.rsp.status;
1554 device_printf(sc->dev,
1555 "%s failed - cmd status: %d addi status: %d\n",
1557 fwcmd->hdr.u0.rsp.additional_status);
1560 bcopy(fwcmd->data_buffer, flash_crc, 4);
1566 oce_mbox_get_phy_info(POCE_SOFTC sc, struct oce_phy_info *phy_info)
1570 struct mbx_common_phy_info *fwcmd;
1573 bzero(&mbx, sizeof(struct oce_mbx));
1575 fwcmd = (struct mbx_common_phy_info *)&mbx.payload;
1576 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1577 MBX_SUBSYSTEM_COMMON,
1578 OPCODE_COMMON_GET_PHY_CONFIG,
1580 sizeof(struct mbx_common_phy_info),
1583 mbx.u0.s.embedded = 1;
1584 mbx.payload_length = sizeof(struct mbx_common_phy_info);
1586 /* now post the command */
1587 rc = oce_mbox_post(sc, &mbx, NULL);
1589 rc = fwcmd->hdr.u0.rsp.status;
1591 device_printf(sc->dev,
1592 "%s failed - cmd status: %d addi status: %d\n",
1594 fwcmd->hdr.u0.rsp.additional_status);
1597 phy_info->phy_type = HOST_16(fwcmd->params.rsp.phy_info.phy_type);
1598 phy_info->interface_type =
1599 HOST_16(fwcmd->params.rsp.phy_info.interface_type);
1600 phy_info->auto_speeds_supported =
1601 HOST_16(fwcmd->params.rsp.phy_info.auto_speeds_supported);
1602 phy_info->fixed_speeds_supported =
1603 HOST_16(fwcmd->params.rsp.phy_info.fixed_speeds_supported);
1604 phy_info->misc_params = HOST_32(fwcmd->params.rsp.phy_info.misc_params);
1612 oce_mbox_lancer_write_flashrom(POCE_SOFTC sc, uint32_t data_size,
1613 uint32_t data_offset, POCE_DMA_MEM pdma_mem,
1614 uint32_t *written_data, uint32_t *additional_status)
1618 struct mbx_lancer_common_write_object *fwcmd = NULL;
1619 int rc = 0, payload_len = 0;
1621 bzero(&mbx, sizeof(struct oce_mbx));
1622 payload_len = sizeof(struct mbx_lancer_common_write_object);
1624 mbx.u0.s.embedded = 1;/* Embedded */
1625 mbx.payload_length = payload_len;
1626 fwcmd = (struct mbx_lancer_common_write_object *)&mbx.payload;
1628 /* initialize the ioctl header */
1629 mbx_common_req_hdr_init(&fwcmd->params.req.hdr, 0, 0,
1630 MBX_SUBSYSTEM_COMMON,
1631 OPCODE_COMMON_WRITE_OBJECT,
1636 fwcmd->params.req.write_length = data_size;
1638 fwcmd->params.req.eof = 1;
1640 fwcmd->params.req.eof = 0;
1642 strcpy(fwcmd->params.req.object_name, "/prg");
1643 fwcmd->params.req.descriptor_count = 1;
1644 fwcmd->params.req.write_offset = data_offset;
1645 fwcmd->params.req.buffer_length = data_size;
1646 fwcmd->params.req.address_lower = pdma_mem->paddr & 0xFFFFFFFF;
1647 fwcmd->params.req.address_upper = upper_32_bits(pdma_mem->paddr);
1649 /* post the command */
1650 rc = oce_mbox_post(sc, &mbx, NULL);
1652 rc = fwcmd->params.rsp.status;
1654 device_printf(sc->dev,
1655 "%s failed - cmd status: %d addi status: %d\n",
1657 fwcmd->params.rsp.additional_status);
1660 *written_data = HOST_32(fwcmd->params.rsp.actual_write_length);
1661 *additional_status = fwcmd->params.rsp.additional_status;
1670 oce_mbox_create_rq(struct oce_rq *rq)
1674 struct mbx_create_nic_rq *fwcmd;
1675 POCE_SOFTC sc = rq->parent;
1676 int rc, num_pages = 0;
1678 if (rq->qstate == QCREATED)
1681 bzero(&mbx, sizeof(struct oce_mbx));
1683 fwcmd = (struct mbx_create_nic_rq *)&mbx.payload;
1684 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1686 NIC_CREATE_RQ, MBX_TIMEOUT_SEC,
1687 sizeof(struct mbx_create_nic_rq),
1690 /* oce_page_list will also prepare pages */
1691 num_pages = oce_page_list(rq->ring, &fwcmd->params.req.pages[0]);
1694 fwcmd->params.req.frag_size = rq->cfg.frag_size/2048;
1695 fwcmd->params.req.page_size = 1;
1696 fwcmd->hdr.u0.req.version = OCE_MBX_VER_V1;
1698 fwcmd->params.req.frag_size = OCE_LOG2(rq->cfg.frag_size);
1699 fwcmd->params.req.num_pages = num_pages;
1700 fwcmd->params.req.cq_id = rq->cq->cq_id;
1701 fwcmd->params.req.if_id = sc->if_id;
1702 fwcmd->params.req.max_frame_size = rq->cfg.mtu;
1703 fwcmd->params.req.is_rss_queue = rq->cfg.is_rss_queue;
1705 mbx.u0.s.embedded = 1;
1706 mbx.payload_length = sizeof(struct mbx_create_nic_rq);
1708 rc = oce_mbox_post(sc, &mbx, NULL);
1710 rc = fwcmd->hdr.u0.rsp.status;
1712 device_printf(sc->dev,
1713 "%s failed - cmd status: %d addi status: %d\n",
1715 fwcmd->hdr.u0.rsp.additional_status);
1718 rq->rq_id = HOST_16(fwcmd->params.rsp.rq_id);
1719 rq->rss_cpuid = fwcmd->params.rsp.rss_cpuid;
1728 oce_mbox_create_wq(struct oce_wq *wq)
1731 struct mbx_create_nic_wq *fwcmd;
1732 POCE_SOFTC sc = wq->parent;
1733 int rc = 0, version, num_pages;
1735 bzero(&mbx, sizeof(struct oce_mbx));
1737 fwcmd = (struct mbx_create_nic_wq *)&mbx.payload;
1739 version = OCE_MBX_VER_V1;
1741 IS_PROFILE_SUPER_NIC(sc) ? (version = OCE_MBX_VER_V2)
1742 : (version = OCE_MBX_VER_V0);
1744 version = OCE_MBX_VER_V2;
1746 if (version > OCE_MBX_VER_V0)
1747 fwcmd->params.req.if_id = sc->if_id;
1749 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1751 NIC_CREATE_WQ, MBX_TIMEOUT_SEC,
1752 sizeof(struct mbx_create_nic_wq),
1755 num_pages = oce_page_list(wq->ring, &fwcmd->params.req.pages[0]);
1757 fwcmd->params.req.nic_wq_type = wq->cfg.wq_type;
1758 fwcmd->params.req.num_pages = num_pages;
1759 fwcmd->params.req.wq_size = OCE_LOG2(wq->cfg.q_len) + 1;
1760 fwcmd->params.req.cq_id = wq->cq->cq_id;
1761 fwcmd->params.req.ulp_num = 1;
1763 mbx.u0.s.embedded = 1;
1764 mbx.payload_length = sizeof(struct mbx_create_nic_wq);
1766 rc = oce_mbox_post(sc, &mbx, NULL);
1768 rc = fwcmd->hdr.u0.rsp.status;
1770 device_printf(sc->dev,
1771 "%s failed - cmd status: %d addi status: %d\n",
1773 fwcmd->hdr.u0.rsp.additional_status);
1776 wq->wq_id = HOST_16(fwcmd->params.rsp.wq_id);
1777 if (version == OCE_MBX_VER_V2)
1778 wq->db_offset = HOST_32(fwcmd->params.rsp.db_offset);
1780 wq->db_offset = PD_TXULP_DB;
1789 oce_mbox_create_eq(struct oce_eq *eq)
1792 struct mbx_create_common_eq *fwcmd;
1793 POCE_SOFTC sc = eq->parent;
1797 bzero(&mbx, sizeof(struct oce_mbx));
1799 fwcmd = (struct mbx_create_common_eq *)&mbx.payload;
1801 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1802 MBX_SUBSYSTEM_COMMON,
1803 OPCODE_COMMON_CREATE_EQ, MBX_TIMEOUT_SEC,
1804 sizeof(struct mbx_create_common_eq),
1807 num_pages = oce_page_list(eq->ring, &fwcmd->params.req.pages[0]);
1808 fwcmd->params.req.ctx.num_pages = num_pages;
1809 fwcmd->params.req.ctx.valid = 1;
1810 fwcmd->params.req.ctx.size = (eq->eq_cfg.item_size == 4) ? 0 : 1;
1811 fwcmd->params.req.ctx.count = OCE_LOG2(eq->eq_cfg.q_len / 256);
1812 fwcmd->params.req.ctx.armed = 0;
1813 fwcmd->params.req.ctx.delay_mult = eq->eq_cfg.cur_eqd;
1816 mbx.u0.s.embedded = 1;
1817 mbx.payload_length = sizeof(struct mbx_create_common_eq);
1819 rc = oce_mbox_post(sc, &mbx, NULL);
1821 rc = fwcmd->hdr.u0.rsp.status;
1823 device_printf(sc->dev,
1824 "%s failed - cmd status: %d addi status: %d\n",
1826 fwcmd->hdr.u0.rsp.additional_status);
1829 eq->eq_id = HOST_16(fwcmd->params.rsp.eq_id);
1837 oce_mbox_cq_create(struct oce_cq *cq, uint32_t ncoalesce, uint32_t is_eventable)
1840 struct mbx_create_common_cq *fwcmd;
1841 POCE_SOFTC sc = cq->parent;
1844 uint32_t num_pages, page_size;
1848 bzero(&mbx, sizeof(struct oce_mbx));
1850 fwcmd = (struct mbx_create_common_cq *)&mbx.payload;
1853 version = OCE_MBX_VER_V2;
1855 version = OCE_MBX_VER_V0;
1857 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1858 MBX_SUBSYSTEM_COMMON,
1859 OPCODE_COMMON_CREATE_CQ,
1861 sizeof(struct mbx_create_common_cq),
1864 ctx = &fwcmd->params.req.cq_ctx;
1866 num_pages = oce_page_list(cq->ring, &fwcmd->params.req.pages[0]);
1867 page_size = 1; /* 1 for 4K */
1869 if (version == OCE_MBX_VER_V2) {
1870 ctx->v2.num_pages = LE_16(num_pages);
1871 ctx->v2.page_size = page_size;
1872 ctx->v2.eventable = is_eventable;
1874 ctx->v2.count = OCE_LOG2(cq->cq_cfg.q_len / 256);
1875 ctx->v2.nodelay = cq->cq_cfg.nodelay;
1876 ctx->v2.coalesce_wm = ncoalesce;
1878 ctx->v2.eq_id = cq->eq->eq_id;
1879 if (ctx->v2.count == 3) {
1880 if ((u_int)cq->cq_cfg.q_len > (4*1024)-1)
1881 ctx->v2.cqe_count = (4*1024)-1;
1883 ctx->v2.cqe_count = cq->cq_cfg.q_len;
1886 ctx->v0.num_pages = LE_16(num_pages);
1887 ctx->v0.eventable = is_eventable;
1889 ctx->v0.count = OCE_LOG2(cq->cq_cfg.q_len / 256);
1890 ctx->v0.nodelay = cq->cq_cfg.nodelay;
1891 ctx->v0.coalesce_wm = ncoalesce;
1893 ctx->v0.eq_id = cq->eq->eq_id;
1896 mbx.u0.s.embedded = 1;
1897 mbx.payload_length = sizeof(struct mbx_create_common_cq);
1899 rc = oce_mbox_post(sc, &mbx, NULL);
1901 rc = fwcmd->hdr.u0.rsp.status;
1903 device_printf(sc->dev,
1904 "%s failed - cmd status: %d addi status: %d\n",
1906 fwcmd->hdr.u0.rsp.additional_status);
1909 cq->cq_id = HOST_16(fwcmd->params.rsp.cq_id);
1916 oce_mbox_read_transrecv_data(POCE_SOFTC sc, uint32_t page_num)
1920 struct mbx_read_common_transrecv_data *fwcmd;
1921 struct oce_mq_sge *sgl;
1924 /* Allocate DMA mem*/
1925 if (oce_dma_alloc(sc, sizeof(struct mbx_read_common_transrecv_data),
1929 fwcmd = OCE_DMAPTR(&dma, struct mbx_read_common_transrecv_data);
1930 bzero(fwcmd, sizeof(struct mbx_read_common_transrecv_data));
1932 bzero(&mbx, sizeof(struct oce_mbx));
1933 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1934 MBX_SUBSYSTEM_COMMON,
1935 OPCODE_COMMON_READ_TRANSRECEIVER_DATA,
1937 sizeof(struct mbx_read_common_transrecv_data),
1940 /* fill rest of mbx */
1941 mbx.u0.s.embedded = 0;
1942 mbx.payload_length = sizeof(struct mbx_read_common_transrecv_data);
1943 mbx.u0.s.sge_count = 1;
1944 sgl = &mbx.payload.u0.u1.sgl[0];
1945 sgl->pa_hi = htole32(upper_32_bits(dma.paddr));
1946 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF);
1947 sgl->length = htole32(mbx.payload_length);
1948 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1950 fwcmd->params.req.port = LE_32(sc->port_id);
1951 fwcmd->params.req.page_num = LE_32(page_num);
1954 rc = oce_mbox_post(sc, &mbx, NULL);
1956 rc = fwcmd->hdr.u0.rsp.status;
1958 device_printf(sc->dev,
1959 "%s failed - cmd status: %d addi status: %d\n",
1961 fwcmd->hdr.u0.rsp.additional_status);
1964 if(fwcmd->params.rsp.page_num == PAGE_NUM_A0)
1966 bcopy((char *)fwcmd->params.rsp.page_data,
1967 &sfp_vpd_dump_buffer[0],
1968 TRANSCEIVER_A0_SIZE);
1971 if(fwcmd->params.rsp.page_num == PAGE_NUM_A2)
1973 bcopy((char *)fwcmd->params.rsp.page_data,
1974 &sfp_vpd_dump_buffer[TRANSCEIVER_A0_SIZE],
1975 TRANSCEIVER_A2_SIZE);
1978 oce_dma_free(sc, &dma);
1983 oce_mbox_eqd_modify_periodic(POCE_SOFTC sc, struct oce_set_eqd *set_eqd,
1987 struct mbx_modify_common_eq_delay *fwcmd;
1991 bzero(&mbx, sizeof(struct oce_mbx));
1993 /* Initialize MODIFY_EQ_DELAY ioctl header */
1994 fwcmd = (struct mbx_modify_common_eq_delay *)&mbx.payload;
1995 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1996 MBX_SUBSYSTEM_COMMON,
1997 OPCODE_COMMON_MODIFY_EQ_DELAY,
1999 sizeof(struct mbx_modify_common_eq_delay),
2001 /* fill rest of mbx */
2002 mbx.u0.s.embedded = 1;
2003 mbx.payload_length = sizeof(struct mbx_modify_common_eq_delay);
2004 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
2006 fwcmd->params.req.num_eq = num;
2007 for (i = 0; i < num; i++) {
2008 fwcmd->params.req.delay[i].eq_id =
2009 htole32(set_eqd[i].eq_id);
2010 fwcmd->params.req.delay[i].phase = 0;
2011 fwcmd->params.req.delay[i].dm =
2012 htole32(set_eqd[i].delay_multiplier);
2017 rc = oce_mbox_post(sc, &mbx, NULL);
2020 rc = fwcmd->hdr.u0.rsp.status;
2022 device_printf(sc->dev,
2023 "%s failed - cmd status: %d addi status: %d\n",
2025 fwcmd->hdr.u0.rsp.additional_status);
2029 oce_get_profile_config(POCE_SOFTC sc, uint32_t max_rss)
2032 struct mbx_common_get_profile_config *fwcmd;
2035 struct oce_mq_sge *sgl;
2037 uint32_t desc_count = 0;
2038 struct oce_nic_resc_desc *nic_desc = NULL;
2040 boolean_t nic_desc_valid = FALSE;
2045 /* Allocate DMA mem*/
2046 if (oce_dma_alloc(sc, sizeof(struct mbx_common_get_profile_config),
2050 /* Initialize MODIFY_EQ_DELAY ioctl header */
2051 fwcmd = OCE_DMAPTR(&dma, struct mbx_common_get_profile_config);
2052 bzero(fwcmd, sizeof(struct mbx_common_get_profile_config));
2055 version = OCE_MBX_VER_V1;
2057 version = OCE_MBX_VER_V0;
2059 bzero(&mbx, sizeof(struct oce_mbx));
2060 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
2061 MBX_SUBSYSTEM_COMMON,
2062 OPCODE_COMMON_GET_PROFILE_CONFIG,
2064 sizeof(struct mbx_common_get_profile_config),
2066 /* fill rest of mbx */
2067 mbx.u0.s.embedded = 0;
2068 mbx.payload_length = sizeof(struct mbx_common_get_profile_config);
2069 mbx.u0.s.sge_count = 1;
2070 sgl = &mbx.payload.u0.u1.sgl[0];
2071 sgl->pa_hi = htole32(upper_32_bits(dma.paddr));
2072 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF);
2073 sgl->length = htole32(mbx.payload_length);
2074 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
2076 fwcmd->params.req.type = ACTIVE_PROFILE;
2079 rc = oce_mbox_post(sc, &mbx, NULL);
2081 rc = fwcmd->hdr.u0.rsp.status;
2083 device_printf(sc->dev,
2084 "%s failed - cmd status: %d addi status: %d\n",
2086 fwcmd->hdr.u0.rsp.additional_status);
2090 nic_desc = (struct oce_nic_resc_desc *) fwcmd->params.rsp.resources;
2091 desc_count = HOST_32(fwcmd->params.rsp.desc_count);
2092 for (i = 0; i < desc_count; i++) {
2093 if ((nic_desc->desc_type == NIC_RESC_DESC_TYPE_V0) ||
2094 (nic_desc->desc_type == NIC_RESC_DESC_TYPE_V1)) {
2095 nic_desc_valid = TRUE;
2098 nic_desc = (struct oce_nic_resc_desc *) \
2099 ((char *)nic_desc + nic_desc->desc_len);
2101 if (!nic_desc_valid) {
2106 sc->max_vlans = HOST_16(nic_desc->vlan_count);
2107 sc->nwqs = HOST_16(nic_desc->txq_count);
2109 sc->nwqs = MIN(sc->nwqs, OCE_MAX_WQ);
2111 sc->nwqs = OCE_MAX_WQ;
2113 sc->nrssqs = HOST_16(nic_desc->rssq_count);
2115 sc->nrssqs = MIN(sc->nrssqs, max_rss);
2117 sc->nrssqs = max_rss;
2118 sc->nrqs = sc->nrssqs + 1; /* 1 for def RX */
2122 oce_dma_free(sc, &dma);
2128 oce_get_func_config(POCE_SOFTC sc)
2131 struct mbx_common_get_func_config *fwcmd;
2134 struct oce_mq_sge *sgl;
2136 uint32_t desc_count = 0;
2137 struct oce_nic_resc_desc *nic_desc = NULL;
2139 boolean_t nic_desc_valid = FALSE;
2140 uint32_t max_rss = 0;
2142 if ((IS_BE(sc) || IS_SH(sc)) && (!sc->be3_native))
2143 max_rss = OCE_LEGACY_MODE_RSS;
2145 max_rss = OCE_MAX_RSS;
2147 /* Allocate DMA mem*/
2148 if (oce_dma_alloc(sc, sizeof(struct mbx_common_get_func_config),
2152 /* Initialize MODIFY_EQ_DELAY ioctl header */
2153 fwcmd = OCE_DMAPTR(&dma, struct mbx_common_get_func_config);
2154 bzero(fwcmd, sizeof(struct mbx_common_get_func_config));
2157 version = OCE_MBX_VER_V1;
2159 version = OCE_MBX_VER_V0;
2161 bzero(&mbx, sizeof(struct oce_mbx));
2162 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
2163 MBX_SUBSYSTEM_COMMON,
2164 OPCODE_COMMON_GET_FUNCTION_CONFIG,
2166 sizeof(struct mbx_common_get_func_config),
2168 /* fill rest of mbx */
2169 mbx.u0.s.embedded = 0;
2170 mbx.payload_length = sizeof(struct mbx_common_get_func_config);
2171 mbx.u0.s.sge_count = 1;
2172 sgl = &mbx.payload.u0.u1.sgl[0];
2173 sgl->pa_hi = htole32(upper_32_bits(dma.paddr));
2174 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF);
2175 sgl->length = htole32(mbx.payload_length);
2176 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
2179 rc = oce_mbox_post(sc, &mbx, NULL);
2181 rc = fwcmd->hdr.u0.rsp.status;
2183 device_printf(sc->dev,
2184 "%s failed - cmd status: %d addi status: %d\n",
2186 fwcmd->hdr.u0.rsp.additional_status);
2190 nic_desc = (struct oce_nic_resc_desc *) fwcmd->params.rsp.resources;
2191 desc_count = HOST_32(fwcmd->params.rsp.desc_count);
2192 for (i = 0; i < desc_count; i++) {
2193 if ((nic_desc->desc_type == NIC_RESC_DESC_TYPE_V0) ||
2194 (nic_desc->desc_type == NIC_RESC_DESC_TYPE_V1)) {
2195 nic_desc_valid = TRUE;
2198 nic_desc = (struct oce_nic_resc_desc *) \
2199 ((char *)nic_desc + nic_desc->desc_len);
2201 if (!nic_desc_valid) {
2206 sc->max_vlans = nic_desc->vlan_count;
2207 sc->nwqs = HOST_32(nic_desc->txq_count);
2209 sc->nwqs = MIN(sc->nwqs, OCE_MAX_WQ);
2211 sc->nwqs = OCE_MAX_WQ;
2213 sc->nrssqs = HOST_32(nic_desc->rssq_count);
2215 sc->nrssqs = MIN(sc->nrssqs, max_rss);
2217 sc->nrssqs = max_rss;
2218 sc->nrqs = sc->nrssqs + 1; /* 1 for def RX */
2221 oce_dma_free(sc, &dma);
2226 /* hw lro functions */
2229 oce_mbox_nic_query_lro_capabilities(POCE_SOFTC sc, uint32_t *lro_rq_cnt, uint32_t *lro_flags)
2232 struct mbx_nic_query_lro_capabilities *fwcmd;
2235 bzero(&mbx, sizeof(struct oce_mbx));
2237 fwcmd = (struct mbx_nic_query_lro_capabilities *)&mbx.payload;
2238 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
2240 0x20,MBX_TIMEOUT_SEC,
2241 sizeof(struct mbx_nic_query_lro_capabilities),
2244 mbx.u0.s.embedded = 1;
2245 mbx.payload_length = sizeof(struct mbx_nic_query_lro_capabilities);
2247 rc = oce_mbox_post(sc, &mbx, NULL);
2249 rc = fwcmd->hdr.u0.rsp.status;
2251 device_printf(sc->dev,
2252 "%s failed - cmd status: %d addi status: %d\n",
2254 fwcmd->hdr.u0.rsp.additional_status);
2259 *lro_flags = HOST_32(fwcmd->params.rsp.lro_flags);
2262 *lro_rq_cnt = HOST_16(fwcmd->params.rsp.lro_rq_cnt);
2268 oce_mbox_nic_set_iface_lro_config(POCE_SOFTC sc, int enable)
2271 struct mbx_nic_set_iface_lro_config *fwcmd;
2274 bzero(&mbx, sizeof(struct oce_mbx));
2276 fwcmd = (struct mbx_nic_set_iface_lro_config *)&mbx.payload;
2277 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
2279 0x26,MBX_TIMEOUT_SEC,
2280 sizeof(struct mbx_nic_set_iface_lro_config),
2283 mbx.u0.s.embedded = 1;
2284 mbx.payload_length = sizeof(struct mbx_nic_set_iface_lro_config);
2286 fwcmd->params.req.iface_id = sc->if_id;
2287 fwcmd->params.req.lro_flags = 0;
2290 fwcmd->params.req.lro_flags = LRO_FLAGS_HASH_MODE | LRO_FLAGS_RSS_MODE;
2291 fwcmd->params.req.lro_flags |= LRO_FLAGS_CLSC_IPV4 | LRO_FLAGS_CLSC_IPV6;
2293 fwcmd->params.req.max_clsc_byte_cnt = 64*1024; /* min = 2974, max = 0xfa59 */
2294 fwcmd->params.req.max_clsc_seg_cnt = 43; /* min = 2, max = 64 */
2295 fwcmd->params.req.max_clsc_usec_delay = 18; /* min = 1, max = 256 */
2296 fwcmd->params.req.min_clsc_frame_byte_cnt = 0; /* min = 1, max = 9014 */
2299 rc = oce_mbox_post(sc, &mbx, NULL);
2301 rc = fwcmd->hdr.u0.rsp.status;
2303 device_printf(sc->dev,
2304 "%s failed - cmd status: %d addi status: %d\n",
2306 fwcmd->hdr.u0.rsp.additional_status);
2314 oce_mbox_create_rq_v2(struct oce_rq *rq)
2317 struct mbx_create_nic_rq_v2 *fwcmd;
2318 POCE_SOFTC sc = rq->parent;
2319 int rc = 0, num_pages = 0;
2321 if (rq->qstate == QCREATED)
2324 bzero(&mbx, sizeof(struct oce_mbx));
2326 fwcmd = (struct mbx_create_nic_rq_v2 *)&mbx.payload;
2327 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
2329 0x08, MBX_TIMEOUT_SEC,
2330 sizeof(struct mbx_create_nic_rq_v2),
2333 /* oce_page_list will also prepare pages */
2334 num_pages = oce_page_list(rq->ring, &fwcmd->params.req.pages[0]);
2336 fwcmd->params.req.cq_id = rq->cq->cq_id;
2337 fwcmd->params.req.frag_size = rq->cfg.frag_size/2048;
2338 fwcmd->params.req.num_pages = num_pages;
2340 fwcmd->params.req.if_id = sc->if_id;
2342 fwcmd->params.req.max_frame_size = rq->cfg.mtu;
2343 fwcmd->params.req.page_size = 1;
2344 if(rq->cfg.is_rss_queue) {
2345 fwcmd->params.req.rq_flags = (NIC_RQ_FLAGS_RSS | NIC_RQ_FLAGS_LRO);
2347 device_printf(sc->dev,
2348 "non rss lro queue should not be created \n");
2351 mbx.u0.s.embedded = 1;
2352 mbx.payload_length = sizeof(struct mbx_create_nic_rq_v2);
2354 rc = oce_mbox_post(sc, &mbx, NULL);
2356 rc = fwcmd->hdr.u0.rsp.status;
2358 device_printf(sc->dev,
2359 "%s failed - cmd status: %d addi status: %d\n",
2361 fwcmd->hdr.u0.rsp.additional_status);
2364 rq->rq_id = HOST_16(fwcmd->params.rsp.rq_id);
2365 rq->rss_cpuid = fwcmd->params.rsp.rss_cpuid;