2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (C) 2013 Emulex
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8 * modification, are permitted provided that the following conditions are met:
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18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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33 * Contact Information:
34 * freebsd-drivers@emulex.com
38 * Costa Mesa, CA 92626
44 extern uint32_t sfp_vpd_dump_buffer[TRANSCEIVER_DATA_NUM_ELE];
47 * @brief Reset (firmware) common function
48 * @param sc software handle to the device
49 * @returns 0 on success, ETIMEDOUT on failure
52 oce_reset_fun(POCE_SOFTC sc)
56 struct ioctl_common_function_reset *fwcmd;
59 if (sc->flags & OCE_FLAGS_FUNCRESET_RQD) {
60 mb = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx);
62 bzero(mbx, sizeof(struct oce_mbx));
64 fwcmd = (struct ioctl_common_function_reset *)&mbx->payload;
65 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
67 OPCODE_COMMON_FUNCTION_RESET,
68 10, /* MBX_TIMEOUT_SEC */
70 ioctl_common_function_reset),
73 mbx->u0.s.embedded = 1;
75 sizeof(struct ioctl_common_function_reset);
77 rc = oce_mbox_dispatch(sc, 2);
85 * @brief This funtions tells firmware we are
87 * @param sc software handle to the device
88 * @returns 0 on success, ETIMEDOUT on failure
91 oce_fw_clean(POCE_SOFTC sc)
97 mbx = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx);
98 ptr = (uint8_t *) &mbx->mbx;
100 /* Endian Signature */
110 ret = oce_mbox_dispatch(sc, 2);
117 * @brief Mailbox wait
118 * @param sc software handle to the device
119 * @param tmo_sec timeout in seconds
122 oce_mbox_wait(POCE_SOFTC sc, uint32_t tmo_sec)
125 pd_mpu_mbox_db_t mbox_db;
133 mbox_db.dw0 = OCE_READ_REG32(sc, db, PD_MPU_MBOX_DB);
135 if (mbox_db.bits.ready)
141 device_printf(sc->dev, "Mailbox timed out\n");
148 * @brief Mailbox dispatch
149 * @param sc software handle to the device
150 * @param tmo_sec timeout in seconds
153 oce_mbox_dispatch(POCE_SOFTC sc, uint32_t tmo_sec)
155 pd_mpu_mbox_db_t mbox_db;
159 oce_dma_sync(&sc->bsmbx, BUS_DMASYNC_PREWRITE);
160 pa = (uint32_t) ((uint64_t) sc->bsmbx.paddr >> 34);
161 bzero(&mbox_db, sizeof(pd_mpu_mbox_db_t));
162 mbox_db.bits.ready = 0;
164 mbox_db.bits.address = pa;
166 rc = oce_mbox_wait(sc, tmo_sec);
168 OCE_WRITE_REG32(sc, db, PD_MPU_MBOX_DB, mbox_db.dw0);
170 pa = (uint32_t) ((uint64_t) sc->bsmbx.paddr >> 4) & 0x3fffffff;
171 mbox_db.bits.ready = 0;
173 mbox_db.bits.address = pa;
175 rc = oce_mbox_wait(sc, tmo_sec);
178 OCE_WRITE_REG32(sc, db, PD_MPU_MBOX_DB, mbox_db.dw0);
180 rc = oce_mbox_wait(sc, tmo_sec);
182 oce_dma_sync(&sc->bsmbx, BUS_DMASYNC_POSTWRITE);
192 * @brief Mailbox common request header initialization
193 * @param hdr mailbox header
196 * @param subsys subsystem
197 * @param opcode opcode
198 * @param timeout timeout
199 * @param pyld_len payload length
202 mbx_common_req_hdr_init(struct mbx_hdr *hdr,
203 uint8_t dom, uint8_t port,
204 uint8_t subsys, uint8_t opcode,
205 uint32_t timeout, uint32_t pyld_len,
208 hdr->u0.req.opcode = opcode;
209 hdr->u0.req.subsystem = subsys;
210 hdr->u0.req.port_number = port;
211 hdr->u0.req.domain = dom;
213 hdr->u0.req.timeout = timeout;
214 hdr->u0.req.request_length = pyld_len - sizeof(struct mbx_hdr);
215 hdr->u0.req.version = version;
221 * @brief Function to initialize the hw with host endian information
222 * @param sc software handle to the device
223 * @returns 0 on success, ETIMEDOUT on failure
226 oce_mbox_init(POCE_SOFTC sc)
228 struct oce_bmbx *mbx;
232 if (sc->flags & OCE_FLAGS_MBOX_ENDIAN_RQD) {
233 mbx = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx);
234 ptr = (uint8_t *) &mbx->mbx;
236 /* Endian Signature */
246 ret = oce_mbox_dispatch(sc, 0);
254 * @brief Function to get the firmware version
255 * @param sc software handle to the device
256 * @returns 0 on success, EIO on failure
259 oce_get_fw_version(POCE_SOFTC sc)
262 struct mbx_get_common_fw_version *fwcmd;
265 bzero(&mbx, sizeof(struct oce_mbx));
267 fwcmd = (struct mbx_get_common_fw_version *)&mbx.payload;
268 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
269 MBX_SUBSYSTEM_COMMON,
270 OPCODE_COMMON_GET_FW_VERSION,
272 sizeof(struct mbx_get_common_fw_version),
275 mbx.u0.s.embedded = 1;
276 mbx.payload_length = sizeof(struct mbx_get_common_fw_version);
277 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
279 ret = oce_mbox_post(sc, &mbx, NULL);
281 ret = fwcmd->hdr.u0.rsp.status;
283 device_printf(sc->dev,
284 "%s failed - cmd status: %d addi status: %d\n",
286 fwcmd->hdr.u0.rsp.additional_status);
290 bcopy(fwcmd->params.rsp.fw_ver_str, sc->fw_version, 32);
297 * @brief Firmware will send gracious notifications during
298 * attach only after sending first mcc commnad. We
299 * use MCC queue only for getting async and mailbox
300 * for sending cmds. So to get gracious notifications
301 * atleast send one dummy command on mcc.
304 oce_first_mcc_cmd(POCE_SOFTC sc)
307 struct oce_mq *mq = sc->mq;
308 struct mbx_get_common_fw_version *fwcmd;
311 mbx = RING_GET_PRODUCER_ITEM_VA(mq->ring, struct oce_mbx);
312 bzero(mbx, sizeof(struct oce_mbx));
314 fwcmd = (struct mbx_get_common_fw_version *)&mbx->payload;
315 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
316 MBX_SUBSYSTEM_COMMON,
317 OPCODE_COMMON_GET_FW_VERSION,
319 sizeof(struct mbx_get_common_fw_version),
321 mbx->u0.s.embedded = 1;
322 mbx->payload_length = sizeof(struct mbx_get_common_fw_version);
323 bus_dmamap_sync(mq->ring->dma.tag, mq->ring->dma.map,
324 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
325 RING_PUT(mq->ring, 1);
326 reg_value = (1 << 16) | mq->mq_id;
327 OCE_WRITE_REG32(sc, db, PD_MQ_DB, reg_value);
333 * @brief Function to post a MBX to the mbox
334 * @param sc software handle to the device
335 * @param mbx pointer to the MBX to send
336 * @param mbxctx pointer to the mbx context structure
337 * @returns 0 on success, error on failure
340 oce_mbox_post(POCE_SOFTC sc, struct oce_mbx *mbx, struct oce_mbx_ctx *mbxctx)
342 struct oce_mbx *mb_mbx = NULL;
343 struct oce_mq_cqe *mb_cqe = NULL;
344 struct oce_bmbx *mb = NULL;
347 uint32_t cstatus = 0;
348 uint32_t xstatus = 0;
350 LOCK(&sc->bmbx_lock);
352 mb = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx);
359 /* copy mbx into mbox */
360 bcopy(mbx, mb_mbx, sizeof(struct oce_mbx));
363 rc = oce_mbox_dispatch(sc, tmo);
366 * the command completed successfully. Now get the
367 * completion queue entry
370 DW_SWAP(u32ptr(&mb_cqe->u0.dw[0]), sizeof(struct oce_mq_cqe));
372 /* copy mbox mbx back */
373 bcopy(mb_mbx, mbx, sizeof(struct oce_mbx));
375 /* pick up the mailbox status */
376 cstatus = mb_cqe->u0.s.completion_status;
377 xstatus = mb_cqe->u0.s.extended_status;
380 * store the mbx context in the cqe tag section so that
381 * the upper layer handling the cqe can associate the mbx
384 if (cstatus == 0 && mbxctx) {
386 mbxctx->mbx = mb_mbx;
387 bcopy(&mbxctx, mb_cqe->u0.s.mq_tag,
388 sizeof(struct oce_mbx_ctx *));
392 UNLOCK(&sc->bmbx_lock);
398 * @brief Function to read the mac address associated with an interface
399 * @param sc software handle to the device
400 * @param if_id interface id to read the address from
401 * @param perm set to 1 if reading the factory mac address.
402 * In this case if_id is ignored
403 * @param type type of the mac address, whether network or storage
404 * @param[out] mac [OUTPUT] pointer to a buffer containing the
405 * mac address when the command succeeds.
406 * @returns 0 on success, EIO on failure
409 oce_read_mac_addr(POCE_SOFTC sc, uint32_t if_id,
410 uint8_t perm, uint8_t type, struct mac_address_format *mac)
413 struct mbx_query_common_iface_mac *fwcmd;
416 bzero(&mbx, sizeof(struct oce_mbx));
418 fwcmd = (struct mbx_query_common_iface_mac *)&mbx.payload;
419 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
420 MBX_SUBSYSTEM_COMMON,
421 OPCODE_COMMON_QUERY_IFACE_MAC,
423 sizeof(struct mbx_query_common_iface_mac),
426 fwcmd->params.req.permanent = perm;
428 fwcmd->params.req.if_id = (uint16_t) if_id;
430 fwcmd->params.req.if_id = 0;
432 fwcmd->params.req.type = type;
434 mbx.u0.s.embedded = 1;
435 mbx.payload_length = sizeof(struct mbx_query_common_iface_mac);
436 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
438 ret = oce_mbox_post(sc, &mbx, NULL);
440 ret = fwcmd->hdr.u0.rsp.status;
442 device_printf(sc->dev,
443 "%s failed - cmd status: %d addi status: %d\n",
445 fwcmd->hdr.u0.rsp.additional_status);
449 /* copy the mac addres in the output parameter */
450 mac->size_of_struct = fwcmd->params.rsp.mac.size_of_struct;
451 bcopy(&fwcmd->params.rsp.mac.mac_addr[0], &mac->mac_addr[0],
452 mac->size_of_struct);
458 * @brief Function to query the fw attributes from the hw
459 * @param sc software handle to the device
460 * @returns 0 on success, EIO on failure
463 oce_get_fw_config(POCE_SOFTC sc)
466 struct mbx_common_query_fw_config *fwcmd;
469 bzero(&mbx, sizeof(struct oce_mbx));
471 fwcmd = (struct mbx_common_query_fw_config *)&mbx.payload;
472 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
473 MBX_SUBSYSTEM_COMMON,
474 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG,
476 sizeof(struct mbx_common_query_fw_config),
479 mbx.u0.s.embedded = 1;
480 mbx.payload_length = sizeof(struct mbx_common_query_fw_config);
481 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
483 ret = oce_mbox_post(sc, &mbx, NULL);
485 ret = fwcmd->hdr.u0.rsp.status;
487 device_printf(sc->dev,
488 "%s failed - cmd status: %d addi status: %d\n",
490 fwcmd->hdr.u0.rsp.additional_status);
494 DW_SWAP(u32ptr(fwcmd), sizeof(struct mbx_common_query_fw_config));
496 sc->config_number = HOST_32(fwcmd->params.rsp.config_number);
497 sc->asic_revision = HOST_32(fwcmd->params.rsp.asic_revision);
498 sc->port_id = HOST_32(fwcmd->params.rsp.port_id);
499 sc->function_mode = HOST_32(fwcmd->params.rsp.function_mode);
500 if ((sc->function_mode & (ULP_NIC_MODE | ULP_RDMA_MODE)) ==
501 (ULP_NIC_MODE | ULP_RDMA_MODE)) {
502 sc->rdma_flags = OCE_RDMA_FLAG_SUPPORTED;
504 sc->function_caps = HOST_32(fwcmd->params.rsp.function_caps);
506 if (fwcmd->params.rsp.ulp[0].ulp_mode & ULP_NIC_MODE) {
507 sc->max_tx_rings = HOST_32(fwcmd->params.rsp.ulp[0].nic_wq_tot);
508 sc->max_rx_rings = HOST_32(fwcmd->params.rsp.ulp[0].lro_rqid_tot);
510 sc->max_tx_rings = HOST_32(fwcmd->params.rsp.ulp[1].nic_wq_tot);
511 sc->max_rx_rings = HOST_32(fwcmd->params.rsp.ulp[1].lro_rqid_tot);
521 * @brief function to create a device interface
522 * @param sc software handle to the device
523 * @param cap_flags capability flags
524 * @param en_flags enable capability flags
525 * @param vlan_tag optional vlan tag to associate with the if
526 * @param mac_addr pointer to a buffer containing the mac address
527 * @param[out] if_id [OUTPUT] pointer to an integer to hold the ID of the
529 * @returns 0 on success, EIO on failure
532 oce_if_create(POCE_SOFTC sc,
540 struct mbx_create_common_iface *fwcmd;
543 bzero(&mbx, sizeof(struct oce_mbx));
545 fwcmd = (struct mbx_create_common_iface *)&mbx.payload;
546 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
547 MBX_SUBSYSTEM_COMMON,
548 OPCODE_COMMON_CREATE_IFACE,
550 sizeof(struct mbx_create_common_iface),
552 DW_SWAP(u32ptr(&fwcmd->hdr), sizeof(struct mbx_hdr));
554 fwcmd->params.req.version = 0;
555 fwcmd->params.req.cap_flags = LE_32(cap_flags);
556 fwcmd->params.req.enable_flags = LE_32(en_flags);
557 if (mac_addr != NULL) {
558 bcopy(mac_addr, &fwcmd->params.req.mac_addr[0], 6);
559 fwcmd->params.req.vlan_tag.u0.normal.vtag = LE_16(vlan_tag);
560 fwcmd->params.req.mac_invalid = 0;
562 fwcmd->params.req.mac_invalid = 1;
565 mbx.u0.s.embedded = 1;
566 mbx.payload_length = sizeof(struct mbx_create_common_iface);
567 DW_SWAP(u32ptr(&mbx), OCE_BMBX_RHDR_SZ);
569 rc = oce_mbox_post(sc, &mbx, NULL);
571 rc = fwcmd->hdr.u0.rsp.status;
573 device_printf(sc->dev,
574 "%s failed - cmd status: %d addi status: %d\n",
576 fwcmd->hdr.u0.rsp.additional_status);
580 *if_id = HOST_32(fwcmd->params.rsp.if_id);
582 if (mac_addr != NULL)
583 sc->pmac_id = HOST_32(fwcmd->params.rsp.pmac_id);
589 * @brief Function to delete an interface
590 * @param sc software handle to the device
591 * @param if_id ID of the interface to delete
592 * @returns 0 on success, EIO on failure
595 oce_if_del(POCE_SOFTC sc, uint32_t if_id)
598 struct mbx_destroy_common_iface *fwcmd;
601 bzero(&mbx, sizeof(struct oce_mbx));
603 fwcmd = (struct mbx_destroy_common_iface *)&mbx.payload;
604 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
605 MBX_SUBSYSTEM_COMMON,
606 OPCODE_COMMON_DESTROY_IFACE,
608 sizeof(struct mbx_destroy_common_iface),
611 fwcmd->params.req.if_id = if_id;
613 mbx.u0.s.embedded = 1;
614 mbx.payload_length = sizeof(struct mbx_destroy_common_iface);
615 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
617 rc = oce_mbox_post(sc, &mbx, NULL);
619 rc = fwcmd->hdr.u0.rsp.status;
621 device_printf(sc->dev,
622 "%s failed - cmd status: %d addi status: %d\n",
624 fwcmd->hdr.u0.rsp.additional_status);
629 * @brief Function to send the mbx command to configure vlan
630 * @param sc software handle to the device
631 * @param if_id interface identifier index
632 * @param vtag_arr array of vlan tags
633 * @param vtag_cnt number of elements in array
634 * @param untagged boolean TRUE/FLASE
635 * @param enable_promisc flag to enable/disable VLAN promiscuous mode
636 * @returns 0 on success, EIO on failure
639 oce_config_vlan(POCE_SOFTC sc,
641 struct normal_vlan *vtag_arr,
642 uint8_t vtag_cnt, uint32_t untagged, uint32_t enable_promisc)
645 struct mbx_common_config_vlan *fwcmd;
648 if (sc->vlans_added > sc->max_vlans)
651 bzero(&mbx, sizeof(struct oce_mbx));
652 fwcmd = (struct mbx_common_config_vlan *)&mbx.payload;
654 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
655 MBX_SUBSYSTEM_COMMON,
656 OPCODE_COMMON_CONFIG_IFACE_VLAN,
658 sizeof(struct mbx_common_config_vlan),
661 fwcmd->params.req.if_id = (uint8_t) if_id;
662 fwcmd->params.req.promisc = (uint8_t) enable_promisc;
663 fwcmd->params.req.untagged = (uint8_t) untagged;
664 fwcmd->params.req.num_vlans = vtag_cnt;
666 if (!enable_promisc) {
667 bcopy(vtag_arr, fwcmd->params.req.tags.normal_vlans,
668 vtag_cnt * sizeof(struct normal_vlan));
670 mbx.u0.s.embedded = 1;
671 mbx.payload_length = sizeof(struct mbx_common_config_vlan);
672 DW_SWAP(u32ptr(&mbx), (OCE_BMBX_RHDR_SZ + mbx.payload_length));
674 rc = oce_mbox_post(sc, &mbx, NULL);
676 rc = fwcmd->hdr.u0.rsp.status;
678 device_printf(sc->dev,
679 "%s failed - cmd status: %d addi status: %d\n",
681 fwcmd->hdr.u0.rsp.additional_status);
686 /* Enable Vlan Promis */
687 oce_rxf_set_promiscuous(sc, (1 << 1));
688 device_printf(sc->dev,"Enabling Vlan Promisc Mode\n");
695 * @brief Function to set flow control capability in the hardware
696 * @param sc software handle to the device
697 * @param flow_control flow control flags to set
698 * @returns 0 on success, EIO on failure
701 oce_set_flow_control(POCE_SOFTC sc, uint32_t flow_control)
704 struct mbx_common_get_set_flow_control *fwcmd =
705 (struct mbx_common_get_set_flow_control *)&mbx.payload;
708 bzero(&mbx, sizeof(struct oce_mbx));
710 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
711 MBX_SUBSYSTEM_COMMON,
712 OPCODE_COMMON_SET_FLOW_CONTROL,
714 sizeof(struct mbx_common_get_set_flow_control),
717 if (flow_control & OCE_FC_TX)
718 fwcmd->tx_flow_control = 1;
720 if (flow_control & OCE_FC_RX)
721 fwcmd->rx_flow_control = 1;
723 mbx.u0.s.embedded = 1;
724 mbx.payload_length = sizeof(struct mbx_common_get_set_flow_control);
725 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
727 rc = oce_mbox_post(sc, &mbx, NULL);
729 rc = fwcmd->hdr.u0.rsp.status;
731 device_printf(sc->dev,
732 "%s failed - cmd status: %d addi status: %d\n",
734 fwcmd->hdr.u0.rsp.additional_status);
739 * @brief Initialize the RSS CPU indirection table
741 * The table is used to choose the queue to place the incomming packets.
742 * Incomming packets are hashed. The lowest bits in the hash result
743 * are used as the index into the CPU indirection table.
744 * Each entry in the table contains the RSS CPU-ID returned by the NIC
745 * create. Based on the CPU ID, the receive completion is routed to
746 * the corresponding RSS CQs. (Non-RSS packets are always completed
747 * on the default (0) CQ).
749 * @param sc software handle to the device
750 * @param *fwcmd pointer to the rss mbox command
754 oce_rss_itbl_init(POCE_SOFTC sc, struct mbx_config_nic_rss *fwcmd)
756 int i = 0, j = 0, rc = 0;
757 uint8_t *tbl = fwcmd->params.req.cputable;
758 struct oce_rq *rq = NULL;
761 for (j = 0; j < INDIRECTION_TABLE_ENTRIES ; j += (sc->nrqs - 1)) {
762 for_all_rss_queues(sc, rq, i) {
763 if ((j + i) >= INDIRECTION_TABLE_ENTRIES)
765 tbl[j + i] = rq->rss_cpuid;
769 device_printf(sc->dev, "error: Invalid number of RSS RQ's\n");
774 /* fill log2 value indicating the size of the CPU table */
776 fwcmd->params.req.cpu_tbl_sz_log2 = LE_16(OCE_LOG2(INDIRECTION_TABLE_ENTRIES));
782 * @brief Function to set flow control capability in the hardware
783 * @param sc software handle to the device
784 * @param if_id interface id to read the address from
785 * @param enable_rss 0=disable, RSS_ENABLE_xxx flags otherwise
786 * @returns 0 on success, EIO on failure
789 oce_config_nic_rss(POCE_SOFTC sc, uint32_t if_id, uint16_t enable_rss)
793 struct mbx_config_nic_rss *fwcmd =
794 (struct mbx_config_nic_rss *)&mbx.payload;
797 bzero(&mbx, sizeof(struct oce_mbx));
799 if (IS_XE201(sc) || IS_SH(sc)) {
800 version = OCE_MBX_VER_V1;
801 fwcmd->params.req.enable_rss = RSS_ENABLE_UDP_IPV4 |
804 version = OCE_MBX_VER_V0;
806 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
810 sizeof(struct mbx_config_nic_rss),
813 fwcmd->params.req.enable_rss |= (RSS_ENABLE_IPV4 |
814 RSS_ENABLE_TCP_IPV4 |
816 RSS_ENABLE_TCP_IPV6);
818 if(!sc->enable_hwlro)
819 fwcmd->params.req.flush = OCE_FLUSH;
821 fwcmd->params.req.flush = 0;
823 fwcmd->params.req.if_id = LE_32(if_id);
825 srandom(arc4random()); /* random entropy seed */
826 read_random(fwcmd->params.req.hash, sizeof(fwcmd->params.req.hash));
828 rc = oce_rss_itbl_init(sc, fwcmd);
830 mbx.u0.s.embedded = 1;
831 mbx.payload_length = sizeof(struct mbx_config_nic_rss);
832 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
834 rc = oce_mbox_post(sc, &mbx, NULL);
836 rc = fwcmd->hdr.u0.rsp.status;
838 device_printf(sc->dev,
839 "%s failed - cmd status: %d addi status: %d\n",
841 fwcmd->hdr.u0.rsp.additional_status);
847 * @brief RXF function to enable/disable device promiscuous mode
848 * @param sc software handle to the device
849 * @param enable enable/disable flag
850 * @returns 0 on success, EIO on failure
852 * The NIC_CONFIG_PROMISCUOUS command deprecated for Lancer.
853 * This function uses the COMMON_SET_IFACE_RX_FILTER command instead.
856 oce_rxf_set_promiscuous(POCE_SOFTC sc, uint8_t enable)
858 struct mbx_set_common_iface_rx_filter *fwcmd;
859 int sz = sizeof(struct mbx_set_common_iface_rx_filter);
860 iface_rx_filter_ctx_t *req;
864 /* allocate mbx payload's dma scatter/gather memory */
865 rc = oce_dma_alloc(sc, sz, &sgl, 0);
869 fwcmd = OCE_DMAPTR(&sgl, struct mbx_set_common_iface_rx_filter);
871 req = &fwcmd->params.req;
872 req->iface_flags_mask = MBX_RX_IFACE_FLAGS_PROMISCUOUS |
873 MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS;
874 /* Bit 0 Mac promisc, Bit 1 Vlan promisc */
876 req->iface_flags = MBX_RX_IFACE_FLAGS_PROMISCUOUS;
879 req->iface_flags |= MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS;
881 req->if_id = sc->if_id;
883 rc = oce_set_common_iface_rx_filter(sc, &sgl);
884 oce_dma_free(sc, &sgl);
891 * @brief Function modify and select rx filter options
892 * @param sc software handle to the device
893 * @param sgl scatter/gather request/response
894 * @returns 0 on success, error code on failure
897 oce_set_common_iface_rx_filter(POCE_SOFTC sc, POCE_DMA_MEM sgl)
900 int mbx_sz = sizeof(struct mbx_set_common_iface_rx_filter);
901 struct mbx_set_common_iface_rx_filter *fwcmd;
904 bzero(&mbx, sizeof(struct oce_mbx));
905 fwcmd = OCE_DMAPTR(sgl, struct mbx_set_common_iface_rx_filter);
907 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
908 MBX_SUBSYSTEM_COMMON,
909 OPCODE_COMMON_SET_IFACE_RX_FILTER,
914 oce_dma_sync(sgl, BUS_DMASYNC_PREWRITE);
915 mbx.u0.s.embedded = 0;
916 mbx.u0.s.sge_count = 1;
917 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(sgl->paddr);
918 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(sgl->paddr);
919 mbx.payload.u0.u1.sgl[0].length = mbx_sz;
920 mbx.payload_length = mbx_sz;
921 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
923 rc = oce_mbox_post(sc, &mbx, NULL);
925 rc = fwcmd->hdr.u0.rsp.status;
927 device_printf(sc->dev,
928 "%s failed - cmd status: %d addi status: %d\n",
930 fwcmd->hdr.u0.rsp.additional_status);
935 * @brief Function to query the link status from the hardware
936 * @param sc software handle to the device
937 * @param[out] link pointer to the structure returning link attributes
938 * @returns 0 on success, EIO on failure
941 oce_get_link_status(POCE_SOFTC sc, struct link_status *link)
944 struct mbx_query_common_link_config *fwcmd;
947 bzero(&mbx, sizeof(struct oce_mbx));
949 IS_BE2(sc) ? (version = OCE_MBX_VER_V0) : (version = OCE_MBX_VER_V1);
951 fwcmd = (struct mbx_query_common_link_config *)&mbx.payload;
952 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
953 MBX_SUBSYSTEM_COMMON,
954 OPCODE_COMMON_QUERY_LINK_CONFIG,
956 sizeof(struct mbx_query_common_link_config),
959 mbx.u0.s.embedded = 1;
960 mbx.payload_length = sizeof(struct mbx_query_common_link_config);
961 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
963 rc = oce_mbox_post(sc, &mbx, NULL);
966 rc = fwcmd->hdr.u0.rsp.status;
968 device_printf(sc->dev,
969 "%s failed - cmd status: %d addi status: %d\n",
971 fwcmd->hdr.u0.rsp.additional_status);
974 /* interpret response */
975 link->qos_link_speed = HOST_16(fwcmd->params.rsp.qos_link_speed);
976 link->phys_port_speed = fwcmd->params.rsp.physical_port_speed;
977 link->logical_link_status = fwcmd->params.rsp.logical_link_status;
984 * @brief Function to get NIC statistics
985 * @param sc software handle to the device
986 * @param *stats pointer to where to store statistics
987 * @param reset_stats resets statistics of set
988 * @returns 0 on success, EIO on failure
989 * @note command depricated in Lancer
991 #define OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, version) \
993 oce_mbox_get_nic_stats_v##version(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem) \
995 struct oce_mbx mbx; \
996 struct mbx_get_nic_stats_v##version *fwcmd; \
999 bzero(&mbx, sizeof(struct oce_mbx)); \
1000 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_nic_stats_v##version); \
1001 bzero(fwcmd, sizeof(*fwcmd)); \
1003 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, \
1004 MBX_SUBSYSTEM_NIC, \
1008 OCE_MBX_VER_V##version); \
1010 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */ \
1011 mbx.u0.s.sge_count = 1; /* using scatter gather instead */ \
1013 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE); \
1014 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr); \
1015 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr); \
1016 mbx.payload.u0.u1.sgl[0].length = sizeof(*fwcmd); \
1017 mbx.payload_length = sizeof(*fwcmd); \
1018 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); \
1020 rc = oce_mbox_post(sc, &mbx, NULL); \
1021 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE); \
1023 rc = fwcmd->hdr.u0.rsp.status; \
1025 device_printf(sc->dev, \
1026 "%s failed - cmd status: %d addi status: %d\n", \
1028 fwcmd->hdr.u0.rsp.additional_status); \
1032 OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, 0);
1033 OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, 1);
1034 OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, 2);
1038 * @brief Function to get pport (physical port) statistics
1039 * @param sc software handle to the device
1040 * @param *stats pointer to where to store statistics
1041 * @param reset_stats resets statistics of set
1042 * @returns 0 on success, EIO on failure
1045 oce_mbox_get_pport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1046 uint32_t reset_stats)
1049 struct mbx_get_pport_stats *fwcmd;
1052 bzero(&mbx, sizeof(struct oce_mbx));
1053 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_pport_stats);
1054 bzero(fwcmd, sizeof(struct mbx_get_pport_stats));
1056 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1058 NIC_GET_PPORT_STATS,
1060 sizeof(struct mbx_get_pport_stats),
1063 fwcmd->params.req.reset_stats = reset_stats;
1064 fwcmd->params.req.port_number = sc->port_id;
1066 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */
1067 mbx.u0.s.sge_count = 1; /* using scatter gather instead */
1069 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE);
1070 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr);
1071 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr);
1072 mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_pport_stats);
1074 mbx.payload_length = sizeof(struct mbx_get_pport_stats);
1075 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1077 rc = oce_mbox_post(sc, &mbx, NULL);
1078 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE);
1081 rc = fwcmd->hdr.u0.rsp.status;
1083 device_printf(sc->dev,
1084 "%s failed - cmd status: %d addi status: %d\n",
1086 fwcmd->hdr.u0.rsp.additional_status);
1092 * @brief Function to get vport (virtual port) statistics
1093 * @param sc software handle to the device
1094 * @param *stats pointer to where to store statistics
1095 * @param reset_stats resets statistics of set
1096 * @returns 0 on success, EIO on failure
1099 oce_mbox_get_vport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1100 uint32_t req_size, uint32_t reset_stats)
1103 struct mbx_get_vport_stats *fwcmd;
1106 bzero(&mbx, sizeof(struct oce_mbx));
1108 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_vport_stats);
1109 bzero(fwcmd, sizeof(struct mbx_get_vport_stats));
1111 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1113 NIC_GET_VPORT_STATS,
1115 sizeof(struct mbx_get_vport_stats),
1118 fwcmd->params.req.reset_stats = reset_stats;
1119 fwcmd->params.req.vport_number = sc->if_id;
1121 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */
1122 mbx.u0.s.sge_count = 1; /* using scatter gather instead */
1124 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE);
1125 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr);
1126 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr);
1127 mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_vport_stats);
1129 mbx.payload_length = sizeof(struct mbx_get_vport_stats);
1130 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1132 rc = oce_mbox_post(sc, &mbx, NULL);
1133 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE);
1136 rc = fwcmd->hdr.u0.rsp.status;
1138 device_printf(sc->dev,
1139 "%s failed - cmd status: %d addi status: %d\n",
1141 fwcmd->hdr.u0.rsp.additional_status);
1147 * @brief Function to update the muticast filter with
1149 * @param sc software handle to the device
1150 * @param dma_mem pointer to dma memory region
1151 * @returns 0 on success, EIO on failure
1154 oce_update_multicast(POCE_SOFTC sc, POCE_DMA_MEM pdma_mem)
1157 struct oce_mq_sge *sgl;
1158 struct mbx_set_common_iface_multicast *req = NULL;
1161 req = OCE_DMAPTR(pdma_mem, struct mbx_set_common_iface_multicast);
1162 mbx_common_req_hdr_init(&req->hdr, 0, 0,
1163 MBX_SUBSYSTEM_COMMON,
1164 OPCODE_COMMON_SET_IFACE_MULTICAST,
1166 sizeof(struct mbx_set_common_iface_multicast),
1169 bzero(&mbx, sizeof(struct oce_mbx));
1171 mbx.u0.s.embedded = 0; /*Non embeded*/
1172 mbx.payload_length = sizeof(struct mbx_set_common_iface_multicast);
1173 mbx.u0.s.sge_count = 1;
1174 sgl = &mbx.payload.u0.u1.sgl[0];
1175 sgl->pa_hi = htole32(upper_32_bits(pdma_mem->paddr));
1176 sgl->pa_lo = htole32((pdma_mem->paddr) & 0xFFFFFFFF);
1177 sgl->length = htole32(mbx.payload_length);
1179 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1181 rc = oce_mbox_post(sc, &mbx, NULL);
1183 rc = req->hdr.u0.rsp.status;
1185 device_printf(sc->dev,
1186 "%s failed - cmd status: %d addi status: %d\n",
1188 req->hdr.u0.rsp.additional_status);
1194 * @brief Function to send passthrough Ioctls
1195 * @param sc software handle to the device
1196 * @param dma_mem pointer to dma memory region
1197 * @param req_size size of dma_mem
1198 * @returns 0 on success, EIO on failure
1201 oce_pass_through_mbox(POCE_SOFTC sc, POCE_DMA_MEM dma_mem, uint32_t req_size)
1204 struct oce_mq_sge *sgl;
1207 bzero(&mbx, sizeof(struct oce_mbx));
1209 mbx.u0.s.embedded = 0; /*Non embeded*/
1210 mbx.payload_length = req_size;
1211 mbx.u0.s.sge_count = 1;
1212 sgl = &mbx.payload.u0.u1.sgl[0];
1213 sgl->pa_hi = htole32(upper_32_bits(dma_mem->paddr));
1214 sgl->pa_lo = htole32((dma_mem->paddr) & 0xFFFFFFFF);
1215 sgl->length = htole32(req_size);
1217 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1219 rc = oce_mbox_post(sc, &mbx, NULL);
1225 oce_mbox_macaddr_add(POCE_SOFTC sc, uint8_t *mac_addr,
1226 uint32_t if_id, uint32_t *pmac_id)
1229 struct mbx_add_common_iface_mac *fwcmd;
1232 bzero(&mbx, sizeof(struct oce_mbx));
1234 fwcmd = (struct mbx_add_common_iface_mac *)&mbx.payload;
1235 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1236 MBX_SUBSYSTEM_COMMON,
1237 OPCODE_COMMON_ADD_IFACE_MAC,
1239 sizeof(struct mbx_add_common_iface_mac),
1242 fwcmd->params.req.if_id = (uint16_t) if_id;
1243 bcopy(mac_addr, fwcmd->params.req.mac_address, 6);
1245 mbx.u0.s.embedded = 1;
1246 mbx.payload_length = sizeof(struct mbx_add_common_iface_mac);
1247 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1248 rc = oce_mbox_post(sc, &mbx, NULL);
1250 rc = fwcmd->hdr.u0.rsp.status;
1252 device_printf(sc->dev,
1253 "%s failed - cmd status: %d addi status: %d\n",
1255 fwcmd->hdr.u0.rsp.additional_status);
1258 *pmac_id = fwcmd->params.rsp.pmac_id;
1265 oce_mbox_macaddr_del(POCE_SOFTC sc, uint32_t if_id, uint32_t pmac_id)
1268 struct mbx_del_common_iface_mac *fwcmd;
1271 bzero(&mbx, sizeof(struct oce_mbx));
1273 fwcmd = (struct mbx_del_common_iface_mac *)&mbx.payload;
1274 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1275 MBX_SUBSYSTEM_COMMON,
1276 OPCODE_COMMON_DEL_IFACE_MAC,
1278 sizeof(struct mbx_del_common_iface_mac),
1281 fwcmd->params.req.if_id = (uint16_t)if_id;
1282 fwcmd->params.req.pmac_id = pmac_id;
1284 mbx.u0.s.embedded = 1;
1285 mbx.payload_length = sizeof(struct mbx_del_common_iface_mac);
1286 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1288 rc = oce_mbox_post(sc, &mbx, NULL);
1290 rc = fwcmd->hdr.u0.rsp.status;
1292 device_printf(sc->dev,
1293 "%s failed - cmd status: %d addi status: %d\n",
1295 fwcmd->hdr.u0.rsp.additional_status);
1302 oce_mbox_check_native_mode(POCE_SOFTC sc)
1305 struct mbx_common_set_function_cap *fwcmd;
1308 bzero(&mbx, sizeof(struct oce_mbx));
1310 fwcmd = (struct mbx_common_set_function_cap *)&mbx.payload;
1311 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1312 MBX_SUBSYSTEM_COMMON,
1313 OPCODE_COMMON_SET_FUNCTIONAL_CAPS,
1315 sizeof(struct mbx_common_set_function_cap),
1318 fwcmd->params.req.valid_capability_flags = CAP_SW_TIMESTAMPS |
1319 CAP_BE3_NATIVE_ERX_API;
1321 fwcmd->params.req.capability_flags = CAP_BE3_NATIVE_ERX_API;
1323 mbx.u0.s.embedded = 1;
1324 mbx.payload_length = sizeof(struct mbx_common_set_function_cap);
1325 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1327 rc = oce_mbox_post(sc, &mbx, NULL);
1329 rc = fwcmd->hdr.u0.rsp.status;
1331 device_printf(sc->dev,
1332 "%s failed - cmd status: %d addi status: %d\n",
1334 fwcmd->hdr.u0.rsp.additional_status);
1337 sc->be3_native = HOST_32(fwcmd->params.rsp.capability_flags)
1338 & CAP_BE3_NATIVE_ERX_API;
1347 oce_mbox_cmd_set_loopback(POCE_SOFTC sc, uint8_t port_num,
1348 uint8_t loopback_type, uint8_t enable)
1351 struct mbx_lowlevel_set_loopback_mode *fwcmd;
1355 bzero(&mbx, sizeof(struct oce_mbx));
1357 fwcmd = (struct mbx_lowlevel_set_loopback_mode *)&mbx.payload;
1358 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1359 MBX_SUBSYSTEM_LOWLEVEL,
1360 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
1362 sizeof(struct mbx_lowlevel_set_loopback_mode),
1365 fwcmd->params.req.src_port = port_num;
1366 fwcmd->params.req.dest_port = port_num;
1367 fwcmd->params.req.loopback_type = loopback_type;
1368 fwcmd->params.req.loopback_state = enable;
1370 mbx.u0.s.embedded = 1;
1371 mbx.payload_length = sizeof(struct mbx_lowlevel_set_loopback_mode);
1372 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1374 rc = oce_mbox_post(sc, &mbx, NULL);
1376 rc = fwcmd->hdr.u0.rsp.status;
1378 device_printf(sc->dev,
1379 "%s failed - cmd status: %d addi status: %d\n",
1381 fwcmd->hdr.u0.rsp.additional_status);
1388 oce_mbox_cmd_test_loopback(POCE_SOFTC sc, uint32_t port_num,
1389 uint32_t loopback_type, uint32_t pkt_size, uint32_t num_pkts,
1394 struct mbx_lowlevel_test_loopback_mode *fwcmd;
1398 bzero(&mbx, sizeof(struct oce_mbx));
1400 fwcmd = (struct mbx_lowlevel_test_loopback_mode *)&mbx.payload;
1401 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1402 MBX_SUBSYSTEM_LOWLEVEL,
1403 OPCODE_LOWLEVEL_TEST_LOOPBACK,
1405 sizeof(struct mbx_lowlevel_test_loopback_mode),
1408 fwcmd->params.req.pattern = pattern;
1409 fwcmd->params.req.src_port = port_num;
1410 fwcmd->params.req.dest_port = port_num;
1411 fwcmd->params.req.pkt_size = pkt_size;
1412 fwcmd->params.req.num_pkts = num_pkts;
1413 fwcmd->params.req.loopback_type = loopback_type;
1415 mbx.u0.s.embedded = 1;
1416 mbx.payload_length = sizeof(struct mbx_lowlevel_test_loopback_mode);
1417 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1419 rc = oce_mbox_post(sc, &mbx, NULL);
1421 rc = fwcmd->hdr.u0.rsp.status;
1423 device_printf(sc->dev,
1424 "%s failed - cmd status: %d addi status: %d\n",
1426 fwcmd->hdr.u0.rsp.additional_status);
1432 oce_mbox_write_flashrom(POCE_SOFTC sc, uint32_t optype,uint32_t opcode,
1433 POCE_DMA_MEM pdma_mem, uint32_t num_bytes)
1437 struct oce_mq_sge *sgl = NULL;
1438 struct mbx_common_read_write_flashrom *fwcmd = NULL;
1439 int rc = 0, payload_len = 0;
1441 bzero(&mbx, sizeof(struct oce_mbx));
1442 fwcmd = OCE_DMAPTR(pdma_mem, struct mbx_common_read_write_flashrom);
1443 payload_len = sizeof(struct mbx_common_read_write_flashrom) + 32*1024;
1445 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1446 MBX_SUBSYSTEM_COMMON,
1447 OPCODE_COMMON_WRITE_FLASHROM,
1452 fwcmd->flash_op_type = LE_32(optype);
1453 fwcmd->flash_op_code = LE_32(opcode);
1454 fwcmd->data_buffer_size = LE_32(num_bytes);
1456 mbx.u0.s.embedded = 0; /*Non embeded*/
1457 mbx.payload_length = payload_len;
1458 mbx.u0.s.sge_count = 1;
1460 sgl = &mbx.payload.u0.u1.sgl[0];
1461 sgl->pa_hi = upper_32_bits(pdma_mem->paddr);
1462 sgl->pa_lo = pdma_mem->paddr & 0xFFFFFFFF;
1463 sgl->length = payload_len;
1465 /* post the command */
1466 rc = oce_mbox_post(sc, &mbx, NULL);
1468 rc = fwcmd->hdr.u0.rsp.status;
1470 device_printf(sc->dev,
1471 "%s failed - cmd status: %d addi status: %d\n",
1473 fwcmd->hdr.u0.rsp.additional_status);
1480 oce_mbox_get_flashrom_crc(POCE_SOFTC sc, uint8_t *flash_crc,
1481 uint32_t offset, uint32_t optype)
1484 int rc = 0, payload_len = 0;
1486 struct mbx_common_read_write_flashrom *fwcmd;
1488 bzero(&mbx, sizeof(struct oce_mbx));
1490 fwcmd = (struct mbx_common_read_write_flashrom *)&mbx.payload;
1492 /* Firmware requires extra 4 bytes with this ioctl. Since there
1493 is enough room in the mbx payload it should be good enough
1494 Reference: Bug 14853
1496 payload_len = sizeof(struct mbx_common_read_write_flashrom) + 4;
1498 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1499 MBX_SUBSYSTEM_COMMON,
1500 OPCODE_COMMON_READ_FLASHROM,
1505 fwcmd->flash_op_type = optype;
1506 fwcmd->flash_op_code = FLASHROM_OPER_REPORT;
1507 fwcmd->data_offset = offset;
1508 fwcmd->data_buffer_size = 0x4;
1510 mbx.u0.s.embedded = 1;
1511 mbx.payload_length = payload_len;
1513 /* post the command */
1514 rc = oce_mbox_post(sc, &mbx, NULL);
1516 rc = fwcmd->hdr.u0.rsp.status;
1518 device_printf(sc->dev,
1519 "%s failed - cmd status: %d addi status: %d\n",
1521 fwcmd->hdr.u0.rsp.additional_status);
1524 bcopy(fwcmd->data_buffer, flash_crc, 4);
1530 oce_mbox_get_phy_info(POCE_SOFTC sc, struct oce_phy_info *phy_info)
1534 struct mbx_common_phy_info *fwcmd;
1537 bzero(&mbx, sizeof(struct oce_mbx));
1539 fwcmd = (struct mbx_common_phy_info *)&mbx.payload;
1540 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1541 MBX_SUBSYSTEM_COMMON,
1542 OPCODE_COMMON_GET_PHY_CONFIG,
1544 sizeof(struct mbx_common_phy_info),
1547 mbx.u0.s.embedded = 1;
1548 mbx.payload_length = sizeof(struct mbx_common_phy_info);
1550 /* now post the command */
1551 rc = oce_mbox_post(sc, &mbx, NULL);
1553 rc = fwcmd->hdr.u0.rsp.status;
1555 device_printf(sc->dev,
1556 "%s failed - cmd status: %d addi status: %d\n",
1558 fwcmd->hdr.u0.rsp.additional_status);
1561 phy_info->phy_type = HOST_16(fwcmd->params.rsp.phy_info.phy_type);
1562 phy_info->interface_type =
1563 HOST_16(fwcmd->params.rsp.phy_info.interface_type);
1564 phy_info->auto_speeds_supported =
1565 HOST_16(fwcmd->params.rsp.phy_info.auto_speeds_supported);
1566 phy_info->fixed_speeds_supported =
1567 HOST_16(fwcmd->params.rsp.phy_info.fixed_speeds_supported);
1568 phy_info->misc_params = HOST_32(fwcmd->params.rsp.phy_info.misc_params);
1576 oce_mbox_lancer_write_flashrom(POCE_SOFTC sc, uint32_t data_size,
1577 uint32_t data_offset, POCE_DMA_MEM pdma_mem,
1578 uint32_t *written_data, uint32_t *additional_status)
1582 struct mbx_lancer_common_write_object *fwcmd = NULL;
1583 int rc = 0, payload_len = 0;
1585 bzero(&mbx, sizeof(struct oce_mbx));
1586 payload_len = sizeof(struct mbx_lancer_common_write_object);
1588 mbx.u0.s.embedded = 1;/* Embedded */
1589 mbx.payload_length = payload_len;
1590 fwcmd = (struct mbx_lancer_common_write_object *)&mbx.payload;
1592 /* initialize the ioctl header */
1593 mbx_common_req_hdr_init(&fwcmd->params.req.hdr, 0, 0,
1594 MBX_SUBSYSTEM_COMMON,
1595 OPCODE_COMMON_WRITE_OBJECT,
1600 fwcmd->params.req.write_length = data_size;
1602 fwcmd->params.req.eof = 1;
1604 fwcmd->params.req.eof = 0;
1606 strcpy(fwcmd->params.req.object_name, "/prg");
1607 fwcmd->params.req.descriptor_count = 1;
1608 fwcmd->params.req.write_offset = data_offset;
1609 fwcmd->params.req.buffer_length = data_size;
1610 fwcmd->params.req.address_lower = pdma_mem->paddr & 0xFFFFFFFF;
1611 fwcmd->params.req.address_upper = upper_32_bits(pdma_mem->paddr);
1613 /* post the command */
1614 rc = oce_mbox_post(sc, &mbx, NULL);
1616 rc = fwcmd->params.rsp.status;
1618 device_printf(sc->dev,
1619 "%s failed - cmd status: %d addi status: %d\n",
1621 fwcmd->params.rsp.additional_status);
1624 *written_data = HOST_32(fwcmd->params.rsp.actual_write_length);
1625 *additional_status = fwcmd->params.rsp.additional_status;
1634 oce_mbox_create_rq(struct oce_rq *rq)
1638 struct mbx_create_nic_rq *fwcmd;
1639 POCE_SOFTC sc = rq->parent;
1640 int rc, num_pages = 0;
1642 if (rq->qstate == QCREATED)
1645 bzero(&mbx, sizeof(struct oce_mbx));
1647 fwcmd = (struct mbx_create_nic_rq *)&mbx.payload;
1648 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1650 NIC_CREATE_RQ, MBX_TIMEOUT_SEC,
1651 sizeof(struct mbx_create_nic_rq),
1654 /* oce_page_list will also prepare pages */
1655 num_pages = oce_page_list(rq->ring, &fwcmd->params.req.pages[0]);
1658 fwcmd->params.req.frag_size = rq->cfg.frag_size/2048;
1659 fwcmd->params.req.page_size = 1;
1660 fwcmd->hdr.u0.req.version = OCE_MBX_VER_V1;
1662 fwcmd->params.req.frag_size = OCE_LOG2(rq->cfg.frag_size);
1663 fwcmd->params.req.num_pages = num_pages;
1664 fwcmd->params.req.cq_id = rq->cq->cq_id;
1665 fwcmd->params.req.if_id = sc->if_id;
1666 fwcmd->params.req.max_frame_size = rq->cfg.mtu;
1667 fwcmd->params.req.is_rss_queue = rq->cfg.is_rss_queue;
1669 mbx.u0.s.embedded = 1;
1670 mbx.payload_length = sizeof(struct mbx_create_nic_rq);
1672 rc = oce_mbox_post(sc, &mbx, NULL);
1674 rc = fwcmd->hdr.u0.rsp.status;
1676 device_printf(sc->dev,
1677 "%s failed - cmd status: %d addi status: %d\n",
1679 fwcmd->hdr.u0.rsp.additional_status);
1682 rq->rq_id = HOST_16(fwcmd->params.rsp.rq_id);
1683 rq->rss_cpuid = fwcmd->params.rsp.rss_cpuid;
1692 oce_mbox_create_wq(struct oce_wq *wq)
1695 struct mbx_create_nic_wq *fwcmd;
1696 POCE_SOFTC sc = wq->parent;
1697 int rc = 0, version, num_pages;
1699 bzero(&mbx, sizeof(struct oce_mbx));
1701 fwcmd = (struct mbx_create_nic_wq *)&mbx.payload;
1703 version = OCE_MBX_VER_V1;
1705 IS_PROFILE_SUPER_NIC(sc) ? (version = OCE_MBX_VER_V2)
1706 : (version = OCE_MBX_VER_V0);
1708 version = OCE_MBX_VER_V2;
1710 if (version > OCE_MBX_VER_V0)
1711 fwcmd->params.req.if_id = sc->if_id;
1713 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1715 NIC_CREATE_WQ, MBX_TIMEOUT_SEC,
1716 sizeof(struct mbx_create_nic_wq),
1719 num_pages = oce_page_list(wq->ring, &fwcmd->params.req.pages[0]);
1721 fwcmd->params.req.nic_wq_type = wq->cfg.wq_type;
1722 fwcmd->params.req.num_pages = num_pages;
1723 fwcmd->params.req.wq_size = OCE_LOG2(wq->cfg.q_len) + 1;
1724 fwcmd->params.req.cq_id = wq->cq->cq_id;
1725 fwcmd->params.req.ulp_num = 1;
1727 mbx.u0.s.embedded = 1;
1728 mbx.payload_length = sizeof(struct mbx_create_nic_wq);
1730 rc = oce_mbox_post(sc, &mbx, NULL);
1732 rc = fwcmd->hdr.u0.rsp.status;
1734 device_printf(sc->dev,
1735 "%s failed - cmd status: %d addi status: %d\n",
1737 fwcmd->hdr.u0.rsp.additional_status);
1740 wq->wq_id = HOST_16(fwcmd->params.rsp.wq_id);
1741 if (version == OCE_MBX_VER_V2)
1742 wq->db_offset = HOST_32(fwcmd->params.rsp.db_offset);
1744 wq->db_offset = PD_TXULP_DB;
1753 oce_mbox_create_eq(struct oce_eq *eq)
1756 struct mbx_create_common_eq *fwcmd;
1757 POCE_SOFTC sc = eq->parent;
1761 bzero(&mbx, sizeof(struct oce_mbx));
1763 fwcmd = (struct mbx_create_common_eq *)&mbx.payload;
1765 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1766 MBX_SUBSYSTEM_COMMON,
1767 OPCODE_COMMON_CREATE_EQ, MBX_TIMEOUT_SEC,
1768 sizeof(struct mbx_create_common_eq),
1771 num_pages = oce_page_list(eq->ring, &fwcmd->params.req.pages[0]);
1772 fwcmd->params.req.ctx.num_pages = num_pages;
1773 fwcmd->params.req.ctx.valid = 1;
1774 fwcmd->params.req.ctx.size = (eq->eq_cfg.item_size == 4) ? 0 : 1;
1775 fwcmd->params.req.ctx.count = OCE_LOG2(eq->eq_cfg.q_len / 256);
1776 fwcmd->params.req.ctx.armed = 0;
1777 fwcmd->params.req.ctx.delay_mult = eq->eq_cfg.cur_eqd;
1780 mbx.u0.s.embedded = 1;
1781 mbx.payload_length = sizeof(struct mbx_create_common_eq);
1783 rc = oce_mbox_post(sc, &mbx, NULL);
1785 rc = fwcmd->hdr.u0.rsp.status;
1787 device_printf(sc->dev,
1788 "%s failed - cmd status: %d addi status: %d\n",
1790 fwcmd->hdr.u0.rsp.additional_status);
1793 eq->eq_id = HOST_16(fwcmd->params.rsp.eq_id);
1801 oce_mbox_cq_create(struct oce_cq *cq, uint32_t ncoalesce, uint32_t is_eventable)
1804 struct mbx_create_common_cq *fwcmd;
1805 POCE_SOFTC sc = cq->parent;
1808 uint32_t num_pages, page_size;
1812 bzero(&mbx, sizeof(struct oce_mbx));
1814 fwcmd = (struct mbx_create_common_cq *)&mbx.payload;
1817 version = OCE_MBX_VER_V2;
1819 version = OCE_MBX_VER_V0;
1821 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1822 MBX_SUBSYSTEM_COMMON,
1823 OPCODE_COMMON_CREATE_CQ,
1825 sizeof(struct mbx_create_common_cq),
1828 ctx = &fwcmd->params.req.cq_ctx;
1830 num_pages = oce_page_list(cq->ring, &fwcmd->params.req.pages[0]);
1831 page_size = 1; /* 1 for 4K */
1833 if (version == OCE_MBX_VER_V2) {
1834 ctx->v2.num_pages = LE_16(num_pages);
1835 ctx->v2.page_size = page_size;
1836 ctx->v2.eventable = is_eventable;
1838 ctx->v2.count = OCE_LOG2(cq->cq_cfg.q_len / 256);
1839 ctx->v2.nodelay = cq->cq_cfg.nodelay;
1840 ctx->v2.coalesce_wm = ncoalesce;
1842 ctx->v2.eq_id = cq->eq->eq_id;
1843 if (ctx->v2.count == 3) {
1844 if ((u_int)cq->cq_cfg.q_len > (4*1024)-1)
1845 ctx->v2.cqe_count = (4*1024)-1;
1847 ctx->v2.cqe_count = cq->cq_cfg.q_len;
1850 ctx->v0.num_pages = LE_16(num_pages);
1851 ctx->v0.eventable = is_eventable;
1853 ctx->v0.count = OCE_LOG2(cq->cq_cfg.q_len / 256);
1854 ctx->v0.nodelay = cq->cq_cfg.nodelay;
1855 ctx->v0.coalesce_wm = ncoalesce;
1857 ctx->v0.eq_id = cq->eq->eq_id;
1860 mbx.u0.s.embedded = 1;
1861 mbx.payload_length = sizeof(struct mbx_create_common_cq);
1863 rc = oce_mbox_post(sc, &mbx, NULL);
1865 rc = fwcmd->hdr.u0.rsp.status;
1867 device_printf(sc->dev,
1868 "%s failed - cmd status: %d addi status: %d\n",
1870 fwcmd->hdr.u0.rsp.additional_status);
1873 cq->cq_id = HOST_16(fwcmd->params.rsp.cq_id);
1880 oce_mbox_read_transrecv_data(POCE_SOFTC sc, uint32_t page_num)
1884 struct mbx_read_common_transrecv_data *fwcmd;
1885 struct oce_mq_sge *sgl;
1888 /* Allocate DMA mem*/
1889 if (oce_dma_alloc(sc, sizeof(struct mbx_read_common_transrecv_data),
1893 fwcmd = OCE_DMAPTR(&dma, struct mbx_read_common_transrecv_data);
1894 bzero(fwcmd, sizeof(struct mbx_read_common_transrecv_data));
1896 bzero(&mbx, sizeof(struct oce_mbx));
1897 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1898 MBX_SUBSYSTEM_COMMON,
1899 OPCODE_COMMON_READ_TRANSRECEIVER_DATA,
1901 sizeof(struct mbx_read_common_transrecv_data),
1904 /* fill rest of mbx */
1905 mbx.u0.s.embedded = 0;
1906 mbx.payload_length = sizeof(struct mbx_read_common_transrecv_data);
1907 mbx.u0.s.sge_count = 1;
1908 sgl = &mbx.payload.u0.u1.sgl[0];
1909 sgl->pa_hi = htole32(upper_32_bits(dma.paddr));
1910 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF);
1911 sgl->length = htole32(mbx.payload_length);
1912 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1914 fwcmd->params.req.port = LE_32(sc->port_id);
1915 fwcmd->params.req.page_num = LE_32(page_num);
1918 rc = oce_mbox_post(sc, &mbx, NULL);
1920 rc = fwcmd->hdr.u0.rsp.status;
1922 device_printf(sc->dev,
1923 "%s failed - cmd status: %d addi status: %d\n",
1925 fwcmd->hdr.u0.rsp.additional_status);
1928 if(fwcmd->params.rsp.page_num == PAGE_NUM_A0)
1930 bcopy((char *)fwcmd->params.rsp.page_data,
1931 (char *)&sfp_vpd_dump_buffer[0],
1932 TRANSCEIVER_A0_SIZE);
1935 if(fwcmd->params.rsp.page_num == PAGE_NUM_A2)
1937 bcopy((char *)fwcmd->params.rsp.page_data,
1938 (char *)&sfp_vpd_dump_buffer[32],
1939 TRANSCEIVER_A2_SIZE);
1942 oce_dma_free(sc, &dma);
1947 oce_mbox_eqd_modify_periodic(POCE_SOFTC sc, struct oce_set_eqd *set_eqd,
1951 struct mbx_modify_common_eq_delay *fwcmd;
1955 bzero(&mbx, sizeof(struct oce_mbx));
1957 /* Initialize MODIFY_EQ_DELAY ioctl header */
1958 fwcmd = (struct mbx_modify_common_eq_delay *)&mbx.payload;
1959 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1960 MBX_SUBSYSTEM_COMMON,
1961 OPCODE_COMMON_MODIFY_EQ_DELAY,
1963 sizeof(struct mbx_modify_common_eq_delay),
1965 /* fill rest of mbx */
1966 mbx.u0.s.embedded = 1;
1967 mbx.payload_length = sizeof(struct mbx_modify_common_eq_delay);
1968 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1970 fwcmd->params.req.num_eq = num;
1971 for (i = 0; i < num; i++) {
1972 fwcmd->params.req.delay[i].eq_id =
1973 htole32(set_eqd[i].eq_id);
1974 fwcmd->params.req.delay[i].phase = 0;
1975 fwcmd->params.req.delay[i].dm =
1976 htole32(set_eqd[i].delay_multiplier);
1981 rc = oce_mbox_post(sc, &mbx, NULL);
1984 rc = fwcmd->hdr.u0.rsp.status;
1986 device_printf(sc->dev,
1987 "%s failed - cmd status: %d addi status: %d\n",
1989 fwcmd->hdr.u0.rsp.additional_status);
1993 oce_get_profile_config(POCE_SOFTC sc, uint32_t max_rss)
1996 struct mbx_common_get_profile_config *fwcmd;
1999 struct oce_mq_sge *sgl;
2001 uint32_t desc_count = 0;
2002 struct oce_nic_resc_desc *nic_desc = NULL;
2004 boolean_t nic_desc_valid = FALSE;
2009 /* Allocate DMA mem*/
2010 if (oce_dma_alloc(sc, sizeof(struct mbx_common_get_profile_config),
2014 /* Initialize MODIFY_EQ_DELAY ioctl header */
2015 fwcmd = OCE_DMAPTR(&dma, struct mbx_common_get_profile_config);
2016 bzero(fwcmd, sizeof(struct mbx_common_get_profile_config));
2019 version = OCE_MBX_VER_V1;
2021 version = OCE_MBX_VER_V0;
2023 bzero(&mbx, sizeof(struct oce_mbx));
2024 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
2025 MBX_SUBSYSTEM_COMMON,
2026 OPCODE_COMMON_GET_PROFILE_CONFIG,
2028 sizeof(struct mbx_common_get_profile_config),
2030 /* fill rest of mbx */
2031 mbx.u0.s.embedded = 0;
2032 mbx.payload_length = sizeof(struct mbx_common_get_profile_config);
2033 mbx.u0.s.sge_count = 1;
2034 sgl = &mbx.payload.u0.u1.sgl[0];
2035 sgl->pa_hi = htole32(upper_32_bits(dma.paddr));
2036 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF);
2037 sgl->length = htole32(mbx.payload_length);
2038 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
2040 fwcmd->params.req.type = ACTIVE_PROFILE;
2043 rc = oce_mbox_post(sc, &mbx, NULL);
2045 rc = fwcmd->hdr.u0.rsp.status;
2047 device_printf(sc->dev,
2048 "%s failed - cmd status: %d addi status: %d\n",
2050 fwcmd->hdr.u0.rsp.additional_status);
2054 nic_desc = (struct oce_nic_resc_desc *) fwcmd->params.rsp.resources;
2055 desc_count = HOST_32(fwcmd->params.rsp.desc_count);
2056 for (i = 0; i < desc_count; i++) {
2057 if ((nic_desc->desc_type == NIC_RESC_DESC_TYPE_V0) ||
2058 (nic_desc->desc_type == NIC_RESC_DESC_TYPE_V1)) {
2059 nic_desc_valid = TRUE;
2062 nic_desc = (struct oce_nic_resc_desc *) \
2063 ((char *)nic_desc + nic_desc->desc_len);
2065 if (!nic_desc_valid) {
2070 sc->max_vlans = HOST_16(nic_desc->vlan_count);
2071 sc->nwqs = HOST_16(nic_desc->txq_count);
2073 sc->nwqs = MIN(sc->nwqs, OCE_MAX_WQ);
2075 sc->nwqs = OCE_MAX_WQ;
2077 sc->nrssqs = HOST_16(nic_desc->rssq_count);
2079 sc->nrssqs = MIN(sc->nrssqs, max_rss);
2081 sc->nrssqs = max_rss;
2082 sc->nrqs = sc->nrssqs + 1; /* 1 for def RX */
2086 oce_dma_free(sc, &dma);
2092 oce_get_func_config(POCE_SOFTC sc)
2095 struct mbx_common_get_func_config *fwcmd;
2098 struct oce_mq_sge *sgl;
2100 uint32_t desc_count = 0;
2101 struct oce_nic_resc_desc *nic_desc = NULL;
2103 boolean_t nic_desc_valid = FALSE;
2104 uint32_t max_rss = 0;
2106 if ((IS_BE(sc) || IS_SH(sc)) && (!sc->be3_native))
2107 max_rss = OCE_LEGACY_MODE_RSS;
2109 max_rss = OCE_MAX_RSS;
2111 /* Allocate DMA mem*/
2112 if (oce_dma_alloc(sc, sizeof(struct mbx_common_get_func_config),
2116 /* Initialize MODIFY_EQ_DELAY ioctl header */
2117 fwcmd = OCE_DMAPTR(&dma, struct mbx_common_get_func_config);
2118 bzero(fwcmd, sizeof(struct mbx_common_get_func_config));
2121 version = OCE_MBX_VER_V1;
2123 version = OCE_MBX_VER_V0;
2125 bzero(&mbx, sizeof(struct oce_mbx));
2126 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
2127 MBX_SUBSYSTEM_COMMON,
2128 OPCODE_COMMON_GET_FUNCTION_CONFIG,
2130 sizeof(struct mbx_common_get_func_config),
2132 /* fill rest of mbx */
2133 mbx.u0.s.embedded = 0;
2134 mbx.payload_length = sizeof(struct mbx_common_get_func_config);
2135 mbx.u0.s.sge_count = 1;
2136 sgl = &mbx.payload.u0.u1.sgl[0];
2137 sgl->pa_hi = htole32(upper_32_bits(dma.paddr));
2138 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF);
2139 sgl->length = htole32(mbx.payload_length);
2140 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
2143 rc = oce_mbox_post(sc, &mbx, NULL);
2145 rc = fwcmd->hdr.u0.rsp.status;
2147 device_printf(sc->dev,
2148 "%s failed - cmd status: %d addi status: %d\n",
2150 fwcmd->hdr.u0.rsp.additional_status);
2154 nic_desc = (struct oce_nic_resc_desc *) fwcmd->params.rsp.resources;
2155 desc_count = HOST_32(fwcmd->params.rsp.desc_count);
2156 for (i = 0; i < desc_count; i++) {
2157 if ((nic_desc->desc_type == NIC_RESC_DESC_TYPE_V0) ||
2158 (nic_desc->desc_type == NIC_RESC_DESC_TYPE_V1)) {
2159 nic_desc_valid = TRUE;
2162 nic_desc = (struct oce_nic_resc_desc *) \
2163 ((char *)nic_desc + nic_desc->desc_len);
2165 if (!nic_desc_valid) {
2170 sc->max_vlans = nic_desc->vlan_count;
2171 sc->nwqs = HOST_32(nic_desc->txq_count);
2173 sc->nwqs = MIN(sc->nwqs, OCE_MAX_WQ);
2175 sc->nwqs = OCE_MAX_WQ;
2177 sc->nrssqs = HOST_32(nic_desc->rssq_count);
2179 sc->nrssqs = MIN(sc->nrssqs, max_rss);
2181 sc->nrssqs = max_rss;
2182 sc->nrqs = sc->nrssqs + 1; /* 1 for def RX */
2185 oce_dma_free(sc, &dma);
2190 /* hw lro functions */
2193 oce_mbox_nic_query_lro_capabilities(POCE_SOFTC sc, uint32_t *lro_rq_cnt, uint32_t *lro_flags)
2196 struct mbx_nic_query_lro_capabilities *fwcmd;
2199 bzero(&mbx, sizeof(struct oce_mbx));
2201 fwcmd = (struct mbx_nic_query_lro_capabilities *)&mbx.payload;
2202 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
2204 0x20,MBX_TIMEOUT_SEC,
2205 sizeof(struct mbx_nic_query_lro_capabilities),
2208 mbx.u0.s.embedded = 1;
2209 mbx.payload_length = sizeof(struct mbx_nic_query_lro_capabilities);
2211 rc = oce_mbox_post(sc, &mbx, NULL);
2213 rc = fwcmd->hdr.u0.rsp.status;
2215 device_printf(sc->dev,
2216 "%s failed - cmd status: %d addi status: %d\n",
2218 fwcmd->hdr.u0.rsp.additional_status);
2223 *lro_flags = HOST_32(fwcmd->params.rsp.lro_flags);
2226 *lro_rq_cnt = HOST_16(fwcmd->params.rsp.lro_rq_cnt);
2232 oce_mbox_nic_set_iface_lro_config(POCE_SOFTC sc, int enable)
2235 struct mbx_nic_set_iface_lro_config *fwcmd;
2238 bzero(&mbx, sizeof(struct oce_mbx));
2240 fwcmd = (struct mbx_nic_set_iface_lro_config *)&mbx.payload;
2241 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
2243 0x26,MBX_TIMEOUT_SEC,
2244 sizeof(struct mbx_nic_set_iface_lro_config),
2247 mbx.u0.s.embedded = 1;
2248 mbx.payload_length = sizeof(struct mbx_nic_set_iface_lro_config);
2250 fwcmd->params.req.iface_id = sc->if_id;
2251 fwcmd->params.req.lro_flags = 0;
2254 fwcmd->params.req.lro_flags = LRO_FLAGS_HASH_MODE | LRO_FLAGS_RSS_MODE;
2255 fwcmd->params.req.lro_flags |= LRO_FLAGS_CLSC_IPV4 | LRO_FLAGS_CLSC_IPV6;
2257 fwcmd->params.req.max_clsc_byte_cnt = 64*1024; /* min = 2974, max = 0xfa59 */
2258 fwcmd->params.req.max_clsc_seg_cnt = 43; /* min = 2, max = 64 */
2259 fwcmd->params.req.max_clsc_usec_delay = 18; /* min = 1, max = 256 */
2260 fwcmd->params.req.min_clsc_frame_byte_cnt = 0; /* min = 1, max = 9014 */
2263 rc = oce_mbox_post(sc, &mbx, NULL);
2265 rc = fwcmd->hdr.u0.rsp.status;
2267 device_printf(sc->dev,
2268 "%s failed - cmd status: %d addi status: %d\n",
2270 fwcmd->hdr.u0.rsp.additional_status);
2278 oce_mbox_create_rq_v2(struct oce_rq *rq)
2281 struct mbx_create_nic_rq_v2 *fwcmd;
2282 POCE_SOFTC sc = rq->parent;
2283 int rc = 0, num_pages = 0;
2285 if (rq->qstate == QCREATED)
2288 bzero(&mbx, sizeof(struct oce_mbx));
2290 fwcmd = (struct mbx_create_nic_rq_v2 *)&mbx.payload;
2291 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
2293 0x08, MBX_TIMEOUT_SEC,
2294 sizeof(struct mbx_create_nic_rq_v2),
2297 /* oce_page_list will also prepare pages */
2298 num_pages = oce_page_list(rq->ring, &fwcmd->params.req.pages[0]);
2300 fwcmd->params.req.cq_id = rq->cq->cq_id;
2301 fwcmd->params.req.frag_size = rq->cfg.frag_size/2048;
2302 fwcmd->params.req.num_pages = num_pages;
2304 fwcmd->params.req.if_id = sc->if_id;
2306 fwcmd->params.req.max_frame_size = rq->cfg.mtu;
2307 fwcmd->params.req.page_size = 1;
2308 if(rq->cfg.is_rss_queue) {
2309 fwcmd->params.req.rq_flags = (NIC_RQ_FLAGS_RSS | NIC_RQ_FLAGS_LRO);
2311 device_printf(sc->dev,
2312 "non rss lro queue should not be created \n");
2315 mbx.u0.s.embedded = 1;
2316 mbx.payload_length = sizeof(struct mbx_create_nic_rq_v2);
2318 rc = oce_mbox_post(sc, &mbx, NULL);
2320 rc = fwcmd->hdr.u0.rsp.status;
2322 device_printf(sc->dev,
2323 "%s failed - cmd status: %d addi status: %d\n",
2325 fwcmd->hdr.u0.rsp.additional_status);
2328 rq->rq_id = HOST_16(fwcmd->params.rsp.rq_id);
2329 rq->rss_cpuid = fwcmd->params.rsp.rss_cpuid;