2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (C) 2013 Emulex
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of the Emulex Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
33 * Contact Information:
34 * freebsd-drivers@emulex.com
38 * Costa Mesa, CA 92626
46 oce_wait_ready(POCE_SOFTC sc)
48 #define SLIPORT_READY_TIMEOUT 30000
49 uint32_t sliport_status, i;
54 for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
55 sliport_status = OCE_READ_REG32(sc, db, SLIPORT_STATUS_OFFSET);
56 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
59 if (sliport_status & SLIPORT_STATUS_ERR_MASK &&
60 !(sliport_status & SLIPORT_STATUS_RN_MASK)) {
61 device_printf(sc->dev, "Error detected in the card\n");
68 device_printf(sc->dev, "Firmware wait timed out\n");
74 * @brief Reset (firmware) common function
75 * @param sc software handle to the device
76 * @returns 0 on success, ETIMEDOUT on failure
79 oce_reset_fun(POCE_SOFTC sc)
83 struct ioctl_common_function_reset *fwcmd;
87 OCE_WRITE_REG32(sc, db, SLIPORT_CONTROL_OFFSET,
88 SLI_PORT_CONTROL_IP_MASK);
90 rc = oce_wait_ready(sc);
92 device_printf(sc->dev, "Firmware reset Failed\n");
98 mb = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx);
100 bzero(mbx, sizeof(struct oce_mbx));
102 fwcmd = (struct ioctl_common_function_reset *)&mbx->payload;
103 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
104 MBX_SUBSYSTEM_COMMON,
105 OPCODE_COMMON_FUNCTION_RESET,
106 10, /* MBX_TIMEOUT_SEC */
108 ioctl_common_function_reset),
111 mbx->u0.s.embedded = 1;
112 mbx->payload_length =
113 sizeof(struct ioctl_common_function_reset);
115 rc = oce_mbox_dispatch(sc, 2);
121 * @brief This functions tells firmware we are
122 * done with commands.
123 * @param sc software handle to the device
124 * @returns 0 on success, ETIMEDOUT on failure
127 oce_fw_clean(POCE_SOFTC sc)
129 struct oce_bmbx *mbx;
133 mbx = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx);
134 ptr = (uint8_t *) &mbx->mbx;
136 /* Endian Signature */
146 ret = oce_mbox_dispatch(sc, 2);
152 * @brief Mailbox wait
153 * @param sc software handle to the device
154 * @param tmo_sec timeout in seconds
157 oce_mbox_wait(POCE_SOFTC sc, uint32_t tmo_sec)
160 pd_mpu_mbox_db_t mbox_db;
168 mbox_db.dw0 = OCE_READ_REG32(sc, db, PD_MPU_MBOX_DB);
170 if (mbox_db.bits.ready)
176 device_printf(sc->dev, "Mailbox timed out\n");
182 * @brief Mailbox dispatch
183 * @param sc software handle to the device
184 * @param tmo_sec timeout in seconds
187 oce_mbox_dispatch(POCE_SOFTC sc, uint32_t tmo_sec)
189 pd_mpu_mbox_db_t mbox_db;
193 oce_dma_sync(&sc->bsmbx, BUS_DMASYNC_PREWRITE);
194 pa = (uint32_t) ((uint64_t) sc->bsmbx.paddr >> 34);
195 bzero(&mbox_db, sizeof(pd_mpu_mbox_db_t));
196 mbox_db.bits.ready = 0;
198 mbox_db.bits.address = pa;
200 rc = oce_mbox_wait(sc, tmo_sec);
202 OCE_WRITE_REG32(sc, db, PD_MPU_MBOX_DB, mbox_db.dw0);
204 pa = (uint32_t) ((uint64_t) sc->bsmbx.paddr >> 4) & 0x3fffffff;
205 mbox_db.bits.ready = 0;
207 mbox_db.bits.address = pa;
209 rc = oce_mbox_wait(sc, tmo_sec);
212 OCE_WRITE_REG32(sc, db, PD_MPU_MBOX_DB, mbox_db.dw0);
214 rc = oce_mbox_wait(sc, tmo_sec);
216 oce_dma_sync(&sc->bsmbx, BUS_DMASYNC_POSTWRITE);
224 * @brief Mailbox common request header initialization
225 * @param hdr mailbox header
228 * @param subsys subsystem
229 * @param opcode opcode
230 * @param timeout timeout
231 * @param pyld_len payload length
234 mbx_common_req_hdr_init(struct mbx_hdr *hdr,
235 uint8_t dom, uint8_t port,
236 uint8_t subsys, uint8_t opcode,
237 uint32_t timeout, uint32_t pyld_len,
240 hdr->u0.req.opcode = opcode;
241 hdr->u0.req.subsystem = subsys;
242 hdr->u0.req.port_number = port;
243 hdr->u0.req.domain = dom;
245 hdr->u0.req.timeout = timeout;
246 hdr->u0.req.request_length = pyld_len - sizeof(struct mbx_hdr);
247 hdr->u0.req.version = version;
251 * @brief Function to initialize the hw with host endian information
252 * @param sc software handle to the device
253 * @returns 0 on success, ETIMEDOUT on failure
256 oce_mbox_init(POCE_SOFTC sc)
258 struct oce_bmbx *mbx;
262 if (sc->flags & OCE_FLAGS_MBOX_ENDIAN_RQD) {
263 mbx = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx);
264 ptr = (uint8_t *) &mbx->mbx;
266 /* Endian Signature */
276 ret = oce_mbox_dispatch(sc, 0);
283 * @brief Function to get the firmware version
284 * @param sc software handle to the device
285 * @returns 0 on success, EIO on failure
288 oce_get_fw_version(POCE_SOFTC sc)
291 struct mbx_get_common_fw_version *fwcmd;
294 bzero(&mbx, sizeof(struct oce_mbx));
296 fwcmd = (struct mbx_get_common_fw_version *)&mbx.payload;
297 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
298 MBX_SUBSYSTEM_COMMON,
299 OPCODE_COMMON_GET_FW_VERSION,
301 sizeof(struct mbx_get_common_fw_version),
304 mbx.u0.s.embedded = 1;
305 mbx.payload_length = sizeof(struct mbx_get_common_fw_version);
306 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
308 ret = oce_mbox_post(sc, &mbx, NULL);
310 ret = fwcmd->hdr.u0.rsp.status;
312 device_printf(sc->dev,
313 "%s failed - cmd status: %d addi status: %d\n",
315 fwcmd->hdr.u0.rsp.additional_status);
319 bcopy(fwcmd->params.rsp.fw_ver_str, sc->fw_version, 32);
325 * @brief Firmware will send gracious notifications during
326 * attach only after sending first mcc commnad. We
327 * use MCC queue only for getting async and mailbox
328 * for sending cmds. So to get gracious notifications
329 * atleast send one dummy command on mcc.
332 oce_first_mcc_cmd(POCE_SOFTC sc)
335 struct oce_mq *mq = sc->mq;
336 struct mbx_get_common_fw_version *fwcmd;
339 mbx = RING_GET_PRODUCER_ITEM_VA(mq->ring, struct oce_mbx);
340 bzero(mbx, sizeof(struct oce_mbx));
342 fwcmd = (struct mbx_get_common_fw_version *)&mbx->payload;
343 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
344 MBX_SUBSYSTEM_COMMON,
345 OPCODE_COMMON_GET_FW_VERSION,
347 sizeof(struct mbx_get_common_fw_version),
349 mbx->u0.s.embedded = 1;
350 mbx->payload_length = sizeof(struct mbx_get_common_fw_version);
351 bus_dmamap_sync(mq->ring->dma.tag, mq->ring->dma.map,
352 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
353 RING_PUT(mq->ring, 1);
354 reg_value = (1 << 16) | mq->mq_id;
355 OCE_WRITE_REG32(sc, db, PD_MQ_DB, reg_value);
361 * @brief Function to post a MBX to the mbox
362 * @param sc software handle to the device
363 * @param mbx pointer to the MBX to send
364 * @param mbxctx pointer to the mbx context structure
365 * @returns 0 on success, error on failure
368 oce_mbox_post(POCE_SOFTC sc, struct oce_mbx *mbx, struct oce_mbx_ctx *mbxctx)
370 struct oce_mbx *mb_mbx = NULL;
371 struct oce_mq_cqe *mb_cqe = NULL;
372 struct oce_bmbx *mb = NULL;
375 uint32_t cstatus = 0;
377 LOCK(&sc->bmbx_lock);
379 mb = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx);
386 /* copy mbx into mbox */
387 bcopy(mbx, mb_mbx, sizeof(struct oce_mbx));
390 rc = oce_mbox_dispatch(sc, tmo);
393 * the command completed successfully. Now get the
394 * completion queue entry
397 DW_SWAP(u32ptr(&mb_cqe->u0.dw[0]), sizeof(struct oce_mq_cqe));
399 /* copy mbox mbx back */
400 bcopy(mb_mbx, mbx, sizeof(struct oce_mbx));
402 /* pick up the mailbox status */
403 cstatus = mb_cqe->u0.s.completion_status;
406 * store the mbx context in the cqe tag section so that
407 * the upper layer handling the cqe can associate the mbx
410 if (cstatus == 0 && mbxctx) {
412 mbxctx->mbx = mb_mbx;
413 bcopy(&mbxctx, mb_cqe->u0.s.mq_tag,
414 sizeof(struct oce_mbx_ctx *));
418 UNLOCK(&sc->bmbx_lock);
424 * @brief Function to read the mac address associated with an interface
425 * @param sc software handle to the device
426 * @param if_id interface id to read the address from
427 * @param perm set to 1 if reading the factory mac address.
428 * In this case if_id is ignored
429 * @param type type of the mac address, whether network or storage
430 * @param[out] mac [OUTPUT] pointer to a buffer containing the
431 * mac address when the command succeeds.
432 * @returns 0 on success, EIO on failure
435 oce_read_mac_addr(POCE_SOFTC sc, uint32_t if_id,
436 uint8_t perm, uint8_t type, struct mac_address_format *mac)
439 struct mbx_query_common_iface_mac *fwcmd;
442 bzero(&mbx, sizeof(struct oce_mbx));
444 fwcmd = (struct mbx_query_common_iface_mac *)&mbx.payload;
445 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
446 MBX_SUBSYSTEM_COMMON,
447 OPCODE_COMMON_QUERY_IFACE_MAC,
449 sizeof(struct mbx_query_common_iface_mac),
452 fwcmd->params.req.permanent = perm;
454 fwcmd->params.req.if_id = (uint16_t) if_id;
456 fwcmd->params.req.if_id = 0;
458 fwcmd->params.req.type = type;
460 mbx.u0.s.embedded = 1;
461 mbx.payload_length = sizeof(struct mbx_query_common_iface_mac);
462 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
464 ret = oce_mbox_post(sc, &mbx, NULL);
466 ret = fwcmd->hdr.u0.rsp.status;
468 device_printf(sc->dev,
469 "%s failed - cmd status: %d addi status: %d\n",
471 fwcmd->hdr.u0.rsp.additional_status);
475 /* copy the mac addres in the output parameter */
476 mac->size_of_struct = fwcmd->params.rsp.mac.size_of_struct;
477 bcopy(&fwcmd->params.rsp.mac.mac_addr[0], &mac->mac_addr[0],
478 mac->size_of_struct);
484 * @brief Function to query the fw attributes from the hw
485 * @param sc software handle to the device
486 * @returns 0 on success, EIO on failure
489 oce_get_fw_config(POCE_SOFTC sc)
492 struct mbx_common_query_fw_config *fwcmd;
495 bzero(&mbx, sizeof(struct oce_mbx));
497 fwcmd = (struct mbx_common_query_fw_config *)&mbx.payload;
498 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
499 MBX_SUBSYSTEM_COMMON,
500 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG,
502 sizeof(struct mbx_common_query_fw_config),
505 mbx.u0.s.embedded = 1;
506 mbx.payload_length = sizeof(struct mbx_common_query_fw_config);
507 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
509 ret = oce_mbox_post(sc, &mbx, NULL);
511 ret = fwcmd->hdr.u0.rsp.status;
513 device_printf(sc->dev,
514 "%s failed - cmd status: %d addi status: %d\n",
516 fwcmd->hdr.u0.rsp.additional_status);
520 DW_SWAP(u32ptr(fwcmd), sizeof(struct mbx_common_query_fw_config));
522 sc->config_number = HOST_32(fwcmd->params.rsp.config_number);
523 sc->asic_revision = HOST_32(fwcmd->params.rsp.asic_revision);
524 sc->port_id = HOST_32(fwcmd->params.rsp.port_id);
525 sc->function_mode = HOST_32(fwcmd->params.rsp.function_mode);
526 if ((sc->function_mode & (ULP_NIC_MODE | ULP_RDMA_MODE)) ==
527 (ULP_NIC_MODE | ULP_RDMA_MODE)) {
528 sc->rdma_flags = OCE_RDMA_FLAG_SUPPORTED;
530 sc->function_caps = HOST_32(fwcmd->params.rsp.function_caps);
532 if (fwcmd->params.rsp.ulp[0].ulp_mode & ULP_NIC_MODE) {
533 sc->max_tx_rings = HOST_32(fwcmd->params.rsp.ulp[0].nic_wq_tot);
534 sc->max_rx_rings = HOST_32(fwcmd->params.rsp.ulp[0].lro_rqid_tot);
536 sc->max_tx_rings = HOST_32(fwcmd->params.rsp.ulp[1].nic_wq_tot);
537 sc->max_rx_rings = HOST_32(fwcmd->params.rsp.ulp[1].lro_rqid_tot);
547 * @brief function to create a device interface
548 * @param sc software handle to the device
549 * @param cap_flags capability flags
550 * @param en_flags enable capability flags
551 * @param vlan_tag optional vlan tag to associate with the if
552 * @param mac_addr pointer to a buffer containing the mac address
553 * @param[out] if_id [OUTPUT] pointer to an integer to hold the ID of the
555 * @returns 0 on success, EIO on failure
558 oce_if_create(POCE_SOFTC sc,
566 struct mbx_create_common_iface *fwcmd;
569 bzero(&mbx, sizeof(struct oce_mbx));
571 fwcmd = (struct mbx_create_common_iface *)&mbx.payload;
572 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
573 MBX_SUBSYSTEM_COMMON,
574 OPCODE_COMMON_CREATE_IFACE,
576 sizeof(struct mbx_create_common_iface),
578 DW_SWAP(u32ptr(&fwcmd->hdr), sizeof(struct mbx_hdr));
580 fwcmd->params.req.version = 0;
581 fwcmd->params.req.cap_flags = LE_32(cap_flags);
582 fwcmd->params.req.enable_flags = LE_32(en_flags);
583 if (mac_addr != NULL) {
584 bcopy(mac_addr, &fwcmd->params.req.mac_addr[0], 6);
585 fwcmd->params.req.vlan_tag.u0.normal.vtag = LE_16(vlan_tag);
586 fwcmd->params.req.mac_invalid = 0;
588 fwcmd->params.req.mac_invalid = 1;
591 mbx.u0.s.embedded = 1;
592 mbx.payload_length = sizeof(struct mbx_create_common_iface);
593 DW_SWAP(u32ptr(&mbx), OCE_BMBX_RHDR_SZ);
595 rc = oce_mbox_post(sc, &mbx, NULL);
597 rc = fwcmd->hdr.u0.rsp.status;
599 device_printf(sc->dev,
600 "%s failed - cmd status: %d addi status: %d\n",
602 fwcmd->hdr.u0.rsp.additional_status);
606 *if_id = HOST_32(fwcmd->params.rsp.if_id);
608 if (mac_addr != NULL)
609 sc->pmac_id = HOST_32(fwcmd->params.rsp.pmac_id);
615 * @brief Function to delete an interface
616 * @param sc software handle to the device
617 * @param if_id ID of the interface to delete
618 * @returns 0 on success, EIO on failure
621 oce_if_del(POCE_SOFTC sc, uint32_t if_id)
624 struct mbx_destroy_common_iface *fwcmd;
627 bzero(&mbx, sizeof(struct oce_mbx));
629 fwcmd = (struct mbx_destroy_common_iface *)&mbx.payload;
630 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
631 MBX_SUBSYSTEM_COMMON,
632 OPCODE_COMMON_DESTROY_IFACE,
634 sizeof(struct mbx_destroy_common_iface),
637 fwcmd->params.req.if_id = if_id;
639 mbx.u0.s.embedded = 1;
640 mbx.payload_length = sizeof(struct mbx_destroy_common_iface);
641 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
643 rc = oce_mbox_post(sc, &mbx, NULL);
645 rc = fwcmd->hdr.u0.rsp.status;
647 device_printf(sc->dev,
648 "%s failed - cmd status: %d addi status: %d\n",
650 fwcmd->hdr.u0.rsp.additional_status);
655 * @brief Function to send the mbx command to configure vlan
656 * @param sc software handle to the device
657 * @param if_id interface identifier index
658 * @param vtag_arr array of vlan tags
659 * @param vtag_cnt number of elements in array
660 * @param untagged boolean TRUE/FLASE
661 * @param enable_promisc flag to enable/disable VLAN promiscuous mode
662 * @returns 0 on success, EIO on failure
665 oce_config_vlan(POCE_SOFTC sc,
667 struct normal_vlan *vtag_arr,
668 uint8_t vtag_cnt, uint32_t untagged, uint32_t enable_promisc)
671 struct mbx_common_config_vlan *fwcmd;
674 if (sc->vlans_added > sc->max_vlans)
677 bzero(&mbx, sizeof(struct oce_mbx));
678 fwcmd = (struct mbx_common_config_vlan *)&mbx.payload;
680 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
681 MBX_SUBSYSTEM_COMMON,
682 OPCODE_COMMON_CONFIG_IFACE_VLAN,
684 sizeof(struct mbx_common_config_vlan),
687 fwcmd->params.req.if_id = (uint8_t) if_id;
688 fwcmd->params.req.promisc = (uint8_t) enable_promisc;
689 fwcmd->params.req.untagged = (uint8_t) untagged;
690 fwcmd->params.req.num_vlans = vtag_cnt;
692 if (!enable_promisc) {
693 bcopy(vtag_arr, fwcmd->params.req.tags.normal_vlans,
694 vtag_cnt * sizeof(struct normal_vlan));
696 mbx.u0.s.embedded = 1;
697 mbx.payload_length = sizeof(struct mbx_common_config_vlan);
698 DW_SWAP(u32ptr(&mbx), (OCE_BMBX_RHDR_SZ + mbx.payload_length));
700 rc = oce_mbox_post(sc, &mbx, NULL);
702 rc = fwcmd->hdr.u0.rsp.status;
704 device_printf(sc->dev,
705 "%s failed - cmd status: %d addi status: %d\n",
707 fwcmd->hdr.u0.rsp.additional_status);
712 /* Enable Vlan Promis */
713 oce_rxf_set_promiscuous(sc, (1 << 1));
714 device_printf(sc->dev,"Enabling Vlan Promisc Mode\n");
721 * @brief Function to set flow control capability in the hardware
722 * @param sc software handle to the device
723 * @param flow_control flow control flags to set
724 * @returns 0 on success, EIO on failure
727 oce_set_flow_control(POCE_SOFTC sc, uint32_t flow_control)
730 struct mbx_common_get_set_flow_control *fwcmd =
731 (struct mbx_common_get_set_flow_control *)&mbx.payload;
734 bzero(&mbx, sizeof(struct oce_mbx));
736 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
737 MBX_SUBSYSTEM_COMMON,
738 OPCODE_COMMON_SET_FLOW_CONTROL,
740 sizeof(struct mbx_common_get_set_flow_control),
743 if (flow_control & OCE_FC_TX)
744 fwcmd->tx_flow_control = 1;
746 if (flow_control & OCE_FC_RX)
747 fwcmd->rx_flow_control = 1;
749 mbx.u0.s.embedded = 1;
750 mbx.payload_length = sizeof(struct mbx_common_get_set_flow_control);
751 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
753 rc = oce_mbox_post(sc, &mbx, NULL);
755 rc = fwcmd->hdr.u0.rsp.status;
757 device_printf(sc->dev,
758 "%s failed - cmd status: %d addi status: %d\n",
760 fwcmd->hdr.u0.rsp.additional_status);
765 * @brief Initialize the RSS CPU indirection table
767 * The table is used to choose the queue to place the incomming packets.
768 * Incomming packets are hashed. The lowest bits in the hash result
769 * are used as the index into the CPU indirection table.
770 * Each entry in the table contains the RSS CPU-ID returned by the NIC
771 * create. Based on the CPU ID, the receive completion is routed to
772 * the corresponding RSS CQs. (Non-RSS packets are always completed
773 * on the default (0) CQ).
775 * @param sc software handle to the device
776 * @param *fwcmd pointer to the rss mbox command
780 oce_rss_itbl_init(POCE_SOFTC sc, struct mbx_config_nic_rss *fwcmd)
782 int i = 0, j = 0, rc = 0;
783 uint8_t *tbl = fwcmd->params.req.cputable;
784 struct oce_rq *rq = NULL;
786 for (j = 0; j < INDIRECTION_TABLE_ENTRIES ; j += (sc->nrqs - 1)) {
787 for_all_rss_queues(sc, rq, i) {
788 if ((j + i) >= INDIRECTION_TABLE_ENTRIES)
790 tbl[j + i] = rq->rss_cpuid;
794 device_printf(sc->dev, "error: Invalid number of RSS RQ's\n");
799 /* fill log2 value indicating the size of the CPU table */
801 fwcmd->params.req.cpu_tbl_sz_log2 = LE_16(OCE_LOG2(INDIRECTION_TABLE_ENTRIES));
807 * @brief Function to set flow control capability in the hardware
808 * @param sc software handle to the device
809 * @param if_id interface id to read the address from
810 * @param enable_rss 0=disable, RSS_ENABLE_xxx flags otherwise
811 * @returns 0 on success, EIO on failure
814 oce_config_nic_rss(POCE_SOFTC sc, uint32_t if_id, uint16_t enable_rss)
818 struct mbx_config_nic_rss *fwcmd =
819 (struct mbx_config_nic_rss *)&mbx.payload;
822 bzero(&mbx, sizeof(struct oce_mbx));
824 if (IS_XE201(sc) || IS_SH(sc)) {
825 version = OCE_MBX_VER_V1;
826 fwcmd->params.req.enable_rss = RSS_ENABLE_UDP_IPV4 |
829 version = OCE_MBX_VER_V0;
831 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
835 sizeof(struct mbx_config_nic_rss),
838 fwcmd->params.req.enable_rss |= (RSS_ENABLE_IPV4 |
839 RSS_ENABLE_TCP_IPV4 |
841 RSS_ENABLE_TCP_IPV6);
843 if(!sc->enable_hwlro)
844 fwcmd->params.req.flush = OCE_FLUSH;
846 fwcmd->params.req.flush = 0;
848 fwcmd->params.req.if_id = LE_32(if_id);
850 read_random(fwcmd->params.req.hash, sizeof(fwcmd->params.req.hash));
852 rc = oce_rss_itbl_init(sc, fwcmd);
854 mbx.u0.s.embedded = 1;
855 mbx.payload_length = sizeof(struct mbx_config_nic_rss);
856 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
858 rc = oce_mbox_post(sc, &mbx, NULL);
860 rc = fwcmd->hdr.u0.rsp.status;
862 device_printf(sc->dev,
863 "%s failed - cmd status: %d addi status: %d\n",
865 fwcmd->hdr.u0.rsp.additional_status);
871 * @brief RXF function to enable/disable device promiscuous mode
872 * @param sc software handle to the device
873 * @param enable enable/disable flag
874 * @returns 0 on success, EIO on failure
876 * The NIC_CONFIG_PROMISCUOUS command deprecated for Lancer.
877 * This function uses the COMMON_SET_IFACE_RX_FILTER command instead.
880 oce_rxf_set_promiscuous(POCE_SOFTC sc, uint8_t enable)
882 struct mbx_set_common_iface_rx_filter *fwcmd;
883 int sz = sizeof(struct mbx_set_common_iface_rx_filter);
884 iface_rx_filter_ctx_t *req;
888 /* allocate mbx payload's dma scatter/gather memory */
889 rc = oce_dma_alloc(sc, sz, &sgl, 0);
893 fwcmd = OCE_DMAPTR(&sgl, struct mbx_set_common_iface_rx_filter);
895 req = &fwcmd->params.req;
896 req->iface_flags_mask = MBX_RX_IFACE_FLAGS_PROMISCUOUS |
897 MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS;
898 /* Bit 0 Mac promisc, Bit 1 Vlan promisc */
900 req->iface_flags = MBX_RX_IFACE_FLAGS_PROMISCUOUS;
903 req->iface_flags |= MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS;
905 req->if_id = sc->if_id;
907 rc = oce_set_common_iface_rx_filter(sc, &sgl);
908 oce_dma_free(sc, &sgl);
914 * @brief Function modify and select rx filter options
915 * @param sc software handle to the device
916 * @param sgl scatter/gather request/response
917 * @returns 0 on success, error code on failure
920 oce_set_common_iface_rx_filter(POCE_SOFTC sc, POCE_DMA_MEM sgl)
923 int mbx_sz = sizeof(struct mbx_set_common_iface_rx_filter);
924 struct mbx_set_common_iface_rx_filter *fwcmd;
927 bzero(&mbx, sizeof(struct oce_mbx));
928 fwcmd = OCE_DMAPTR(sgl, struct mbx_set_common_iface_rx_filter);
930 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
931 MBX_SUBSYSTEM_COMMON,
932 OPCODE_COMMON_SET_IFACE_RX_FILTER,
937 oce_dma_sync(sgl, BUS_DMASYNC_PREWRITE);
938 mbx.u0.s.embedded = 0;
939 mbx.u0.s.sge_count = 1;
940 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(sgl->paddr);
941 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(sgl->paddr);
942 mbx.payload.u0.u1.sgl[0].length = mbx_sz;
943 mbx.payload_length = mbx_sz;
944 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
946 rc = oce_mbox_post(sc, &mbx, NULL);
948 rc = fwcmd->hdr.u0.rsp.status;
950 device_printf(sc->dev,
951 "%s failed - cmd status: %d addi status: %d\n",
953 fwcmd->hdr.u0.rsp.additional_status);
958 * @brief Function to query the link status from the hardware
959 * @param sc software handle to the device
960 * @param[out] link pointer to the structure returning link attributes
961 * @returns 0 on success, EIO on failure
964 oce_get_link_status(POCE_SOFTC sc, struct link_status *link)
967 struct mbx_query_common_link_config *fwcmd;
970 bzero(&mbx, sizeof(struct oce_mbx));
972 IS_BE2(sc) ? (version = OCE_MBX_VER_V0) : (version = OCE_MBX_VER_V1);
974 fwcmd = (struct mbx_query_common_link_config *)&mbx.payload;
975 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
976 MBX_SUBSYSTEM_COMMON,
977 OPCODE_COMMON_QUERY_LINK_CONFIG,
979 sizeof(struct mbx_query_common_link_config),
982 mbx.u0.s.embedded = 1;
983 mbx.payload_length = sizeof(struct mbx_query_common_link_config);
984 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
986 rc = oce_mbox_post(sc, &mbx, NULL);
989 rc = fwcmd->hdr.u0.rsp.status;
991 device_printf(sc->dev,
992 "%s failed - cmd status: %d addi status: %d\n",
994 fwcmd->hdr.u0.rsp.additional_status);
997 /* interpret response */
998 link->qos_link_speed = HOST_16(fwcmd->params.rsp.qos_link_speed);
999 link->phys_port_speed = fwcmd->params.rsp.physical_port_speed;
1000 link->logical_link_status = fwcmd->params.rsp.logical_link_status;
1006 * @brief Function to get NIC statistics
1007 * @param sc software handle to the device
1008 * @param *stats pointer to where to store statistics
1009 * @param reset_stats resets statistics of set
1010 * @returns 0 on success, EIO on failure
1011 * @note command depricated in Lancer
1013 #define OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, version) \
1015 oce_mbox_get_nic_stats_v##version(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem) \
1017 struct oce_mbx mbx; \
1018 struct mbx_get_nic_stats_v##version *fwcmd; \
1021 bzero(&mbx, sizeof(struct oce_mbx)); \
1022 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_nic_stats_v##version); \
1023 bzero(fwcmd, sizeof(*fwcmd)); \
1025 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, \
1026 MBX_SUBSYSTEM_NIC, \
1030 OCE_MBX_VER_V##version); \
1032 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */ \
1033 mbx.u0.s.sge_count = 1; /* using scatter gather instead */ \
1035 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE); \
1036 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr); \
1037 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr); \
1038 mbx.payload.u0.u1.sgl[0].length = sizeof(*fwcmd); \
1039 mbx.payload_length = sizeof(*fwcmd); \
1040 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); \
1042 rc = oce_mbox_post(sc, &mbx, NULL); \
1043 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE); \
1045 rc = fwcmd->hdr.u0.rsp.status; \
1047 device_printf(sc->dev, \
1048 "%s failed - cmd status: %d addi status: %d\n", \
1050 fwcmd->hdr.u0.rsp.additional_status); \
1054 OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, 0);
1055 OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, 1);
1056 OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, 2);
1059 * @brief Function to get pport (physical port) statistics
1060 * @param sc software handle to the device
1061 * @param *stats pointer to where to store statistics
1062 * @param reset_stats resets statistics of set
1063 * @returns 0 on success, EIO on failure
1066 oce_mbox_get_pport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1067 uint32_t reset_stats)
1070 struct mbx_get_pport_stats *fwcmd;
1073 bzero(&mbx, sizeof(struct oce_mbx));
1074 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_pport_stats);
1075 bzero(fwcmd, sizeof(struct mbx_get_pport_stats));
1077 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1079 NIC_GET_PPORT_STATS,
1081 sizeof(struct mbx_get_pport_stats),
1084 fwcmd->params.req.reset_stats = reset_stats;
1085 fwcmd->params.req.port_number = sc->port_id;
1087 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */
1088 mbx.u0.s.sge_count = 1; /* using scatter gather instead */
1090 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE);
1091 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr);
1092 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr);
1093 mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_pport_stats);
1095 mbx.payload_length = sizeof(struct mbx_get_pport_stats);
1096 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1098 rc = oce_mbox_post(sc, &mbx, NULL);
1099 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE);
1102 rc = fwcmd->hdr.u0.rsp.status;
1104 device_printf(sc->dev,
1105 "%s failed - cmd status: %d addi status: %d\n",
1107 fwcmd->hdr.u0.rsp.additional_status);
1112 * @brief Function to get vport (virtual port) statistics
1113 * @param sc software handle to the device
1114 * @param *stats pointer to where to store statistics
1115 * @param reset_stats resets statistics of set
1116 * @returns 0 on success, EIO on failure
1119 oce_mbox_get_vport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1120 uint32_t req_size, uint32_t reset_stats)
1123 struct mbx_get_vport_stats *fwcmd;
1126 bzero(&mbx, sizeof(struct oce_mbx));
1128 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_vport_stats);
1129 bzero(fwcmd, sizeof(struct mbx_get_vport_stats));
1131 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1133 NIC_GET_VPORT_STATS,
1135 sizeof(struct mbx_get_vport_stats),
1138 fwcmd->params.req.reset_stats = reset_stats;
1139 fwcmd->params.req.vport_number = sc->if_id;
1141 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */
1142 mbx.u0.s.sge_count = 1; /* using scatter gather instead */
1144 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE);
1145 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr);
1146 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr);
1147 mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_vport_stats);
1149 mbx.payload_length = sizeof(struct mbx_get_vport_stats);
1150 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1152 rc = oce_mbox_post(sc, &mbx, NULL);
1153 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE);
1156 rc = fwcmd->hdr.u0.rsp.status;
1158 device_printf(sc->dev,
1159 "%s failed - cmd status: %d addi status: %d\n",
1161 fwcmd->hdr.u0.rsp.additional_status);
1166 * @brief Function to update the muticast filter with
1168 * @param sc software handle to the device
1169 * @param dma_mem pointer to dma memory region
1170 * @returns 0 on success, EIO on failure
1173 oce_update_multicast(POCE_SOFTC sc, POCE_DMA_MEM pdma_mem)
1176 struct oce_mq_sge *sgl;
1177 struct mbx_set_common_iface_multicast *req = NULL;
1180 req = OCE_DMAPTR(pdma_mem, struct mbx_set_common_iface_multicast);
1181 mbx_common_req_hdr_init(&req->hdr, 0, 0,
1182 MBX_SUBSYSTEM_COMMON,
1183 OPCODE_COMMON_SET_IFACE_MULTICAST,
1185 sizeof(struct mbx_set_common_iface_multicast),
1188 bzero(&mbx, sizeof(struct oce_mbx));
1190 mbx.u0.s.embedded = 0; /*Non embeded*/
1191 mbx.payload_length = sizeof(struct mbx_set_common_iface_multicast);
1192 mbx.u0.s.sge_count = 1;
1193 sgl = &mbx.payload.u0.u1.sgl[0];
1194 sgl->pa_hi = htole32(upper_32_bits(pdma_mem->paddr));
1195 sgl->pa_lo = htole32((pdma_mem->paddr) & 0xFFFFFFFF);
1196 sgl->length = htole32(mbx.payload_length);
1198 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1200 rc = oce_mbox_post(sc, &mbx, NULL);
1202 rc = req->hdr.u0.rsp.status;
1204 device_printf(sc->dev,
1205 "%s failed - cmd status: %d addi status: %d\n",
1207 req->hdr.u0.rsp.additional_status);
1212 * @brief Function to send passthrough Ioctls
1213 * @param sc software handle to the device
1214 * @param dma_mem pointer to dma memory region
1215 * @param req_size size of dma_mem
1216 * @returns 0 on success, EIO on failure
1219 oce_pass_through_mbox(POCE_SOFTC sc, POCE_DMA_MEM dma_mem, uint32_t req_size)
1222 struct oce_mq_sge *sgl;
1225 bzero(&mbx, sizeof(struct oce_mbx));
1227 mbx.u0.s.embedded = 0; /*Non embeded*/
1228 mbx.payload_length = req_size;
1229 mbx.u0.s.sge_count = 1;
1230 sgl = &mbx.payload.u0.u1.sgl[0];
1231 sgl->pa_hi = htole32(upper_32_bits(dma_mem->paddr));
1232 sgl->pa_lo = htole32((dma_mem->paddr) & 0xFFFFFFFF);
1233 sgl->length = htole32(req_size);
1235 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1237 rc = oce_mbox_post(sc, &mbx, NULL);
1242 oce_mbox_macaddr_add(POCE_SOFTC sc, uint8_t *mac_addr,
1243 uint32_t if_id, uint32_t *pmac_id)
1246 struct mbx_add_common_iface_mac *fwcmd;
1249 bzero(&mbx, sizeof(struct oce_mbx));
1251 fwcmd = (struct mbx_add_common_iface_mac *)&mbx.payload;
1252 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1253 MBX_SUBSYSTEM_COMMON,
1254 OPCODE_COMMON_ADD_IFACE_MAC,
1256 sizeof(struct mbx_add_common_iface_mac),
1259 fwcmd->params.req.if_id = (uint16_t) if_id;
1260 bcopy(mac_addr, fwcmd->params.req.mac_address, 6);
1262 mbx.u0.s.embedded = 1;
1263 mbx.payload_length = sizeof(struct mbx_add_common_iface_mac);
1264 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1265 rc = oce_mbox_post(sc, &mbx, NULL);
1267 rc = fwcmd->hdr.u0.rsp.status;
1269 device_printf(sc->dev,
1270 "%s failed - cmd status: %d addi status: %d\n",
1272 fwcmd->hdr.u0.rsp.additional_status);
1275 *pmac_id = fwcmd->params.rsp.pmac_id;
1281 oce_mbox_macaddr_del(POCE_SOFTC sc, uint32_t if_id, uint32_t pmac_id)
1284 struct mbx_del_common_iface_mac *fwcmd;
1287 bzero(&mbx, sizeof(struct oce_mbx));
1289 fwcmd = (struct mbx_del_common_iface_mac *)&mbx.payload;
1290 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1291 MBX_SUBSYSTEM_COMMON,
1292 OPCODE_COMMON_DEL_IFACE_MAC,
1294 sizeof(struct mbx_del_common_iface_mac),
1297 fwcmd->params.req.if_id = (uint16_t)if_id;
1298 fwcmd->params.req.pmac_id = pmac_id;
1300 mbx.u0.s.embedded = 1;
1301 mbx.payload_length = sizeof(struct mbx_del_common_iface_mac);
1302 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1304 rc = oce_mbox_post(sc, &mbx, NULL);
1306 rc = fwcmd->hdr.u0.rsp.status;
1308 device_printf(sc->dev,
1309 "%s failed - cmd status: %d addi status: %d\n",
1311 fwcmd->hdr.u0.rsp.additional_status);
1316 oce_mbox_check_native_mode(POCE_SOFTC sc)
1319 struct mbx_common_set_function_cap *fwcmd;
1322 bzero(&mbx, sizeof(struct oce_mbx));
1324 fwcmd = (struct mbx_common_set_function_cap *)&mbx.payload;
1325 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1326 MBX_SUBSYSTEM_COMMON,
1327 OPCODE_COMMON_SET_FUNCTIONAL_CAPS,
1329 sizeof(struct mbx_common_set_function_cap),
1332 fwcmd->params.req.valid_capability_flags = CAP_SW_TIMESTAMPS |
1333 CAP_BE3_NATIVE_ERX_API;
1335 fwcmd->params.req.capability_flags = CAP_BE3_NATIVE_ERX_API;
1337 mbx.u0.s.embedded = 1;
1338 mbx.payload_length = sizeof(struct mbx_common_set_function_cap);
1339 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1341 rc = oce_mbox_post(sc, &mbx, NULL);
1343 rc = fwcmd->hdr.u0.rsp.status;
1345 device_printf(sc->dev,
1346 "%s failed - cmd status: %d addi status: %d\n",
1348 fwcmd->hdr.u0.rsp.additional_status);
1351 sc->be3_native = HOST_32(fwcmd->params.rsp.capability_flags)
1352 & CAP_BE3_NATIVE_ERX_API;
1359 oce_mbox_cmd_set_loopback(POCE_SOFTC sc, uint8_t port_num,
1360 uint8_t loopback_type, uint8_t enable)
1363 struct mbx_lowlevel_set_loopback_mode *fwcmd;
1366 bzero(&mbx, sizeof(struct oce_mbx));
1368 fwcmd = (struct mbx_lowlevel_set_loopback_mode *)&mbx.payload;
1369 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1370 MBX_SUBSYSTEM_LOWLEVEL,
1371 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
1373 sizeof(struct mbx_lowlevel_set_loopback_mode),
1376 fwcmd->params.req.src_port = port_num;
1377 fwcmd->params.req.dest_port = port_num;
1378 fwcmd->params.req.loopback_type = loopback_type;
1379 fwcmd->params.req.loopback_state = enable;
1381 mbx.u0.s.embedded = 1;
1382 mbx.payload_length = sizeof(struct mbx_lowlevel_set_loopback_mode);
1383 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1385 rc = oce_mbox_post(sc, &mbx, NULL);
1387 rc = fwcmd->hdr.u0.rsp.status;
1389 device_printf(sc->dev,
1390 "%s failed - cmd status: %d addi status: %d\n",
1392 fwcmd->hdr.u0.rsp.additional_status);
1399 oce_mbox_cmd_test_loopback(POCE_SOFTC sc, uint32_t port_num,
1400 uint32_t loopback_type, uint32_t pkt_size, uint32_t num_pkts,
1405 struct mbx_lowlevel_test_loopback_mode *fwcmd;
1408 bzero(&mbx, sizeof(struct oce_mbx));
1410 fwcmd = (struct mbx_lowlevel_test_loopback_mode *)&mbx.payload;
1411 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1412 MBX_SUBSYSTEM_LOWLEVEL,
1413 OPCODE_LOWLEVEL_TEST_LOOPBACK,
1415 sizeof(struct mbx_lowlevel_test_loopback_mode),
1418 fwcmd->params.req.pattern = pattern;
1419 fwcmd->params.req.src_port = port_num;
1420 fwcmd->params.req.dest_port = port_num;
1421 fwcmd->params.req.pkt_size = pkt_size;
1422 fwcmd->params.req.num_pkts = num_pkts;
1423 fwcmd->params.req.loopback_type = loopback_type;
1425 mbx.u0.s.embedded = 1;
1426 mbx.payload_length = sizeof(struct mbx_lowlevel_test_loopback_mode);
1427 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1429 rc = oce_mbox_post(sc, &mbx, NULL);
1431 rc = fwcmd->hdr.u0.rsp.status;
1433 device_printf(sc->dev,
1434 "%s failed - cmd status: %d addi status: %d\n",
1436 fwcmd->hdr.u0.rsp.additional_status);
1442 oce_mbox_write_flashrom(POCE_SOFTC sc, uint32_t optype,uint32_t opcode,
1443 POCE_DMA_MEM pdma_mem, uint32_t num_bytes)
1447 struct oce_mq_sge *sgl = NULL;
1448 struct mbx_common_read_write_flashrom *fwcmd = NULL;
1449 int rc = 0, payload_len = 0;
1451 bzero(&mbx, sizeof(struct oce_mbx));
1452 fwcmd = OCE_DMAPTR(pdma_mem, struct mbx_common_read_write_flashrom);
1453 payload_len = sizeof(struct mbx_common_read_write_flashrom) + 32*1024;
1455 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1456 MBX_SUBSYSTEM_COMMON,
1457 OPCODE_COMMON_WRITE_FLASHROM,
1462 fwcmd->flash_op_type = LE_32(optype);
1463 fwcmd->flash_op_code = LE_32(opcode);
1464 fwcmd->data_buffer_size = LE_32(num_bytes);
1466 mbx.u0.s.embedded = 0; /*Non embeded*/
1467 mbx.payload_length = payload_len;
1468 mbx.u0.s.sge_count = 1;
1470 sgl = &mbx.payload.u0.u1.sgl[0];
1471 sgl->pa_hi = upper_32_bits(pdma_mem->paddr);
1472 sgl->pa_lo = pdma_mem->paddr & 0xFFFFFFFF;
1473 sgl->length = payload_len;
1475 /* post the command */
1476 rc = oce_mbox_post(sc, &mbx, NULL);
1478 rc = fwcmd->hdr.u0.rsp.status;
1480 device_printf(sc->dev,
1481 "%s failed - cmd status: %d addi status: %d\n",
1483 fwcmd->hdr.u0.rsp.additional_status);
1490 oce_mbox_get_flashrom_crc(POCE_SOFTC sc, uint8_t *flash_crc,
1491 uint32_t offset, uint32_t optype)
1494 int rc = 0, payload_len = 0;
1496 struct mbx_common_read_write_flashrom *fwcmd;
1498 bzero(&mbx, sizeof(struct oce_mbx));
1500 fwcmd = (struct mbx_common_read_write_flashrom *)&mbx.payload;
1502 /* Firmware requires extra 4 bytes with this ioctl. Since there
1503 is enough room in the mbx payload it should be good enough
1504 Reference: Bug 14853
1506 payload_len = sizeof(struct mbx_common_read_write_flashrom) + 4;
1508 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1509 MBX_SUBSYSTEM_COMMON,
1510 OPCODE_COMMON_READ_FLASHROM,
1515 fwcmd->flash_op_type = optype;
1516 fwcmd->flash_op_code = FLASHROM_OPER_REPORT;
1517 fwcmd->data_offset = offset;
1518 fwcmd->data_buffer_size = 0x4;
1520 mbx.u0.s.embedded = 1;
1521 mbx.payload_length = payload_len;
1523 /* post the command */
1524 rc = oce_mbox_post(sc, &mbx, NULL);
1526 rc = fwcmd->hdr.u0.rsp.status;
1528 device_printf(sc->dev,
1529 "%s failed - cmd status: %d addi status: %d\n",
1531 fwcmd->hdr.u0.rsp.additional_status);
1534 bcopy(fwcmd->data_buffer, flash_crc, 4);
1540 oce_mbox_get_phy_info(POCE_SOFTC sc, struct oce_phy_info *phy_info)
1544 struct mbx_common_phy_info *fwcmd;
1547 bzero(&mbx, sizeof(struct oce_mbx));
1549 fwcmd = (struct mbx_common_phy_info *)&mbx.payload;
1550 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1551 MBX_SUBSYSTEM_COMMON,
1552 OPCODE_COMMON_GET_PHY_CONFIG,
1554 sizeof(struct mbx_common_phy_info),
1557 mbx.u0.s.embedded = 1;
1558 mbx.payload_length = sizeof(struct mbx_common_phy_info);
1560 /* now post the command */
1561 rc = oce_mbox_post(sc, &mbx, NULL);
1563 rc = fwcmd->hdr.u0.rsp.status;
1565 device_printf(sc->dev,
1566 "%s failed - cmd status: %d addi status: %d\n",
1568 fwcmd->hdr.u0.rsp.additional_status);
1571 phy_info->phy_type = HOST_16(fwcmd->params.rsp.phy_info.phy_type);
1572 phy_info->interface_type =
1573 HOST_16(fwcmd->params.rsp.phy_info.interface_type);
1574 phy_info->auto_speeds_supported =
1575 HOST_16(fwcmd->params.rsp.phy_info.auto_speeds_supported);
1576 phy_info->fixed_speeds_supported =
1577 HOST_16(fwcmd->params.rsp.phy_info.fixed_speeds_supported);
1578 phy_info->misc_params = HOST_32(fwcmd->params.rsp.phy_info.misc_params);
1585 oce_mbox_lancer_write_flashrom(POCE_SOFTC sc, uint32_t data_size,
1586 uint32_t data_offset, POCE_DMA_MEM pdma_mem,
1587 uint32_t *written_data, uint32_t *additional_status)
1591 struct mbx_lancer_common_write_object *fwcmd = NULL;
1592 int rc = 0, payload_len = 0;
1594 bzero(&mbx, sizeof(struct oce_mbx));
1595 payload_len = sizeof(struct mbx_lancer_common_write_object);
1597 mbx.u0.s.embedded = 1;/* Embedded */
1598 mbx.payload_length = payload_len;
1599 fwcmd = (struct mbx_lancer_common_write_object *)&mbx.payload;
1601 /* initialize the ioctl header */
1602 mbx_common_req_hdr_init(&fwcmd->params.req.hdr, 0, 0,
1603 MBX_SUBSYSTEM_COMMON,
1604 OPCODE_COMMON_WRITE_OBJECT,
1609 fwcmd->params.req.write_length = data_size;
1611 fwcmd->params.req.eof = 1;
1613 fwcmd->params.req.eof = 0;
1615 strcpy(fwcmd->params.req.object_name, "/prg");
1616 fwcmd->params.req.descriptor_count = 1;
1617 fwcmd->params.req.write_offset = data_offset;
1618 fwcmd->params.req.buffer_length = data_size;
1619 fwcmd->params.req.address_lower = pdma_mem->paddr & 0xFFFFFFFF;
1620 fwcmd->params.req.address_upper = upper_32_bits(pdma_mem->paddr);
1622 /* post the command */
1623 rc = oce_mbox_post(sc, &mbx, NULL);
1625 rc = fwcmd->params.rsp.status;
1627 device_printf(sc->dev,
1628 "%s failed - cmd status: %d addi status: %d\n",
1630 fwcmd->params.rsp.additional_status);
1633 *written_data = HOST_32(fwcmd->params.rsp.actual_write_length);
1634 *additional_status = fwcmd->params.rsp.additional_status;
1641 oce_mbox_create_rq(struct oce_rq *rq)
1645 struct mbx_create_nic_rq *fwcmd;
1646 POCE_SOFTC sc = rq->parent;
1647 int rc, num_pages = 0;
1649 if (rq->qstate == QCREATED)
1652 bzero(&mbx, sizeof(struct oce_mbx));
1654 fwcmd = (struct mbx_create_nic_rq *)&mbx.payload;
1655 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1657 NIC_CREATE_RQ, MBX_TIMEOUT_SEC,
1658 sizeof(struct mbx_create_nic_rq),
1661 /* oce_page_list will also prepare pages */
1662 num_pages = oce_page_list(rq->ring, &fwcmd->params.req.pages[0]);
1665 fwcmd->params.req.frag_size = rq->cfg.frag_size/2048;
1666 fwcmd->params.req.page_size = 1;
1667 fwcmd->hdr.u0.req.version = OCE_MBX_VER_V1;
1669 fwcmd->params.req.frag_size = OCE_LOG2(rq->cfg.frag_size);
1670 fwcmd->params.req.num_pages = num_pages;
1671 fwcmd->params.req.cq_id = rq->cq->cq_id;
1672 fwcmd->params.req.if_id = sc->if_id;
1673 fwcmd->params.req.max_frame_size = rq->cfg.mtu;
1674 fwcmd->params.req.is_rss_queue = rq->cfg.is_rss_queue;
1676 mbx.u0.s.embedded = 1;
1677 mbx.payload_length = sizeof(struct mbx_create_nic_rq);
1679 rc = oce_mbox_post(sc, &mbx, NULL);
1681 rc = fwcmd->hdr.u0.rsp.status;
1683 device_printf(sc->dev,
1684 "%s failed - cmd status: %d addi status: %d\n",
1686 fwcmd->hdr.u0.rsp.additional_status);
1689 rq->rq_id = HOST_16(fwcmd->params.rsp.rq_id);
1690 rq->rss_cpuid = fwcmd->params.rsp.rss_cpuid;
1697 oce_mbox_create_wq(struct oce_wq *wq)
1700 struct mbx_create_nic_wq *fwcmd;
1701 POCE_SOFTC sc = wq->parent;
1702 int rc = 0, version, num_pages;
1704 bzero(&mbx, sizeof(struct oce_mbx));
1706 fwcmd = (struct mbx_create_nic_wq *)&mbx.payload;
1708 version = OCE_MBX_VER_V1;
1710 IS_PROFILE_SUPER_NIC(sc) ? (version = OCE_MBX_VER_V2)
1711 : (version = OCE_MBX_VER_V0);
1713 version = OCE_MBX_VER_V2;
1715 if (version > OCE_MBX_VER_V0)
1716 fwcmd->params.req.if_id = sc->if_id;
1718 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1720 NIC_CREATE_WQ, MBX_TIMEOUT_SEC,
1721 sizeof(struct mbx_create_nic_wq),
1724 num_pages = oce_page_list(wq->ring, &fwcmd->params.req.pages[0]);
1726 fwcmd->params.req.nic_wq_type = wq->cfg.wq_type;
1727 fwcmd->params.req.num_pages = num_pages;
1728 fwcmd->params.req.wq_size = OCE_LOG2(wq->cfg.q_len) + 1;
1729 fwcmd->params.req.cq_id = wq->cq->cq_id;
1730 fwcmd->params.req.ulp_num = 1;
1732 mbx.u0.s.embedded = 1;
1733 mbx.payload_length = sizeof(struct mbx_create_nic_wq);
1735 rc = oce_mbox_post(sc, &mbx, NULL);
1737 rc = fwcmd->hdr.u0.rsp.status;
1739 device_printf(sc->dev,
1740 "%s failed - cmd status: %d addi status: %d\n",
1742 fwcmd->hdr.u0.rsp.additional_status);
1745 wq->wq_id = HOST_16(fwcmd->params.rsp.wq_id);
1746 if (version == OCE_MBX_VER_V2)
1747 wq->db_offset = HOST_32(fwcmd->params.rsp.db_offset);
1749 wq->db_offset = PD_TXULP_DB;
1756 oce_mbox_create_eq(struct oce_eq *eq)
1759 struct mbx_create_common_eq *fwcmd;
1760 POCE_SOFTC sc = eq->parent;
1764 bzero(&mbx, sizeof(struct oce_mbx));
1766 fwcmd = (struct mbx_create_common_eq *)&mbx.payload;
1768 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1769 MBX_SUBSYSTEM_COMMON,
1770 OPCODE_COMMON_CREATE_EQ, MBX_TIMEOUT_SEC,
1771 sizeof(struct mbx_create_common_eq),
1774 num_pages = oce_page_list(eq->ring, &fwcmd->params.req.pages[0]);
1775 fwcmd->params.req.ctx.num_pages = num_pages;
1776 fwcmd->params.req.ctx.valid = 1;
1777 fwcmd->params.req.ctx.size = (eq->eq_cfg.item_size == 4) ? 0 : 1;
1778 fwcmd->params.req.ctx.count = OCE_LOG2(eq->eq_cfg.q_len / 256);
1779 fwcmd->params.req.ctx.armed = 0;
1780 fwcmd->params.req.ctx.delay_mult = eq->eq_cfg.cur_eqd;
1782 mbx.u0.s.embedded = 1;
1783 mbx.payload_length = sizeof(struct mbx_create_common_eq);
1785 rc = oce_mbox_post(sc, &mbx, NULL);
1787 rc = fwcmd->hdr.u0.rsp.status;
1789 device_printf(sc->dev,
1790 "%s failed - cmd status: %d addi status: %d\n",
1792 fwcmd->hdr.u0.rsp.additional_status);
1795 eq->eq_id = HOST_16(fwcmd->params.rsp.eq_id);
1801 oce_mbox_cq_create(struct oce_cq *cq, uint32_t ncoalesce, uint32_t is_eventable)
1804 struct mbx_create_common_cq *fwcmd;
1805 POCE_SOFTC sc = cq->parent;
1808 uint32_t num_pages, page_size;
1811 bzero(&mbx, sizeof(struct oce_mbx));
1813 fwcmd = (struct mbx_create_common_cq *)&mbx.payload;
1816 version = OCE_MBX_VER_V2;
1818 version = OCE_MBX_VER_V0;
1820 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1821 MBX_SUBSYSTEM_COMMON,
1822 OPCODE_COMMON_CREATE_CQ,
1824 sizeof(struct mbx_create_common_cq),
1827 ctx = &fwcmd->params.req.cq_ctx;
1829 num_pages = oce_page_list(cq->ring, &fwcmd->params.req.pages[0]);
1830 page_size = 1; /* 1 for 4K */
1832 if (version == OCE_MBX_VER_V2) {
1833 ctx->v2.num_pages = LE_16(num_pages);
1834 ctx->v2.page_size = page_size;
1835 ctx->v2.eventable = is_eventable;
1837 ctx->v2.count = OCE_LOG2(cq->cq_cfg.q_len / 256);
1838 ctx->v2.nodelay = cq->cq_cfg.nodelay;
1839 ctx->v2.coalesce_wm = ncoalesce;
1841 ctx->v2.eq_id = cq->eq->eq_id;
1842 if (ctx->v2.count == 3) {
1843 if ((u_int)cq->cq_cfg.q_len > (4*1024)-1)
1844 ctx->v2.cqe_count = (4*1024)-1;
1846 ctx->v2.cqe_count = cq->cq_cfg.q_len;
1849 ctx->v0.num_pages = LE_16(num_pages);
1850 ctx->v0.eventable = is_eventable;
1852 ctx->v0.count = OCE_LOG2(cq->cq_cfg.q_len / 256);
1853 ctx->v0.nodelay = cq->cq_cfg.nodelay;
1854 ctx->v0.coalesce_wm = ncoalesce;
1856 ctx->v0.eq_id = cq->eq->eq_id;
1859 mbx.u0.s.embedded = 1;
1860 mbx.payload_length = sizeof(struct mbx_create_common_cq);
1862 rc = oce_mbox_post(sc, &mbx, NULL);
1864 rc = fwcmd->hdr.u0.rsp.status;
1866 device_printf(sc->dev,
1867 "%s failed - cmd status: %d addi status: %d\n",
1869 fwcmd->hdr.u0.rsp.additional_status);
1872 cq->cq_id = HOST_16(fwcmd->params.rsp.cq_id);
1879 oce_mbox_read_transrecv_data(POCE_SOFTC sc, uint32_t page_num)
1883 struct mbx_read_common_transrecv_data *fwcmd;
1884 struct oce_mq_sge *sgl;
1887 /* Allocate DMA mem*/
1888 if (oce_dma_alloc(sc, sizeof(struct mbx_read_common_transrecv_data),
1892 fwcmd = OCE_DMAPTR(&dma, struct mbx_read_common_transrecv_data);
1893 bzero(fwcmd, sizeof(struct mbx_read_common_transrecv_data));
1895 bzero(&mbx, sizeof(struct oce_mbx));
1896 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1897 MBX_SUBSYSTEM_COMMON,
1898 OPCODE_COMMON_READ_TRANSRECEIVER_DATA,
1900 sizeof(struct mbx_read_common_transrecv_data),
1903 /* fill rest of mbx */
1904 mbx.u0.s.embedded = 0;
1905 mbx.payload_length = sizeof(struct mbx_read_common_transrecv_data);
1906 mbx.u0.s.sge_count = 1;
1907 sgl = &mbx.payload.u0.u1.sgl[0];
1908 sgl->pa_hi = htole32(upper_32_bits(dma.paddr));
1909 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF);
1910 sgl->length = htole32(mbx.payload_length);
1911 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1913 fwcmd->params.req.port = LE_32(sc->port_id);
1914 fwcmd->params.req.page_num = LE_32(page_num);
1917 rc = oce_mbox_post(sc, &mbx, NULL);
1919 rc = fwcmd->hdr.u0.rsp.status;
1921 device_printf(sc->dev,
1922 "%s failed - cmd status: %d addi status: %d\n",
1924 fwcmd->hdr.u0.rsp.additional_status);
1927 if(fwcmd->params.rsp.page_num == PAGE_NUM_A0)
1929 bcopy((char *)fwcmd->params.rsp.page_data,
1930 &sfp_vpd_dump_buffer[0],
1931 TRANSCEIVER_A0_SIZE);
1934 if(fwcmd->params.rsp.page_num == PAGE_NUM_A2)
1936 bcopy((char *)fwcmd->params.rsp.page_data,
1937 &sfp_vpd_dump_buffer[TRANSCEIVER_A0_SIZE],
1938 TRANSCEIVER_A2_SIZE);
1941 oce_dma_free(sc, &dma);
1946 oce_mbox_eqd_modify_periodic(POCE_SOFTC sc, struct oce_set_eqd *set_eqd,
1950 struct mbx_modify_common_eq_delay *fwcmd;
1954 bzero(&mbx, sizeof(struct oce_mbx));
1956 /* Initialize MODIFY_EQ_DELAY ioctl header */
1957 fwcmd = (struct mbx_modify_common_eq_delay *)&mbx.payload;
1958 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1959 MBX_SUBSYSTEM_COMMON,
1960 OPCODE_COMMON_MODIFY_EQ_DELAY,
1962 sizeof(struct mbx_modify_common_eq_delay),
1964 /* fill rest of mbx */
1965 mbx.u0.s.embedded = 1;
1966 mbx.payload_length = sizeof(struct mbx_modify_common_eq_delay);
1967 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1969 fwcmd->params.req.num_eq = num;
1970 for (i = 0; i < num; i++) {
1971 fwcmd->params.req.delay[i].eq_id =
1972 htole32(set_eqd[i].eq_id);
1973 fwcmd->params.req.delay[i].phase = 0;
1974 fwcmd->params.req.delay[i].dm =
1975 htole32(set_eqd[i].delay_multiplier);
1979 rc = oce_mbox_post(sc, &mbx, NULL);
1982 rc = fwcmd->hdr.u0.rsp.status;
1984 device_printf(sc->dev,
1985 "%s failed - cmd status: %d addi status: %d\n",
1987 fwcmd->hdr.u0.rsp.additional_status);
1991 oce_get_profile_config(POCE_SOFTC sc, uint32_t max_rss)
1994 struct mbx_common_get_profile_config *fwcmd;
1997 struct oce_mq_sge *sgl;
1999 uint32_t desc_count = 0;
2000 struct oce_nic_resc_desc *nic_desc = NULL;
2002 boolean_t nic_desc_valid = FALSE;
2007 /* Allocate DMA mem*/
2008 if (oce_dma_alloc(sc, sizeof(struct mbx_common_get_profile_config),
2012 /* Initialize MODIFY_EQ_DELAY ioctl header */
2013 fwcmd = OCE_DMAPTR(&dma, struct mbx_common_get_profile_config);
2014 bzero(fwcmd, sizeof(struct mbx_common_get_profile_config));
2017 version = OCE_MBX_VER_V1;
2019 version = OCE_MBX_VER_V0;
2021 bzero(&mbx, sizeof(struct oce_mbx));
2022 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
2023 MBX_SUBSYSTEM_COMMON,
2024 OPCODE_COMMON_GET_PROFILE_CONFIG,
2026 sizeof(struct mbx_common_get_profile_config),
2028 /* fill rest of mbx */
2029 mbx.u0.s.embedded = 0;
2030 mbx.payload_length = sizeof(struct mbx_common_get_profile_config);
2031 mbx.u0.s.sge_count = 1;
2032 sgl = &mbx.payload.u0.u1.sgl[0];
2033 sgl->pa_hi = htole32(upper_32_bits(dma.paddr));
2034 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF);
2035 sgl->length = htole32(mbx.payload_length);
2036 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
2038 fwcmd->params.req.type = ACTIVE_PROFILE;
2041 rc = oce_mbox_post(sc, &mbx, NULL);
2043 rc = fwcmd->hdr.u0.rsp.status;
2045 device_printf(sc->dev,
2046 "%s failed - cmd status: %d addi status: %d\n",
2048 fwcmd->hdr.u0.rsp.additional_status);
2052 nic_desc = (struct oce_nic_resc_desc *) fwcmd->params.rsp.resources;
2053 desc_count = HOST_32(fwcmd->params.rsp.desc_count);
2054 for (i = 0; i < desc_count; i++) {
2055 if ((nic_desc->desc_type == NIC_RESC_DESC_TYPE_V0) ||
2056 (nic_desc->desc_type == NIC_RESC_DESC_TYPE_V1)) {
2057 nic_desc_valid = TRUE;
2060 nic_desc = (struct oce_nic_resc_desc *) \
2061 ((char *)nic_desc + nic_desc->desc_len);
2063 if (!nic_desc_valid) {
2068 sc->max_vlans = HOST_16(nic_desc->vlan_count);
2069 sc->nwqs = HOST_16(nic_desc->txq_count);
2071 sc->nwqs = MIN(sc->nwqs, OCE_MAX_WQ);
2073 sc->nwqs = OCE_MAX_WQ;
2075 sc->nrssqs = HOST_16(nic_desc->rssq_count);
2077 sc->nrssqs = MIN(sc->nrssqs, max_rss);
2079 sc->nrssqs = max_rss;
2080 sc->nrqs = sc->nrssqs + 1; /* 1 for def RX */
2083 oce_dma_free(sc, &dma);
2089 oce_get_func_config(POCE_SOFTC sc)
2092 struct mbx_common_get_func_config *fwcmd;
2095 struct oce_mq_sge *sgl;
2097 uint32_t desc_count = 0;
2098 struct oce_nic_resc_desc *nic_desc = NULL;
2100 boolean_t nic_desc_valid = FALSE;
2101 uint32_t max_rss = 0;
2103 if ((IS_BE(sc) || IS_SH(sc)) && (!sc->be3_native))
2104 max_rss = OCE_LEGACY_MODE_RSS;
2106 max_rss = OCE_MAX_RSS;
2108 /* Allocate DMA mem*/
2109 if (oce_dma_alloc(sc, sizeof(struct mbx_common_get_func_config),
2113 /* Initialize MODIFY_EQ_DELAY ioctl header */
2114 fwcmd = OCE_DMAPTR(&dma, struct mbx_common_get_func_config);
2115 bzero(fwcmd, sizeof(struct mbx_common_get_func_config));
2118 version = OCE_MBX_VER_V1;
2120 version = OCE_MBX_VER_V0;
2122 bzero(&mbx, sizeof(struct oce_mbx));
2123 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
2124 MBX_SUBSYSTEM_COMMON,
2125 OPCODE_COMMON_GET_FUNCTION_CONFIG,
2127 sizeof(struct mbx_common_get_func_config),
2129 /* fill rest of mbx */
2130 mbx.u0.s.embedded = 0;
2131 mbx.payload_length = sizeof(struct mbx_common_get_func_config);
2132 mbx.u0.s.sge_count = 1;
2133 sgl = &mbx.payload.u0.u1.sgl[0];
2134 sgl->pa_hi = htole32(upper_32_bits(dma.paddr));
2135 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF);
2136 sgl->length = htole32(mbx.payload_length);
2137 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
2140 rc = oce_mbox_post(sc, &mbx, NULL);
2142 rc = fwcmd->hdr.u0.rsp.status;
2144 device_printf(sc->dev,
2145 "%s failed - cmd status: %d addi status: %d\n",
2147 fwcmd->hdr.u0.rsp.additional_status);
2151 nic_desc = (struct oce_nic_resc_desc *) fwcmd->params.rsp.resources;
2152 desc_count = HOST_32(fwcmd->params.rsp.desc_count);
2153 for (i = 0; i < desc_count; i++) {
2154 if ((nic_desc->desc_type == NIC_RESC_DESC_TYPE_V0) ||
2155 (nic_desc->desc_type == NIC_RESC_DESC_TYPE_V1)) {
2156 nic_desc_valid = TRUE;
2159 nic_desc = (struct oce_nic_resc_desc *) \
2160 ((char *)nic_desc + nic_desc->desc_len);
2162 if (!nic_desc_valid) {
2167 sc->max_vlans = nic_desc->vlan_count;
2168 sc->nwqs = HOST_32(nic_desc->txq_count);
2170 sc->nwqs = MIN(sc->nwqs, OCE_MAX_WQ);
2172 sc->nwqs = OCE_MAX_WQ;
2174 sc->nrssqs = HOST_32(nic_desc->rssq_count);
2176 sc->nrssqs = MIN(sc->nrssqs, max_rss);
2178 sc->nrssqs = max_rss;
2179 sc->nrqs = sc->nrssqs + 1; /* 1 for def RX */
2182 oce_dma_free(sc, &dma);
2187 /* hw lro functions */
2190 oce_mbox_nic_query_lro_capabilities(POCE_SOFTC sc, uint32_t *lro_rq_cnt, uint32_t *lro_flags)
2193 struct mbx_nic_query_lro_capabilities *fwcmd;
2196 bzero(&mbx, sizeof(struct oce_mbx));
2198 fwcmd = (struct mbx_nic_query_lro_capabilities *)&mbx.payload;
2199 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
2201 0x20,MBX_TIMEOUT_SEC,
2202 sizeof(struct mbx_nic_query_lro_capabilities),
2205 mbx.u0.s.embedded = 1;
2206 mbx.payload_length = sizeof(struct mbx_nic_query_lro_capabilities);
2208 rc = oce_mbox_post(sc, &mbx, NULL);
2210 rc = fwcmd->hdr.u0.rsp.status;
2212 device_printf(sc->dev,
2213 "%s failed - cmd status: %d addi status: %d\n",
2215 fwcmd->hdr.u0.rsp.additional_status);
2220 *lro_flags = HOST_32(fwcmd->params.rsp.lro_flags);
2223 *lro_rq_cnt = HOST_16(fwcmd->params.rsp.lro_rq_cnt);
2229 oce_mbox_nic_set_iface_lro_config(POCE_SOFTC sc, int enable)
2232 struct mbx_nic_set_iface_lro_config *fwcmd;
2235 bzero(&mbx, sizeof(struct oce_mbx));
2237 fwcmd = (struct mbx_nic_set_iface_lro_config *)&mbx.payload;
2238 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
2240 0x26,MBX_TIMEOUT_SEC,
2241 sizeof(struct mbx_nic_set_iface_lro_config),
2244 mbx.u0.s.embedded = 1;
2245 mbx.payload_length = sizeof(struct mbx_nic_set_iface_lro_config);
2247 fwcmd->params.req.iface_id = sc->if_id;
2248 fwcmd->params.req.lro_flags = 0;
2251 fwcmd->params.req.lro_flags = LRO_FLAGS_HASH_MODE | LRO_FLAGS_RSS_MODE;
2252 fwcmd->params.req.lro_flags |= LRO_FLAGS_CLSC_IPV4 | LRO_FLAGS_CLSC_IPV6;
2254 fwcmd->params.req.max_clsc_byte_cnt = 64*1024; /* min = 2974, max = 0xfa59 */
2255 fwcmd->params.req.max_clsc_seg_cnt = 43; /* min = 2, max = 64 */
2256 fwcmd->params.req.max_clsc_usec_delay = 18; /* min = 1, max = 256 */
2257 fwcmd->params.req.min_clsc_frame_byte_cnt = 0; /* min = 1, max = 9014 */
2260 rc = oce_mbox_post(sc, &mbx, NULL);
2262 rc = fwcmd->hdr.u0.rsp.status;
2264 device_printf(sc->dev,
2265 "%s failed - cmd status: %d addi status: %d\n",
2267 fwcmd->hdr.u0.rsp.additional_status);
2275 oce_mbox_create_rq_v2(struct oce_rq *rq)
2278 struct mbx_create_nic_rq_v2 *fwcmd;
2279 POCE_SOFTC sc = rq->parent;
2280 int rc = 0, num_pages = 0;
2282 if (rq->qstate == QCREATED)
2285 bzero(&mbx, sizeof(struct oce_mbx));
2287 fwcmd = (struct mbx_create_nic_rq_v2 *)&mbx.payload;
2288 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
2290 0x08, MBX_TIMEOUT_SEC,
2291 sizeof(struct mbx_create_nic_rq_v2),
2294 /* oce_page_list will also prepare pages */
2295 num_pages = oce_page_list(rq->ring, &fwcmd->params.req.pages[0]);
2297 fwcmd->params.req.cq_id = rq->cq->cq_id;
2298 fwcmd->params.req.frag_size = rq->cfg.frag_size/2048;
2299 fwcmd->params.req.num_pages = num_pages;
2301 fwcmd->params.req.if_id = sc->if_id;
2303 fwcmd->params.req.max_frame_size = rq->cfg.mtu;
2304 fwcmd->params.req.page_size = 1;
2305 if(rq->cfg.is_rss_queue) {
2306 fwcmd->params.req.rq_flags = (NIC_RQ_FLAGS_RSS | NIC_RQ_FLAGS_LRO);
2308 device_printf(sc->dev,
2309 "non rss lro queue should not be created \n");
2312 mbx.u0.s.embedded = 1;
2313 mbx.payload_length = sizeof(struct mbx_create_nic_rq_v2);
2315 rc = oce_mbox_post(sc, &mbx, NULL);
2317 rc = fwcmd->hdr.u0.rsp.status;
2319 device_printf(sc->dev,
2320 "%s failed - cmd status: %d addi status: %d\n",
2322 fwcmd->hdr.u0.rsp.additional_status);
2325 rq->rq_id = HOST_16(fwcmd->params.rsp.rq_id);
2326 rq->rss_cpuid = fwcmd->params.rsp.rss_cpuid;