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3 * The term "Broadcom" refers to Broadcom Limited and/or its subsidiaries.
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29 * POSSIBILITY OF SUCH DAMAGE.
36 * Define common SLI-4 structures and function prototypes.
44 #define SLI_PAGE_SIZE (4096)
45 #define SLI_SUB_PAGE_MASK (SLI_PAGE_SIZE - 1)
46 #define SLI_PAGE_SHIFT 12
47 #define SLI_ROUND_PAGE(b) (((b) + SLI_SUB_PAGE_MASK) & ~SLI_SUB_PAGE_MASK)
49 #define SLI4_BMBX_TIMEOUT_MSEC 30000
50 #define SLI4_FW_READY_TIMEOUT_MSEC 30000
52 static inline uint32_t
53 sli_page_count(size_t bytes, uint32_t page_size)
55 uint32_t mask = page_size - 1;
78 return (bytes + mask) >> shift;
81 /*************************************************************************
82 * Common PCI configuration space register definitions
85 #define SLI4_PCI_CLASS_REVISION 0x0008 /** register offset */
86 #define SLI4_PCI_REV_ID_SHIFT 0
87 #define SLI4_PCI_REV_ID_MASK 0xff
88 #define SLI4_PCI_CLASS_SHIFT 8
89 #define SLI4_PCI_CLASS_MASK 0xfff
91 #define SLI4_PCI_SOFT_RESET_CSR 0x005c /** register offset */
92 #define SLI4_PCI_SOFT_RESET_MASK 0x0080
94 /*************************************************************************
95 * Common SLI-4 register offsets and field definitions
99 * @brief SLI_INTF - SLI Interface Definition Register
101 #define SLI4_INTF_REG 0x0058 /** register offset */
102 #define SLI4_INTF_VALID_SHIFT 29
103 #define SLI4_INTF_VALID_MASK 0x7
104 #define SLI4_INTF_VALID 0x6
105 #define SLI4_INTF_IF_TYPE_SHIFT 12
106 #define SLI4_INTF_IF_TYPE_MASK 0xf
107 #define SLI4_INTF_SLI_FAMILY_SHIFT 8
108 #define SLI4_INTF_SLI_FAMILY_MASK 0xf
109 #define SLI4_INTF_SLI_REVISION_SHIFT 4
110 #define SLI4_INTF_SLI_REVISION_MASK 0xf
111 #define SLI4_FAMILY_CHECK_ASIC_TYPE 0xf
113 #define SLI4_IF_TYPE_BE3_SKH_PF 0
114 #define SLI4_IF_TYPE_BE3_SKH_VF 1
115 #define SLI4_IF_TYPE_LANCER_FC_ETH 2
116 #define SLI4_IF_TYPE_LANCER_RDMA 3
117 #define SLI4_IF_TYPE_LANCER_G7 6
118 #define SLI4_MAX_IF_TYPES 7
121 * @brief ASIC_ID - SLI ASIC Type and Revision Register
123 #define SLI4_ASIC_ID_REG 0x009c /* register offset */
124 #define SLI4_ASIC_REV_SHIFT 0
125 #define SLI4_ASIC_REV_MASK 0xf
126 #define SLI4_ASIC_VER_SHIFT 4
127 #define SLI4_ASIC_VER_MASK 0xf
128 #define SLI4_ASIC_GEN_SHIFT 8
129 #define SLI4_ASIC_GEN_MASK 0xff
130 #define SLI4_ASIC_GEN_BE2 0x00
131 #define SLI4_ASIC_GEN_BE3 0x03
132 #define SLI4_ASIC_GEN_SKYHAWK 0x04
133 #define SLI4_ASIC_GEN_CORSAIR 0x05
134 #define SLI4_ASIC_GEN_LANCER 0x0b
137 * @brief BMBX - Bootstrap Mailbox Register
139 #define SLI4_BMBX_REG 0x0160 /* register offset */
140 #define SLI4_BMBX_MASK_HI 0x3
141 #define SLI4_BMBX_MASK_LO 0xf
142 #define SLI4_BMBX_RDY BIT(0)
143 #define SLI4_BMBX_HI BIT(1)
144 #define SLI4_BMBX_WRITE_HI(r) ((ocs_addr32_hi(r) & ~SLI4_BMBX_MASK_HI) | \
146 #define SLI4_BMBX_WRITE_LO(r) (((ocs_addr32_hi(r) & SLI4_BMBX_MASK_HI) << 30) | \
147 (((r) & ~SLI4_BMBX_MASK_LO) >> 2))
149 #define SLI4_BMBX_SIZE 256
152 * @brief EQCQ_DOORBELL - EQ and CQ Doorbell Register
154 #define SLI4_EQCQ_DOORBELL_REG 0x120
155 #define SLI4_EQCQ_DOORBELL_CI BIT(9)
156 #define SLI4_EQCQ_DOORBELL_QT BIT(10)
157 #define SLI4_EQCQ_DOORBELL_ARM BIT(29)
158 #define SLI4_EQCQ_DOORBELL_SE BIT(31)
159 #define SLI4_EQCQ_NUM_SHIFT 16
160 #define SLI4_EQCQ_NUM_MASK 0x01ff
161 #define SLI4_EQCQ_EQ_ID_MASK 0x3fff
162 #define SLI4_EQCQ_CQ_ID_MASK 0x7fff
163 #define SLI4_EQCQ_EQ_ID_MASK_LO 0x01ff
164 #define SLI4_EQCQ_CQ_ID_MASK_LO 0x03ff
165 #define SLI4_EQCQ_EQCQ_ID_MASK_HI 0xf800
166 #define SLI4_IF6_EQ_DOORBELL_REG 0x120
167 #define SLI4_IF6_CQ_DOORBELL_REG 0xC0
170 * @brief SLIPORT_CONTROL - SLI Port Control Register
172 #define SLI4_SLIPORT_CONTROL_REG 0x0408
173 #define SLI4_SLIPORT_CONTROL_END BIT(30)
174 #define SLI4_SLIPORT_CONTROL_LITTLE_ENDIAN (0)
175 #define SLI4_SLIPORT_CONTROL_BIG_ENDIAN BIT(30)
176 #define SLI4_SLIPORT_CONTROL_IP BIT(27)
177 #define SLI4_SLIPORT_CONTROL_IDIS BIT(22)
178 #define SLI4_SLIPORT_CONTROL_FDD BIT(31)
181 * @brief SLI4_SLIPORT_ERROR1 - SLI Port Error Register
183 #define SLI4_SLIPORT_ERROR1 0x040c
186 * @brief SLI4_SLIPORT_ERROR2 - SLI Port Error Register
188 #define SLI4_SLIPORT_ERROR2 0x0410
191 * @brief User error registers
193 #define SLI4_UERR_STATUS_LOW_REG 0xA0
194 #define SLI4_UERR_STATUS_HIGH_REG 0xA4
195 #define SLI4_UERR_MASK_LOW_REG 0xA8
196 #define SLI4_UERR_MASK_HIGH_REG 0xAC
199 * @brief Registers for generating software UE (BE3)
201 #define SLI4_SW_UE_CSR1 0x138
202 #define SLI4_SW_UE_CSR2 0x1FFFC
205 * @brief Registers for generating software UE (Skyhawk)
207 #define SLI4_SW_UE_REG 0x5C /* register offset */
209 static inline uint32_t sli_eq_doorbell(uint16_t n_popped, uint16_t id, uint8_t arm)
212 #if BYTE_ORDER == LITTLE_ENDIAN
215 ci:1, /* clear interrupt */
216 qt:1, /* queue type */
222 } * eq_doorbell = (void *)®
224 #error big endian version not defined
227 eq_doorbell->eq_id_lo = id & SLI4_EQCQ_EQ_ID_MASK_LO;
228 eq_doorbell->qt = 1; /* EQ is type 1 (section 2.2.3.3 SLI Arch) */
229 eq_doorbell->eq_id_hi = (id >> 9) & 0x1f;
230 eq_doorbell->number_popped = n_popped;
231 eq_doorbell->arm = arm;
232 eq_doorbell->ci = TRUE;
237 static inline uint32_t sli_cq_doorbell(uint16_t n_popped, uint16_t id, uint8_t arm)
240 #if BYTE_ORDER == LITTLE_ENDIAN
242 uint32_t cq_id_lo:10,
243 qt:1, /* queue type */
249 } * cq_doorbell = (void *)®
251 #error big endian version not defined
254 cq_doorbell->cq_id_lo = id & SLI4_EQCQ_CQ_ID_MASK_LO;
255 cq_doorbell->qt = 0; /* CQ is type 0 (section 2.2.3.3 SLI Arch) */
256 cq_doorbell->cq_id_hi = (id >> 10) & 0x1f;
257 cq_doorbell->number_popped = n_popped;
258 cq_doorbell->arm = arm;
263 static inline uint32_t sli_iftype6_eq_doorbell(uint16_t n_popped, uint16_t id, uint8_t arm)
266 #if BYTE_ORDER == LITTLE_ENDIAN
269 :4, /* clear interrupt */
274 } * eq_doorbell = (void *)®
276 #error big endian version not defined
279 eq_doorbell->eq_id = id;
280 eq_doorbell->number_popped = n_popped;
281 eq_doorbell->arm = arm;
286 static inline uint32_t sli_iftype6_cq_doorbell(uint16_t n_popped, uint16_t id, uint8_t arm)
289 #if BYTE_ORDER == LITTLE_ENDIAN
296 } * cq_doorbell = (void *)®
298 #error big endian version not defined
301 cq_doorbell->cq_id = id;
302 cq_doorbell->number_popped = n_popped;
303 cq_doorbell->arm = arm;
309 * @brief MQ_DOORBELL - MQ Doorbell Register
311 #define SLI4_MQ_DOORBELL_REG 0x0140 /* register offset */
312 #define SLI4_IF6_MQ_DOORBELL_REG 0x0160 /* register offset if_type = 6 */
313 #define SLI4_MQ_DOORBELL_NUM_SHIFT 16
314 #define SLI4_MQ_DOORBELL_NUM_MASK 0x3fff
315 #define SLI4_MQ_DOORBELL_ID_MASK 0xffff
316 #define SLI4_MQ_DOORBELL(n, i) ((((n) & SLI4_MQ_DOORBELL_NUM_MASK) << SLI4_MQ_DOORBELL_NUM_SHIFT) | \
317 ((i) & SLI4_MQ_DOORBELL_ID_MASK))
320 * @brief RQ_DOORBELL - RQ Doorbell Register
322 #define SLI4_RQ_DOORBELL_REG 0x0a0 /* register offset */
323 #define SLI4_IF6_RQ_DOORBELL_REG 0x0080 /* register offset of if_type = 6 */
324 #define SLI4_RQ_DOORBELL_NUM_SHIFT 16
325 #define SLI4_RQ_DOORBELL_NUM_MASK 0x3fff
326 #define SLI4_RQ_DOORBELL_ID_MASK 0xffff
327 #define SLI4_RQ_DOORBELL(n, i) ((((n) & SLI4_RQ_DOORBELL_NUM_MASK) << SLI4_RQ_DOORBELL_NUM_SHIFT) | \
328 ((i) & SLI4_RQ_DOORBELL_ID_MASK))
331 * @brief WQ_DOORBELL - WQ Doorbell Register
333 #define SLI4_IO_WQ_DOORBELL_REG 0x040 /* register offset */
334 #define SLI4_IF6_WQ_DOORBELL_REG 0x040 /* register offset for if_type = 6 */
335 #define SLI4_WQ_DOORBELL_IDX_SHIFT 16
336 #define SLI4_WQ_DOORBELL_IDX_MASK 0x00ff
337 #define SLI4_WQ_DOORBELL_NUM_SHIFT 24
338 #define SLI4_WQ_DOORBELL_NUM_MASK 0x00ff
339 #define SLI4_WQ_DOORBELL_ID_MASK 0xffff
340 #define SLI4_WQ_DOORBELL(n, x, i) ((((n) & SLI4_WQ_DOORBELL_NUM_MASK) << SLI4_WQ_DOORBELL_NUM_SHIFT) | \
341 (((x) & SLI4_WQ_DOORBELL_IDX_MASK) << SLI4_WQ_DOORBELL_IDX_SHIFT) | \
342 ((i) & SLI4_WQ_DOORBELL_ID_MASK))
345 * @brief SLIPORT_SEMAPHORE - SLI Port Host and Port Status Register
347 #define SLI4_PORT_SEMAPHORE_REG_0 0x00ac /** register offset Interface Type 0 + 1 */
348 #define SLI4_PORT_SEMAPHORE_REG_1 0x0180 /** register offset Interface Type 0 + 1 */
349 #define SLI4_PORT_SEMAPHORE_REG_236 0x0400 /** register offset Interface Type 2 + 3 + 6*/
350 #define SLI4_PORT_SEMAPHORE_PORT_MASK 0x0000ffff
351 #define SLI4_PORT_SEMAPHORE_PORT(r) ((r) & SLI4_PORT_SEMAPHORE_PORT_MASK)
352 #define SLI4_PORT_SEMAPHORE_HOST_MASK 0x00ff0000
353 #define SLI4_PORT_SEMAPHORE_HOST_SHIFT 16
354 #define SLI4_PORT_SEMAPHORE_HOST(r) (((r) & SLI4_PORT_SEMAPHORE_HOST_MASK) >> \
355 SLI4_PORT_SEMAPHORE_HOST_SHIFT)
356 #define SLI4_PORT_SEMAPHORE_SCR2 BIT(26) /** scratch area 2 */
357 #define SLI4_PORT_SEMAPHORE_SCR1 BIT(27) /** scratch area 1 */
358 #define SLI4_PORT_SEMAPHORE_IPC BIT(28) /** IP conflict */
359 #define SLI4_PORT_SEMAPHORE_NIP BIT(29) /** no IP address */
360 #define SLI4_PORT_SEMAPHORE_SFI BIT(30) /** secondary firmware image used */
361 #define SLI4_PORT_SEMAPHORE_PERR BIT(31) /** POST fatal error */
363 #define SLI4_PORT_SEMAPHORE_STATUS_POST_READY 0xc000
364 #define SLI4_PORT_SEMAPHORE_STATUS_UNRECOV_ERR 0xf000
365 #define SLI4_PORT_SEMAPHORE_STATUS_ERR_MASK 0xf000
366 #define SLI4_PORT_SEMAPHORE_IN_ERR(r) (SLI4_PORT_SEMAPHORE_STATUS_UNRECOV_ERR == ((r) & \
367 SLI4_PORT_SEMAPHORE_STATUS_ERR_MASK))
370 * @brief SLIPORT_STATUS - SLI Port Status Register
373 #define SLI4_PORT_STATUS_REG_236 0x0404 /** register offset Interface Type 2 + 3 + 6*/
374 #define SLI4_PORT_STATUS_FDP BIT(21) /** function specific dump present */
375 #define SLI4_PORT_STATUS_RDY BIT(23) /** ready */
376 #define SLI4_PORT_STATUS_RN BIT(24) /** reset needed */
377 #define SLI4_PORT_STATUS_DIP BIT(25) /** dump present */
378 #define SLI4_PORT_STATUS_OTI BIT(29) /** over temp indicator */
379 #define SLI4_PORT_STATUS_END BIT(30) /** endianness */
380 #define SLI4_PORT_STATUS_ERR BIT(31) /** SLI port error */
381 #define SLI4_PORT_STATUS_READY(r) ((r) & SLI4_PORT_STATUS_RDY)
382 #define SLI4_PORT_STATUS_ERROR(r) ((r) & SLI4_PORT_STATUS_ERR)
383 #define SLI4_PORT_STATUS_DUMP_PRESENT(r) ((r) & SLI4_PORT_STATUS_DIP)
384 #define SLI4_PORT_STATUS_FDP_PRESENT(r) ((r) & SLI4_PORT_STATUS_FDP)
386 #define SLI4_PHSDEV_CONTROL_REG_236 0x0414 /** register offset Interface Type 2 + 3 + 6*/
387 #define SLI4_PHYDEV_CONTROL_DRST BIT(0) /** physical device reset */
388 #define SLI4_PHYDEV_CONTROL_FRST BIT(1) /** firmware reset */
389 #define SLI4_PHYDEV_CONTROL_DD BIT(2) /** diagnostic dump */
390 #define SLI4_PHYDEV_CONTROL_FRL_MASK 0x000000f0
391 #define SLI4_PHYDEV_CONTROL_FRL_SHIFT 4
392 #define SLI4_PHYDEV_CONTROL_FRL(r) (((r) & SLI4_PHYDEV_CONTROL_FRL_MASK) >> \
393 SLI4_PHYDEV_CONTROL_FRL_SHIFT_SHIFT)
395 /*************************************************************************
396 * SLI-4 mailbox command formats and definitions
399 typedef struct sli4_mbox_command_header_s {
400 #if BYTE_ORDER == LITTLE_ENDIAN
403 status:16; /** Port writes to indicate success / fail */
405 #error big endian version not defined
407 } sli4_mbox_command_header_t;
409 #define SLI4_MBOX_COMMAND_CONFIG_LINK 0x07
410 #define SLI4_MBOX_COMMAND_DUMP 0x17
411 #define SLI4_MBOX_COMMAND_DOWN_LINK 0x06
412 #define SLI4_MBOX_COMMAND_INIT_LINK 0x05
413 #define SLI4_MBOX_COMMAND_INIT_VFI 0xa3
414 #define SLI4_MBOX_COMMAND_INIT_VPI 0xa4
415 #define SLI4_MBOX_COMMAND_POST_XRI 0xa7
416 #define SLI4_MBOX_COMMAND_RELEASE_XRI 0xac
417 #define SLI4_MBOX_COMMAND_READ_CONFIG 0x0b
418 #define SLI4_MBOX_COMMAND_READ_STATUS 0x0e
419 #define SLI4_MBOX_COMMAND_READ_NVPARMS 0x02
420 #define SLI4_MBOX_COMMAND_READ_REV 0x11
421 #define SLI4_MBOX_COMMAND_READ_LNK_STAT 0x12
422 #define SLI4_MBOX_COMMAND_READ_SPARM64 0x8d
423 #define SLI4_MBOX_COMMAND_READ_TOPOLOGY 0x95
424 #define SLI4_MBOX_COMMAND_REG_FCFI 0xa0
425 #define SLI4_MBOX_COMMAND_REG_FCFI_MRQ 0xaf
426 #define SLI4_MBOX_COMMAND_REG_RPI 0x93
427 #define SLI4_MBOX_COMMAND_REG_RX_RQ 0xa6
428 #define SLI4_MBOX_COMMAND_REG_VFI 0x9f
429 #define SLI4_MBOX_COMMAND_REG_VPI 0x96
430 #define SLI4_MBOX_COMMAND_REQUEST_FEATURES 0x9d
431 #define SLI4_MBOX_COMMAND_SLI_CONFIG 0x9b
432 #define SLI4_MBOX_COMMAND_UNREG_FCFI 0xa2
433 #define SLI4_MBOX_COMMAND_UNREG_RPI 0x14
434 #define SLI4_MBOX_COMMAND_UNREG_VFI 0xa1
435 #define SLI4_MBOX_COMMAND_UNREG_VPI 0x97
436 #define SLI4_MBOX_COMMAND_WRITE_NVPARMS 0x03
437 #define SLI4_MBOX_COMMAND_CONFIG_AUTO_XFER_RDY 0xAD
438 #define SLI4_MBOX_COMMAND_CONFIG_AUTO_XFER_RDY_HP 0xAE
440 #define SLI4_MBOX_STATUS_SUCCESS 0x0000
441 #define SLI4_MBOX_STATUS_FAILURE 0x0001
442 #define SLI4_MBOX_STATUS_RPI_NOT_REG 0x1400
445 * @brief Buffer Descriptor Entry (BDE)
447 typedef struct sli4_bde_s {
448 #if BYTE_ORDER == LITTLE_ENDIAN
449 uint32_t buffer_length:24,
453 uint32_t buffer_address_low;
454 uint32_t buffer_address_high;
461 uint32_t sgl_segment_address_low;
462 uint32_t sgl_segment_address_high;
466 #error big endian version not defined
470 #define SLI4_BDE_TYPE_BDE_64 0x00 /** Generic 64-bit data */
471 #define SLI4_BDE_TYPE_BDE_IMM 0x01 /** Immediate data */
472 #define SLI4_BDE_TYPE_BLP 0x40 /** Buffer List Pointer */
475 * @brief Scatter-Gather Entry (SGE)
477 typedef struct sli4_sge_s {
478 #if BYTE_ORDER == LITTLE_ENDIAN
479 uint32_t buffer_address_high;
480 uint32_t buffer_address_low;
481 uint32_t data_offset:27,
484 uint32_t buffer_length;
486 #error big endian version not defined
491 * @brief T10 DIF Scatter-Gather Entry (SGE)
493 typedef struct sli4_dif_sge_s {
494 #if BYTE_ORDER == LITTLE_ENDIAN
495 uint32_t buffer_address_high;
496 uint32_t buffer_address_low;
502 #error big endian version not defined
507 * @brief T10 DIF Seed Scatter-Gather Entry (SGE)
509 typedef struct sli4_diseed_sge_s {
510 #if BYTE_ORDER == LITTLE_ENDIAN
511 uint32_t ref_tag_cmp;
512 uint32_t ref_tag_repl;
513 uint32_t app_tag_repl:16,
526 uint32_t app_tag_cmp:16,
536 #error big endian version not defined
541 * @brief List Segment Pointer Scatter-Gather Entry (SGE)
543 typedef struct sli4_lsp_sge_s {
544 #if BYTE_ORDER == LITTLE_ENDIAN
545 uint32_t buffer_address_high;
546 uint32_t buffer_address_low;
550 uint32_t segment_length:24,
553 #error big endian version not defined
557 #define SLI4_SGE_MAX_RESERVED 3
559 #define SLI4_SGE_DIF_OP_IN_NODIF_OUT_CRC 0x00
560 #define SLI4_SGE_DIF_OP_IN_CRC_OUT_NODIF 0x01
561 #define SLI4_SGE_DIF_OP_IN_NODIF_OUT_CHKSUM 0x02
562 #define SLI4_SGE_DIF_OP_IN_CHKSUM_OUT_NODIF 0x03
563 #define SLI4_SGE_DIF_OP_IN_CRC_OUT_CRC 0x04
564 #define SLI4_SGE_DIF_OP_IN_CHKSUM_OUT_CHKSUM 0x05
565 #define SLI4_SGE_DIF_OP_IN_CRC_OUT_CHKSUM 0x06
566 #define SLI4_SGE_DIF_OP_IN_CHKSUM_OUT_CRC 0x07
567 #define SLI4_SGE_DIF_OP_IN_RAW_OUT_RAW 0x08
569 #define SLI4_SGE_TYPE_DATA 0x00
570 #define SLI4_SGE_TYPE_CHAIN 0x03 /** Skyhawk only */
571 #define SLI4_SGE_TYPE_DIF 0x04 /** Data Integrity Field */
572 #define SLI4_SGE_TYPE_LSP 0x05 /** List Segment Pointer */
573 #define SLI4_SGE_TYPE_PEDIF 0x06 /** Post Encryption Engine DIF */
574 #define SLI4_SGE_TYPE_PESEED 0x07 /** Post Encryption Engine DIF Seed */
575 #define SLI4_SGE_TYPE_DISEED 0x08 /** DIF Seed */
576 #define SLI4_SGE_TYPE_ENC 0x09 /** Encryption */
577 #define SLI4_SGE_TYPE_ATM 0x0a /** DIF Application Tag Mask */
578 #define SLI4_SGE_TYPE_SKIP 0x0c /** SKIP */
580 #define OCS_MAX_SGE_SIZE 0x80000000 /* Maximum data allowed in a SGE */
585 typedef struct sli4_cmd_config_link_s {
586 sli4_mbox_command_header_t hdr;
587 #if BYTE_ORDER == LITTLE_ENDIAN
588 uint32_t maxbbc:8, /** Max buffer-to-buffer credit */
601 bbscn:4, /** buffer-to-buffer state change number */
602 cscn:1, /** configure BBSCN */
605 #error big endian version not defined
607 } sli4_cmd_config_link_t;
612 #define SLI4_WKI_TAG_SAT_TEM 0x1040
613 typedef struct sli4_cmd_dump4_s {
614 sli4_mbox_command_header_t hdr;
615 #if BYTE_ORDER == LITTLE_ENDIAN
618 uint32_t wki_selection:16,
621 uint32_t returned_byte_cnt;
622 uint32_t resp_data[59];
624 #error big endian version not defined
629 * @brief FW_INITIALIZE - initialize a SLI port
631 * @note This command uses a different format than all others.
634 extern const uint8_t sli4_fw_initialize[8];
637 * @brief FW_DEINITIALIZE - deinitialize a SLI port
639 * @note This command uses a different format than all others.
642 extern const uint8_t sli4_fw_deinitialize[8];
645 * @brief INIT_LINK - initialize the link for a FC/FCoE port
647 typedef struct sli4_cmd_init_link_flags_s {
650 #define FC_TOPOLOGY_FCAL 0
651 #define FC_TOPOLOGY_P2P 1
655 gen_loop_validity_check:1,
657 enable_topology_failover:1,
660 select_hightest_al_pa:1,
661 :16; /* pad to 32 bits */
662 } sli4_cmd_init_link_flags_t;
664 #define SLI4_INIT_LINK_F_LOOP_BACK BIT(0)
665 #define SLI4_INIT_LINK_F_UNFAIR BIT(6)
666 #define SLI4_INIT_LINK_F_NO_LIRP BIT(7)
667 #define SLI4_INIT_LINK_F_LOOP_VALID_CHK BIT(8)
668 #define SLI4_INIT_LINK_F_NO_LISA BIT(9)
669 #define SLI4_INIT_LINK_F_FAIL_OVER BIT(10)
670 #define SLI4_INIT_LINK_F_NO_AUTOSPEED BIT(11)
671 #define SLI4_INIT_LINK_F_PICK_HI_ALPA BIT(15)
673 #define SLI4_INIT_LINK_F_P2P_ONLY 1
674 #define SLI4_INIT_LINK_F_FCAL_ONLY 2
676 #define SLI4_INIT_LINK_F_FCAL_FAIL_OVER 0
677 #define SLI4_INIT_LINK_F_P2P_FAIL_OVER 1
679 typedef struct sli4_cmd_init_link_s {
680 sli4_mbox_command_header_t hdr;
681 #if BYTE_ORDER == LITTLE_ENDIAN
682 uint32_t selective_reset_al_pa:8,
684 sli4_cmd_init_link_flags_t link_flags;
685 uint32_t link_speed_selection_code;
686 #define FC_LINK_SPEED_1G 1
687 #define FC_LINK_SPEED_2G 2
688 #define FC_LINK_SPEED_AUTO_1_2 3
689 #define FC_LINK_SPEED_4G 4
690 #define FC_LINK_SPEED_AUTO_4_1 5
691 #define FC_LINK_SPEED_AUTO_4_2 6
692 #define FC_LINK_SPEED_AUTO_4_2_1 7
693 #define FC_LINK_SPEED_8G 8
694 #define FC_LINK_SPEED_AUTO_8_1 9
695 #define FC_LINK_SPEED_AUTO_8_2 10
696 #define FC_LINK_SPEED_AUTO_8_2_1 11
697 #define FC_LINK_SPEED_AUTO_8_4 12
698 #define FC_LINK_SPEED_AUTO_8_4_1 13
699 #define FC_LINK_SPEED_AUTO_8_4_2 14
700 #define FC_LINK_SPEED_10G 16
701 #define FC_LINK_SPEED_16G 17
702 #define FC_LINK_SPEED_AUTO_16_8_4 18
703 #define FC_LINK_SPEED_AUTO_16_8 19
704 #define FC_LINK_SPEED_32G 20
705 #define FC_LINK_SPEED_AUTO_32_16_8 21
706 #define FC_LINK_SPEED_AUTO_32_16 22
708 #error big endian version not defined
710 } sli4_cmd_init_link_t;
713 * @brief INIT_VFI - initialize the VFI resource
715 typedef struct sli4_cmd_init_vfi_s {
716 sli4_mbox_command_header_t hdr;
717 #if BYTE_ORDER == LITTLE_ENDIAN
732 #error big endian version not defined
734 } sli4_cmd_init_vfi_t;
737 * @brief INIT_VPI - initialize the VPI resource
739 typedef struct sli4_cmd_init_vpi_s {
740 sli4_mbox_command_header_t hdr;
741 #if BYTE_ORDER == LITTLE_ENDIAN
745 #error big endian version not defined
747 } sli4_cmd_init_vpi_t;
750 * @brief POST_XRI - post XRI resources to the SLI Port
752 typedef struct sli4_cmd_post_xri_s {
753 sli4_mbox_command_header_t hdr;
754 #if BYTE_ORDER == LITTLE_ENDIAN
755 uint32_t xri_base:16,
762 #error big endian version not defined
764 } sli4_cmd_post_xri_t;
767 * @brief RELEASE_XRI - Release XRI resources from the SLI Port
769 typedef struct sli4_cmd_release_xri_s {
770 sli4_mbox_command_header_t hdr;
771 #if BYTE_ORDER == LITTLE_ENDIAN
772 uint32_t released_xri_count:5,
777 uint32_t xri_tag0:16,
781 #error big endian version not defined
783 } sli4_cmd_release_xri_t;
786 * @brief READ_CONFIG - read SLI port configuration parameters
788 typedef struct sli4_cmd_read_config_s {
789 sli4_mbox_command_header_t hdr;
790 } sli4_cmd_read_config_t;
792 typedef struct sli4_res_read_config_s {
793 sli4_mbox_command_header_t hdr;
794 #if BYTE_ORDER == LITTLE_ENDIAN
796 ext:1; /** Resource Extents */
807 uint32_t lmt:16, /** Link Module Type */
811 uint32_t xri_base:16,
813 uint32_t rpi_base:16,
815 uint32_t vpi_base:16,
817 uint32_t vfi_base:16,
821 uint32_t rq_count:16,
823 uint32_t wq_count:16,
827 #error big endian version not defined
829 } sli4_res_read_config_t;
831 #define SLI4_READ_CFG_TOPO_FCOE 0x0 /** FCoE topology */
832 #define SLI4_READ_CFG_TOPO_FC 0x1 /** FC topology unknown */
833 #define SLI4_READ_CFG_TOPO_FC_DA 0x2 /** FC Direct Attach (non FC-AL) topology */
834 #define SLI4_READ_CFG_TOPO_FC_AL 0x3 /** FC-AL topology */
837 * @brief READ_NVPARMS - read SLI port configuration parameters
839 typedef struct sli4_cmd_read_nvparms_s {
840 sli4_mbox_command_header_t hdr;
841 #if BYTE_ORDER == LITTLE_ENDIAN
848 uint32_t hard_alpa:8,
851 #error big endian version not defined
853 } sli4_cmd_read_nvparms_t;
856 * @brief WRITE_NVPARMS - write SLI port configuration parameters
858 typedef struct sli4_cmd_write_nvparms_s {
859 sli4_mbox_command_header_t hdr;
860 #if BYTE_ORDER == LITTLE_ENDIAN
867 uint32_t hard_alpa:8,
870 #error big endian version not defined
872 } sli4_cmd_write_nvparms_t;
875 * @brief READ_REV - read the Port revision levels
877 typedef struct sli4_cmd_read_rev_s {
878 sli4_mbox_command_header_t hdr;
879 #if BYTE_ORDER == LITTLE_ENDIAN
887 uint32_t first_hw_revision;
888 uint32_t second_hw_revision;
890 uint32_t third_hw_revision;
891 uint32_t fc_ph_low:8,
894 feature_level_high:8;
896 uint32_t first_fw_id;
897 char first_fw_name[16];
898 uint32_t second_fw_id;
899 char second_fw_name[16];
901 uint32_t available_length:24,
903 uint32_t physical_address_low;
904 uint32_t physical_address_high;
905 uint32_t returned_vpd_length;
906 uint32_t actual_vpd_length;
908 #error big endian version not defined
910 } sli4_cmd_read_rev_t;
913 * @brief READ_SPARM64 - read the Port service parameters
915 typedef struct sli4_cmd_read_sparm64_s {
916 sli4_mbox_command_header_t hdr;
917 #if BYTE_ORDER == LITTLE_ENDIAN
923 uint32_t port_name_start:16,
925 uint32_t node_name_start:16,
928 #error big endian version not defined
930 } sli4_cmd_read_sparm64_t;
932 #define SLI4_READ_SPARM64_VPI_DEFAULT 0
933 #define SLI4_READ_SPARM64_VPI_SPECIAL UINT16_MAX
935 #define SLI4_READ_SPARM64_WWPN_OFFSET (4 * sizeof(uint32_t))
936 #define SLI4_READ_SPARM64_WWNN_OFFSET (SLI4_READ_SPARM64_WWPN_OFFSET + sizeof(uint64_t))
938 typedef struct sli4_port_state_s {
939 #if BYTE_ORDER == LITTLE_ENDIAN
940 uint32_t nx_port_recv_state:2,
941 nx_port_trans_state:2,
942 nx_port_state_machine:4,
948 #error big endian version not defined
953 * @brief READ_TOPOLOGY - read the link event information
955 typedef struct sli4_cmd_read_topology_s {
956 sli4_mbox_command_header_t hdr;
957 #if BYTE_ORDER == LITTLE_ENDIAN
959 uint32_t attention_type:8,
967 sli4_bde_t bde_loop_map;
968 sli4_port_state_t link_down;
969 sli4_port_state_t link_current;
979 uint32_t acquired_al_pa:8,
983 uint32_t initial_n_port_id:24,
986 #error big endian version not defined
988 } sli4_cmd_read_topology_t;
990 #define SLI4_MIN_LOOP_MAP_BYTES 128
992 #define SLI4_READ_TOPOLOGY_LINK_UP 0x1
993 #define SLI4_READ_TOPOLOGY_LINK_DOWN 0x2
994 #define SLI4_READ_TOPOLOGY_LINK_NO_ALPA 0x3
996 #define SLI4_READ_TOPOLOGY_UNKNOWN 0x0
997 #define SLI4_READ_TOPOLOGY_NPORT 0x1
998 #define SLI4_READ_TOPOLOGY_FC_AL 0x2
1000 #define SLI4_READ_TOPOLOGY_SPEED_NONE 0x00
1001 #define SLI4_READ_TOPOLOGY_SPEED_1G 0x04
1002 #define SLI4_READ_TOPOLOGY_SPEED_2G 0x08
1003 #define SLI4_READ_TOPOLOGY_SPEED_4G 0x10
1004 #define SLI4_READ_TOPOLOGY_SPEED_8G 0x20
1005 #define SLI4_READ_TOPOLOGY_SPEED_10G 0x40
1006 #define SLI4_READ_TOPOLOGY_SPEED_16G 0x80
1007 #define SLI4_READ_TOPOLOGY_SPEED_32G 0x90
1010 * @brief REG_FCFI - activate a FC Forwarder
1012 #define SLI4_CMD_REG_FCFI_NUM_RQ_CFG 4
1013 typedef struct sli4_cmd_reg_fcfi_s {
1014 sli4_mbox_command_header_t hdr;
1015 #if BYTE_ORDER == LITTLE_ENDIAN
1016 uint32_t fcf_index:16,
1018 uint32_t rq_id_1:16,
1020 uint32_t rq_id_3:16,
1023 uint32_t r_ctl_mask:8,
1027 } rq_cfg[SLI4_CMD_REG_FCFI_NUM_RQ_CFG];
1028 uint32_t vlan_tag:12,
1032 #error big endian version not defined
1034 } sli4_cmd_reg_fcfi_t;
1036 #define SLI4_CMD_REG_FCFI_MRQ_NUM_RQ_CFG 4
1037 #define SLI4_CMD_REG_FCFI_MRQ_MAX_NUM_RQ 32
1038 #define SLI4_CMD_REG_FCFI_SET_FCFI_MODE 0
1039 #define SLI4_CMD_REG_FCFI_SET_MRQ_MODE 1
1041 typedef struct sli4_cmd_reg_fcfi_mrq_s {
1042 sli4_mbox_command_header_t hdr;
1043 #if BYTE_ORDER == LITTLE_ENDIAN
1044 uint32_t fcf_index:16,
1047 uint32_t rq_id_1:16,
1050 uint32_t rq_id_3:16,
1054 uint32_t r_ctl_mask:8,
1058 } rq_cfg[SLI4_CMD_REG_FCFI_MRQ_NUM_RQ_CFG];
1060 uint32_t vlan_tag:12,
1065 uint32_t num_mrq_pairs:8,
1066 mrq_filter_bitmask:4,
1067 rq_selection_policy:4,
1070 } sli4_cmd_reg_fcfi_mrq_t;
1073 * @brief REG_RPI - register a Remote Port Indicator
1075 typedef struct sli4_cmd_reg_rpi_s {
1076 sli4_mbox_command_header_t hdr;
1077 #if BYTE_ORDER == LITTLE_ENDIAN
1080 uint32_t remote_n_port_id:24,
1092 #error big endian version not defined
1094 } sli4_cmd_reg_rpi_t;
1095 #define SLI4_REG_RPI_BUF_LEN 0x70
1098 * @brief REG_VFI - register a Virtual Fabric Indicator
1100 typedef struct sli4_cmd_reg_vfi_s {
1101 sli4_mbox_command_header_t hdr;
1102 #if BYTE_ORDER == LITTLE_ENDIAN
1109 vpi:16; /* vp=TRUE */
1110 uint8_t wwpn[8]; /* vp=TRUE */
1111 sli4_bde_t sparm; /* either FLOGI or PLOGI */
1114 uint32_t local_n_port_id:24, /* vp=TRUE */
1117 #error big endian version not defined
1119 } sli4_cmd_reg_vfi_t;
1122 * @brief REG_VPI - register a Virtual Port Indicator
1124 typedef struct sli4_cmd_reg_vpi_s {
1125 sli4_mbox_command_header_t hdr;
1126 #if BYTE_ORDER == LITTLE_ENDIAN
1128 uint32_t local_n_port_id:24,
1136 #error big endian version not defined
1138 } sli4_cmd_reg_vpi_t;
1141 * @brief REQUEST_FEATURES - request / query SLI features
1144 #if BYTE_ORDER == LITTLE_ENDIAN
1146 uint32_t iaab:1, /** inhibit auto-ABTS originator */
1147 npiv:1, /** NPIV support */
1148 dif:1, /** DIF/DIX support */
1149 vf:1, /** virtual fabric support */
1150 fcpi:1, /** FCP initiator support */
1151 fcpt:1, /** FCP target support */
1152 fcpc:1, /** combined FCP initiator/target */
1154 rqd:1, /** recovery qualified delay */
1155 iaar:1, /** inhibit auto-ABTS responder */
1156 hlm:1, /** High Login Mode */
1157 perfh:1, /** performance hints */
1158 rxseq:1, /** RX Sequence Coalescing */
1159 rxri:1, /** Release XRI variant of Coalescing */
1160 dcl2:1, /** Disable Class 2 */
1161 rsco:1, /** Receive Sequence Coalescing Optimizations */
1162 mrqp:1, /** Multi RQ Pair Mode Support */
1167 #error big endian version not defined
1171 typedef struct sli4_cmd_request_features_s {
1172 sli4_mbox_command_header_t hdr;
1173 #if BYTE_ORDER == LITTLE_ENDIAN
1177 #error big endian version not defined
1179 sli4_features_t command;
1180 sli4_features_t response;
1181 } sli4_cmd_request_features_t;
1184 * @brief SLI_CONFIG - submit a configuration command to Port
1186 * Command is either embedded as part of the payload (embed) or located
1187 * in a separate memory buffer (mem)
1190 typedef struct sli4_sli_config_pmd_s {
1191 uint32_t address_low;
1192 uint32_t address_high;
1195 } sli4_sli_config_pmd_t;
1197 typedef struct sli4_cmd_sli_config_s {
1198 sli4_mbox_command_header_t hdr;
1199 #if BYTE_ORDER == LITTLE_ENDIAN
1204 uint32_t payload_length;
1209 uint8_t embed[58 * sizeof(uint32_t)];
1210 sli4_sli_config_pmd_t mem;
1213 #error big endian version not defined
1215 } sli4_cmd_sli_config_t;
1218 * @brief READ_STATUS - read tx/rx status of a particular port
1222 typedef struct sli4_cmd_read_status_s {
1223 sli4_mbox_command_header_t hdr;
1224 #if BYTE_ORDER == LITTLE_ENDIAN
1228 uint32_t transmit_kbyte_count;
1229 uint32_t receive_kbyte_count;
1230 uint32_t transmit_frame_count;
1231 uint32_t receive_frame_count;
1232 uint32_t transmit_sequence_count;
1233 uint32_t receive_sequence_count;
1234 uint32_t total_exchanges_originator;
1235 uint32_t total_exchanges_responder;
1236 uint32_t receive_p_bsy_count;
1237 uint32_t receive_f_bsy_count;
1238 uint32_t dropped_frames_due_to_no_rq_buffer_count;
1239 uint32_t empty_rq_timeout_count;
1240 uint32_t dropped_frames_due_to_no_xri_count;
1241 uint32_t empty_xri_pool_count;
1244 #error big endian version not defined
1246 } sli4_cmd_read_status_t;
1249 * @brief READ_LNK_STAT - read link status of a particular port
1253 typedef struct sli4_cmd_read_link_stats_s {
1254 sli4_mbox_command_header_t hdr;
1255 #if BYTE_ORDER == LITTLE_ENDIAN
1281 uint32_t link_failure_error_count;
1282 uint32_t loss_of_sync_error_count;
1283 uint32_t loss_of_signal_error_count;
1284 uint32_t primitive_sequence_error_count;
1285 uint32_t invalid_transmission_word_error_count;
1286 uint32_t crc_error_count;
1287 uint32_t primitive_sequence_event_timeout_count;
1288 uint32_t elastic_buffer_overrun_error_count;
1289 uint32_t arbitration_fc_al_timout_count;
1290 uint32_t advertised_receive_bufftor_to_buffer_credit;
1291 uint32_t current_receive_buffer_to_buffer_credit;
1292 uint32_t advertised_transmit_buffer_to_buffer_credit;
1293 uint32_t current_transmit_buffer_to_buffer_credit;
1294 uint32_t received_eofa_count;
1295 uint32_t received_eofdti_count;
1296 uint32_t received_eofni_count;
1297 uint32_t received_soff_count;
1298 uint32_t received_dropped_no_aer_count;
1299 uint32_t received_dropped_no_available_rpi_resources_count;
1300 uint32_t received_dropped_no_available_xri_resources_count;
1303 #error big endian version not defined
1305 } sli4_cmd_read_link_stats_t;
1308 * @brief Format a WQE with WQ_ID Association performance hint
1311 * PHWQ works by over-writing part of Word 10 in the WQE with the WQ ID.
1313 * @param entry Pointer to the WQE.
1314 * @param q_id Queue ID.
1319 sli_set_wq_id_association(void *entry, uint16_t q_id)
1321 uint32_t *wqe = entry;
1324 * Set Word 10, bit 0 to zero
1325 * Set Word 10, bits 15:1 to the WQ ID
1327 #if BYTE_ORDER == LITTLE_ENDIAN
1329 wqe[10] |= q_id << 1;
1331 #error big endian version not defined
1336 * @brief UNREG_FCFI - unregister a FCFI
1338 typedef struct sli4_cmd_unreg_fcfi_s {
1339 sli4_mbox_command_header_t hdr;
1341 #if BYTE_ORDER == LITTLE_ENDIAN
1345 #error big endian version not defined
1347 } sli4_cmd_unreg_fcfi_t;
1350 * @brief UNREG_RPI - unregister one or more RPI
1352 typedef struct sli4_cmd_unreg_rpi_s {
1353 sli4_mbox_command_header_t hdr;
1354 #if BYTE_ORDER == LITTLE_ENDIAN
1359 uint32_t destination_n_port_id:24,
1362 #error big endian version not defined
1364 } sli4_cmd_unreg_rpi_t;
1366 #define SLI4_UNREG_RPI_II_RPI 0x0
1367 #define SLI4_UNREG_RPI_II_VPI 0x1
1368 #define SLI4_UNREG_RPI_II_VFI 0x2
1369 #define SLI4_UNREG_RPI_II_FCFI 0x3
1372 * @brief UNREG_VFI - unregister one or more VFI
1374 typedef struct sli4_cmd_unreg_vfi_s {
1375 sli4_mbox_command_header_t hdr;
1376 #if BYTE_ORDER == LITTLE_ENDIAN
1382 #error big endian version not defined
1384 } sli4_cmd_unreg_vfi_t;
1386 #define SLI4_UNREG_VFI_II_VFI 0x0
1387 #define SLI4_UNREG_VFI_II_FCFI 0x3
1390 SLI4_UNREG_TYPE_PORT,
1391 SLI4_UNREG_TYPE_DOMAIN,
1392 SLI4_UNREG_TYPE_FCF,
1397 * @brief UNREG_VPI - unregister one or more VPI
1399 typedef struct sli4_cmd_unreg_vpi_s {
1400 sli4_mbox_command_header_t hdr;
1401 #if BYTE_ORDER == LITTLE_ENDIAN
1407 #error big endian version not defined
1409 } sli4_cmd_unreg_vpi_t;
1411 #define SLI4_UNREG_VPI_II_VPI 0x0
1412 #define SLI4_UNREG_VPI_II_VFI 0x2
1413 #define SLI4_UNREG_VPI_II_FCFI 0x3
1416 * @brief AUTO_XFER_RDY - Configure the auto-generate XFER-RDY feature.
1418 typedef struct sli4_cmd_config_auto_xfer_rdy_s {
1419 sli4_mbox_command_header_t hdr;
1420 #if BYTE_ORDER == LITTLE_ENDIAN
1422 uint32_t max_burst_len;
1424 #error big endian version not defined
1426 } sli4_cmd_config_auto_xfer_rdy_t;
1428 typedef struct sli4_cmd_config_auto_xfer_rdy_hp_s {
1429 sli4_mbox_command_header_t hdr;
1430 #if BYTE_ORDER == LITTLE_ENDIAN
1432 uint32_t max_burst_len;
1435 uint32_t block_size:16,
1438 #error big endian version not defined
1440 } sli4_cmd_config_auto_xfer_rdy_hp_t;
1442 /*************************************************************************
1443 * SLI-4 common configuration command formats and definitions
1446 #define SLI4_CFG_STATUS_SUCCESS 0x00
1447 #define SLI4_CFG_STATUS_FAILED 0x01
1448 #define SLI4_CFG_STATUS_ILLEGAL_REQUEST 0x02
1449 #define SLI4_CFG_STATUS_ILLEGAL_FIELD 0x03
1451 #define SLI4_MGMT_STATUS_FLASHROM_READ_FAILED 0xcb
1453 #define SLI4_CFG_ADD_STATUS_NO_STATUS 0x00
1454 #define SLI4_CFG_ADD_STATUS_INVALID_OPCODE 0x1e
1459 #define SLI4_SUBSYSTEM_COMMON 0x01
1460 #define SLI4_SUBSYSTEM_LOWLEVEL 0x0B
1461 #define SLI4_SUBSYSTEM_FCFCOE 0x0c
1462 #define SLI4_SUBSYSTEM_DMTF 0x11
1464 #define SLI4_OPC_LOWLEVEL_SET_WATCHDOG 0X36
1467 * Common opcode (OPC) values.
1469 #define SLI4_OPC_COMMON_FUNCTION_RESET 0x3d
1470 #define SLI4_OPC_COMMON_CREATE_CQ 0x0c
1471 #define SLI4_OPC_COMMON_CREATE_CQ_SET 0x1d
1472 #define SLI4_OPC_COMMON_DESTROY_CQ 0x36
1473 #define SLI4_OPC_COMMON_MODIFY_EQ_DELAY 0x29
1474 #define SLI4_OPC_COMMON_CREATE_EQ 0x0d
1475 #define SLI4_OPC_COMMON_DESTROY_EQ 0x37
1476 #define SLI4_OPC_COMMON_CREATE_MQ_EXT 0x5a
1477 #define SLI4_OPC_COMMON_DESTROY_MQ 0x35
1478 #define SLI4_OPC_COMMON_GET_CNTL_ATTRIBUTES 0x20
1479 #define SLI4_OPC_COMMON_NOP 0x21
1480 #define SLI4_OPC_COMMON_GET_RESOURCE_EXTENT_INFO 0x9a
1481 #define SLI4_OPC_COMMON_GET_SLI4_PARAMETERS 0xb5
1482 #define SLI4_OPC_COMMON_QUERY_FW_CONFIG 0x3a
1483 #define SLI4_OPC_COMMON_GET_PORT_NAME 0x4d
1485 #define SLI4_OPC_COMMON_WRITE_FLASHROM 0x07
1486 #define SLI4_OPC_COMMON_MANAGE_FAT 0x44
1487 #define SLI4_OPC_COMMON_READ_TRANSCEIVER_DATA 0x49
1488 #define SLI4_OPC_COMMON_GET_CNTL_ADDL_ATTRIBUTES 0x79
1489 #define SLI4_OPC_COMMON_GET_EXT_FAT_CAPABILITIES 0x7d
1490 #define SLI4_OPC_COMMON_SET_EXT_FAT_CAPABILITIES 0x7e
1491 #define SLI4_OPC_COMMON_EXT_FAT_CONFIGURE_SNAPSHOT 0x7f
1492 #define SLI4_OPC_COMMON_EXT_FAT_RETRIEVE_SNAPSHOT 0x80
1493 #define SLI4_OPC_COMMON_EXT_FAT_READ_STRING_TABLE 0x82
1494 #define SLI4_OPC_COMMON_GET_FUNCTION_CONFIG 0xa0
1495 #define SLI4_OPC_COMMON_GET_PROFILE_CONFIG 0xa4
1496 #define SLI4_OPC_COMMON_SET_PROFILE_CONFIG 0xa5
1497 #define SLI4_OPC_COMMON_GET_PROFILE_LIST 0xa6
1498 #define SLI4_OPC_COMMON_GET_ACTIVE_PROFILE 0xa7
1499 #define SLI4_OPC_COMMON_SET_ACTIVE_PROFILE 0xa8
1500 #define SLI4_OPC_COMMON_READ_OBJECT 0xab
1501 #define SLI4_OPC_COMMON_WRITE_OBJECT 0xac
1502 #define SLI4_OPC_COMMON_DELETE_OBJECT 0xae
1503 #define SLI4_OPC_COMMON_READ_OBJECT_LIST 0xad
1504 #define SLI4_OPC_COMMON_SET_DUMP_LOCATION 0xb8
1505 #define SLI4_OPC_COMMON_SET_FEATURES 0xbf
1506 #define SLI4_OPC_COMMON_GET_RECONFIG_LINK_INFO 0xc9
1507 #define SLI4_OPC_COMMON_SET_RECONFIG_LINK_ID 0xca
1510 * DMTF opcode (OPC) values.
1512 #define SLI4_OPC_DMTF_EXEC_CLP_CMD 0x01
1515 * @brief Generic Command Request header
1517 typedef struct sli4_req_hdr_s {
1518 #if BYTE_ORDER == LITTLE_ENDIAN
1523 uint32_t request_length;
1527 #error big endian version not defined
1532 * @brief Generic Command Response header
1534 typedef struct sli4_res_hdr_s {
1535 #if BYTE_ORDER == LITTLE_ENDIAN
1540 additional_status:8,
1542 uint32_t response_length;
1543 uint32_t actual_response_length;
1545 #error big endian version not defined
1550 * @brief COMMON_FUNCTION_RESET
1552 * Resets the Port, returning it to a power-on state. This configuration
1553 * command does not have a payload and should set/expect the lengths to
1556 typedef struct sli4_req_common_function_reset_s {
1558 } sli4_req_common_function_reset_t;
1560 typedef struct sli4_res_common_function_reset_s {
1562 } sli4_res_common_function_reset_t;
1565 * @brief COMMON_CREATE_CQ_V0
1567 * Create a Completion Queue.
1569 typedef struct sli4_req_common_create_cq_v0_s {
1571 #if BYTE_ORDER == LITTLE_ENDIAN
1572 uint32_t num_pages:16,
1590 } page_physical_address[0];
1592 #error big endian version not defined
1594 } sli4_req_common_create_cq_v0_t;
1597 * @brief COMMON_CREATE_CQ_V2
1599 * Create a Completion Queue.
1601 typedef struct sli4_req_common_create_cq_v2_s {
1603 #if BYTE_ORDER == LITTLE_ENDIAN
1604 uint32_t num_pages:16,
1620 uint32_t cqe_count:16,
1626 } page_physical_address[0];
1628 #error big endian version not defined
1630 } sli4_req_common_create_cq_v2_t;
1633 * @brief COMMON_CREATE_CQ_SET_V0
1635 * Create a set of Completion Queues.
1637 typedef struct sli4_req_common_create_cq_set_v0_s {
1639 #if BYTE_ORDER == LITTLE_ENDIAN
1640 uint32_t num_pages:16,
1652 uint32_t num_cq_req:16,
1659 } page_physical_address[0];
1661 #error big endian version not defined
1663 } sli4_req_common_create_cq_set_v0_t;
1668 #define SLI4_CQ_CNT_256 0
1669 #define SLI4_CQ_CNT_512 1
1670 #define SLI4_CQ_CNT_1024 2
1671 #define SLI4_CQ_CNT_LARGE 3
1673 #define SLI4_CQE_BYTES (4 * sizeof(uint32_t))
1675 #define SLI4_COMMON_CREATE_CQ_V2_MAX_PAGES 8
1678 * @brief Generic Common Create EQ/CQ/MQ/WQ/RQ Queue completion
1680 typedef struct sli4_res_common_create_queue_s {
1682 #if BYTE_ORDER == LITTLE_ENDIAN
1690 #error big endian version not defined
1692 } sli4_res_common_create_queue_t;
1694 typedef struct sli4_res_common_create_queue_set_s {
1696 #if BYTE_ORDER == LITTLE_ENDIAN
1700 #error big endian version not defined
1702 } sli4_res_common_create_queue_set_t;
1705 * @brief Common Destroy CQ
1707 typedef struct sli4_req_common_destroy_cq_s {
1709 #if BYTE_ORDER == LITTLE_ENDIAN
1713 #error big endian version not defined
1715 } sli4_req_common_destroy_cq_t;
1718 * @brief COMMON_MODIFY_EQ_DELAY
1720 * Modify the delay multiplier for EQs
1722 typedef struct sli4_req_common_modify_eq_delay_s {
1724 #if BYTE_ORDER == LITTLE_ENDIAN
1729 uint32_t delay_multiplier;
1730 } eq_delay_record[8];
1732 #error big endian version not defined
1734 } sli4_req_common_modify_eq_delay_t;
1737 * @brief COMMON_CREATE_EQ
1739 * Create an Event Queue.
1741 typedef struct sli4_req_common_create_eq_s {
1743 #if BYTE_ORDER == LITTLE_ENDIAN
1744 uint32_t num_pages:16,
1756 delay_multiplier:10,
1764 #error big endian version not defined
1766 } sli4_req_common_create_eq_t;
1768 #define SLI4_EQ_CNT_256 0
1769 #define SLI4_EQ_CNT_512 1
1770 #define SLI4_EQ_CNT_1024 2
1771 #define SLI4_EQ_CNT_2048 3
1772 #define SLI4_EQ_CNT_4096 4
1774 #define SLI4_EQE_SIZE_4 0
1775 #define SLI4_EQE_SIZE_16 1
1778 * @brief Common Destroy EQ
1780 typedef struct sli4_req_common_destroy_eq_s {
1782 #if BYTE_ORDER == LITTLE_ENDIAN
1786 #error big endian version not defined
1788 } sli4_req_common_destroy_eq_t;
1791 * @brief COMMON_CREATE_MQ_EXT
1793 * Create a Mailbox Queue; accommodate v0 and v1 forms.
1795 typedef struct sli4_req_common_create_mq_ext_s {
1797 #if BYTE_ORDER == LITTLE_ENDIAN
1798 uint32_t num_pages:16,
1800 uint32_t async_event_bitmap;
1801 uint32_t async_cq_id_v1:16,
1814 } page_physical_address[8];
1816 #error big endian version not defined
1818 } sli4_req_common_create_mq_ext_t;
1820 #define SLI4_MQE_SIZE_16 0x05
1821 #define SLI4_MQE_SIZE_32 0x06
1822 #define SLI4_MQE_SIZE_64 0x07
1823 #define SLI4_MQE_SIZE_128 0x08
1825 #define SLI4_ASYNC_EVT_LINK_STATE BIT(1)
1826 #define SLI4_ASYNC_EVT_FCOE_FIP BIT(2)
1827 #define SLI4_ASYNC_EVT_DCBX BIT(3)
1828 #define SLI4_ASYNC_EVT_ISCSI BIT(4)
1829 #define SLI4_ASYNC_EVT_GRP5 BIT(5)
1830 #define SLI4_ASYNC_EVT_FC BIT(16)
1831 #define SLI4_ASYNC_EVT_SLI_PORT BIT(17)
1832 #define SLI4_ASYNC_EVT_VF BIT(18)
1833 #define SLI4_ASYNC_EVT_MR BIT(19)
1835 #define SLI4_ASYNC_EVT_ALL \
1836 SLI4_ASYNC_EVT_LINK_STATE | \
1837 SLI4_ASYNC_EVT_FCOE_FIP | \
1838 SLI4_ASYNC_EVT_DCBX | \
1839 SLI4_ASYNC_EVT_ISCSI | \
1840 SLI4_ASYNC_EVT_GRP5 | \
1841 SLI4_ASYNC_EVT_FC | \
1842 SLI4_ASYNC_EVT_SLI_PORT | \
1843 SLI4_ASYNC_EVT_VF |\
1846 #define SLI4_ASYNC_EVT_FC_FCOE \
1847 SLI4_ASYNC_EVT_LINK_STATE | \
1848 SLI4_ASYNC_EVT_FCOE_FIP | \
1849 SLI4_ASYNC_EVT_GRP5 | \
1850 SLI4_ASYNC_EVT_FC | \
1851 SLI4_ASYNC_EVT_SLI_PORT
1854 * @brief Common Destroy MQ
1856 typedef struct sli4_req_common_destroy_mq_s {
1858 #if BYTE_ORDER == LITTLE_ENDIAN
1862 #error big endian version not defined
1864 } sli4_req_common_destroy_mq_t;
1867 * @brief COMMON_GET_CNTL_ATTRIBUTES
1869 * Query for information about the SLI Port
1871 typedef struct sli4_res_common_get_cntl_attributes_s {
1873 #if BYTE_ORDER == LITTLE_ENDIAN
1874 uint8_t version_string[32];
1875 uint8_t manufacturer_name[32];
1876 uint32_t supported_modes;
1877 uint32_t eprom_version_lo:8,
1880 uint32_t mbx_data_structure_version;
1881 uint32_t ep_firmware_data_structure_version;
1882 uint8_t ncsi_version_string[12];
1883 uint32_t default_extended_timeout;
1884 uint8_t model_number[32];
1885 uint8_t description[64];
1886 uint8_t serial_number[32];
1887 uint8_t ip_version_string[32];
1888 uint8_t fw_version_string[32];
1889 uint8_t bios_version_string[32];
1890 uint8_t redboot_version_string[32];
1891 uint8_t driver_version_string[32];
1892 uint8_t fw_on_flash_version_string[32];
1893 uint32_t functionalities_supported;
1894 uint32_t max_cdb_length:16,
1896 generational_guid0:8;
1897 uint32_t generational_guid1_12[3];
1898 uint32_t generational_guid13:24,
1900 uint32_t default_link_down_timeout:16,
1901 iscsi_version_min_max:8,
1902 multifunctional_device:8;
1903 uint32_t cache_valid:8,
1905 max_domains_supported:8,
1908 uint32_t firmware_post_status;
1910 uint32_t iscsi_features:8,
1912 uint32_t pci_vendor_id:16,
1914 uint32_t pci_sub_vendor_id:16,
1915 pci_sub_system_id:16;
1916 uint32_t pci_bus_number:8,
1917 pci_device_number:8,
1918 pci_function_number:8,
1920 uint64_t unique_identifier;
1921 uint32_t number_of_netfilters:8,
1924 #error big endian version not defined
1926 } sli4_res_common_get_cntl_attributes_t;
1929 * @brief COMMON_GET_CNTL_ATTRIBUTES
1931 * This command queries the controller information from the Flash ROM.
1933 typedef struct sli4_req_common_get_cntl_addl_attributes_s {
1935 } sli4_req_common_get_cntl_addl_attributes_t;
1937 typedef struct sli4_res_common_get_cntl_addl_attributes_s {
1939 uint16_t ipl_file_number;
1940 uint8_t ipl_file_version;
1942 uint8_t on_die_temperature;
1944 uint32_t driver_advanced_features_supported;
1946 char fcoe_universal_bios_version[32];
1947 char fcoe_x86_bios_version[32];
1948 char fcoe_efi_bios_version[32];
1949 char fcoe_fcode_version[32];
1950 char uefi_bios_version[32];
1951 char uefi_nic_version[32];
1952 char uefi_fcode_version[32];
1953 char uefi_iscsi_version[32];
1954 char iscsi_x86_bios_version[32];
1955 char pxe_x86_bios_version[32];
1956 uint8_t fcoe_default_wwpn[8];
1957 uint8_t ext_phy_version[32];
1958 uint8_t fc_universal_bios_version[32];
1959 uint8_t fc_x86_bios_version[32];
1960 uint8_t fc_efi_bios_version[32];
1961 uint8_t fc_fcode_version[32];
1962 uint8_t ext_phy_crc_label[8];
1963 uint8_t ipl_file_name[16];
1965 } sli4_res_common_get_cntl_addl_attributes_t;
1970 * This command does not do anything; it only returns the payload in the completion.
1972 typedef struct sli4_req_common_nop_s {
1974 #if BYTE_ORDER == LITTLE_ENDIAN
1975 uint32_t context[2];
1977 #error big endian version not defined
1979 } sli4_req_common_nop_t;
1981 typedef struct sli4_res_common_nop_s {
1983 #if BYTE_ORDER == LITTLE_ENDIAN
1984 uint32_t context[2];
1986 #error big endian version not defined
1988 } sli4_res_common_nop_t;
1991 * @brief COMMON_GET_RESOURCE_EXTENT_INFO
1993 typedef struct sli4_req_common_get_resource_extent_info_s {
1995 #if BYTE_ORDER == LITTLE_ENDIAN
1996 uint32_t resource_type:16,
1999 #error big endian version not defined
2001 } sli4_req_common_get_resource_extent_info_t;
2003 #define SLI4_RSC_TYPE_ISCSI_INI_XRI 0x0c
2004 #define SLI4_RSC_TYPE_FCOE_VFI 0x20
2005 #define SLI4_RSC_TYPE_FCOE_VPI 0x21
2006 #define SLI4_RSC_TYPE_FCOE_RPI 0x22
2007 #define SLI4_RSC_TYPE_FCOE_XRI 0x23
2009 typedef struct sli4_res_common_get_resource_extent_info_s {
2011 #if BYTE_ORDER == LITTLE_ENDIAN
2012 uint32_t resource_extent_count:16,
2013 resource_extent_size:16;
2015 #error big endian version not defined
2017 } sli4_res_common_get_resource_extent_info_t;
2019 #define SLI4_128BYTE_WQE_SUPPORT 0x02
2021 * @brief COMMON_GET_SLI4_PARAMETERS
2023 typedef struct sli4_res_common_get_sli4_parameters_s {
2025 #if BYTE_ORDER == LITTLE_ENDIAN
2026 uint32_t protocol_type:8,
2036 uint32_t eq_page_cnt:4,
2043 uint32_t eqe_count_mask:16,
2045 uint32_t cq_page_cnt:4,
2053 uint32_t cqe_count_mask:16,
2055 uint32_t mq_page_cnt:4,
2061 uint32_t mqe_count_mask:16,
2063 uint32_t wq_page_cnt:4,
2071 uint32_t wqe_count_mask:16,
2073 uint32_t rq_page_cnt:4,
2081 uint32_t rqe_count_mask:16,
2099 phwq:1, /** Performance Hint WQ_ID Association */
2113 uint32_t sge_supported_length;
2114 uint32_t sgl_page_cnt:4,
2119 uint32_t min_rq_buffer_size:16,
2121 uint32_t max_rq_buffer_size;
2122 uint32_t physical_xri_max:16,
2123 physical_rpi_max:16;
2124 uint32_t physical_vpi_max:16,
2125 physical_vfi_max:16;
2127 uint32_t frag_num_field_offset:16, /* dword 20 */
2128 frag_num_field_size:16;
2129 uint32_t sgl_index_field_offset:16, /* dword 21 */
2130 sgl_index_field_size:16;
2131 uint32_t chain_sge_initial_value_lo; /* dword 22 */
2132 uint32_t chain_sge_initial_value_hi; /* dword 23 */
2134 #error big endian version not defined
2136 } sli4_res_common_get_sli4_parameters_t;
2139 * @brief COMMON_QUERY_FW_CONFIG
2141 * This command retrieves firmware configuration parameters and adapter
2142 * resources available to the driver.
2144 typedef struct sli4_req_common_query_fw_config_s {
2146 } sli4_req_common_query_fw_config_t;
2148 #define SLI4_FUNCTION_MODE_FCOE_INI_MODE 0x40
2149 #define SLI4_FUNCTION_MODE_FCOE_TGT_MODE 0x80
2150 #define SLI4_FUNCTION_MODE_DUA_MODE 0x800
2152 #define SLI4_ULP_MODE_FCOE_INI 0x40
2153 #define SLI4_ULP_MODE_FCOE_TGT 0x80
2155 typedef struct sli4_res_common_query_fw_config_s {
2157 uint32_t config_number;
2159 uint32_t physical_port;
2160 uint32_t function_mode;
2162 uint32_t ulp0_nic_wqid_base;
2163 uint32_t ulp0_nic_wq_total; /* Dword 10 */
2164 uint32_t ulp0_toe_wqid_base;
2165 uint32_t ulp0_toe_wq_total;
2166 uint32_t ulp0_toe_rqid_base;
2167 uint32_t ulp0_toe_rq_total;
2168 uint32_t ulp0_toe_defrqid_base;
2169 uint32_t ulp0_toe_defrq_total;
2170 uint32_t ulp0_lro_rqid_base;
2171 uint32_t ulp0_lro_rq_total;
2172 uint32_t ulp0_iscsi_icd_base;
2173 uint32_t ulp0_iscsi_icd_total; /* Dword 20 */
2175 uint32_t ulp1_nic_wqid_base;
2176 uint32_t ulp1_nic_wq_total;
2177 uint32_t ulp1_toe_wqid_base;
2178 uint32_t ulp1_toe_wq_total;
2179 uint32_t ulp1_toe_rqid_base;
2180 uint32_t ulp1_toe_rq_total;
2181 uint32_t ulp1_toe_defrqid_base;
2182 uint32_t ulp1_toe_defrq_total;
2183 uint32_t ulp1_lro_rqid_base; /* Dword 30 */
2184 uint32_t ulp1_lro_rq_total;
2185 uint32_t ulp1_iscsi_icd_base;
2186 uint32_t ulp1_iscsi_icd_total;
2187 uint32_t function_capabilities;
2188 uint32_t ulp0_cq_base;
2189 uint32_t ulp0_cq_total;
2190 uint32_t ulp0_eq_base;
2191 uint32_t ulp0_eq_total;
2192 uint32_t ulp0_iscsi_chain_icd_base;
2193 uint32_t ulp0_iscsi_chain_icd_total; /* Dword 40 */
2194 uint32_t ulp1_iscsi_chain_icd_base;
2195 uint32_t ulp1_iscsi_chain_icd_total;
2196 } sli4_res_common_query_fw_config_t;
2199 * @brief COMMON_GET_PORT_NAME
2201 typedef struct sli4_req_common_get_port_name_s {
2203 #if BYTE_ORDER == LITTLE_ENDIAN
2204 uint32_t pt:2, /* only COMMON_GET_PORT_NAME_V1 */
2207 #error big endian version not defined
2209 } sli4_req_common_get_port_name_t;
2211 typedef struct sli4_res_common_get_port_name_s {
2214 } sli4_res_common_get_port_name_t;
2217 * @brief COMMON_WRITE_FLASHROM
2219 typedef struct sli4_req_common_write_flashrom_s {
2221 #if BYTE_ORDER == LITTLE_ENDIAN
2222 uint32_t flash_rom_access_opcode;
2223 uint32_t flash_rom_access_operation_type;
2224 uint32_t data_buffer_size;
2226 uint8_t data_buffer[4];
2228 #error big endian version not defined
2230 } sli4_req_common_write_flashrom_t;
2232 #define SLI4_MGMT_FLASHROM_OPCODE_FLASH 0x01
2233 #define SLI4_MGMT_FLASHROM_OPCODE_SAVE 0x02
2234 #define SLI4_MGMT_FLASHROM_OPCODE_CLEAR 0x03
2235 #define SLI4_MGMT_FLASHROM_OPCODE_REPORT 0x04
2236 #define SLI4_MGMT_FLASHROM_OPCODE_IMAGE_INFO 0x05
2237 #define SLI4_MGMT_FLASHROM_OPCODE_IMAGE_CRC 0x06
2238 #define SLI4_MGMT_FLASHROM_OPCODE_OFFSET_BASED_FLASH 0x07
2239 #define SLI4_MGMT_FLASHROM_OPCODE_OFFSET_BASED_SAVE 0x08
2240 #define SLI4_MGMT_PHY_FLASHROM_OPCODE_FLASH 0x09
2241 #define SLI4_MGMT_PHY_FLASHROM_OPCODE_SAVE 0x0a
2243 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_ISCSI 0x00
2244 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_REDBOOT 0x01
2245 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_BIOS 0x02
2246 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_PXE_BIOS 0x03
2247 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_CODE_CONTROL 0x04
2248 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_IPSEC_CFG 0x05
2249 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_INIT_DATA 0x06
2250 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_ROM_OFFSET 0x07
2251 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_FCOE_BIOS 0x08
2252 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_ISCSI_BAK 0x09
2253 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_FCOE_ACT 0x0a
2254 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_FCOE_BAK 0x0b
2255 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_CODE_CTRL_P 0x0c
2256 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_NCSI 0x0d
2257 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_NIC 0x0e
2258 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_DCBX 0x0f
2259 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_PXE_BIOS_CFG 0x10
2260 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_ALL_CFG_DATA 0x11
2263 * @brief COMMON_MANAGE_FAT
2265 typedef struct sli4_req_common_manage_fat_s {
2267 #if BYTE_ORDER == LITTLE_ENDIAN
2268 uint32_t fat_operation;
2269 uint32_t read_log_offset;
2270 uint32_t read_log_length;
2271 uint32_t data_buffer_size;
2272 uint32_t data_buffer; /* response only */
2274 #error big endian version not defined
2276 } sli4_req_common_manage_fat_t;
2279 * @brief COMMON_GET_EXT_FAT_CAPABILITIES
2281 typedef struct sli4_req_common_get_ext_fat_capabilities_s {
2283 #if BYTE_ORDER == LITTLE_ENDIAN
2284 uint32_t parameter_type;
2286 #error big endian version not defined
2288 } sli4_req_common_get_ext_fat_capabilities_t;
2291 * @brief COMMON_SET_EXT_FAT_CAPABILITIES
2293 typedef struct sli4_req_common_set_ext_fat_capabilities_s {
2295 #if BYTE_ORDER == LITTLE_ENDIAN
2296 uint32_t maximum_log_entries;
2297 uint32_t log_entry_size;
2298 uint32_t logging_type:8,
2299 maximum_logging_functions:8,
2300 maximum_logging_ports:8,
2302 uint32_t supported_modes;
2303 uint32_t number_modules;
2304 uint32_t debug_module[14];
2306 #error big endian version not defined
2308 } sli4_req_common_set_ext_fat_capabilities_t;
2311 * @brief COMMON_EXT_FAT_CONFIGURE_SNAPSHOT
2313 typedef struct sli4_req_common_ext_fat_configure_snapshot_s {
2315 #if BYTE_ORDER == LITTLE_ENDIAN
2316 uint32_t total_log_entries;
2318 #error big endian version not defined
2320 } sli4_req_common_ext_fat_configure_snapshot_t;
2323 * @brief COMMON_EXT_FAT_RETRIEVE_SNAPSHOT
2325 typedef struct sli4_req_common_ext_fat_retrieve_snapshot_s {
2327 #if BYTE_ORDER == LITTLE_ENDIAN
2328 uint32_t snapshot_mode;
2329 uint32_t start_index;
2330 uint32_t number_log_entries;
2332 #error big endian version not defined
2334 } sli4_req_common_ext_fat_retrieve_snapshot_t;
2336 typedef struct sli4_res_common_ext_fat_retrieve_snapshot_s {
2338 #if BYTE_ORDER == LITTLE_ENDIAN
2339 uint32_t number_log_entries;
2343 uint32_t trace_level;
2344 uint32_t module_mask[2];
2345 uint32_t trace_table_index;
2347 uint8_t string_data[16];
2350 #error big endian version not defined
2352 } sli4_res_common_ext_fat_retrieve_snapshot_t;
2355 * @brief COMMON_EXT_FAT_READ_STRING_TABLE
2357 typedef struct sli4_req_common_ext_fat_read_string_table_s {
2359 #if BYTE_ORDER == LITTLE_ENDIAN
2360 uint32_t byte_offset;
2361 uint32_t number_bytes;
2363 #error big endian version not defined
2365 } sli4_req_common_ext_fat_read_string_table_t;
2367 typedef struct sli4_res_common_ext_fat_read_string_table_s {
2369 #if BYTE_ORDER == LITTLE_ENDIAN
2370 uint32_t number_returned_bytes;
2371 uint32_t number_remaining_bytes;
2372 uint32_t table_data0:8,
2374 uint8_t table_data[0];
2376 #error big endian version not defined
2378 } sli4_res_common_ext_fat_read_string_table_t;
2381 * @brief COMMON_READ_TRANSCEIVER_DATA
2383 * This command reads SFF transceiver data(Format is defined
2384 * by the SFF-8472 specification).
2386 typedef struct sli4_req_common_read_transceiver_data_s {
2388 #if BYTE_ORDER == LITTLE_ENDIAN
2389 uint32_t page_number;
2392 #error big endian version not defined
2394 } sli4_req_common_read_transceiver_data_t;
2396 typedef struct sli4_res_common_read_transceiver_data_s {
2398 #if BYTE_ORDER == LITTLE_ENDIAN
2399 uint32_t page_number;
2401 uint32_t page_data[32];
2402 uint32_t page_data_2[32];
2404 #error big endian version not defined
2406 } sli4_res_common_read_transceiver_data_t;
2409 * @brief COMMON_READ_OBJECT
2411 typedef struct sli4_req_common_read_object_s {
2413 #if BYTE_ORDER == LITTLE_ENDIAN
2414 uint32_t desired_read_length:24,
2416 uint32_t read_offset;
2417 uint8_t object_name[104];
2418 uint32_t host_buffer_descriptor_count;
2419 sli4_bde_t host_buffer_descriptor[0];
2421 #error big endian version not defined
2423 } sli4_req_common_read_object_t;
2425 typedef struct sli4_res_common_read_object_s {
2427 #if BYTE_ORDER == LITTLE_ENDIAN
2428 uint32_t actual_read_length;
2432 #error big endian version not defined
2434 } sli4_res_common_read_object_t;
2437 * @brief COMMON_WRITE_OBJECT
2439 typedef struct sli4_req_common_write_object_s {
2441 #if BYTE_ORDER == LITTLE_ENDIAN
2442 uint32_t desired_write_length:24,
2446 uint32_t write_offset;
2447 uint8_t object_name[104];
2448 uint32_t host_buffer_descriptor_count;
2449 sli4_bde_t host_buffer_descriptor[0];
2451 #error big endian version not defined
2453 } sli4_req_common_write_object_t;
2455 typedef struct sli4_res_common_write_object_s {
2457 #if BYTE_ORDER == LITTLE_ENDIAN
2458 uint32_t actual_write_length;
2459 uint32_t change_status:8,
2462 #error big endian version not defined
2464 } sli4_res_common_write_object_t;
2467 * @brief COMMON_DELETE_OBJECT
2469 typedef struct sli4_req_common_delete_object_s {
2471 #if BYTE_ORDER == LITTLE_ENDIAN
2474 uint8_t object_name[104];
2476 #error big endian version not defined
2478 } sli4_req_common_delete_object_t;
2481 * @brief COMMON_READ_OBJECT_LIST
2483 typedef struct sli4_req_common_read_object_list_s {
2485 #if BYTE_ORDER == LITTLE_ENDIAN
2486 uint32_t desired_read_length:24,
2488 uint32_t read_offset;
2489 uint8_t object_name[104];
2490 uint32_t host_buffer_descriptor_count;
2491 sli4_bde_t host_buffer_descriptor[0];
2493 #error big endian version not defined
2495 } sli4_req_common_read_object_list_t;
2498 * @brief COMMON_SET_DUMP_LOCATION
2500 typedef struct sli4_req_common_set_dump_location_s {
2502 #if BYTE_ORDER == LITTLE_ENDIAN
2503 uint32_t buffer_length:24,
2508 uint32_t buf_addr_low;
2509 uint32_t buf_addr_high;
2511 #error big endian version not defined
2513 } sli4_req_common_set_dump_location_t;
2515 typedef struct sli4_res_common_set_dump_location_s {
2517 #if BYTE_ORDER == LITTLE_ENDIAN
2518 uint32_t buffer_length:24,
2521 #error big endian version not defined
2523 }sli4_res_common_set_dump_location_t;
2526 * @brief COMMON_SET_SET_FEATURES
2528 #define SLI4_SET_FEATURES_DIF_SEED 0x01
2529 #define SLI4_SET_FEATURES_XRI_TIMER 0x03
2530 #define SLI4_SET_FEATURES_MAX_PCIE_SPEED 0x04
2531 #define SLI4_SET_FEATURES_FCTL_CHECK 0x05
2532 #define SLI4_SET_FEATURES_FEC 0x06
2533 #define SLI4_SET_FEATURES_PCIE_RECV_DETECT 0x07
2534 #define SLI4_SET_FEATURES_DIF_MEMORY_MODE 0x08
2535 #define SLI4_SET_FEATURES_DISABLE_SLI_PORT_PAUSE_STATE 0x09
2536 #define SLI4_SET_FEATURES_ENABLE_PCIE_OPTIONS 0x0A
2537 #define SLI4_SET_FEATURES_SET_CONFIG_AUTO_XFER_RDY_T10PI 0x0C
2538 #define SLI4_SET_FEATURES_ENABLE_MULTI_RECEIVE_QUEUE 0x0D
2539 #define SLI4_SET_FEATURES_SET_FTD_XFER_HINT 0x0F
2540 #define SLI4_SET_FEATURES_SLI_PORT_HEALTH_CHECK 0x11
2542 typedef struct sli4_req_common_set_features_s {
2544 #if BYTE_ORDER == LITTLE_ENDIAN
2549 #error big endian version not defined
2551 } sli4_req_common_set_features_t;
2553 typedef struct sli4_req_common_set_features_dif_seed_s {
2554 #if BYTE_ORDER == LITTLE_ENDIAN
2558 #error big endian version not defined
2560 } sli4_req_common_set_features_dif_seed_t;
2562 typedef struct sli4_req_common_set_features_t10_pi_mem_model_s {
2563 #if BYTE_ORDER == LITTLE_ENDIAN
2567 #error big endian version not defined
2569 } sli4_req_common_set_features_t10_pi_mem_model_t;
2571 typedef struct sli4_req_common_set_features_multirq_s {
2572 #if BYTE_ORDER == LITTLE_ENDIAN
2573 uint32_t isr:1, /*<< Include Sequence Reporting */
2574 agxfe:1, /*<< Auto Generate XFER-RDY Feature Enabled */
2580 #error big endian version not defined
2582 } sli4_req_common_set_features_multirq_t;
2584 typedef struct sli4_req_common_set_features_xfer_rdy_t10pi_s {
2585 #if BYTE_ORDER == LITTLE_ENDIAN
2593 uint32_t app_tag:16,
2596 #error big endian version not defined
2598 } sli4_req_common_set_features_xfer_rdy_t10pi_t;
2600 typedef struct sli4_req_common_set_features_health_check_s {
2601 #if BYTE_ORDER == LITTLE_ENDIAN
2606 #error big endian version not defined
2608 } sli4_req_common_set_features_health_check_t;
2610 typedef struct sli4_req_common_set_features_set_fdt_xfer_hint_s {
2611 #if BYTE_ORDER == LITTLE_ENDIAN
2612 uint32_t fdt_xfer_hint;
2614 #error big endian version not defined
2616 } sli4_req_common_set_features_set_fdt_xfer_hint_t;
2619 * @brief DMTF_EXEC_CLP_CMD
2621 typedef struct sli4_req_dmtf_exec_clp_cmd_s {
2623 #if BYTE_ORDER == LITTLE_ENDIAN
2624 uint32_t cmd_buf_length;
2625 uint32_t resp_buf_length;
2626 uint32_t cmd_buf_addr_low;
2627 uint32_t cmd_buf_addr_high;
2628 uint32_t resp_buf_addr_low;
2629 uint32_t resp_buf_addr_high;
2631 #error big endian version not defined
2633 } sli4_req_dmtf_exec_clp_cmd_t;
2635 typedef struct sli4_res_dmtf_exec_clp_cmd_s {
2637 #if BYTE_ORDER == LITTLE_ENDIAN
2639 uint32_t resp_length;
2644 uint32_t clp_status;
2645 uint32_t clp_detailed_status;
2647 #error big endian version not defined
2649 } sli4_res_dmtf_exec_clp_cmd_t;
2652 * @brief Resource descriptor
2655 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_PCIE 0x50
2656 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_NIC 0x51
2657 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_ISCSI 0x52
2658 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_FCFCOE 0x53
2659 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_RDMA 0x54
2660 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_PORT 0x55
2661 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_ISAP 0x56
2663 #define SLI4_PROTOCOL_NIC_TOE 0x01
2664 #define SLI4_PROTOCOL_ISCSI 0x02
2665 #define SLI4_PROTOCOL_FCOE 0x04
2666 #define SLI4_PROTOCOL_NIC_TOE_RDMA 0x08
2667 #define SLI4_PROTOCOL_FC 0x10
2668 #define SLI4_PROTOCOL_DEFAULT 0xff
2670 typedef struct sli4_resource_descriptor_v1_s {
2671 uint32_t descriptor_type:8,
2672 descriptor_length:8,
2674 uint32_t type_specific[0];
2675 } sli4_resource_descriptor_v1_t;
2677 typedef struct sli4_pcie_resource_descriptor_v1_s {
2678 uint32_t descriptor_type:8,
2679 descriptor_length:8,
2687 uint32_t sriov_state:8,
2691 uint32_t number_of_vfs:16,
2693 uint32_t mission_roles:8,
2700 } sli4_pcie_resource_descriptor_v1_t;
2702 typedef struct sli4_isap_resource_descriptor_v1_s {
2703 uint32_t descriptor_type:8,
2704 descriptor_length:8,
2706 uint32_t iscsi_tgt:1,
2711 uint32_t fcoe_tgt:1,
2716 uint32_t mc_type0:8,
2721 } sli4_isap_resouce_descriptor_v1_t;
2724 * @brief COMMON_GET_FUNCTION_CONFIG
2726 typedef struct sli4_req_common_get_function_config_s {
2728 } sli4_req_common_get_function_config_t;
2730 typedef struct sli4_res_common_get_function_config_s {
2732 #if BYTE_ORDER == LITTLE_ENDIAN
2733 uint32_t desc_count;
2736 #error big endian version not defined
2738 } sli4_res_common_get_function_config_t;
2741 * @brief COMMON_GET_PROFILE_CONFIG
2743 typedef struct sli4_req_common_get_profile_config_s {
2745 uint32_t profile_id:8,
2748 } sli4_req_common_get_profile_config_t;
2750 typedef struct sli4_res_common_get_profile_config_s {
2752 #if BYTE_ORDER == LITTLE_ENDIAN
2753 uint32_t desc_count;
2756 #error big endian version not defined
2758 } sli4_res_common_get_profile_config_t;
2761 * @brief COMMON_SET_PROFILE_CONFIG
2763 typedef struct sli4_req_common_set_profile_config_s {
2765 uint32_t profile_id:8,
2768 uint32_t desc_count;
2770 } sli4_req_common_set_profile_config_t;
2772 typedef struct sli4_res_common_set_profile_config_s {
2774 #if BYTE_ORDER == LITTLE_ENDIAN
2776 #error big endian version not defined
2778 } sli4_res_common_set_profile_config_t;
2781 * @brief Profile Descriptor for profile functions
2783 typedef struct sli4_profile_descriptor_s {
2784 #if BYTE_ORDER == LITTLE_ENDIAN
2785 uint32_t profile_id:8,
2789 uint32_t profile_description[128];
2791 #error big endian version not defined
2793 } sli4_profile_descriptor_t;
2795 /* We don't know in advance how many descriptors there are. We have
2796 to pick a number that we think will be big enough and ask for that
2799 #define MAX_PRODUCT_DESCRIPTORS 40
2802 * @brief COMMON_GET_PROFILE_LIST
2804 typedef struct sli4_req_common_get_profile_list_s {
2806 #if BYTE_ORDER == LITTLE_ENDIAN
2807 uint32_t start_profile_index:8,
2810 #error big endian version not defined
2812 } sli4_req_common_get_profile_list_t;
2814 typedef struct sli4_res_common_get_profile_list_s {
2816 #if BYTE_ORDER == LITTLE_ENDIAN
2817 uint32_t profile_descriptor_count;
2818 sli4_profile_descriptor_t profile_descriptor[MAX_PRODUCT_DESCRIPTORS];
2820 #error big endian version not defined
2822 } sli4_res_common_get_profile_list_t;
2825 * @brief COMMON_GET_ACTIVE_PROFILE
2827 typedef struct sli4_req_common_get_active_profile_s {
2829 } sli4_req_common_get_active_profile_t;
2831 typedef struct sli4_res_common_get_active_profile_s {
2833 #if BYTE_ORDER == LITTLE_ENDIAN
2834 uint32_t active_profile_id:8,
2839 #error big endian version not defined
2841 } sli4_res_common_get_active_profile_t;
2844 * @brief COMMON_SET_ACTIVE_PROFILE
2846 typedef struct sli4_req_common_set_active_profile_s {
2848 #if BYTE_ORDER == LITTLE_ENDIAN
2849 uint32_t active_profile_id:8,
2853 #error big endian version not defined
2855 } sli4_req_common_set_active_profile_t;
2857 typedef struct sli4_res_common_set_active_profile_s {
2859 } sli4_res_common_set_active_profile_t;
2862 * @brief Link Config Descriptor for link config functions
2864 typedef struct sli4_link_config_descriptor_s {
2865 #if BYTE_ORDER == LITTLE_ENDIAN
2866 uint32_t link_config_id:8,
2868 uint32_t config_description[8];
2870 #error big endian version not defined
2872 } sli4_link_config_descriptor_t;
2874 #define MAX_LINK_CONFIG_DESCRIPTORS 10
2877 * @brief COMMON_GET_RECONFIG_LINK_INFO
2879 typedef struct sli4_req_common_get_reconfig_link_info_s {
2881 #if BYTE_ORDER == LITTLE_ENDIAN
2883 #error big endian version not defined
2885 } sli4_req_common_get_reconfig_link_info_t;
2887 typedef struct sli4_res_common_get_reconfig_link_info_s {
2889 #if BYTE_ORDER == LITTLE_ENDIAN
2890 uint32_t active_link_config_id:8,
2892 next_link_config_id:8,
2894 uint32_t link_configuration_descriptor_count;
2895 sli4_link_config_descriptor_t desc[MAX_LINK_CONFIG_DESCRIPTORS];
2897 #error big endian version not defined
2899 } sli4_res_common_get_reconfig_link_info_t;
2902 * @brief COMMON_SET_RECONFIG_LINK_ID
2904 typedef struct sli4_req_common_set_reconfig_link_id_s {
2906 #if BYTE_ORDER == LITTLE_ENDIAN
2907 uint32_t next_link_config_id:8,
2911 #error big endian version not defined
2913 } sli4_req_common_set_reconfig_link_id_t;
2915 typedef struct sli4_res_common_set_reconfig_link_id_s {
2917 #if BYTE_ORDER == LITTLE_ENDIAN
2919 #error big endian version not defined
2921 } sli4_res_common_set_reconfig_link_id_t;
2923 typedef struct sli4_req_lowlevel_set_watchdog_s {
2925 #if BYTE_ORDER == LITTLE_ENDIAN
2926 uint32_t watchdog_timeout:16,
2929 #error big endian version not defined
2932 } sli4_req_lowlevel_set_watchdog_t;
2934 typedef struct sli4_res_lowlevel_set_watchdog_s {
2936 #if BYTE_ORDER == LITTLE_ENDIAN
2939 #error big endian version not defined
2941 } sli4_res_lowlevel_set_watchdog_t;
2944 * @brief Event Queue Entry
2946 typedef struct sli4_eqe_s {
2947 #if BYTE_ORDER == LITTLE_ENDIAN
2948 uint32_t vld:1, /** valid */
2953 #error big endian version not defined
2957 #define SLI4_MAJOR_CODE_STANDARD 0
2958 #define SLI4_MAJOR_CODE_SENTINEL 1
2961 * @brief Mailbox Completion Queue Entry
2963 * A CQE generated on the completion of a MQE from a MQ.
2965 typedef struct sli4_mcqe_s {
2966 #if BYTE_ORDER == LITTLE_ENDIAN
2967 uint32_t completion_status:16, /** values are protocol specific */
2969 uint32_t mqe_tag_low;
2970 uint32_t mqe_tag_high;
2972 con:1, /** consumed - command now being executed */
2973 cmp:1, /** completed - command still executing if clear */
2975 ae:1, /** async event - this is an ACQE */
2976 val:1; /** valid - contents of CQE are valid */
2978 #error big endian version not defined
2983 * @brief Asynchronous Completion Queue Entry
2985 * A CQE generated asynchronously in response to the link or other internal events.
2987 typedef struct sli4_acqe_s {
2988 #if BYTE_ORDER == LITTLE_ENDIAN
2989 uint32_t event_data[3];
2992 event_type:8, /** values are protocol specific */
2994 ae:1, /** async event - this is an ACQE */
2995 val:1; /** valid - contents of CQE are valid */
2997 #error big endian version not defined
3001 #define SLI4_ACQE_EVENT_CODE_LINK_STATE 0x01
3002 #define SLI4_ACQE_EVENT_CODE_FCOE_FIP 0x02
3003 #define SLI4_ACQE_EVENT_CODE_DCBX 0x03
3004 #define SLI4_ACQE_EVENT_CODE_ISCSI 0x04
3005 #define SLI4_ACQE_EVENT_CODE_GRP_5 0x05
3006 #define SLI4_ACQE_EVENT_CODE_FC_LINK_EVENT 0x10
3007 #define SLI4_ACQE_EVENT_CODE_SLI_PORT_EVENT 0x11
3008 #define SLI4_ACQE_EVENT_CODE_VF_EVENT 0x12
3009 #define SLI4_ACQE_EVENT_CODE_MR_EVENT 0x13
3012 * @brief Register name enums
3016 SLI4_REG_EQ_DOORBELL,
3017 SLI4_REG_CQ_DOORBELL,
3018 SLI4_REG_FCOE_RQ_DOORBELL,
3019 SLI4_REG_IO_WQ_DOORBELL,
3020 SLI4_REG_MQ_DOORBELL,
3021 SLI4_REG_PHYSDEV_CONTROL,
3022 SLI4_REG_SLIPORT_CONTROL,
3023 SLI4_REG_SLIPORT_ERROR1,
3024 SLI4_REG_SLIPORT_ERROR2,
3025 SLI4_REG_SLIPORT_SEMAPHORE,
3026 SLI4_REG_SLIPORT_STATUS,
3027 SLI4_REG_UERR_MASK_HI,
3028 SLI4_REG_UERR_MASK_LO,
3029 SLI4_REG_UERR_STATUS_HI,
3030 SLI4_REG_UERR_STATUS_LO,
3031 SLI4_REG_SW_UE_CSR1,
3032 SLI4_REG_SW_UE_CSR2,
3033 SLI4_REG_MAX /* must be last */
3036 typedef struct sli4_reg_s {
3047 SLI_QTYPE_MAX, /* must be last */
3050 #define SLI_USER_MQ_COUNT 1 /** User specified max mail queues */
3051 #define SLI_MAX_CQ_SET_COUNT 16
3052 #define SLI_MAX_RQ_SET_COUNT 16
3059 SLI_QENTRY_WQ_RELEASE,
3060 SLI_QENTRY_OPT_WRITE_CMD,
3061 SLI_QENTRY_OPT_WRITE_DATA,
3063 SLI_QENTRY_MAX /* must be last */
3066 typedef struct sli4_queue_s {
3067 /* Common to all queue types */
3070 uint32_t index; /** current host entry index */
3071 uint16_t size; /** entry size */
3072 uint16_t length; /** number of entries */
3073 uint16_t n_posted; /** number entries posted */
3074 uint16_t id; /** Port assigned xQ_ID */
3075 uint16_t ulp; /** ULP assigned to this queue */
3076 uint32_t doorbell_offset;/** The offset for the doorbell */
3077 uint16_t doorbell_rset; /** register set for the doorbell */
3078 uint8_t type; /** queue type ie EQ, CQ, ... */
3079 uint32_t proc_limit; /** limit number of CQE processed per iteration */
3080 uint32_t posted_limit; /** number of CQE/EQE to process before ringing doorbell */
3081 uint32_t max_num_processed;
3082 time_t max_process_time;
3084 uint16_t phase; /** For if_type = 6, this value toggle for each iteration
3085 of the queue, a queue entry is valid when a cqe valid
3086 bit matches this value */
3087 /* Type specific gunk */
3089 uint32_t r_idx; /** "read" index (MQ only) */
3091 uint32_t is_mq:1,/** CQ contains MQ/Async completions */
3092 is_hdr:1,/** is a RQ for packet headers */
3093 rq_batch:1;/** RQ index incremented by 8 */
3099 sli_queue_lock(sli4_queue_t *q)
3105 sli_queue_unlock(sli4_queue_t *q)
3107 ocs_unlock(&q->lock);
3110 #define SLI4_QUEUE_DEFAULT_CQ UINT16_MAX /** Use the default CQ */
3112 #define SLI4_QUEUE_RQ_BATCH 8
3117 SLI4_CB_MAX /* must be last */
3122 SLI_LINK_STATUS_DOWN,
3123 SLI_LINK_STATUS_NO_ALPA,
3124 SLI_LINK_STATUS_MAX,
3125 } sli4_link_status_e;
3128 SLI_LINK_TOPO_NPORT = 1, /** fabric or point-to-point */
3130 SLI_LINK_TOPO_LOOPBACK_INTERNAL,
3131 SLI_LINK_TOPO_LOOPBACK_EXTERNAL,
3134 } sli4_link_topology_e;
3136 /* TODO do we need both sli4_port_type_e & sli4_link_medium_e */
3138 SLI_LINK_MEDIUM_ETHERNET,
3140 SLI_LINK_MEDIUM_MAX,
3141 } sli4_link_medium_e;
3143 typedef struct sli4_link_event_s {
3144 sli4_link_status_e status; /* link up/down */
3145 sli4_link_topology_e topology;
3146 sli4_link_medium_e medium; /* Ethernet / FC */
3147 uint32_t speed; /* Mbps */
3150 } sli4_link_event_t;
3153 * @brief Fields retrieved from skyhawk that used used to build chained SGL
3155 typedef struct sli4_sgl_chaining_params_s {
3156 uint8_t chaining_capable;
3157 uint16_t frag_num_field_offset;
3158 uint16_t sgl_index_field_offset;
3159 uint64_t frag_num_field_mask;
3160 uint64_t sgl_index_field_mask;
3161 uint32_t chain_sge_initial_value_lo;
3162 uint32_t chain_sge_initial_value_hi;
3163 } sli4_sgl_chaining_params_t;
3165 typedef struct sli4_fip_event_s {
3167 uint32_t index; /* FCF index or UINT32_MAX if invalid */
3176 SLI_RSRC_MAX /* must be last */
3182 SLI4_PORT_TYPE_MAX /* must be last */
3186 SLI4_ASIC_TYPE_BE3 = 1,
3187 SLI4_ASIC_TYPE_SKYHAWK,
3188 SLI4_ASIC_TYPE_LANCER,
3189 SLI4_ASIC_TYPE_CORSAIR,
3190 SLI4_ASIC_TYPE_LANCERG6,
3191 SLI4_ASIC_TYPE_LANCERG7
3195 SLI4_ASIC_REV_FPGA = 1,
3206 typedef struct sli4_s {
3208 sli4_port_type_e port_type;
3210 uint32_t sli_rev; /* SLI revision number */
3211 uint32_t sli_family;
3212 uint32_t if_type; /* SLI Interface type */
3214 sli4_asic_type_e asic_type; /*<< ASIC type */
3215 sli4_asic_rev_e asic_rev; /*<< ASIC revision */
3216 uint32_t physical_port;
3221 uint16_t max_qcount[SLI_QTYPE_MAX];
3222 uint32_t max_qentries[SLI_QTYPE_MAX];
3223 uint16_t count_mask[SLI_QTYPE_MAX];
3224 uint16_t count_method[SLI_QTYPE_MAX];
3225 uint32_t qpage_count[SLI_QTYPE_MAX];
3226 uint16_t link_module_type;
3228 uint16_t rq_min_buf_size;
3229 uint32_t rq_max_buf_size;
3234 uint8_t fw_name[2][16];
3237 uint8_t port_number;
3239 char bios_version_string[32];
3240 uint8_t dual_ulp_capable;
3241 uint8_t is_ulp_fc[2];
3243 * Tracks the port resources using extents metaphor. For
3244 * devices that don't implement extents (i.e.
3245 * has_extents == FALSE), the code models each resource as
3246 * a single large extent.
3249 uint32_t number; /* number of extents */
3250 uint32_t size; /* number of elements in each extent */
3251 uint32_t n_alloc;/* number of elements allocated */
3253 ocs_bitmap_t *use_map;/* bitmap showing resources in use */
3254 uint32_t map_size;/* number of bits in bitmap */
3255 } extent[SLI_RSRC_MAX];
3256 sli4_features_t features;
3257 uint32_t has_extents:1,
3262 perf_wq_id_association:1,
3263 cq_create_version:2,
3264 mq_create_version:2,
3266 sgl_pre_registered:1,
3267 sgl_pre_registration_required:1,
3268 t10_dif_inline_capable:1,
3269 t10_dif_separate_capable:1;
3270 uint32_t sge_supported_length;
3271 uint32_t sgl_page_sizes;
3272 uint32_t max_sgl_pages;
3273 sli4_sgl_chaining_params_t sgl_chaining_params;
3278 * Callback functions
3280 int32_t (*link)(void *, void *);
3282 int32_t (*fip)(void *, void *);
3286 #if defined(OCS_INCLUDE_DEBUG)
3287 /* Save pointer to physical memory descriptor for non-embedded SLI_CONFIG
3288 * commands for BMBX dumping purposes */
3289 ocs_dma_t *bmbx_non_emb_pmd;
3299 * Get / set parameter functions
3301 static inline uint32_t
3302 sli_get_max_rsrc(sli4_t *sli4, sli4_resource_e rsrc)
3304 if (rsrc >= SLI_RSRC_MAX) {
3308 return sli4->config.extent[rsrc].size;
3311 static inline uint32_t
3312 sli_get_max_queue(sli4_t *sli4, sli4_qtype_e qtype)
3314 if (qtype >= SLI_QTYPE_MAX) {
3317 return sli4->config.max_qcount[qtype];
3320 static inline uint32_t
3321 sli_get_max_qentries(sli4_t *sli4, sli4_qtype_e qtype)
3324 return sli4->config.max_qentries[qtype];
3327 static inline uint32_t
3328 sli_get_max_sge(sli4_t *sli4)
3330 return sli4->config.sge_supported_length;
3333 static inline uint32_t
3334 sli_get_max_sgl(sli4_t *sli4)
3337 if (sli4->config.sgl_page_sizes != 1) {
3338 ocs_log_test(sli4->os, "unsupported SGL page sizes %#x\n",
3339 sli4->config.sgl_page_sizes);
3343 return ((sli4->config.max_sgl_pages * SLI_PAGE_SIZE) / sizeof(sli4_sge_t));
3346 static inline sli4_link_medium_e
3347 sli_get_medium(sli4_t *sli4)
3349 switch (sli4->config.topology) {
3350 case SLI4_READ_CFG_TOPO_FCOE:
3351 return SLI_LINK_MEDIUM_ETHERNET;
3352 case SLI4_READ_CFG_TOPO_FC:
3353 case SLI4_READ_CFG_TOPO_FC_DA:
3354 case SLI4_READ_CFG_TOPO_FC_AL:
3355 return SLI_LINK_MEDIUM_FC;
3357 return SLI_LINK_MEDIUM_MAX;
3362 sli_skh_chain_sge_build(sli4_t *sli4, sli4_sge_t *sge, uint32_t xri_index, uint32_t frag_num, uint32_t offset)
3364 sli4_sgl_chaining_params_t *cparms = &sli4->config.sgl_chaining_params;
3366 ocs_memset(sge, 0, sizeof(*sge));
3367 sge->sge_type = SLI4_SGE_TYPE_CHAIN;
3368 sge->buffer_address_high = (uint32_t)cparms->chain_sge_initial_value_hi;
3369 sge->buffer_address_low =
3370 (uint32_t)((cparms->chain_sge_initial_value_lo |
3371 (((uintptr_t)(xri_index & cparms->sgl_index_field_mask)) <<
3372 cparms->sgl_index_field_offset) |
3373 (((uintptr_t)(frag_num & cparms->frag_num_field_mask)) <<
3374 cparms->frag_num_field_offset) |
3378 static inline uint32_t
3379 sli_get_sli_rev(sli4_t *sli4)
3381 return sli4->sli_rev;
3384 static inline uint32_t
3385 sli_get_sli_family(sli4_t *sli4)
3387 return sli4->sli_family;
3390 static inline uint32_t
3391 sli_get_if_type(sli4_t *sli4)
3393 return sli4->if_type;
3396 static inline void *
3397 sli_get_wwn_port(sli4_t *sli4)
3399 return sli4->config.wwpn;
3402 static inline void *
3403 sli_get_wwn_node(sli4_t *sli4)
3405 return sli4->config.wwnn;
3408 static inline void *
3409 sli_get_vpd(sli4_t *sli4)
3411 return sli4->vpd.data.virt;
3414 static inline uint32_t
3415 sli_get_vpd_len(sli4_t *sli4)
3417 return sli4->vpd.length;
3420 static inline uint32_t
3421 sli_get_fw_revision(sli4_t *sli4, uint32_t which)
3423 return sli4->config.fw_rev[which];
3426 static inline void *
3427 sli_get_fw_name(sli4_t *sli4, uint32_t which)
3429 return sli4->config.fw_name[which];
3432 static inline char *
3433 sli_get_ipl_name(sli4_t *sli4)
3435 return sli4->config.ipl_name;
3438 static inline uint32_t
3439 sli_get_hw_revision(sli4_t *sli4, uint32_t which)
3441 return sli4->config.hw_rev[which];
3444 static inline uint32_t
3445 sli_get_auto_xfer_rdy_capable(sli4_t *sli4)
3447 return sli4->config.auto_xfer_rdy;
3450 static inline uint32_t
3451 sli_get_dif_capable(sli4_t *sli4)
3453 return sli4->config.features.flag.dif;
3456 static inline uint32_t
3457 sli_is_dif_inline_capable(sli4_t *sli4)
3459 return sli_get_dif_capable(sli4) && sli4->config.t10_dif_inline_capable;
3462 static inline uint32_t
3463 sli_is_dif_separate_capable(sli4_t *sli4)
3465 return sli_get_dif_capable(sli4) && sli4->config.t10_dif_separate_capable;
3468 static inline uint32_t
3469 sli_get_is_dual_ulp_capable(sli4_t *sli4)
3471 return sli4->config.dual_ulp_capable;
3474 static inline uint32_t
3475 sli_get_is_sgl_chaining_capable(sli4_t *sli4)
3477 return sli4->config.sgl_chaining_params.chaining_capable;
3480 static inline uint32_t
3481 sli_get_is_ulp_enabled(sli4_t *sli4, uint16_t ulp)
3483 return sli4->config.is_ulp_fc[ulp];
3486 static inline uint32_t
3487 sli_get_hlm_capable(sli4_t *sli4)
3489 return sli4->config.features.flag.hlm;
3492 static inline int32_t
3493 sli_set_hlm(sli4_t *sli4, uint32_t value)
3495 if (value && !sli4->config.features.flag.hlm) {
3496 ocs_log_test(sli4->os, "HLM not supported\n");
3500 sli4->config.high_login_mode = value != 0 ? TRUE : FALSE;
3505 static inline uint32_t
3506 sli_get_hlm(sli4_t *sli4)
3508 return sli4->config.high_login_mode;
3511 static inline uint32_t
3512 sli_get_sgl_preregister_required(sli4_t *sli4)
3514 return sli4->config.sgl_pre_registration_required;
3517 static inline uint32_t
3518 sli_get_sgl_preregister(sli4_t *sli4)
3520 return sli4->config.sgl_pre_registered;
3523 static inline int32_t
3524 sli_set_sgl_preregister(sli4_t *sli4, uint32_t value)
3526 if ((value == 0) && sli4->config.sgl_pre_registration_required) {
3527 ocs_log_test(sli4->os, "SGL pre-registration required\n");
3531 sli4->config.sgl_pre_registered = value != 0 ? TRUE : FALSE;
3536 static inline sli4_asic_type_e
3537 sli_get_asic_type(sli4_t *sli4)
3539 return sli4->asic_type;
3542 static inline sli4_asic_rev_e
3543 sli_get_asic_rev(sli4_t *sli4)
3545 return sli4->asic_rev;
3548 static inline int32_t
3549 sli_set_topology(sli4_t *sli4, uint32_t value)
3554 case SLI4_READ_CFG_TOPO_FCOE:
3555 case SLI4_READ_CFG_TOPO_FC:
3556 case SLI4_READ_CFG_TOPO_FC_DA:
3557 case SLI4_READ_CFG_TOPO_FC_AL:
3558 sli4->config.topology = value;
3561 ocs_log_test(sli4->os, "unsupported topology %#x\n", value);
3568 static inline uint16_t
3569 sli_get_link_module_type(sli4_t *sli4)
3571 return sli4->config.link_module_type;
3574 static inline char *
3575 sli_get_portnum(sli4_t *sli4)
3577 return sli4->config.port_name;
3580 static inline char *
3581 sli_get_bios_version_string(sli4_t *sli4)
3583 return sli4->config.bios_version_string;
3586 static inline uint32_t
3587 sli_convert_mask_to_count(uint32_t method, uint32_t mask)
3592 count = 1 << ocs_lg2(mask);
3602 * @brief Common Create Queue function prototype
3604 typedef int32_t (*sli4_create_q_fn_t)(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t);
3607 * @brief Common Destroy Queue function prototype
3609 typedef int32_t (*sli4_destroy_q_fn_t)(sli4_t *, void *, size_t, uint16_t);
3611 /****************************************************************************
3612 * Function prototypes
3614 extern int32_t sli_cmd_config_auto_xfer_rdy(sli4_t *, void *, size_t, uint32_t);
3615 extern int32_t sli_cmd_config_auto_xfer_rdy_hp(sli4_t *, void *, size_t, uint32_t, uint32_t, uint32_t);
3616 extern int32_t sli_cmd_config_link(sli4_t *, void *, size_t);
3617 extern int32_t sli_cmd_down_link(sli4_t *, void *, size_t);
3618 extern int32_t sli_cmd_dump_type4(sli4_t *, void *, size_t, uint16_t);
3619 extern int32_t sli_cmd_common_read_transceiver_data(sli4_t *, void *, size_t, uint32_t, ocs_dma_t *);
3620 extern int32_t sli_cmd_read_link_stats(sli4_t *, void *, size_t,uint8_t, uint8_t, uint8_t);
3621 extern int32_t sli_cmd_read_status(sli4_t *sli4, void *buf, size_t size, uint8_t clear_counters);
3622 extern int32_t sli_cmd_init_link(sli4_t *, void *, size_t, uint32_t, uint8_t);
3623 extern int32_t sli_cmd_init_vfi(sli4_t *, void *, size_t, uint16_t, uint16_t, uint16_t);
3624 extern int32_t sli_cmd_init_vpi(sli4_t *, void *, size_t, uint16_t, uint16_t);
3625 extern int32_t sli_cmd_post_xri(sli4_t *, void *, size_t, uint16_t, uint16_t);
3626 extern int32_t sli_cmd_release_xri(sli4_t *, void *, size_t, uint8_t);
3627 extern int32_t sli_cmd_read_sparm64(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t);
3628 extern int32_t sli_cmd_read_topology(sli4_t *, void *, size_t, ocs_dma_t *);
3629 extern int32_t sli_cmd_read_nvparms(sli4_t *, void *, size_t);
3630 extern int32_t sli_cmd_write_nvparms(sli4_t *, void *, size_t, uint8_t *, uint8_t *, uint8_t, uint32_t);
3634 uint8_t r_ctl_match;
3637 } sli4_cmd_rq_cfg_t;
3638 extern int32_t sli_cmd_reg_fcfi(sli4_t *, void *, size_t, uint16_t,
3639 sli4_cmd_rq_cfg_t rq_cfg[SLI4_CMD_REG_FCFI_NUM_RQ_CFG], uint16_t);
3640 extern int32_t sli_cmd_reg_fcfi_mrq(sli4_t *, void *, size_t, uint8_t, uint16_t, uint16_t, uint8_t, uint8_t , uint16_t, sli4_cmd_rq_cfg_t *);
3642 extern int32_t sli_cmd_reg_rpi(sli4_t *, void *, size_t, uint32_t, uint16_t, uint16_t, ocs_dma_t *, uint8_t, uint8_t);
3643 extern int32_t sli_cmd_reg_vfi(sli4_t *, void *, size_t, ocs_domain_t *);
3644 extern int32_t sli_cmd_reg_vpi(sli4_t *, void *, size_t, ocs_sli_port_t *, uint8_t);
3645 extern int32_t sli_cmd_sli_config(sli4_t *, void *, size_t, uint32_t, ocs_dma_t *);
3646 extern int32_t sli_cmd_unreg_fcfi(sli4_t *, void *, size_t, uint16_t);
3647 extern int32_t sli_cmd_unreg_rpi(sli4_t *, void *, size_t, uint16_t, sli4_resource_e, uint32_t);
3648 extern int32_t sli_cmd_unreg_vfi(sli4_t *, void *, size_t, ocs_domain_t *, uint32_t);
3649 extern int32_t sli_cmd_unreg_vpi(sli4_t *, void *, size_t, uint16_t, uint32_t);
3650 extern int32_t sli_cmd_common_nop(sli4_t *, void *, size_t, uint64_t);
3651 extern int32_t sli_cmd_common_get_resource_extent_info(sli4_t *, void *, size_t, uint16_t);
3652 extern int32_t sli_cmd_common_get_sli4_parameters(sli4_t *, void *, size_t);
3653 extern int32_t sli_cmd_common_write_object(sli4_t *, void *, size_t,
3654 uint16_t, uint16_t, uint32_t, uint32_t, char *, ocs_dma_t *);
3655 extern int32_t sli_cmd_common_delete_object(sli4_t *, void *, size_t, char *);
3656 extern int32_t sli_cmd_common_read_object(sli4_t *, void *, size_t, uint32_t,
3657 uint32_t, char *, ocs_dma_t *);
3658 extern int32_t sli_cmd_dmtf_exec_clp_cmd(sli4_t *sli4, void *buf, size_t size,
3661 extern int32_t sli_cmd_common_set_dump_location(sli4_t *sli4, void *buf, size_t size,
3662 uint8_t query, uint8_t is_buffer_list,
3663 ocs_dma_t *buffer, uint8_t fdb);
3664 extern int32_t sli_cmd_common_set_features(sli4_t *, void *, size_t, uint32_t, uint32_t, void*);
3665 extern int32_t sli_cmd_common_get_profile_list(sli4_t *sli4, void *buf,
3666 size_t size, uint32_t start_profile_index, ocs_dma_t *dma);
3667 extern int32_t sli_cmd_common_get_active_profile(sli4_t *sli4, void *buf,
3669 extern int32_t sli_cmd_common_set_active_profile(sli4_t *sli4, void *buf,
3672 uint32_t active_profile_id);
3673 extern int32_t sli_cmd_common_get_reconfig_link_info(sli4_t *sli4, void *buf,
3674 size_t size, ocs_dma_t *dma);
3675 extern int32_t sli_cmd_common_set_reconfig_link_id(sli4_t *sli4, void *buf,
3676 size_t size, ocs_dma_t *dma,
3677 uint32_t fd, uint32_t active_link_config_id);
3678 extern int32_t sli_cmd_common_get_function_config(sli4_t *sli4, void *buf,
3680 extern int32_t sli_cmd_common_get_profile_config(sli4_t *sli4, void *buf,
3681 size_t size, ocs_dma_t *dma);
3682 extern int32_t sli_cmd_common_set_profile_config(sli4_t *sli4, void *buf,
3683 size_t size, ocs_dma_t *dma,
3684 uint8_t profile_id, uint32_t descriptor_count,
3687 extern int32_t sli_cqe_mq(void *);
3688 extern int32_t sli_cqe_async(sli4_t *, void *);
3690 extern int32_t sli_setup(sli4_t *, ocs_os_handle_t, sli4_port_type_e);
3691 extern void sli_calc_max_qentries(sli4_t *sli4);
3692 extern int32_t sli_init(sli4_t *);
3693 extern int32_t sli_reset(sli4_t *);
3694 extern int32_t sli_fw_reset(sli4_t *);
3695 extern int32_t sli_teardown(sli4_t *);
3696 extern int32_t sli_callback(sli4_t *, sli4_callback_e, void *, void *);
3697 extern int32_t sli_bmbx_command(sli4_t *);
3698 extern int32_t __sli_queue_init(sli4_t *, sli4_queue_t *, uint32_t, size_t, uint32_t, uint32_t);
3699 extern int32_t __sli_create_queue(sli4_t *, sli4_queue_t *);
3700 extern int32_t sli_eq_modify_delay(sli4_t *sli4, sli4_queue_t *eq, uint32_t num_eq, uint32_t shift, uint32_t delay_mult);
3701 extern int32_t sli_queue_alloc(sli4_t *, uint32_t, sli4_queue_t *, uint32_t, sli4_queue_t *, uint16_t);
3702 extern int32_t sli_cq_alloc_set(sli4_t *, sli4_queue_t *qs[], uint32_t, uint32_t, sli4_queue_t *eqs[]);
3703 extern int32_t sli_get_queue_entry_size(sli4_t *, uint32_t);
3704 extern int32_t sli_queue_free(sli4_t *, sli4_queue_t *, uint32_t, uint32_t);
3705 extern int32_t sli_queue_reset(sli4_t *, sli4_queue_t *);
3706 extern int32_t sli_queue_is_empty(sli4_t *, sli4_queue_t *);
3707 extern int32_t sli_queue_eq_arm(sli4_t *, sli4_queue_t *, uint8_t);
3708 extern int32_t sli_queue_arm(sli4_t *, sli4_queue_t *, uint8_t);
3709 extern int32_t _sli_queue_write(sli4_t *, sli4_queue_t *, uint8_t *);
3710 extern int32_t sli_queue_write(sli4_t *, sli4_queue_t *, uint8_t *);
3711 extern int32_t sli_queue_read(sli4_t *, sli4_queue_t *, uint8_t *);
3712 extern int32_t sli_queue_index(sli4_t *, sli4_queue_t *);
3713 extern int32_t _sli_queue_poke(sli4_t *, sli4_queue_t *, uint32_t, uint8_t *);
3714 extern int32_t sli_queue_poke(sli4_t *, sli4_queue_t *, uint32_t, uint8_t *);
3715 extern int32_t sli_resource_alloc(sli4_t *, sli4_resource_e, uint32_t *, uint32_t *);
3716 extern int32_t sli_resource_free(sli4_t *, sli4_resource_e, uint32_t);
3717 extern int32_t sli_resource_reset(sli4_t *, sli4_resource_e);
3718 extern int32_t sli_eq_parse(sli4_t *, uint8_t *, uint16_t *);
3719 extern int32_t sli_cq_parse(sli4_t *, sli4_queue_t *, uint8_t *, sli4_qentry_e *, uint16_t *);
3721 extern int32_t sli_raise_ue(sli4_t *, uint8_t);
3722 extern int32_t sli_dump_is_ready(sli4_t *);
3723 extern int32_t sli_dump_is_present(sli4_t *);
3724 extern int32_t sli_reset_required(sli4_t *);
3725 extern int32_t sli_fw_error_status(sli4_t *);
3726 extern int32_t sli_fw_ready(sli4_t *);
3727 extern uint32_t sli_reg_read(sli4_t *, sli4_regname_e);
3728 extern void sli_reg_write(sli4_t *, sli4_regname_e, uint32_t);
3729 extern int32_t sli_link_is_configurable(sli4_t *);
3731 #include "ocs_fcp.h"
3734 * @brief Maximum value for a FCFI
3736 * Note that although most commands provide a 16 bit field for the FCFI,
3737 * the FC/FCoE Asynchronous Recived CQE format only provides 6 bits for
3738 * the returned FCFI. Then effectively, the FCFI cannot be larger than
3741 #define SLI4_MAX_FCFI 64
3744 * @brief Maximum value for FCF index
3746 * The SLI-4 specification uses a 16 bit field in most places for the FCF
3747 * index, but practically, this value will be much smaller. Arbitrarily
3748 * limit the max FCF index to match the max FCFI value.
3750 #define SLI4_MAX_FCF_INDEX SLI4_MAX_FCFI
3752 /*************************************************************************
3753 * SLI-4 FC/FCoE mailbox command formats and definitions.
3757 * FC/FCoE opcode (OPC) values.
3759 #define SLI4_OPC_FCOE_WQ_CREATE 0x1
3760 #define SLI4_OPC_FCOE_WQ_DESTROY 0x2
3761 #define SLI4_OPC_FCOE_POST_SGL_PAGES 0x3
3762 #define SLI4_OPC_FCOE_RQ_CREATE 0x5
3763 #define SLI4_OPC_FCOE_RQ_DESTROY 0x6
3764 #define SLI4_OPC_FCOE_READ_FCF_TABLE 0x8
3765 #define SLI4_OPC_FCOE_POST_HDR_TEMPLATES 0xb
3766 #define SLI4_OPC_FCOE_REDISCOVER_FCF 0x10
3768 /* Use the default CQ associated with the WQ */
3769 #define SLI4_CQ_DEFAULT 0xffff
3771 typedef struct sli4_physical_page_descriptor_s {
3774 } sli4_physical_page_descriptor_t;
3777 * @brief FCOE_WQ_CREATE
3779 * Create a Work Queue for FC/FCoE use.
3781 #define SLI4_FCOE_WQ_CREATE_V0_MAX_PAGES 4
3783 typedef struct sli4_req_fcoe_wq_create_s {
3785 #if BYTE_ORDER == LITTLE_ENDIAN
3786 uint32_t num_pages:8,
3790 sli4_physical_page_descriptor_t page_physical_address[SLI4_FCOE_WQ_CREATE_V0_MAX_PAGES];
3796 #error big endian version not defined
3798 } sli4_req_fcoe_wq_create_t;
3801 * @brief FCOE_WQ_CREATE_V1
3803 * Create a version 1 Work Queue for FC/FCoE use.
3805 typedef struct sli4_req_fcoe_wq_create_v1_s {
3807 #if BYTE_ORDER == LITTLE_ENDIAN
3808 uint32_t num_pages:16,
3810 uint32_t page_size:8,
3815 sli4_physical_page_descriptor_t page_physical_address[8];
3817 #error big endian version not defined
3819 } sli4_req_fcoe_wq_create_v1_t;
3821 #define SLI4_FCOE_WQ_CREATE_V1_MAX_PAGES 8
3824 * @brief FCOE_WQ_DESTROY
3826 * Destroy an FC/FCoE Work Queue.
3828 typedef struct sli4_req_fcoe_wq_destroy_s {
3830 #if BYTE_ORDER == LITTLE_ENDIAN
3834 #error big endian version not defined
3836 } sli4_req_fcoe_wq_destroy_t;
3839 * @brief FCOE_POST_SGL_PAGES
3841 * Register the scatter gather list (SGL) memory and associate it with an XRI.
3843 typedef struct sli4_req_fcoe_post_sgl_pages_s {
3845 #if BYTE_ORDER == LITTLE_ENDIAN
3846 uint32_t xri_start:16,
3850 uint32_t page0_high;
3852 uint32_t page1_high;
3855 #error big endian version not defined
3857 } sli4_req_fcoe_post_sgl_pages_t;
3860 * @brief FCOE_RQ_CREATE
3862 * Create a Receive Queue for FC/FCoE use.
3864 typedef struct sli4_req_fcoe_rq_create_s {
3866 #if BYTE_ORDER == LITTLE_ENDIAN
3867 uint32_t num_pages:16,
3876 uint32_t buffer_size:16,
3879 sli4_physical_page_descriptor_t page_physical_address[8];
3881 #error big endian version not defined
3883 } sli4_req_fcoe_rq_create_t;
3885 #define SLI4_FCOE_RQ_CREATE_V0_MAX_PAGES 8
3886 #define SLI4_FCOE_RQ_CREATE_V0_MIN_BUF_SIZE 128
3887 #define SLI4_FCOE_RQ_CREATE_V0_MAX_BUF_SIZE 2048
3890 * @brief FCOE_RQ_CREATE_V1
3892 * Create a version 1 Receive Queue for FC/FCoE use.
3894 typedef struct sli4_req_fcoe_rq_create_v1_s {
3896 #if BYTE_ORDER == LITTLE_ENDIAN
3897 uint32_t num_pages:16,
3902 uint32_t page_size:8,
3909 uint32_t buffer_size;
3910 sli4_physical_page_descriptor_t page_physical_address[8];
3912 #error big endian version not defined
3914 } sli4_req_fcoe_rq_create_v1_t;
3917 * @brief FCOE_RQ_CREATE_V2
3919 * Create a version 2 Receive Queue for FC/FCoE use.
3921 typedef struct sli4_req_fcoe_rq_create_v2_s {
3923 #if BYTE_ORDER == LITTLE_ENDIAN
3924 uint32_t num_pages:16,
3930 uint32_t page_size:8,
3934 uint32_t hdr_buffer_size:16,
3935 payload_buffer_size:16;
3936 uint32_t base_cq_id:16,
3939 sli4_physical_page_descriptor_t page_physical_address[0];
3941 #error big endian version not defined
3943 } sli4_req_fcoe_rq_create_v2_t;
3945 #define SLI4_FCOE_RQ_CREATE_V1_MAX_PAGES 8
3946 #define SLI4_FCOE_RQ_CREATE_V1_MIN_BUF_SIZE 64
3947 #define SLI4_FCOE_RQ_CREATE_V1_MAX_BUF_SIZE 2048
3949 #define SLI4_FCOE_RQE_SIZE_8 0x2
3950 #define SLI4_FCOE_RQE_SIZE_16 0x3
3951 #define SLI4_FCOE_RQE_SIZE_32 0x4
3952 #define SLI4_FCOE_RQE_SIZE_64 0x5
3953 #define SLI4_FCOE_RQE_SIZE_128 0x6
3955 #define SLI4_FCOE_RQ_PAGE_SIZE_4096 0x1
3956 #define SLI4_FCOE_RQ_PAGE_SIZE_8192 0x2
3957 #define SLI4_FCOE_RQ_PAGE_SIZE_16384 0x4
3958 #define SLI4_FCOE_RQ_PAGE_SIZE_32768 0x8
3959 #define SLI4_FCOE_RQ_PAGE_SIZE_64536 0x10
3961 #define SLI4_FCOE_RQE_SIZE 8
3964 * @brief FCOE_RQ_DESTROY
3966 * Destroy an FC/FCoE Receive Queue.
3968 typedef struct sli4_req_fcoe_rq_destroy_s {
3970 #if BYTE_ORDER == LITTLE_ENDIAN
3974 #error big endian version not defined
3976 } sli4_req_fcoe_rq_destroy_t;
3979 * @brief FCOE_READ_FCF_TABLE
3981 * Retrieve a FCF database (also known as a table) entry created by the SLI Port
3982 * during FIP discovery.
3984 typedef struct sli4_req_fcoe_read_fcf_table_s {
3986 #if BYTE_ORDER == LITTLE_ENDIAN
3987 uint32_t fcf_index:16,
3990 #error big endian version not defined
3992 } sli4_req_fcoe_read_fcf_table_t;
3994 /* A FCF index of -1 on the request means return the first valid entry */
3995 #define SLI4_FCOE_FCF_TABLE_FIRST (UINT16_MAX)
3998 * @brief FCF table entry
4000 * This is the information returned by the FCOE_READ_FCF_TABLE command.
4002 typedef struct sli4_fcf_entry_s {
4003 #if BYTE_ORDER == LITTLE_ENDIAN
4004 uint32_t max_receive_size;
4005 uint32_t fip_keep_alive;
4006 uint32_t fip_priority;
4007 uint8_t fcf_mac_address[6];
4008 uint8_t fcf_available;
4009 uint8_t mac_address_provider;
4010 uint8_t fabric_name_id[8];
4016 uint32_t fcf_index:16,
4018 uint8_t vlan_bitmap[512];
4019 uint8_t switch_name[8];
4021 #error big endian version not defined
4026 * @brief FCOE_READ_FCF_TABLE response.
4028 typedef struct sli4_res_fcoe_read_fcf_table_s {
4030 #if BYTE_ORDER == LITTLE_ENDIAN
4032 uint32_t next_index:16,
4034 sli4_fcf_entry_t fcf_entry;
4036 #error big endian version not defined
4038 } sli4_res_fcoe_read_fcf_table_t;
4040 /* A next FCF index of -1 in the response means this is the last valid entry */
4041 #define SLI4_FCOE_FCF_TABLE_LAST (UINT16_MAX)
4044 * @brief FCOE_POST_HDR_TEMPLATES
4046 typedef struct sli4_req_fcoe_post_hdr_templates_s {
4048 #if BYTE_ORDER == LITTLE_ENDIAN
4049 uint32_t rpi_offset:16,
4051 sli4_physical_page_descriptor_t page_descriptor[0];
4053 #error big endian version not defined
4055 } sli4_req_fcoe_post_hdr_templates_t;
4057 #define SLI4_FCOE_HDR_TEMPLATE_SIZE 64
4060 * @brief FCOE_REDISCOVER_FCF
4062 typedef struct sli4_req_fcoe_rediscover_fcf_s {
4064 #if BYTE_ORDER == LITTLE_ENDIAN
4065 uint32_t fcf_count:16,
4068 uint16_t fcf_index[16];
4070 #error big endian version not defined
4072 } sli4_req_fcoe_rediscover_fcf_t;
4075 * Work Queue Entry (WQE) types.
4077 #define SLI4_WQE_ABORT 0x0f
4078 #define SLI4_WQE_ELS_REQUEST64 0x8a
4079 #define SLI4_WQE_FCP_IBIDIR64 0xac
4080 #define SLI4_WQE_FCP_IREAD64 0x9a
4081 #define SLI4_WQE_FCP_IWRITE64 0x98
4082 #define SLI4_WQE_FCP_ICMND64 0x9c
4083 #define SLI4_WQE_FCP_TRECEIVE64 0xa1
4084 #define SLI4_WQE_FCP_CONT_TRECEIVE64 0xe5
4085 #define SLI4_WQE_FCP_TRSP64 0xa3
4086 #define SLI4_WQE_FCP_TSEND64 0x9f
4087 #define SLI4_WQE_GEN_REQUEST64 0xc2
4088 #define SLI4_WQE_SEND_FRAME 0xe1
4089 #define SLI4_WQE_XMIT_BCAST64 0X84
4090 #define SLI4_WQE_XMIT_BLS_RSP 0x97
4091 #define SLI4_WQE_ELS_RSP64 0x95
4092 #define SLI4_WQE_XMIT_SEQUENCE64 0x82
4093 #define SLI4_WQE_REQUEUE_XRI 0x93
4096 * WQE command types.
4098 #define SLI4_CMD_FCP_IREAD64_WQE 0x00
4099 #define SLI4_CMD_FCP_ICMND64_WQE 0x00
4100 #define SLI4_CMD_FCP_IWRITE64_WQE 0x01
4101 #define SLI4_CMD_FCP_TRECEIVE64_WQE 0x02
4102 #define SLI4_CMD_FCP_TRSP64_WQE 0x03
4103 #define SLI4_CMD_FCP_TSEND64_WQE 0x07
4104 #define SLI4_CMD_GEN_REQUEST64_WQE 0x08
4105 #define SLI4_CMD_XMIT_BCAST64_WQE 0x08
4106 #define SLI4_CMD_XMIT_BLS_RSP64_WQE 0x08
4107 #define SLI4_CMD_ABORT_WQE 0x08
4108 #define SLI4_CMD_XMIT_SEQUENCE64_WQE 0x08
4109 #define SLI4_CMD_REQUEUE_XRI_WQE 0x0A
4110 #define SLI4_CMD_SEND_FRAME_WQE 0x0a
4112 #define SLI4_WQE_SIZE 0x05
4113 #define SLI4_WQE_EXT_SIZE 0x06
4115 #define SLI4_WQE_BYTES (16 * sizeof(uint32_t))
4116 #define SLI4_WQE_EXT_BYTES (32 * sizeof(uint32_t))
4118 /* Mask for ccp (CS_CTL) */
4119 #define SLI4_MASK_CCP 0xfe /* Upper 7 bits of CS_CTL is priority */
4122 * @brief Generic WQE
4124 typedef struct sli4_generic_wqe_s {
4125 #if BYTE_ORDER == LITTLE_ENDIAN
4126 uint32_t cmd_spec0_5[6];
4127 uint32_t xri_tag:16,
4139 uint32_t request_tag:16,
4141 uint32_t ebde_cnt:4,
4158 uint32_t cmd_type:4,
4164 #error big endian version not defined
4166 } sli4_generic_wqe_t;
4169 * @brief WQE used to abort exchanges.
4171 typedef struct sli4_abort_wqe_s {
4172 #if BYTE_ORDER == LITTLE_ENDIAN
4181 uint32_t ext_t_mask;
4183 uint32_t xri_tag:16,
4195 uint32_t request_tag:16,
4197 uint32_t ebde_cnt:4,
4214 uint32_t cmd_type:4,
4220 #error big endian version not defined
4224 #define SLI4_ABORT_CRITERIA_XRI_TAG 0x01
4225 #define SLI4_ABORT_CRITERIA_ABORT_TAG 0x02
4226 #define SLI4_ABORT_CRITERIA_REQUEST_TAG 0x03
4227 #define SLI4_ABORT_CRITERIA_EXT_ABORT_TAG 0x04
4232 SLI_ABORT_REQUEST_ID,
4233 SLI_ABORT_MAX, /* must be last */
4234 } sli4_abort_type_e;
4237 * @brief WQE used to create an ELS request.
4239 typedef struct sli4_els_request64_wqe_s {
4240 sli4_bde_t els_request_payload;
4241 #if BYTE_ORDER == LITTLE_ENDIAN
4242 uint32_t els_request_payload_length;
4246 uint32_t remote_id:24,
4248 uint32_t xri_tag:16,
4260 uint32_t request_tag:16,
4262 uint32_t ebde_cnt:4,
4279 uint32_t cmd_type:4,
4284 sli4_bde_t els_response_payload_bde;
4285 uint32_t max_response_payload_length;
4287 #error big endian version not defined
4289 } sli4_els_request64_wqe_t;
4291 #define SLI4_ELS_REQUEST64_CONTEXT_RPI 0x0
4292 #define SLI4_ELS_REQUEST64_CONTEXT_VPI 0x1
4293 #define SLI4_ELS_REQUEST64_CONTEXT_VFI 0x2
4294 #define SLI4_ELS_REQUEST64_CONTEXT_FCFI 0x3
4296 #define SLI4_ELS_REQUEST64_CLASS_2 0x1
4297 #define SLI4_ELS_REQUEST64_CLASS_3 0x2
4299 #define SLI4_ELS_REQUEST64_DIR_WRITE 0x0
4300 #define SLI4_ELS_REQUEST64_DIR_READ 0x1
4302 #define SLI4_ELS_REQUEST64_OTHER 0x0
4303 #define SLI4_ELS_REQUEST64_LOGO 0x1
4304 #define SLI4_ELS_REQUEST64_FDISC 0x2
4305 #define SLI4_ELS_REQUEST64_FLOGIN 0x3
4306 #define SLI4_ELS_REQUEST64_PLOGI 0x4
4308 #define SLI4_ELS_REQUEST64_CMD_GEN 0x08
4309 #define SLI4_ELS_REQUEST64_CMD_NON_FABRIC 0x0c
4310 #define SLI4_ELS_REQUEST64_CMD_FABRIC 0x0d
4313 * @brief WQE used to create an FCP initiator no data command.
4315 typedef struct sli4_fcp_icmnd64_wqe_s {
4317 #if BYTE_ORDER == LITTLE_ENDIAN
4318 uint32_t payload_offset_length:16,
4319 fcp_cmd_buffer_length:16;
4321 uint32_t remote_n_port_id:24,
4323 uint32_t xri_tag:16,
4337 uint32_t request_tag:16,
4339 uint32_t ebde_cnt:4,
4356 uint32_t cmd_type:4,
4366 #error big endian version not defined
4368 } sli4_fcp_icmnd64_wqe_t;
4371 * @brief WQE used to create an FCP initiator read.
4373 typedef struct sli4_fcp_iread64_wqe_s {
4375 #if BYTE_ORDER == LITTLE_ENDIAN
4376 uint32_t payload_offset_length:16,
4377 fcp_cmd_buffer_length:16;
4378 uint32_t total_transfer_length;
4379 uint32_t remote_n_port_id:24,
4381 uint32_t xri_tag:16,
4395 uint32_t request_tag:16,
4397 uint32_t ebde_cnt:4,
4414 uint32_t cmd_type:4,
4421 #error big endian version not defined
4423 sli4_bde_t first_data_bde; /* reserved if performance hints disabled */
4424 } sli4_fcp_iread64_wqe_t;
4427 * @brief WQE used to create an FCP initiator write.
4429 typedef struct sli4_fcp_iwrite64_wqe_s {
4431 #if BYTE_ORDER == LITTLE_ENDIAN
4432 uint32_t payload_offset_length:16,
4433 fcp_cmd_buffer_length:16;
4434 uint32_t total_transfer_length;
4435 uint32_t initial_transfer_length;
4436 uint32_t xri_tag:16,
4450 uint32_t request_tag:16,
4452 uint32_t ebde_cnt:4,
4469 uint32_t cmd_type:4,
4474 uint32_t remote_n_port_id:24,
4477 #error big endian version not defined
4479 sli4_bde_t first_data_bde;
4480 } sli4_fcp_iwrite64_wqe_t;
4482 typedef struct sli4_fcp_128byte_wqe_s {
4484 } sli4_fcp_128byte_wqe_t;
4487 * @brief WQE used to create an FCP target receive, and FCP target
4490 typedef struct sli4_fcp_treceive64_wqe_s {
4492 #if BYTE_ORDER == LITTLE_ENDIAN
4493 uint32_t payload_offset_length;
4494 uint32_t relative_offset;
4496 * DWord 5 can either be the task retry identifier (HLM=0) or
4497 * the remote N_Port ID (HLM=1), or if implementing the Skyhawk
4498 * T10-PI workaround, the secondary xri tag
4501 uint32_t sec_xri_tag:16,
4505 uint32_t xri_tag:16,
4519 uint32_t request_tag:16,
4521 uint32_t ebde_cnt:4,
4540 uint32_t cmd_type:4,
4545 uint32_t fcp_data_receive_length;
4548 #error big endian version not defined
4550 sli4_bde_t first_data_bde; /* For performance hints */
4552 } sli4_fcp_treceive64_wqe_t;
4555 * @brief WQE used to create an FCP target response.
4557 typedef struct sli4_fcp_trsp64_wqe_s {
4559 #if BYTE_ORDER == LITTLE_ENDIAN
4560 uint32_t fcp_response_length;
4563 * DWord 5 can either be the task retry identifier (HLM=0) or
4564 * the remote N_Port ID (HLM=1)
4567 uint32_t xri_tag:16,
4581 uint32_t request_tag:16,
4583 uint32_t ebde_cnt:4,
4602 uint32_t cmd_type:4,
4612 #error big endian version not defined
4614 } sli4_fcp_trsp64_wqe_t;
4617 * @brief WQE used to create an FCP target send (DATA IN).
4619 typedef struct sli4_fcp_tsend64_wqe_s {
4621 #if BYTE_ORDER == LITTLE_ENDIAN
4622 uint32_t payload_offset_length;
4623 uint32_t relative_offset;
4625 * DWord 5 can either be the task retry identifier (HLM=0) or
4626 * the remote N_Port ID (HLM=1)
4629 uint32_t xri_tag:16,
4643 uint32_t request_tag:16,
4645 uint32_t ebde_cnt:4,
4664 uint32_t cmd_type:4,
4669 uint32_t fcp_data_transmit_length;
4672 #error big endian version not defined
4674 sli4_bde_t first_data_bde; /* For performance hints */
4675 } sli4_fcp_tsend64_wqe_t;
4677 #define SLI4_IO_CONTINUATION BIT(0) /** The XRI associated with this IO is already active */
4678 #define SLI4_IO_AUTO_GOOD_RESPONSE BIT(1) /** Automatically generate a good RSP frame */
4679 #define SLI4_IO_NO_ABORT BIT(2)
4680 #define SLI4_IO_DNRX BIT(3) /** Set the DNRX bit because no auto xref rdy buffer is posted */
4682 /* WQE DIF field contents */
4683 #define SLI4_DIF_DISABLED 0
4684 #define SLI4_DIF_PASS_THROUGH 1
4685 #define SLI4_DIF_STRIP 2
4686 #define SLI4_DIF_INSERT 3
4689 * @brief WQE used to create a general request.
4691 typedef struct sli4_gen_request64_wqe_s {
4693 #if BYTE_ORDER == LITTLE_ENDIAN
4694 uint32_t request_payload_length;
4695 uint32_t relative_offset;
4700 uint32_t xri_tag:16,
4712 uint32_t request_tag:16,
4714 uint32_t ebde_cnt:4,
4731 uint32_t cmd_type:4,
4736 uint32_t remote_n_port_id:24,
4740 uint32_t max_response_payload_length;
4742 #error big endian version not defined
4744 } sli4_gen_request64_wqe_t;
4747 * @brief WQE used to create a send frame request.
4749 typedef struct sli4_send_frame_wqe_s {
4751 #if BYTE_ORDER == LITTLE_ENDIAN
4752 uint32_t frame_length;
4753 uint32_t fc_header_0_1[2];
4754 uint32_t xri_tag:16,
4766 uint32_t request_tag:16,
4769 uint32_t ebde_cnt:4,
4786 uint32_t cmd_type:4,
4791 uint32_t fc_header_2_5[4];
4793 #error big endian version not defined
4795 } sli4_send_frame_wqe_t;
4798 * @brief WQE used to create a transmit sequence.
4800 typedef struct sli4_xmit_sequence64_wqe_s {
4802 #if BYTE_ORDER == LITTLE_ENDIAN
4803 uint32_t remote_n_port_id:24,
4805 uint32_t relative_offset;
4815 uint32_t xri_tag:16,
4828 uint32_t request_tag:16,
4830 uint32_t ebde_cnt:4,
4847 uint32_t cmd_type:4,
4852 uint32_t sequence_payload_len;
4857 #error big endian version not defined
4859 } sli4_xmit_sequence64_wqe_t;
4862 * @brief WQE used unblock the specified XRI and to release it to the SLI Port's free pool.
4864 typedef struct sli4_requeue_xri_wqe_s {
4871 #if BYTE_ORDER == LITTLE_ENDIAN
4872 uint32_t xri_tag:16,
4884 uint32_t request_tag:16,
4886 uint32_t ebde_cnt:4,
4903 uint32_t cmd_type:4,
4913 #error big endian version not defined
4915 } sli4_requeue_xri_wqe_t;
4918 * @brief WQE used to send a single frame sequence to broadcast address
4920 typedef struct sli4_xmit_bcast64_wqe_s {
4921 sli4_bde_t sequence_payload;
4922 #if BYTE_ORDER == LITTLE_ENDIAN
4923 uint32_t sequence_payload_length;
4929 uint32_t xri_tag:16,
4941 uint32_t request_tag:16,
4943 uint32_t ebde_cnt:4,
4960 uint32_t cmd_type:4,
4970 #error big endian version not defined
4972 } sli4_xmit_bcast64_wqe_t;
4975 * @brief WQE used to create a BLS response.
4977 typedef struct sli4_xmit_bls_rsp_wqe_s {
4978 #if BYTE_ORDER == LITTLE_ENDIAN
4979 uint32_t payload_word0;
4982 uint32_t high_seq_cnt:16,
4985 uint32_t local_n_port_id:24,
4987 uint32_t remote_id:24,
4991 uint32_t xri_tag:16,
5003 uint32_t request_tag:16,
5005 uint32_t ebde_cnt:4,
5022 uint32_t cmd_type:4,
5027 uint32_t temporary_rpi:16,
5033 #error big endian version not defined
5035 } sli4_xmit_bls_rsp_wqe_t;
5043 typedef struct sli_bls_payload_s {
5044 sli_bls_type_e type;
5049 uint32_t seq_id_validity:8,
5054 uint16_t low_seq_cnt;
5055 uint16_t high_seq_cnt;
5058 uint32_t vendor_unique:8,
5059 reason_explanation:8,
5064 } sli_bls_payload_t;
5067 * @brief WQE used to create an ELS response.
5069 typedef struct sli4_xmit_els_rsp64_wqe_s {
5070 sli4_bde_t els_response_payload;
5071 #if BYTE_ORDER == LITTLE_ENDIAN
5072 uint32_t els_response_payload_length;
5076 uint32_t remote_id:24,
5078 uint32_t xri_tag:16,
5090 uint32_t request_tag:16,
5092 uint32_t ebde_cnt:4,
5109 uint32_t cmd_type:4,
5114 uint32_t temporary_rpi:16,
5120 #error big endian version not defined
5122 } sli4_xmit_els_rsp64_wqe_t;
5125 * @brief Asynchronouse Event: Link State ACQE.
5127 typedef struct sli4_link_state_s {
5128 #if BYTE_ORDER == LITTLE_ENDIAN
5129 uint32_t link_number:6,
5134 uint32_t port_fault:8,
5136 logical_link_speed:16;
5140 event_type:8, /** values are protocol specific */
5142 ae:1, /** async event - this is an ACQE */
5143 val:1; /** valid - contents of CQE are valid */
5145 #error big endian version not defined
5147 } sli4_link_state_t;
5149 #define SLI4_LINK_ATTN_TYPE_LINK_UP 0x01
5150 #define SLI4_LINK_ATTN_TYPE_LINK_DOWN 0x02
5151 #define SLI4_LINK_ATTN_TYPE_NO_HARD_ALPA 0x03
5153 #define SLI4_LINK_ATTN_P2P 0x01
5154 #define SLI4_LINK_ATTN_FC_AL 0x02
5155 #define SLI4_LINK_ATTN_INTERNAL_LOOPBACK 0x03
5156 #define SLI4_LINK_ATTN_SERDES_LOOPBACK 0x04
5158 #define SLI4_LINK_ATTN_1G 0x01
5159 #define SLI4_LINK_ATTN_2G 0x02
5160 #define SLI4_LINK_ATTN_4G 0x04
5161 #define SLI4_LINK_ATTN_8G 0x08
5162 #define SLI4_LINK_ATTN_10G 0x0a
5163 #define SLI4_LINK_ATTN_16G 0x10
5165 #define SLI4_LINK_TYPE_ETHERNET 0x0
5166 #define SLI4_LINK_TYPE_FC 0x1
5169 * @brief Asynchronouse Event: FC Link Attention Event.
5171 typedef struct sli4_link_attention_s {
5172 #if BYTE_ORDER == LITTLE_ENDIAN
5173 uint32_t link_number:8,
5177 uint32_t port_fault:8,
5178 shared_link_status:8,
5179 logical_link_speed:16;
5183 event_type:8, /** values are protocol specific */
5185 ae:1, /** async event - this is an ACQE */
5186 val:1; /** valid - contents of CQE are valid */
5188 #error big endian version not defined
5190 } sli4_link_attention_t;
5193 * @brief FC/FCoE event types.
5195 #define SLI4_LINK_STATE_PHYSICAL 0x00
5196 #define SLI4_LINK_STATE_LOGICAL 0x01
5198 #define SLI4_FCOE_FIP_FCF_DISCOVERED 0x01
5199 #define SLI4_FCOE_FIP_FCF_TABLE_FULL 0x02
5200 #define SLI4_FCOE_FIP_FCF_DEAD 0x03
5201 #define SLI4_FCOE_FIP_FCF_CLEAR_VLINK 0x04
5202 #define SLI4_FCOE_FIP_FCF_MODIFIED 0x05
5204 #define SLI4_GRP5_QOS_SPEED 0x01
5206 #define SLI4_FC_EVENT_LINK_ATTENTION 0x01
5207 #define SLI4_FC_EVENT_SHARED_LINK_ATTENTION 0x02
5209 #define SLI4_PORT_SPEED_NO_LINK 0x0
5210 #define SLI4_PORT_SPEED_10_MBPS 0x1
5211 #define SLI4_PORT_SPEED_100_MBPS 0x2
5212 #define SLI4_PORT_SPEED_1_GBPS 0x3
5213 #define SLI4_PORT_SPEED_10_GBPS 0x4
5215 #define SLI4_PORT_DUPLEX_NONE 0x0
5216 #define SLI4_PORT_DUPLEX_HWF 0x1
5217 #define SLI4_PORT_DUPLEX_FULL 0x2
5219 #define SLI4_PORT_LINK_STATUS_PHYSICAL_DOWN 0x0
5220 #define SLI4_PORT_LINK_STATUS_PHYSICAL_UP 0x1
5221 #define SLI4_PORT_LINK_STATUS_LOGICAL_DOWN 0x2
5222 #define SLI4_PORT_LINK_STATUS_LOGICAL_UP 0x3
5225 * @brief Asynchronouse Event: FCoE/FIP ACQE.
5227 typedef struct sli4_fcoe_fip_s {
5228 #if BYTE_ORDER == LITTLE_ENDIAN
5229 uint32_t event_information;
5230 uint32_t fcf_count:16,
5235 event_type:8, /** values are protocol specific */
5237 ae:1, /** async event - this is an ACQE */
5238 val:1; /** valid - contents of CQE are valid */
5240 #error big endian version not defined
5245 * @brief FC/FCoE WQ completion queue entry.
5247 typedef struct sli4_fc_wcqe_s {
5248 #if BYTE_ORDER == LITTLE_ENDIAN
5249 uint32_t hw_status:8,
5252 uint32_t wqe_specific_1;
5253 uint32_t wqe_specific_2;
5263 #error big endian version not defined
5268 * @brief FC/FCoE WQ consumed CQ queue entry.
5270 typedef struct sli4_fc_wqec_s {
5271 #if BYTE_ORDER == LITTLE_ENDIAN
5274 uint32_t wqe_index:16,
5281 #error big endian version not defined
5286 * @brief FC/FCoE Completion Status Codes.
5288 #define SLI4_FC_WCQE_STATUS_SUCCESS 0x00
5289 #define SLI4_FC_WCQE_STATUS_FCP_RSP_FAILURE 0x01
5290 #define SLI4_FC_WCQE_STATUS_REMOTE_STOP 0x02
5291 #define SLI4_FC_WCQE_STATUS_LOCAL_REJECT 0x03
5292 #define SLI4_FC_WCQE_STATUS_NPORT_RJT 0x04
5293 #define SLI4_FC_WCQE_STATUS_FABRIC_RJT 0x05
5294 #define SLI4_FC_WCQE_STATUS_NPORT_BSY 0x06
5295 #define SLI4_FC_WCQE_STATUS_FABRIC_BSY 0x07
5296 #define SLI4_FC_WCQE_STATUS_LS_RJT 0x09
5297 #define SLI4_FC_WCQE_STATUS_CMD_REJECT 0x0b
5298 #define SLI4_FC_WCQE_STATUS_FCP_TGT_LENCHECK 0x0c
5299 #define SLI4_FC_WCQE_STATUS_RQ_BUF_LEN_EXCEEDED 0x11
5300 #define SLI4_FC_WCQE_STATUS_RQ_INSUFF_BUF_NEEDED 0x12
5301 #define SLI4_FC_WCQE_STATUS_RQ_INSUFF_FRM_DISC 0x13
5302 #define SLI4_FC_WCQE_STATUS_RQ_DMA_FAILURE 0x14
5303 #define SLI4_FC_WCQE_STATUS_FCP_RSP_TRUNCATE 0x15
5304 #define SLI4_FC_WCQE_STATUS_DI_ERROR 0x16
5305 #define SLI4_FC_WCQE_STATUS_BA_RJT 0x17
5306 #define SLI4_FC_WCQE_STATUS_RQ_INSUFF_XRI_NEEDED 0x18
5307 #define SLI4_FC_WCQE_STATUS_RQ_INSUFF_XRI_DISC 0x19
5308 #define SLI4_FC_WCQE_STATUS_RX_ERROR_DETECT 0x1a
5309 #define SLI4_FC_WCQE_STATUS_RX_ABORT_REQUEST 0x1b
5311 /* driver generated status codes; better not overlap with chip's status codes! */
5312 #define SLI4_FC_WCQE_STATUS_TARGET_WQE_TIMEOUT 0xff
5313 #define SLI4_FC_WCQE_STATUS_SHUTDOWN 0xfe
5314 #define SLI4_FC_WCQE_STATUS_DISPATCH_ERROR 0xfd
5317 * @brief DI_ERROR Extended Status
5319 #define SLI4_FC_DI_ERROR_GE (1 << 0) /* Guard Error */
5320 #define SLI4_FC_DI_ERROR_AE (1 << 1) /* Application Tag Error */
5321 #define SLI4_FC_DI_ERROR_RE (1 << 2) /* Reference Tag Error */
5322 #define SLI4_FC_DI_ERROR_TDPV (1 << 3) /* Total Data Placed Valid */
5323 #define SLI4_FC_DI_ERROR_UDB (1 << 4) /* Uninitialized DIF Block */
5324 #define SLI4_FC_DI_ERROR_EDIR (1 << 5) /* Error direction */
5327 * @brief Local Reject Reason Codes.
5329 #define SLI4_FC_LOCAL_REJECT_MISSING_CONTINUE 0x01
5330 #define SLI4_FC_LOCAL_REJECT_SEQUENCE_TIMEOUT 0x02
5331 #define SLI4_FC_LOCAL_REJECT_INTERNAL_ERROR 0x03
5332 #define SLI4_FC_LOCAL_REJECT_INVALID_RPI 0x04
5333 #define SLI4_FC_LOCAL_REJECT_NO_XRI 0x05
5334 #define SLI4_FC_LOCAL_REJECT_ILLEGAL_COMMAND 0x06
5335 #define SLI4_FC_LOCAL_REJECT_XCHG_DROPPED 0x07
5336 #define SLI4_FC_LOCAL_REJECT_ILLEGAL_FIELD 0x08
5337 #define SLI4_FC_LOCAL_REJECT_NO_ABORT_MATCH 0x0c
5338 #define SLI4_FC_LOCAL_REJECT_TX_DMA_FAILED 0x0d
5339 #define SLI4_FC_LOCAL_REJECT_RX_DMA_FAILED 0x0e
5340 #define SLI4_FC_LOCAL_REJECT_ILLEGAL_FRAME 0x0f
5341 #define SLI4_FC_LOCAL_REJECT_NO_RESOURCES 0x11
5342 #define SLI4_FC_LOCAL_REJECT_FCP_CONF_FAILURE 0x12
5343 #define SLI4_FC_LOCAL_REJECT_ILLEGAL_LENGTH 0x13
5344 #define SLI4_FC_LOCAL_REJECT_UNSUPPORTED_FEATURE 0x14
5345 #define SLI4_FC_LOCAL_REJECT_ABORT_IN_PROGRESS 0x15
5346 #define SLI4_FC_LOCAL_REJECT_ABORT_REQUESTED 0x16
5347 #define SLI4_FC_LOCAL_REJECT_RCV_BUFFER_TIMEOUT 0x17
5348 #define SLI4_FC_LOCAL_REJECT_LOOP_OPEN_FAILURE 0x18
5349 #define SLI4_FC_LOCAL_REJECT_LINK_DOWN 0x1a
5350 #define SLI4_FC_LOCAL_REJECT_CORRUPTED_DATA 0x1b
5351 #define SLI4_FC_LOCAL_REJECT_CORRUPTED_RPI 0x1c
5352 #define SLI4_FC_LOCAL_REJECT_OUT_OF_ORDER_DATA 0x1d
5353 #define SLI4_FC_LOCAL_REJECT_OUT_OF_ORDER_ACK 0x1e
5354 #define SLI4_FC_LOCAL_REJECT_DUP_FRAME 0x1f
5355 #define SLI4_FC_LOCAL_REJECT_LINK_CONTROL_FRAME 0x20
5356 #define SLI4_FC_LOCAL_REJECT_BAD_HOST_ADDRESS 0x21
5357 #define SLI4_FC_LOCAL_REJECT_MISSING_HDR_BUFFER 0x23
5358 #define SLI4_FC_LOCAL_REJECT_MSEQ_CHAIN_CORRUPTED 0x24
5359 #define SLI4_FC_LOCAL_REJECT_ABORTMULT_REQUESTED 0x25
5360 #define SLI4_FC_LOCAL_REJECT_BUFFER_SHORTAGE 0x28
5361 #define SLI4_FC_LOCAL_REJECT_RCV_XRIBUF_WAITING 0x29
5362 #define SLI4_FC_LOCAL_REJECT_INVALID_VPI 0x2e
5363 #define SLI4_FC_LOCAL_REJECT_MISSING_XRIBUF 0x30
5364 #define SLI4_FC_LOCAL_REJECT_INVALID_RELOFFSET 0x40
5365 #define SLI4_FC_LOCAL_REJECT_MISSING_RELOFFSET 0x41
5366 #define SLI4_FC_LOCAL_REJECT_INSUFF_BUFFERSPACE 0x42
5367 #define SLI4_FC_LOCAL_REJECT_MISSING_SI 0x43
5368 #define SLI4_FC_LOCAL_REJECT_MISSING_ES 0x44
5369 #define SLI4_FC_LOCAL_REJECT_INCOMPLETE_XFER 0x45
5370 #define SLI4_FC_LOCAL_REJECT_SLER_FAILURE 0x46
5371 #define SLI4_FC_LOCAL_REJECT_SLER_CMD_RCV_FAILURE 0x47
5372 #define SLI4_FC_LOCAL_REJECT_SLER_REC_RJT_ERR 0x48
5373 #define SLI4_FC_LOCAL_REJECT_SLER_REC_SRR_RETRY_ERR 0x49
5374 #define SLI4_FC_LOCAL_REJECT_SLER_SRR_RJT_ERR 0x4a
5375 #define SLI4_FC_LOCAL_REJECT_SLER_RRQ_RJT_ERR 0x4c
5376 #define SLI4_FC_LOCAL_REJECT_SLER_RRQ_RETRY_ERR 0x4d
5377 #define SLI4_FC_LOCAL_REJECT_SLER_ABTS_ERR 0x4e
5379 typedef struct sli4_fc_async_rcqe_s {
5380 #if BYTE_ORDER == LITTLE_ENDIAN
5383 rq_element_index:12,
5388 payload_data_placement_length:16;
5389 uint32_t sof_byte:8,
5392 header_data_placement_length:6,
5396 #error big endian version not defined
5398 } sli4_fc_async_rcqe_t;
5400 typedef struct sli4_fc_async_rcqe_v1_s {
5401 #if BYTE_ORDER == LITTLE_ENDIAN
5404 rq_element_index:12,
5409 payload_data_placement_length:16;
5410 uint32_t sof_byte:8,
5413 header_data_placement_length:6,
5417 #error big endian version not defined
5419 } sli4_fc_async_rcqe_v1_t;
5421 #define SLI4_FC_ASYNC_RQ_SUCCESS 0x10
5422 #define SLI4_FC_ASYNC_RQ_BUF_LEN_EXCEEDED 0x11
5423 #define SLI4_FC_ASYNC_RQ_INSUFF_BUF_NEEDED 0x12
5424 #define SLI4_FC_ASYNC_RQ_INSUFF_BUF_FRM_DISC 0x13
5425 #define SLI4_FC_ASYNC_RQ_DMA_FAILURE 0x14
5427 typedef struct sli4_fc_coalescing_rcqe_s {
5428 #if BYTE_ORDER == LITTLE_ENDIAN
5431 rq_element_index:12,
5435 sequence_reporting_placement_length:16;
5441 #error big endian version not defined
5443 } sli4_fc_coalescing_rcqe_t;
5445 #define SLI4_FC_COALESCE_RQ_SUCCESS 0x10
5446 #define SLI4_FC_COALESCE_RQ_INSUFF_XRI_NEEDED 0x18
5448 typedef struct sli4_fc_optimized_write_cmd_cqe_s {
5449 #if BYTE_ORDER == LITTLE_ENDIAN
5452 rq_element_index:15,
5460 payload_data_placement_length:16;
5463 header_data_placement_length:6,
5467 #error big endian version not defined
5469 } sli4_fc_optimized_write_cmd_cqe_t;
5471 typedef struct sli4_fc_optimized_write_data_cqe_s {
5472 #if BYTE_ORDER == LITTLE_ENDIAN
5473 uint32_t hw_status:8,
5476 uint32_t total_data_placed;
5477 uint32_t extended_status;
5487 #error big endian version not defined
5489 } sli4_fc_optimized_write_data_cqe_t;
5491 typedef struct sli4_fc_xri_aborted_cqe_s {
5492 #if BYTE_ORDER == LITTLE_ENDIAN
5496 uint32_t extended_status;
5508 #error big endian version not defined
5510 } sli4_fc_xri_aborted_cqe_t;
5513 * Code definitions applicable to all FC/FCoE CQE types.
5515 #define SLI4_CQE_CODE_OFFSET 14
5517 #define SLI4_CQE_CODE_WORK_REQUEST_COMPLETION 0x01
5518 #define SLI4_CQE_CODE_RELEASE_WQE 0x02
5519 #define SLI4_CQE_CODE_RQ_ASYNC 0x04
5520 #define SLI4_CQE_CODE_XRI_ABORTED 0x05
5521 #define SLI4_CQE_CODE_RQ_COALESCING 0x06
5522 #define SLI4_CQE_CODE_RQ_CONSUMPTION 0x07
5523 #define SLI4_CQE_CODE_MEASUREMENT_REPORTING 0x08
5524 #define SLI4_CQE_CODE_RQ_ASYNC_V1 0x09
5525 #define SLI4_CQE_CODE_OPTIMIZED_WRITE_CMD 0x0B
5526 #define SLI4_CQE_CODE_OPTIMIZED_WRITE_DATA 0x0C
5528 extern int32_t sli_fc_process_link_state(sli4_t *, void *);
5529 extern int32_t sli_fc_process_link_attention(sli4_t *, void *);
5530 extern int32_t sli_fc_cqe_parse(sli4_t *, sli4_queue_t *, uint8_t *, sli4_qentry_e *, uint16_t *);
5531 extern uint32_t sli_fc_response_length(sli4_t *, uint8_t *);
5532 extern uint32_t sli_fc_io_length(sli4_t *, uint8_t *);
5533 extern int32_t sli_fc_els_did(sli4_t *, uint8_t *, uint32_t *);
5534 extern uint32_t sli_fc_ext_status(sli4_t *, uint8_t *);
5535 extern int32_t sli_fc_rqe_rqid_and_index(sli4_t *, uint8_t *, uint16_t *, uint32_t *);
5536 extern int32_t sli_fc_process_fcoe(sli4_t *, void *);
5537 extern int32_t sli_cmd_fcoe_wq_create(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t);
5538 extern int32_t sli_cmd_fcoe_wq_create_v1(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t);
5539 extern int32_t sli_cmd_fcoe_wq_destroy(sli4_t *, void *, size_t, uint16_t);
5540 extern int32_t sli_cmd_fcoe_post_sgl_pages(sli4_t *, void *, size_t, uint16_t, uint32_t, ocs_dma_t **, ocs_dma_t **,
5542 extern int32_t sli_cmd_fcoe_rq_create(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t, uint16_t);
5543 extern int32_t sli_cmd_fcoe_rq_create_v1(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t, uint16_t);
5544 extern int32_t sli_cmd_fcoe_rq_destroy(sli4_t *, void *, size_t, uint16_t);
5545 extern int32_t sli_cmd_fcoe_read_fcf_table(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t);
5546 extern int32_t sli_cmd_fcoe_post_hdr_templates(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, ocs_dma_t *);
5547 extern int32_t sli_cmd_fcoe_rediscover_fcf(sli4_t *, void *, size_t, uint16_t);
5548 extern int32_t sli_fc_rq_alloc(sli4_t *, sli4_queue_t *, uint32_t, uint32_t, sli4_queue_t *, uint16_t, uint8_t);
5549 extern int32_t sli_fc_rq_set_alloc(sli4_t *, uint32_t, sli4_queue_t *[], uint32_t, uint32_t, uint32_t, uint32_t, uint16_t);
5550 extern uint32_t sli_fc_get_rpi_requirements(sli4_t *, uint32_t);
5551 extern int32_t sli_abort_wqe(sli4_t *, void *, size_t, sli4_abort_type_e, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t);
5553 extern int32_t sli_els_request64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint8_t, uint32_t, uint32_t, uint8_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *);
5554 extern int32_t sli_fcp_iread64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t);
5555 extern int32_t sli_fcp_iwrite64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t);
5556 extern int32_t sli_fcp_icmnd64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint8_t);
5558 extern int32_t sli_fcp_treceive64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint32_t, uint8_t, uint8_t, uint8_t, uint32_t);
5559 extern int32_t sli_fcp_trsp64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint32_t, uint8_t, uint8_t, uint32_t);
5560 extern int32_t sli_fcp_tsend64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint32_t, uint8_t, uint8_t, uint8_t, uint32_t);
5561 extern int32_t sli_fcp_cont_treceive64_wqe(sli4_t *, void*, size_t, ocs_dma_t *, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint32_t, uint8_t, uint8_t, uint8_t, uint32_t);
5562 extern int32_t sli_gen_request64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t,uint8_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t);
5563 extern int32_t sli_send_frame_wqe(sli4_t *sli4, void *buf, size_t size, uint8_t sof, uint8_t eof, uint32_t *hdr,
5564 ocs_dma_t *payload, uint32_t req_len, uint8_t timeout,
5565 uint16_t xri, uint16_t req_tag);
5566 extern int32_t sli_xmit_sequence64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint8_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t);
5567 extern int32_t sli_xmit_bcast64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint8_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t);
5568 extern int32_t sli_xmit_bls_rsp64_wqe(sli4_t *, void *, size_t, sli_bls_payload_t *, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint32_t);
5569 extern int32_t sli_xmit_els_rsp64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint32_t, uint32_t);
5570 extern int32_t sli_requeue_xri_wqe(sli4_t *, void *, size_t, uint16_t, uint16_t, uint16_t);
5571 extern void sli4_cmd_lowlevel_set_watchdog(sli4_t *sli4, void *buf, size_t size, uint16_t timeout);
5575 * @brief Retrieve the received header and payload length.
5577 * @param sli4 SLI context.
5578 * @param cqe Pointer to the CQ entry.
5579 * @param len_hdr Pointer where the header length is written.
5580 * @param len_data Pointer where the payload length is written.
5582 * @return Returns 0 on success, or a non-zero value on failure.
5584 static inline int32_t
5585 sli_fc_rqe_length(sli4_t *sli4, void *cqe, uint32_t *len_hdr, uint32_t *len_data)
5587 sli4_fc_async_rcqe_t *rcqe = cqe;
5589 *len_hdr = *len_data = 0;
5591 if (SLI4_FC_ASYNC_RQ_SUCCESS == rcqe->status) {
5592 *len_hdr = rcqe->header_data_placement_length;
5593 *len_data = rcqe->payload_data_placement_length;
5602 * @brief Retrieve the received FCFI.
5604 * @param sli4 SLI context.
5605 * @param cqe Pointer to the CQ entry.
5607 * @return Returns the FCFI in the CQE. or UINT8_MAX if invalid CQE code.
5609 static inline uint8_t
5610 sli_fc_rqe_fcfi(sli4_t *sli4, void *cqe)
5612 uint8_t code = ((uint8_t*)cqe)[SLI4_CQE_CODE_OFFSET];
5613 uint8_t fcfi = UINT8_MAX;
5616 case SLI4_CQE_CODE_RQ_ASYNC: {
5617 sli4_fc_async_rcqe_t *rcqe = cqe;
5621 case SLI4_CQE_CODE_RQ_ASYNC_V1: {
5622 sli4_fc_async_rcqe_v1_t *rcqev1 = cqe;
5623 fcfi = rcqev1->fcfi;
5626 case SLI4_CQE_CODE_OPTIMIZED_WRITE_CMD: {
5627 sli4_fc_optimized_write_cmd_cqe_t *opt_wr = cqe;
5628 fcfi = opt_wr->fcfi;
5636 extern const char *sli_fc_get_status_string(uint32_t status);
5638 #endif /* !_SLI4_H */