2 * Copyright (c) 2017 Broadcom. All rights reserved.
3 * The term "Broadcom" refers to Broadcom Limited and/or its subsidiaries.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
15 * 3. Neither the name of the copyright holder nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
36 * Define common SLI-4 structures and function prototypes.
44 #define SLI_PAGE_SIZE (4096)
45 #define SLI_SUB_PAGE_MASK (SLI_PAGE_SIZE - 1)
46 #define SLI_PAGE_SHIFT 12
47 #define SLI_ROUND_PAGE(b) (((b) + SLI_SUB_PAGE_MASK) & ~SLI_SUB_PAGE_MASK)
49 #define SLI4_BMBX_TIMEOUT_MSEC 30000
50 #define SLI4_FW_READY_TIMEOUT_MSEC 30000
52 static inline uint32_t
53 sli_page_count(size_t bytes, uint32_t page_size)
55 uint32_t mask = page_size - 1;
78 return (bytes + mask) >> shift;
81 /*************************************************************************
82 * Common PCI configuration space register definitions
85 #define SLI4_PCI_CLASS_REVISION 0x0008 /** register offset */
86 #define SLI4_PCI_REV_ID_SHIFT 0
87 #define SLI4_PCI_REV_ID_MASK 0xff
88 #define SLI4_PCI_CLASS_SHIFT 8
89 #define SLI4_PCI_CLASS_MASK 0xfff
91 #define SLI4_PCI_SOFT_RESET_CSR 0x005c /** register offset */
92 #define SLI4_PCI_SOFT_RESET_MASK 0x0080
94 /*************************************************************************
95 * Common SLI-4 register offsets and field definitions
99 * @brief SLI_INTF - SLI Interface Definition Register
101 #define SLI4_INTF_REG 0x0058 /** register offset */
102 #define SLI4_INTF_VALID_SHIFT 29
103 #define SLI4_INTF_VALID_MASK 0x7
104 #define SLI4_INTF_VALID 0x6
105 #define SLI4_INTF_IF_TYPE_SHIFT 12
106 #define SLI4_INTF_IF_TYPE_MASK 0xf
107 #define SLI4_INTF_SLI_FAMILY_SHIFT 8
108 #define SLI4_INTF_SLI_FAMILY_MASK 0xf
109 #define SLI4_INTF_SLI_REVISION_SHIFT 4
110 #define SLI4_INTF_SLI_REVISION_MASK 0xf
111 #define SLI4_FAMILY_CHECK_ASIC_TYPE 0xf
113 #define SLI4_IF_TYPE_BE3_SKH_PF 0
114 #define SLI4_IF_TYPE_BE3_SKH_VF 1
115 #define SLI4_IF_TYPE_LANCER_FC_ETH 2
116 #define SLI4_IF_TYPE_LANCER_RDMA 3
117 #define SLI4_MAX_IF_TYPES 4
120 * @brief ASIC_ID - SLI ASIC Type and Revision Register
122 #define SLI4_ASIC_ID_REG 0x009c /* register offset */
123 #define SLI4_ASIC_REV_SHIFT 0
124 #define SLI4_ASIC_REV_MASK 0xf
125 #define SLI4_ASIC_VER_SHIFT 4
126 #define SLI4_ASIC_VER_MASK 0xf
127 #define SLI4_ASIC_GEN_SHIFT 8
128 #define SLI4_ASIC_GEN_MASK 0xff
129 #define SLI4_ASIC_GEN_BE2 0x00
130 #define SLI4_ASIC_GEN_BE3 0x03
131 #define SLI4_ASIC_GEN_SKYHAWK 0x04
132 #define SLI4_ASIC_GEN_CORSAIR 0x05
133 #define SLI4_ASIC_GEN_LANCER 0x0b
137 * @brief BMBX - Bootstrap Mailbox Register
139 #define SLI4_BMBX_REG 0x0160 /* register offset */
140 #define SLI4_BMBX_MASK_HI 0x3
141 #define SLI4_BMBX_MASK_LO 0xf
142 #define SLI4_BMBX_RDY BIT(0)
143 #define SLI4_BMBX_HI BIT(1)
144 #define SLI4_BMBX_WRITE_HI(r) ((ocs_addr32_hi(r) & ~SLI4_BMBX_MASK_HI) | \
146 #define SLI4_BMBX_WRITE_LO(r) (((ocs_addr32_hi(r) & SLI4_BMBX_MASK_HI) << 30) | \
147 (((r) & ~SLI4_BMBX_MASK_LO) >> 2))
149 #define SLI4_BMBX_SIZE 256
153 * @brief EQCQ_DOORBELL - EQ and CQ Doorbell Register
155 #define SLI4_EQCQ_DOORBELL_REG 0x120
156 #define SLI4_EQCQ_DOORBELL_CI BIT(9)
157 #define SLI4_EQCQ_DOORBELL_QT BIT(10)
158 #define SLI4_EQCQ_DOORBELL_ARM BIT(29)
159 #define SLI4_EQCQ_DOORBELL_SE BIT(31)
160 #define SLI4_EQCQ_NUM_SHIFT 16
161 #define SLI4_EQCQ_NUM_MASK 0x01ff
162 #define SLI4_EQCQ_EQ_ID_MASK 0x3fff
163 #define SLI4_EQCQ_CQ_ID_MASK 0x7fff
164 #define SLI4_EQCQ_EQ_ID_MASK_LO 0x01ff
165 #define SLI4_EQCQ_CQ_ID_MASK_LO 0x03ff
166 #define SLI4_EQCQ_EQCQ_ID_MASK_HI 0xf800
169 * @brief SLIPORT_CONTROL - SLI Port Control Register
171 #define SLI4_SLIPORT_CONTROL_REG 0x0408
172 #define SLI4_SLIPORT_CONTROL_END BIT(30)
173 #define SLI4_SLIPORT_CONTROL_LITTLE_ENDIAN (0)
174 #define SLI4_SLIPORT_CONTROL_BIG_ENDIAN BIT(30)
175 #define SLI4_SLIPORT_CONTROL_IP BIT(27)
176 #define SLI4_SLIPORT_CONTROL_IDIS BIT(22)
177 #define SLI4_SLIPORT_CONTROL_FDD BIT(31)
180 * @brief SLI4_SLIPORT_ERROR1 - SLI Port Error Register
182 #define SLI4_SLIPORT_ERROR1 0x040c
185 * @brief SLI4_SLIPORT_ERROR2 - SLI Port Error Register
187 #define SLI4_SLIPORT_ERROR2 0x0410
190 * @brief User error registers
192 #define SLI4_UERR_STATUS_LOW_REG 0xA0
193 #define SLI4_UERR_STATUS_HIGH_REG 0xA4
194 #define SLI4_UERR_MASK_LOW_REG 0xA8
195 #define SLI4_UERR_MASK_HIGH_REG 0xAC
198 * @brief Registers for generating software UE (BE3)
200 #define SLI4_SW_UE_CSR1 0x138
201 #define SLI4_SW_UE_CSR2 0x1FFFC
204 * @brief Registers for generating software UE (Skyhawk)
206 #define SLI4_SW_UE_REG 0x5C /* register offset */
208 static inline uint32_t sli_eq_doorbell(uint16_t n_popped, uint16_t id, uint8_t arm)
211 #if BYTE_ORDER == LITTLE_ENDIAN
214 ci:1, /* clear interrupt */
215 qt:1, /* queue type */
221 } * eq_doorbell = (void *)®
223 #error big endian version not defined
226 eq_doorbell->eq_id_lo = id & SLI4_EQCQ_EQ_ID_MASK_LO;
227 eq_doorbell->qt = 1; /* EQ is type 1 (section 2.2.3.3 SLI Arch) */
228 eq_doorbell->eq_id_hi = (id >> 9) & 0x1f;
229 eq_doorbell->number_popped = n_popped;
230 eq_doorbell->arm = arm;
231 eq_doorbell->ci = TRUE;
236 static inline uint32_t sli_cq_doorbell(uint16_t n_popped, uint16_t id, uint8_t arm)
239 #if BYTE_ORDER == LITTLE_ENDIAN
241 uint32_t cq_id_lo:10,
242 qt:1, /* queue type */
248 } * cq_doorbell = (void *)®
250 #error big endian version not defined
253 cq_doorbell->cq_id_lo = id & SLI4_EQCQ_CQ_ID_MASK_LO;
254 cq_doorbell->qt = 0; /* CQ is type 0 (section 2.2.3.3 SLI Arch) */
255 cq_doorbell->cq_id_hi = (id >> 10) & 0x1f;
256 cq_doorbell->number_popped = n_popped;
257 cq_doorbell->arm = arm;
263 * @brief MQ_DOORBELL - MQ Doorbell Register
265 #define SLI4_MQ_DOORBELL_REG 0x0140 /* register offset */
266 #define SLI4_MQ_DOORBELL_NUM_SHIFT 16
267 #define SLI4_MQ_DOORBELL_NUM_MASK 0x3fff
268 #define SLI4_MQ_DOORBELL_ID_MASK 0xffff
269 #define SLI4_MQ_DOORBELL(n, i) ((((n) & SLI4_MQ_DOORBELL_NUM_MASK) << SLI4_MQ_DOORBELL_NUM_SHIFT) | \
270 ((i) & SLI4_MQ_DOORBELL_ID_MASK))
273 * @brief RQ_DOORBELL - RQ Doorbell Register
275 #define SLI4_RQ_DOORBELL_REG 0x0a0 /* register offset */
276 #define SLI4_RQ_DOORBELL_NUM_SHIFT 16
277 #define SLI4_RQ_DOORBELL_NUM_MASK 0x3fff
278 #define SLI4_RQ_DOORBELL_ID_MASK 0xffff
279 #define SLI4_RQ_DOORBELL(n, i) ((((n) & SLI4_RQ_DOORBELL_NUM_MASK) << SLI4_RQ_DOORBELL_NUM_SHIFT) | \
280 ((i) & SLI4_RQ_DOORBELL_ID_MASK))
283 * @brief WQ_DOORBELL - WQ Doorbell Register
285 #define SLI4_IO_WQ_DOORBELL_REG 0x040 /* register offset */
286 #define SLI4_WQ_DOORBELL_IDX_SHIFT 16
287 #define SLI4_WQ_DOORBELL_IDX_MASK 0x00ff
288 #define SLI4_WQ_DOORBELL_NUM_SHIFT 24
289 #define SLI4_WQ_DOORBELL_NUM_MASK 0x00ff
290 #define SLI4_WQ_DOORBELL_ID_MASK 0xffff
291 #define SLI4_WQ_DOORBELL(n, x, i) ((((n) & SLI4_WQ_DOORBELL_NUM_MASK) << SLI4_WQ_DOORBELL_NUM_SHIFT) | \
292 (((x) & SLI4_WQ_DOORBELL_IDX_MASK) << SLI4_WQ_DOORBELL_IDX_SHIFT) | \
293 ((i) & SLI4_WQ_DOORBELL_ID_MASK))
296 * @brief SLIPORT_SEMAPHORE - SLI Port Host and Port Status Register
298 #define SLI4_PORT_SEMAPHORE_REG_0 0x00ac /** register offset Interface Type 0 + 1 */
299 #define SLI4_PORT_SEMAPHORE_REG_1 0x0180 /** register offset Interface Type 0 + 1 */
300 #define SLI4_PORT_SEMAPHORE_REG_23 0x0400 /** register offset Interface Type 2 + 3 */
301 #define SLI4_PORT_SEMAPHORE_PORT_MASK 0x0000ffff
302 #define SLI4_PORT_SEMAPHORE_PORT(r) ((r) & SLI4_PORT_SEMAPHORE_PORT_MASK)
303 #define SLI4_PORT_SEMAPHORE_HOST_MASK 0x00ff0000
304 #define SLI4_PORT_SEMAPHORE_HOST_SHIFT 16
305 #define SLI4_PORT_SEMAPHORE_HOST(r) (((r) & SLI4_PORT_SEMAPHORE_HOST_MASK) >> \
306 SLI4_PORT_SEMAPHORE_HOST_SHIFT)
307 #define SLI4_PORT_SEMAPHORE_SCR2 BIT(26) /** scratch area 2 */
308 #define SLI4_PORT_SEMAPHORE_SCR1 BIT(27) /** scratch area 1 */
309 #define SLI4_PORT_SEMAPHORE_IPC BIT(28) /** IP conflict */
310 #define SLI4_PORT_SEMAPHORE_NIP BIT(29) /** no IP address */
311 #define SLI4_PORT_SEMAPHORE_SFI BIT(30) /** secondary firmware image used */
312 #define SLI4_PORT_SEMAPHORE_PERR BIT(31) /** POST fatal error */
314 #define SLI4_PORT_SEMAPHORE_STATUS_POST_READY 0xc000
315 #define SLI4_PORT_SEMAPHORE_STATUS_UNRECOV_ERR 0xf000
316 #define SLI4_PORT_SEMAPHORE_STATUS_ERR_MASK 0xf000
317 #define SLI4_PORT_SEMAPHORE_IN_ERR(r) (SLI4_PORT_SEMAPHORE_STATUS_UNRECOV_ERR == ((r) & \
318 SLI4_PORT_SEMAPHORE_STATUS_ERR_MASK))
321 * @brief SLIPORT_STATUS - SLI Port Status Register
324 #define SLI4_PORT_STATUS_REG_23 0x0404 /** register offset Interface Type 2 + 3 */
325 #define SLI4_PORT_STATUS_FDP BIT(21) /** function specific dump present */
326 #define SLI4_PORT_STATUS_RDY BIT(23) /** ready */
327 #define SLI4_PORT_STATUS_RN BIT(24) /** reset needed */
328 #define SLI4_PORT_STATUS_DIP BIT(25) /** dump present */
329 #define SLI4_PORT_STATUS_OTI BIT(29) /** over temp indicator */
330 #define SLI4_PORT_STATUS_END BIT(30) /** endianness */
331 #define SLI4_PORT_STATUS_ERR BIT(31) /** SLI port error */
332 #define SLI4_PORT_STATUS_READY(r) ((r) & SLI4_PORT_STATUS_RDY)
333 #define SLI4_PORT_STATUS_ERROR(r) ((r) & SLI4_PORT_STATUS_ERR)
334 #define SLI4_PORT_STATUS_DUMP_PRESENT(r) ((r) & SLI4_PORT_STATUS_DIP)
335 #define SLI4_PORT_STATUS_FDP_PRESENT(r) ((r) & SLI4_PORT_STATUS_FDP)
338 #define SLI4_PHSDEV_CONTROL_REG_23 0x0414 /** register offset Interface Type 2 + 3 */
339 #define SLI4_PHYDEV_CONTROL_DRST BIT(0) /** physical device reset */
340 #define SLI4_PHYDEV_CONTROL_FRST BIT(1) /** firmware reset */
341 #define SLI4_PHYDEV_CONTROL_DD BIT(2) /** diagnostic dump */
342 #define SLI4_PHYDEV_CONTROL_FRL_MASK 0x000000f0
343 #define SLI4_PHYDEV_CONTROL_FRL_SHIFT 4
344 #define SLI4_PHYDEV_CONTROL_FRL(r) (((r) & SLI4_PHYDEV_CONTROL_FRL_MASK) >> \
345 SLI4_PHYDEV_CONTROL_FRL_SHIFT_SHIFT)
347 /*************************************************************************
348 * SLI-4 mailbox command formats and definitions
351 typedef struct sli4_mbox_command_header_s {
352 #if BYTE_ORDER == LITTLE_ENDIAN
355 status:16; /** Port writes to indicate success / fail */
357 #error big endian version not defined
359 } sli4_mbox_command_header_t;
361 #define SLI4_MBOX_COMMAND_CONFIG_LINK 0x07
362 #define SLI4_MBOX_COMMAND_DUMP 0x17
363 #define SLI4_MBOX_COMMAND_DOWN_LINK 0x06
364 #define SLI4_MBOX_COMMAND_INIT_LINK 0x05
365 #define SLI4_MBOX_COMMAND_INIT_VFI 0xa3
366 #define SLI4_MBOX_COMMAND_INIT_VPI 0xa4
367 #define SLI4_MBOX_COMMAND_POST_XRI 0xa7
368 #define SLI4_MBOX_COMMAND_RELEASE_XRI 0xac
369 #define SLI4_MBOX_COMMAND_READ_CONFIG 0x0b
370 #define SLI4_MBOX_COMMAND_READ_STATUS 0x0e
371 #define SLI4_MBOX_COMMAND_READ_NVPARMS 0x02
372 #define SLI4_MBOX_COMMAND_READ_REV 0x11
373 #define SLI4_MBOX_COMMAND_READ_LNK_STAT 0x12
374 #define SLI4_MBOX_COMMAND_READ_SPARM64 0x8d
375 #define SLI4_MBOX_COMMAND_READ_TOPOLOGY 0x95
376 #define SLI4_MBOX_COMMAND_REG_FCFI 0xa0
377 #define SLI4_MBOX_COMMAND_REG_FCFI_MRQ 0xaf
378 #define SLI4_MBOX_COMMAND_REG_RPI 0x93
379 #define SLI4_MBOX_COMMAND_REG_RX_RQ 0xa6
380 #define SLI4_MBOX_COMMAND_REG_VFI 0x9f
381 #define SLI4_MBOX_COMMAND_REG_VPI 0x96
382 #define SLI4_MBOX_COMMAND_REQUEST_FEATURES 0x9d
383 #define SLI4_MBOX_COMMAND_SLI_CONFIG 0x9b
384 #define SLI4_MBOX_COMMAND_UNREG_FCFI 0xa2
385 #define SLI4_MBOX_COMMAND_UNREG_RPI 0x14
386 #define SLI4_MBOX_COMMAND_UNREG_VFI 0xa1
387 #define SLI4_MBOX_COMMAND_UNREG_VPI 0x97
388 #define SLI4_MBOX_COMMAND_WRITE_NVPARMS 0x03
389 #define SLI4_MBOX_COMMAND_CONFIG_AUTO_XFER_RDY 0xAD
390 #define SLI4_MBOX_COMMAND_CONFIG_AUTO_XFER_RDY_HP 0xAE
392 #define SLI4_MBOX_STATUS_SUCCESS 0x0000
393 #define SLI4_MBOX_STATUS_FAILURE 0x0001
394 #define SLI4_MBOX_STATUS_RPI_NOT_REG 0x1400
397 * @brief Buffer Descriptor Entry (BDE)
399 typedef struct sli4_bde_s {
400 #if BYTE_ORDER == LITTLE_ENDIAN
401 uint32_t buffer_length:24,
405 uint32_t buffer_address_low;
406 uint32_t buffer_address_high;
413 uint32_t sgl_segment_address_low;
414 uint32_t sgl_segment_address_high;
418 #error big endian version not defined
422 #define SLI4_BDE_TYPE_BDE_64 0x00 /** Generic 64-bit data */
423 #define SLI4_BDE_TYPE_BDE_IMM 0x01 /** Immediate data */
424 #define SLI4_BDE_TYPE_BLP 0x40 /** Buffer List Pointer */
427 * @brief Scatter-Gather Entry (SGE)
429 typedef struct sli4_sge_s {
430 #if BYTE_ORDER == LITTLE_ENDIAN
431 uint32_t buffer_address_high;
432 uint32_t buffer_address_low;
433 uint32_t data_offset:27,
436 uint32_t buffer_length;
438 #error big endian version not defined
443 * @brief T10 DIF Scatter-Gather Entry (SGE)
445 typedef struct sli4_dif_sge_s {
446 #if BYTE_ORDER == LITTLE_ENDIAN
447 uint32_t buffer_address_high;
448 uint32_t buffer_address_low;
454 #error big endian version not defined
459 * @brief T10 DIF Seed Scatter-Gather Entry (SGE)
461 typedef struct sli4_diseed_sge_s {
462 #if BYTE_ORDER == LITTLE_ENDIAN
463 uint32_t ref_tag_cmp;
464 uint32_t ref_tag_repl;
465 uint32_t app_tag_repl:16,
478 uint32_t app_tag_cmp:16,
488 #error big endian version not defined
493 * @brief List Segment Pointer Scatter-Gather Entry (SGE)
495 typedef struct sli4_lsp_sge_s {
496 #if BYTE_ORDER == LITTLE_ENDIAN
497 uint32_t buffer_address_high;
498 uint32_t buffer_address_low;
502 uint32_t segment_length:24,
505 #error big endian version not defined
509 #define SLI4_SGE_MAX_RESERVED 3
511 #define SLI4_SGE_DIF_OP_IN_NODIF_OUT_CRC 0x00
512 #define SLI4_SGE_DIF_OP_IN_CRC_OUT_NODIF 0x01
513 #define SLI4_SGE_DIF_OP_IN_NODIF_OUT_CHKSUM 0x02
514 #define SLI4_SGE_DIF_OP_IN_CHKSUM_OUT_NODIF 0x03
515 #define SLI4_SGE_DIF_OP_IN_CRC_OUT_CRC 0x04
516 #define SLI4_SGE_DIF_OP_IN_CHKSUM_OUT_CHKSUM 0x05
517 #define SLI4_SGE_DIF_OP_IN_CRC_OUT_CHKSUM 0x06
518 #define SLI4_SGE_DIF_OP_IN_CHKSUM_OUT_CRC 0x07
519 #define SLI4_SGE_DIF_OP_IN_RAW_OUT_RAW 0x08
521 #define SLI4_SGE_TYPE_DATA 0x00
522 #define SLI4_SGE_TYPE_CHAIN 0x03 /** Skyhawk only */
523 #define SLI4_SGE_TYPE_DIF 0x04 /** Data Integrity Field */
524 #define SLI4_SGE_TYPE_LSP 0x05 /** List Segment Pointer */
525 #define SLI4_SGE_TYPE_PEDIF 0x06 /** Post Encryption Engine DIF */
526 #define SLI4_SGE_TYPE_PESEED 0x07 /** Post Encryption Engine DIF Seed */
527 #define SLI4_SGE_TYPE_DISEED 0x08 /** DIF Seed */
528 #define SLI4_SGE_TYPE_ENC 0x09 /** Encryption */
529 #define SLI4_SGE_TYPE_ATM 0x0a /** DIF Application Tag Mask */
530 #define SLI4_SGE_TYPE_SKIP 0x0c /** SKIP */
532 #define OCS_MAX_SGE_SIZE 0x80000000 /* Maximum data allowed in a SGE */
537 typedef struct sli4_cmd_config_link_s {
538 sli4_mbox_command_header_t hdr;
539 #if BYTE_ORDER == LITTLE_ENDIAN
540 uint32_t maxbbc:8, /** Max buffer-to-buffer credit */
553 bbscn:4, /** buffer-to-buffer state change number */
554 cscn:1, /** configure BBSCN */
557 #error big endian version not defined
559 } sli4_cmd_config_link_t;
564 #define SLI4_WKI_TAG_SAT_TEM 0x1040
565 typedef struct sli4_cmd_dump4_s {
566 sli4_mbox_command_header_t hdr;
567 #if BYTE_ORDER == LITTLE_ENDIAN
570 uint32_t wki_selection:16,
573 uint32_t returned_byte_cnt;
574 uint32_t resp_data[59];
576 #error big endian version not defined
581 * @brief FW_INITIALIZE - initialize a SLI port
583 * @note This command uses a different format than all others.
586 extern const uint8_t sli4_fw_initialize[8];
589 * @brief FW_DEINITIALIZE - deinitialize a SLI port
591 * @note This command uses a different format than all others.
594 extern const uint8_t sli4_fw_deinitialize[8];
597 * @brief INIT_LINK - initialize the link for a FC/FCoE port
599 typedef struct sli4_cmd_init_link_flags_s {
602 #define FC_TOPOLOGY_FCAL 0
603 #define FC_TOPOLOGY_P2P 1
607 gen_loop_validity_check:1,
609 enable_topology_failover:1,
612 select_hightest_al_pa:1,
613 :16; /* pad to 32 bits */
614 } sli4_cmd_init_link_flags_t;
616 #define SLI4_INIT_LINK_F_LOOP_BACK BIT(0)
617 #define SLI4_INIT_LINK_F_UNFAIR BIT(6)
618 #define SLI4_INIT_LINK_F_NO_LIRP BIT(7)
619 #define SLI4_INIT_LINK_F_LOOP_VALID_CHK BIT(8)
620 #define SLI4_INIT_LINK_F_NO_LISA BIT(9)
621 #define SLI4_INIT_LINK_F_FAIL_OVER BIT(10)
622 #define SLI4_INIT_LINK_F_NO_AUTOSPEED BIT(11)
623 #define SLI4_INIT_LINK_F_PICK_HI_ALPA BIT(15)
625 #define SLI4_INIT_LINK_F_P2P_ONLY 1
626 #define SLI4_INIT_LINK_F_FCAL_ONLY 2
628 #define SLI4_INIT_LINK_F_FCAL_FAIL_OVER 0
629 #define SLI4_INIT_LINK_F_P2P_FAIL_OVER 1
631 typedef struct sli4_cmd_init_link_s {
632 sli4_mbox_command_header_t hdr;
633 #if BYTE_ORDER == LITTLE_ENDIAN
634 uint32_t selective_reset_al_pa:8,
636 sli4_cmd_init_link_flags_t link_flags;
637 uint32_t link_speed_selection_code;
638 #define FC_LINK_SPEED_1G 1
639 #define FC_LINK_SPEED_2G 2
640 #define FC_LINK_SPEED_AUTO_1_2 3
641 #define FC_LINK_SPEED_4G 4
642 #define FC_LINK_SPEED_AUTO_4_1 5
643 #define FC_LINK_SPEED_AUTO_4_2 6
644 #define FC_LINK_SPEED_AUTO_4_2_1 7
645 #define FC_LINK_SPEED_8G 8
646 #define FC_LINK_SPEED_AUTO_8_1 9
647 #define FC_LINK_SPEED_AUTO_8_2 10
648 #define FC_LINK_SPEED_AUTO_8_2_1 11
649 #define FC_LINK_SPEED_AUTO_8_4 12
650 #define FC_LINK_SPEED_AUTO_8_4_1 13
651 #define FC_LINK_SPEED_AUTO_8_4_2 14
652 #define FC_LINK_SPEED_10G 16
653 #define FC_LINK_SPEED_16G 17
654 #define FC_LINK_SPEED_AUTO_16_8_4 18
655 #define FC_LINK_SPEED_AUTO_16_8 19
656 #define FC_LINK_SPEED_32G 20
657 #define FC_LINK_SPEED_AUTO_32_16_8 21
658 #define FC_LINK_SPEED_AUTO_32_16 22
660 #error big endian version not defined
662 } sli4_cmd_init_link_t;
665 * @brief INIT_VFI - initialize the VFI resource
667 typedef struct sli4_cmd_init_vfi_s {
668 sli4_mbox_command_header_t hdr;
669 #if BYTE_ORDER == LITTLE_ENDIAN
684 #error big endian version not defined
686 } sli4_cmd_init_vfi_t;
689 * @brief INIT_VPI - initialize the VPI resource
691 typedef struct sli4_cmd_init_vpi_s {
692 sli4_mbox_command_header_t hdr;
693 #if BYTE_ORDER == LITTLE_ENDIAN
697 #error big endian version not defined
699 } sli4_cmd_init_vpi_t;
702 * @brief POST_XRI - post XRI resources to the SLI Port
704 typedef struct sli4_cmd_post_xri_s {
705 sli4_mbox_command_header_t hdr;
706 #if BYTE_ORDER == LITTLE_ENDIAN
707 uint32_t xri_base:16,
714 #error big endian version not defined
716 } sli4_cmd_post_xri_t;
719 * @brief RELEASE_XRI - Release XRI resources from the SLI Port
721 typedef struct sli4_cmd_release_xri_s {
722 sli4_mbox_command_header_t hdr;
723 #if BYTE_ORDER == LITTLE_ENDIAN
724 uint32_t released_xri_count:5,
729 uint32_t xri_tag0:16,
733 #error big endian version not defined
735 } sli4_cmd_release_xri_t;
738 * @brief READ_CONFIG - read SLI port configuration parameters
740 typedef struct sli4_cmd_read_config_s {
741 sli4_mbox_command_header_t hdr;
742 } sli4_cmd_read_config_t;
744 typedef struct sli4_res_read_config_s {
745 sli4_mbox_command_header_t hdr;
746 #if BYTE_ORDER == LITTLE_ENDIAN
748 ext:1; /** Resource Extents */
759 uint32_t lmt:16, /** Link Module Type */
763 uint32_t xri_base:16,
765 uint32_t rpi_base:16,
767 uint32_t vpi_base:16,
769 uint32_t vfi_base:16,
773 uint32_t rq_count:16,
775 uint32_t wq_count:16,
779 #error big endian version not defined
781 } sli4_res_read_config_t;
783 #define SLI4_READ_CFG_TOPO_FCOE 0x0 /** FCoE topology */
784 #define SLI4_READ_CFG_TOPO_FC 0x1 /** FC topology unknown */
785 #define SLI4_READ_CFG_TOPO_FC_DA 0x2 /** FC Direct Attach (non FC-AL) topology */
786 #define SLI4_READ_CFG_TOPO_FC_AL 0x3 /** FC-AL topology */
789 * @brief READ_NVPARMS - read SLI port configuration parameters
791 typedef struct sli4_cmd_read_nvparms_s {
792 sli4_mbox_command_header_t hdr;
793 #if BYTE_ORDER == LITTLE_ENDIAN
800 uint32_t hard_alpa:8,
803 #error big endian version not defined
805 } sli4_cmd_read_nvparms_t;
808 * @brief WRITE_NVPARMS - write SLI port configuration parameters
810 typedef struct sli4_cmd_write_nvparms_s {
811 sli4_mbox_command_header_t hdr;
812 #if BYTE_ORDER == LITTLE_ENDIAN
819 uint32_t hard_alpa:8,
822 #error big endian version not defined
824 } sli4_cmd_write_nvparms_t;
827 * @brief READ_REV - read the Port revision levels
829 typedef struct sli4_cmd_read_rev_s {
830 sli4_mbox_command_header_t hdr;
831 #if BYTE_ORDER == LITTLE_ENDIAN
839 uint32_t first_hw_revision;
840 uint32_t second_hw_revision;
842 uint32_t third_hw_revision;
843 uint32_t fc_ph_low:8,
846 feature_level_high:8;
848 uint32_t first_fw_id;
849 char first_fw_name[16];
850 uint32_t second_fw_id;
851 char second_fw_name[16];
853 uint32_t available_length:24,
855 uint32_t physical_address_low;
856 uint32_t physical_address_high;
857 uint32_t returned_vpd_length;
858 uint32_t actual_vpd_length;
860 #error big endian version not defined
862 } sli4_cmd_read_rev_t;
865 * @brief READ_SPARM64 - read the Port service parameters
867 typedef struct sli4_cmd_read_sparm64_s {
868 sli4_mbox_command_header_t hdr;
869 #if BYTE_ORDER == LITTLE_ENDIAN
875 uint32_t port_name_start:16,
877 uint32_t node_name_start:16,
880 #error big endian version not defined
882 } sli4_cmd_read_sparm64_t;
884 #define SLI4_READ_SPARM64_VPI_DEFAULT 0
885 #define SLI4_READ_SPARM64_VPI_SPECIAL UINT16_MAX
887 #define SLI4_READ_SPARM64_WWPN_OFFSET (4 * sizeof(uint32_t))
888 #define SLI4_READ_SPARM64_WWNN_OFFSET (SLI4_READ_SPARM64_WWPN_OFFSET + sizeof(uint64_t))
890 typedef struct sli4_port_state_s {
891 #if BYTE_ORDER == LITTLE_ENDIAN
892 uint32_t nx_port_recv_state:2,
893 nx_port_trans_state:2,
894 nx_port_state_machine:4,
900 #error big endian version not defined
905 * @brief READ_TOPOLOGY - read the link event information
907 typedef struct sli4_cmd_read_topology_s {
908 sli4_mbox_command_header_t hdr;
909 #if BYTE_ORDER == LITTLE_ENDIAN
911 uint32_t attention_type:8,
919 sli4_bde_t bde_loop_map;
920 sli4_port_state_t link_down;
921 sli4_port_state_t link_current;
931 uint32_t acquired_al_pa:8,
935 uint32_t initial_n_port_id:24,
938 #error big endian version not defined
940 } sli4_cmd_read_topology_t;
942 #define SLI4_MIN_LOOP_MAP_BYTES 128
944 #define SLI4_READ_TOPOLOGY_LINK_UP 0x1
945 #define SLI4_READ_TOPOLOGY_LINK_DOWN 0x2
946 #define SLI4_READ_TOPOLOGY_LINK_NO_ALPA 0x3
948 #define SLI4_READ_TOPOLOGY_UNKNOWN 0x0
949 #define SLI4_READ_TOPOLOGY_NPORT 0x1
950 #define SLI4_READ_TOPOLOGY_FC_AL 0x2
952 #define SLI4_READ_TOPOLOGY_SPEED_NONE 0x00
953 #define SLI4_READ_TOPOLOGY_SPEED_1G 0x04
954 #define SLI4_READ_TOPOLOGY_SPEED_2G 0x08
955 #define SLI4_READ_TOPOLOGY_SPEED_4G 0x10
956 #define SLI4_READ_TOPOLOGY_SPEED_8G 0x20
957 #define SLI4_READ_TOPOLOGY_SPEED_10G 0x40
958 #define SLI4_READ_TOPOLOGY_SPEED_16G 0x80
959 #define SLI4_READ_TOPOLOGY_SPEED_32G 0x90
962 * @brief REG_FCFI - activate a FC Forwarder
964 #define SLI4_CMD_REG_FCFI_NUM_RQ_CFG 4
965 typedef struct sli4_cmd_reg_fcfi_s {
966 sli4_mbox_command_header_t hdr;
967 #if BYTE_ORDER == LITTLE_ENDIAN
968 uint32_t fcf_index:16,
975 uint32_t r_ctl_mask:8,
979 } rq_cfg[SLI4_CMD_REG_FCFI_NUM_RQ_CFG];
980 uint32_t vlan_tag:12,
984 #error big endian version not defined
986 } sli4_cmd_reg_fcfi_t;
988 #define SLI4_CMD_REG_FCFI_MRQ_NUM_RQ_CFG 4
989 #define SLI4_CMD_REG_FCFI_MRQ_MAX_NUM_RQ 32
990 #define SLI4_CMD_REG_FCFI_SET_FCFI_MODE 0
991 #define SLI4_CMD_REG_FCFI_SET_MRQ_MODE 1
993 typedef struct sli4_cmd_reg_fcfi_mrq_s {
994 sli4_mbox_command_header_t hdr;
995 #if BYTE_ORDER == LITTLE_ENDIAN
996 uint32_t fcf_index:16,
1002 uint32_t rq_id_3:16,
1006 uint32_t r_ctl_mask:8,
1010 } rq_cfg[SLI4_CMD_REG_FCFI_MRQ_NUM_RQ_CFG];
1012 uint32_t vlan_tag:12,
1017 uint32_t num_mrq_pairs:8,
1018 mrq_filter_bitmask:4,
1019 rq_selection_policy:4,
1022 } sli4_cmd_reg_fcfi_mrq_t;
1025 * @brief REG_RPI - register a Remote Port Indicator
1027 typedef struct sli4_cmd_reg_rpi_s {
1028 sli4_mbox_command_header_t hdr;
1029 #if BYTE_ORDER == LITTLE_ENDIAN
1032 uint32_t remote_n_port_id:24,
1044 #error big endian version not defined
1046 } sli4_cmd_reg_rpi_t;
1047 #define SLI4_REG_RPI_BUF_LEN 0x70
1051 * @brief REG_VFI - register a Virtual Fabric Indicator
1053 typedef struct sli4_cmd_reg_vfi_s {
1054 sli4_mbox_command_header_t hdr;
1055 #if BYTE_ORDER == LITTLE_ENDIAN
1062 vpi:16; /* vp=TRUE */
1063 uint8_t wwpn[8]; /* vp=TRUE */
1064 sli4_bde_t sparm; /* either FLOGI or PLOGI */
1067 uint32_t local_n_port_id:24, /* vp=TRUE */
1070 #error big endian version not defined
1072 } sli4_cmd_reg_vfi_t;
1075 * @brief REG_VPI - register a Virtual Port Indicator
1077 typedef struct sli4_cmd_reg_vpi_s {
1078 sli4_mbox_command_header_t hdr;
1079 #if BYTE_ORDER == LITTLE_ENDIAN
1081 uint32_t local_n_port_id:24,
1089 #error big endian version not defined
1091 } sli4_cmd_reg_vpi_t;
1094 * @brief REQUEST_FEATURES - request / query SLI features
1097 #if BYTE_ORDER == LITTLE_ENDIAN
1099 uint32_t iaab:1, /** inhibit auto-ABTS originator */
1100 npiv:1, /** NPIV support */
1101 dif:1, /** DIF/DIX support */
1102 vf:1, /** virtual fabric support */
1103 fcpi:1, /** FCP initiator support */
1104 fcpt:1, /** FCP target support */
1105 fcpc:1, /** combined FCP initiator/target */
1107 rqd:1, /** recovery qualified delay */
1108 iaar:1, /** inhibit auto-ABTS responder */
1109 hlm:1, /** High Login Mode */
1110 perfh:1, /** performance hints */
1111 rxseq:1, /** RX Sequence Coalescing */
1112 rxri:1, /** Release XRI variant of Coalescing */
1113 dcl2:1, /** Disable Class 2 */
1114 rsco:1, /** Receive Sequence Coalescing Optimizations */
1115 mrqp:1, /** Multi RQ Pair Mode Support */
1120 #error big endian version not defined
1124 typedef struct sli4_cmd_request_features_s {
1125 sli4_mbox_command_header_t hdr;
1126 #if BYTE_ORDER == LITTLE_ENDIAN
1130 #error big endian version not defined
1132 sli4_features_t command;
1133 sli4_features_t response;
1134 } sli4_cmd_request_features_t;
1137 * @brief SLI_CONFIG - submit a configuration command to Port
1139 * Command is either embedded as part of the payload (embed) or located
1140 * in a separate memory buffer (mem)
1144 typedef struct sli4_sli_config_pmd_s {
1145 uint32_t address_low;
1146 uint32_t address_high;
1149 } sli4_sli_config_pmd_t;
1151 typedef struct sli4_cmd_sli_config_s {
1152 sli4_mbox_command_header_t hdr;
1153 #if BYTE_ORDER == LITTLE_ENDIAN
1158 uint32_t payload_length;
1163 uint8_t embed[58 * sizeof(uint32_t)];
1164 sli4_sli_config_pmd_t mem;
1167 #error big endian version not defined
1169 } sli4_cmd_sli_config_t;
1172 * @brief READ_STATUS - read tx/rx status of a particular port
1176 typedef struct sli4_cmd_read_status_s {
1177 sli4_mbox_command_header_t hdr;
1178 #if BYTE_ORDER == LITTLE_ENDIAN
1182 uint32_t transmit_kbyte_count;
1183 uint32_t receive_kbyte_count;
1184 uint32_t transmit_frame_count;
1185 uint32_t receive_frame_count;
1186 uint32_t transmit_sequence_count;
1187 uint32_t receive_sequence_count;
1188 uint32_t total_exchanges_originator;
1189 uint32_t total_exchanges_responder;
1190 uint32_t receive_p_bsy_count;
1191 uint32_t receive_f_bsy_count;
1192 uint32_t dropped_frames_due_to_no_rq_buffer_count;
1193 uint32_t empty_rq_timeout_count;
1194 uint32_t dropped_frames_due_to_no_xri_count;
1195 uint32_t empty_xri_pool_count;
1198 #error big endian version not defined
1200 } sli4_cmd_read_status_t;
1203 * @brief READ_LNK_STAT - read link status of a particular port
1207 typedef struct sli4_cmd_read_link_stats_s {
1208 sli4_mbox_command_header_t hdr;
1209 #if BYTE_ORDER == LITTLE_ENDIAN
1235 uint32_t link_failure_error_count;
1236 uint32_t loss_of_sync_error_count;
1237 uint32_t loss_of_signal_error_count;
1238 uint32_t primitive_sequence_error_count;
1239 uint32_t invalid_transmission_word_error_count;
1240 uint32_t crc_error_count;
1241 uint32_t primitive_sequence_event_timeout_count;
1242 uint32_t elastic_buffer_overrun_error_count;
1243 uint32_t arbitration_fc_al_timout_count;
1244 uint32_t advertised_receive_bufftor_to_buffer_credit;
1245 uint32_t current_receive_buffer_to_buffer_credit;
1246 uint32_t advertised_transmit_buffer_to_buffer_credit;
1247 uint32_t current_transmit_buffer_to_buffer_credit;
1248 uint32_t received_eofa_count;
1249 uint32_t received_eofdti_count;
1250 uint32_t received_eofni_count;
1251 uint32_t received_soff_count;
1252 uint32_t received_dropped_no_aer_count;
1253 uint32_t received_dropped_no_available_rpi_resources_count;
1254 uint32_t received_dropped_no_available_xri_resources_count;
1257 #error big endian version not defined
1259 } sli4_cmd_read_link_stats_t;
1262 * @brief Format a WQE with WQ_ID Association performance hint
1265 * PHWQ works by over-writing part of Word 10 in the WQE with the WQ ID.
1267 * @param entry Pointer to the WQE.
1268 * @param q_id Queue ID.
1273 sli_set_wq_id_association(void *entry, uint16_t q_id)
1275 uint32_t *wqe = entry;
1278 * Set Word 10, bit 0 to zero
1279 * Set Word 10, bits 15:1 to the WQ ID
1281 #if BYTE_ORDER == LITTLE_ENDIAN
1283 wqe[10] |= q_id << 1;
1285 #error big endian version not defined
1290 * @brief UNREG_FCFI - unregister a FCFI
1292 typedef struct sli4_cmd_unreg_fcfi_s {
1293 sli4_mbox_command_header_t hdr;
1295 #if BYTE_ORDER == LITTLE_ENDIAN
1299 #error big endian version not defined
1301 } sli4_cmd_unreg_fcfi_t;
1304 * @brief UNREG_RPI - unregister one or more RPI
1306 typedef struct sli4_cmd_unreg_rpi_s {
1307 sli4_mbox_command_header_t hdr;
1308 #if BYTE_ORDER == LITTLE_ENDIAN
1313 uint32_t destination_n_port_id:24,
1316 #error big endian version not defined
1318 } sli4_cmd_unreg_rpi_t;
1320 #define SLI4_UNREG_RPI_II_RPI 0x0
1321 #define SLI4_UNREG_RPI_II_VPI 0x1
1322 #define SLI4_UNREG_RPI_II_VFI 0x2
1323 #define SLI4_UNREG_RPI_II_FCFI 0x3
1326 * @brief UNREG_VFI - unregister one or more VFI
1328 typedef struct sli4_cmd_unreg_vfi_s {
1329 sli4_mbox_command_header_t hdr;
1330 #if BYTE_ORDER == LITTLE_ENDIAN
1336 #error big endian version not defined
1338 } sli4_cmd_unreg_vfi_t;
1340 #define SLI4_UNREG_VFI_II_VFI 0x0
1341 #define SLI4_UNREG_VFI_II_FCFI 0x3
1344 SLI4_UNREG_TYPE_PORT,
1345 SLI4_UNREG_TYPE_DOMAIN,
1346 SLI4_UNREG_TYPE_FCF,
1351 * @brief UNREG_VPI - unregister one or more VPI
1353 typedef struct sli4_cmd_unreg_vpi_s {
1354 sli4_mbox_command_header_t hdr;
1355 #if BYTE_ORDER == LITTLE_ENDIAN
1361 #error big endian version not defined
1363 } sli4_cmd_unreg_vpi_t;
1365 #define SLI4_UNREG_VPI_II_VPI 0x0
1366 #define SLI4_UNREG_VPI_II_VFI 0x2
1367 #define SLI4_UNREG_VPI_II_FCFI 0x3
1371 * @brief AUTO_XFER_RDY - Configure the auto-generate XFER-RDY feature.
1373 typedef struct sli4_cmd_config_auto_xfer_rdy_s {
1374 sli4_mbox_command_header_t hdr;
1375 #if BYTE_ORDER == LITTLE_ENDIAN
1377 uint32_t max_burst_len;
1379 #error big endian version not defined
1381 } sli4_cmd_config_auto_xfer_rdy_t;
1383 typedef struct sli4_cmd_config_auto_xfer_rdy_hp_s {
1384 sli4_mbox_command_header_t hdr;
1385 #if BYTE_ORDER == LITTLE_ENDIAN
1387 uint32_t max_burst_len;
1390 uint32_t block_size:16,
1393 #error big endian version not defined
1395 } sli4_cmd_config_auto_xfer_rdy_hp_t;
1398 /*************************************************************************
1399 * SLI-4 common configuration command formats and definitions
1402 #define SLI4_CFG_STATUS_SUCCESS 0x00
1403 #define SLI4_CFG_STATUS_FAILED 0x01
1404 #define SLI4_CFG_STATUS_ILLEGAL_REQUEST 0x02
1405 #define SLI4_CFG_STATUS_ILLEGAL_FIELD 0x03
1407 #define SLI4_MGMT_STATUS_FLASHROM_READ_FAILED 0xcb
1409 #define SLI4_CFG_ADD_STATUS_NO_STATUS 0x00
1410 #define SLI4_CFG_ADD_STATUS_INVALID_OPCODE 0x1e
1415 #define SLI4_SUBSYSTEM_COMMON 0x01
1416 #define SLI4_SUBSYSTEM_LOWLEVEL 0x0B
1417 #define SLI4_SUBSYSTEM_FCFCOE 0x0c
1418 #define SLI4_SUBSYSTEM_DMTF 0x11
1420 #define SLI4_OPC_LOWLEVEL_SET_WATCHDOG 0X36
1423 * Common opcode (OPC) values.
1425 #define SLI4_OPC_COMMON_FUNCTION_RESET 0x3d
1426 #define SLI4_OPC_COMMON_CREATE_CQ 0x0c
1427 #define SLI4_OPC_COMMON_CREATE_CQ_SET 0x1d
1428 #define SLI4_OPC_COMMON_DESTROY_CQ 0x36
1429 #define SLI4_OPC_COMMON_MODIFY_EQ_DELAY 0x29
1430 #define SLI4_OPC_COMMON_CREATE_EQ 0x0d
1431 #define SLI4_OPC_COMMON_DESTROY_EQ 0x37
1432 #define SLI4_OPC_COMMON_CREATE_MQ_EXT 0x5a
1433 #define SLI4_OPC_COMMON_DESTROY_MQ 0x35
1434 #define SLI4_OPC_COMMON_GET_CNTL_ATTRIBUTES 0x20
1435 #define SLI4_OPC_COMMON_NOP 0x21
1436 #define SLI4_OPC_COMMON_GET_RESOURCE_EXTENT_INFO 0x9a
1437 #define SLI4_OPC_COMMON_GET_SLI4_PARAMETERS 0xb5
1438 #define SLI4_OPC_COMMON_QUERY_FW_CONFIG 0x3a
1439 #define SLI4_OPC_COMMON_GET_PORT_NAME 0x4d
1441 #define SLI4_OPC_COMMON_WRITE_FLASHROM 0x07
1442 #define SLI4_OPC_COMMON_MANAGE_FAT 0x44
1443 #define SLI4_OPC_COMMON_READ_TRANSCEIVER_DATA 0x49
1444 #define SLI4_OPC_COMMON_GET_CNTL_ADDL_ATTRIBUTES 0x79
1445 #define SLI4_OPC_COMMON_GET_EXT_FAT_CAPABILITIES 0x7d
1446 #define SLI4_OPC_COMMON_SET_EXT_FAT_CAPABILITIES 0x7e
1447 #define SLI4_OPC_COMMON_EXT_FAT_CONFIGURE_SNAPSHOT 0x7f
1448 #define SLI4_OPC_COMMON_EXT_FAT_RETRIEVE_SNAPSHOT 0x80
1449 #define SLI4_OPC_COMMON_EXT_FAT_READ_STRING_TABLE 0x82
1450 #define SLI4_OPC_COMMON_GET_FUNCTION_CONFIG 0xa0
1451 #define SLI4_OPC_COMMON_GET_PROFILE_CONFIG 0xa4
1452 #define SLI4_OPC_COMMON_SET_PROFILE_CONFIG 0xa5
1453 #define SLI4_OPC_COMMON_GET_PROFILE_LIST 0xa6
1454 #define SLI4_OPC_COMMON_GET_ACTIVE_PROFILE 0xa7
1455 #define SLI4_OPC_COMMON_SET_ACTIVE_PROFILE 0xa8
1456 #define SLI4_OPC_COMMON_READ_OBJECT 0xab
1457 #define SLI4_OPC_COMMON_WRITE_OBJECT 0xac
1458 #define SLI4_OPC_COMMON_DELETE_OBJECT 0xae
1459 #define SLI4_OPC_COMMON_READ_OBJECT_LIST 0xad
1460 #define SLI4_OPC_COMMON_SET_DUMP_LOCATION 0xb8
1461 #define SLI4_OPC_COMMON_SET_FEATURES 0xbf
1462 #define SLI4_OPC_COMMON_GET_RECONFIG_LINK_INFO 0xc9
1463 #define SLI4_OPC_COMMON_SET_RECONFIG_LINK_ID 0xca
1466 * DMTF opcode (OPC) values.
1468 #define SLI4_OPC_DMTF_EXEC_CLP_CMD 0x01
1471 * @brief Generic Command Request header
1473 typedef struct sli4_req_hdr_s {
1474 #if BYTE_ORDER == LITTLE_ENDIAN
1479 uint32_t request_length;
1483 #error big endian version not defined
1488 * @brief Generic Command Response header
1490 typedef struct sli4_res_hdr_s {
1491 #if BYTE_ORDER == LITTLE_ENDIAN
1496 additional_status:8,
1498 uint32_t response_length;
1499 uint32_t actual_response_length;
1501 #error big endian version not defined
1506 * @brief COMMON_FUNCTION_RESET
1508 * Resets the Port, returning it to a power-on state. This configuration
1509 * command does not have a payload and should set/expect the lengths to
1512 typedef struct sli4_req_common_function_reset_s {
1514 } sli4_req_common_function_reset_t;
1517 typedef struct sli4_res_common_function_reset_s {
1519 } sli4_res_common_function_reset_t;
1522 * @brief COMMON_CREATE_CQ_V0
1524 * Create a Completion Queue.
1526 typedef struct sli4_req_common_create_cq_v0_s {
1528 #if BYTE_ORDER == LITTLE_ENDIAN
1529 uint32_t num_pages:16,
1547 } page_physical_address[0];
1549 #error big endian version not defined
1551 } sli4_req_common_create_cq_v0_t;
1554 * @brief COMMON_CREATE_CQ_V2
1556 * Create a Completion Queue.
1558 typedef struct sli4_req_common_create_cq_v2_s {
1560 #if BYTE_ORDER == LITTLE_ENDIAN
1561 uint32_t num_pages:16,
1576 uint32_t cqe_count:16,
1582 } page_physical_address[0];
1584 #error big endian version not defined
1586 } sli4_req_common_create_cq_v2_t;
1591 * @brief COMMON_CREATE_CQ_SET_V0
1593 * Create a set of Completion Queues.
1595 typedef struct sli4_req_common_create_cq_set_v0_s {
1597 #if BYTE_ORDER == LITTLE_ENDIAN
1598 uint32_t num_pages:16,
1610 uint32_t num_cq_req:16,
1617 } page_physical_address[0];
1619 #error big endian version not defined
1621 } sli4_req_common_create_cq_set_v0_t;
1626 #define SLI4_CQ_CNT_256 0
1627 #define SLI4_CQ_CNT_512 1
1628 #define SLI4_CQ_CNT_1024 2
1629 #define SLI4_CQ_CNT_LARGE 3
1631 #define SLI4_CQE_BYTES (4 * sizeof(uint32_t))
1633 #define SLI4_COMMON_CREATE_CQ_V2_MAX_PAGES 8
1636 * @brief Generic Common Create EQ/CQ/MQ/WQ/RQ Queue completion
1638 typedef struct sli4_res_common_create_queue_s {
1640 #if BYTE_ORDER == LITTLE_ENDIAN
1648 #error big endian version not defined
1650 } sli4_res_common_create_queue_t;
1653 typedef struct sli4_res_common_create_queue_set_s {
1655 #if BYTE_ORDER == LITTLE_ENDIAN
1659 #error big endian version not defined
1661 } sli4_res_common_create_queue_set_t;
1665 * @brief Common Destroy CQ
1667 typedef struct sli4_req_common_destroy_cq_s {
1669 #if BYTE_ORDER == LITTLE_ENDIAN
1673 #error big endian version not defined
1675 } sli4_req_common_destroy_cq_t;
1678 * @brief COMMON_MODIFY_EQ_DELAY
1680 * Modify the delay multiplier for EQs
1682 typedef struct sli4_req_common_modify_eq_delay_s {
1684 #if BYTE_ORDER == LITTLE_ENDIAN
1689 uint32_t delay_multiplier;
1690 } eq_delay_record[8];
1692 #error big endian version not defined
1694 } sli4_req_common_modify_eq_delay_t;
1697 * @brief COMMON_CREATE_EQ
1699 * Create an Event Queue.
1701 typedef struct sli4_req_common_create_eq_s {
1703 #if BYTE_ORDER == LITTLE_ENDIAN
1704 uint32_t num_pages:16,
1715 delay_multiplier:10,
1723 #error big endian version not defined
1725 } sli4_req_common_create_eq_t;
1727 #define SLI4_EQ_CNT_256 0
1728 #define SLI4_EQ_CNT_512 1
1729 #define SLI4_EQ_CNT_1024 2
1730 #define SLI4_EQ_CNT_2048 3
1731 #define SLI4_EQ_CNT_4096 4
1733 #define SLI4_EQE_SIZE_4 0
1734 #define SLI4_EQE_SIZE_16 1
1737 * @brief Common Destroy EQ
1739 typedef struct sli4_req_common_destroy_eq_s {
1741 #if BYTE_ORDER == LITTLE_ENDIAN
1745 #error big endian version not defined
1747 } sli4_req_common_destroy_eq_t;
1750 * @brief COMMON_CREATE_MQ_EXT
1752 * Create a Mailbox Queue; accommodate v0 and v1 forms.
1754 typedef struct sli4_req_common_create_mq_ext_s {
1756 #if BYTE_ORDER == LITTLE_ENDIAN
1757 uint32_t num_pages:16,
1759 uint32_t async_event_bitmap;
1760 uint32_t async_cq_id_v1:16,
1773 } page_physical_address[8];
1775 #error big endian version not defined
1777 } sli4_req_common_create_mq_ext_t;
1779 #define SLI4_MQE_SIZE_16 0x05
1780 #define SLI4_MQE_SIZE_32 0x06
1781 #define SLI4_MQE_SIZE_64 0x07
1782 #define SLI4_MQE_SIZE_128 0x08
1784 #define SLI4_ASYNC_EVT_LINK_STATE BIT(1)
1785 #define SLI4_ASYNC_EVT_FCOE_FIP BIT(2)
1786 #define SLI4_ASYNC_EVT_DCBX BIT(3)
1787 #define SLI4_ASYNC_EVT_ISCSI BIT(4)
1788 #define SLI4_ASYNC_EVT_GRP5 BIT(5)
1789 #define SLI4_ASYNC_EVT_FC BIT(16)
1790 #define SLI4_ASYNC_EVT_SLI_PORT BIT(17)
1791 #define SLI4_ASYNC_EVT_VF BIT(18)
1792 #define SLI4_ASYNC_EVT_MR BIT(19)
1794 #define SLI4_ASYNC_EVT_ALL \
1795 SLI4_ASYNC_EVT_LINK_STATE | \
1796 SLI4_ASYNC_EVT_FCOE_FIP | \
1797 SLI4_ASYNC_EVT_DCBX | \
1798 SLI4_ASYNC_EVT_ISCSI | \
1799 SLI4_ASYNC_EVT_GRP5 | \
1800 SLI4_ASYNC_EVT_FC | \
1801 SLI4_ASYNC_EVT_SLI_PORT | \
1802 SLI4_ASYNC_EVT_VF |\
1805 #define SLI4_ASYNC_EVT_FC_FCOE \
1806 SLI4_ASYNC_EVT_LINK_STATE | \
1807 SLI4_ASYNC_EVT_FCOE_FIP | \
1808 SLI4_ASYNC_EVT_GRP5 | \
1809 SLI4_ASYNC_EVT_FC | \
1810 SLI4_ASYNC_EVT_SLI_PORT
1813 * @brief Common Destroy MQ
1815 typedef struct sli4_req_common_destroy_mq_s {
1817 #if BYTE_ORDER == LITTLE_ENDIAN
1821 #error big endian version not defined
1823 } sli4_req_common_destroy_mq_t;
1826 * @brief COMMON_GET_CNTL_ATTRIBUTES
1828 * Query for information about the SLI Port
1830 typedef struct sli4_res_common_get_cntl_attributes_s {
1832 #if BYTE_ORDER == LITTLE_ENDIAN
1833 uint8_t version_string[32];
1834 uint8_t manufacturer_name[32];
1835 uint32_t supported_modes;
1836 uint32_t eprom_version_lo:8,
1839 uint32_t mbx_data_structure_version;
1840 uint32_t ep_firmware_data_structure_version;
1841 uint8_t ncsi_version_string[12];
1842 uint32_t default_extended_timeout;
1843 uint8_t model_number[32];
1844 uint8_t description[64];
1845 uint8_t serial_number[32];
1846 uint8_t ip_version_string[32];
1847 uint8_t fw_version_string[32];
1848 uint8_t bios_version_string[32];
1849 uint8_t redboot_version_string[32];
1850 uint8_t driver_version_string[32];
1851 uint8_t fw_on_flash_version_string[32];
1852 uint32_t functionalities_supported;
1853 uint32_t max_cdb_length:16,
1855 generational_guid0:8;
1856 uint32_t generational_guid1_12[3];
1857 uint32_t generational_guid13:24,
1859 uint32_t default_link_down_timeout:16,
1860 iscsi_version_min_max:8,
1861 multifunctional_device:8;
1862 uint32_t cache_valid:8,
1864 max_domains_supported:8,
1867 uint32_t firmware_post_status;
1869 uint32_t iscsi_features:8,
1871 uint32_t pci_vendor_id:16,
1873 uint32_t pci_sub_vendor_id:16,
1874 pci_sub_system_id:16;
1875 uint32_t pci_bus_number:8,
1876 pci_device_number:8,
1877 pci_function_number:8,
1879 uint64_t unique_identifier;
1880 uint32_t number_of_netfilters:8,
1883 #error big endian version not defined
1885 } sli4_res_common_get_cntl_attributes_t;
1888 * @brief COMMON_GET_CNTL_ATTRIBUTES
1890 * This command queries the controller information from the Flash ROM.
1892 typedef struct sli4_req_common_get_cntl_addl_attributes_s {
1894 } sli4_req_common_get_cntl_addl_attributes_t;
1897 typedef struct sli4_res_common_get_cntl_addl_attributes_s {
1899 uint16_t ipl_file_number;
1900 uint8_t ipl_file_version;
1902 uint8_t on_die_temperature;
1904 uint32_t driver_advanced_features_supported;
1906 char fcoe_universal_bios_version[32];
1907 char fcoe_x86_bios_version[32];
1908 char fcoe_efi_bios_version[32];
1909 char fcoe_fcode_version[32];
1910 char uefi_bios_version[32];
1911 char uefi_nic_version[32];
1912 char uefi_fcode_version[32];
1913 char uefi_iscsi_version[32];
1914 char iscsi_x86_bios_version[32];
1915 char pxe_x86_bios_version[32];
1916 uint8_t fcoe_default_wwpn[8];
1917 uint8_t ext_phy_version[32];
1918 uint8_t fc_universal_bios_version[32];
1919 uint8_t fc_x86_bios_version[32];
1920 uint8_t fc_efi_bios_version[32];
1921 uint8_t fc_fcode_version[32];
1922 uint8_t ext_phy_crc_label[8];
1923 uint8_t ipl_file_name[16];
1925 } sli4_res_common_get_cntl_addl_attributes_t;
1930 * This command does not do anything; it only returns the payload in the completion.
1932 typedef struct sli4_req_common_nop_s {
1934 #if BYTE_ORDER == LITTLE_ENDIAN
1935 uint32_t context[2];
1937 #error big endian version not defined
1939 } sli4_req_common_nop_t;
1941 typedef struct sli4_res_common_nop_s {
1943 #if BYTE_ORDER == LITTLE_ENDIAN
1944 uint32_t context[2];
1946 #error big endian version not defined
1948 } sli4_res_common_nop_t;
1951 * @brief COMMON_GET_RESOURCE_EXTENT_INFO
1953 typedef struct sli4_req_common_get_resource_extent_info_s {
1955 #if BYTE_ORDER == LITTLE_ENDIAN
1956 uint32_t resource_type:16,
1959 #error big endian version not defined
1961 } sli4_req_common_get_resource_extent_info_t;
1963 #define SLI4_RSC_TYPE_ISCSI_INI_XRI 0x0c
1964 #define SLI4_RSC_TYPE_FCOE_VFI 0x20
1965 #define SLI4_RSC_TYPE_FCOE_VPI 0x21
1966 #define SLI4_RSC_TYPE_FCOE_RPI 0x22
1967 #define SLI4_RSC_TYPE_FCOE_XRI 0x23
1969 typedef struct sli4_res_common_get_resource_extent_info_s {
1971 #if BYTE_ORDER == LITTLE_ENDIAN
1972 uint32_t resource_extent_count:16,
1973 resource_extent_size:16;
1975 #error big endian version not defined
1977 } sli4_res_common_get_resource_extent_info_t;
1980 #define SLI4_128BYTE_WQE_SUPPORT 0x02
1982 * @brief COMMON_GET_SLI4_PARAMETERS
1984 typedef struct sli4_res_common_get_sli4_parameters_s {
1986 #if BYTE_ORDER == LITTLE_ENDIAN
1987 uint32_t protocol_type:8,
1997 uint32_t eq_page_cnt:4,
2004 uint32_t eqe_count_mask:16,
2006 uint32_t cq_page_cnt:4,
2014 uint32_t cqe_count_mask:16,
2016 uint32_t mq_page_cnt:4,
2022 uint32_t mqe_count_mask:16,
2024 uint32_t wq_page_cnt:4,
2032 uint32_t wqe_count_mask:16,
2034 uint32_t rq_page_cnt:4,
2042 uint32_t rqe_count_mask:16,
2060 phwq:1, /** Performance Hint WQ_ID Association */
2074 uint32_t sge_supported_length;
2075 uint32_t sgl_page_cnt:4,
2080 uint32_t min_rq_buffer_size:16,
2082 uint32_t max_rq_buffer_size;
2083 uint32_t physical_xri_max:16,
2084 physical_rpi_max:16;
2085 uint32_t physical_vpi_max:16,
2086 physical_vfi_max:16;
2088 uint32_t frag_num_field_offset:16, /* dword 20 */
2089 frag_num_field_size:16;
2090 uint32_t sgl_index_field_offset:16, /* dword 21 */
2091 sgl_index_field_size:16;
2092 uint32_t chain_sge_initial_value_lo; /* dword 22 */
2093 uint32_t chain_sge_initial_value_hi; /* dword 23 */
2095 #error big endian version not defined
2097 } sli4_res_common_get_sli4_parameters_t;
2101 * @brief COMMON_QUERY_FW_CONFIG
2103 * This command retrieves firmware configuration parameters and adapter
2104 * resources available to the driver.
2106 typedef struct sli4_req_common_query_fw_config_s {
2108 } sli4_req_common_query_fw_config_t;
2111 #define SLI4_FUNCTION_MODE_FCOE_INI_MODE 0x40
2112 #define SLI4_FUNCTION_MODE_FCOE_TGT_MODE 0x80
2113 #define SLI4_FUNCTION_MODE_DUA_MODE 0x800
2115 #define SLI4_ULP_MODE_FCOE_INI 0x40
2116 #define SLI4_ULP_MODE_FCOE_TGT 0x80
2118 typedef struct sli4_res_common_query_fw_config_s {
2120 uint32_t config_number;
2122 uint32_t physical_port;
2123 uint32_t function_mode;
2125 uint32_t ulp0_nic_wqid_base;
2126 uint32_t ulp0_nic_wq_total; /* Dword 10 */
2127 uint32_t ulp0_toe_wqid_base;
2128 uint32_t ulp0_toe_wq_total;
2129 uint32_t ulp0_toe_rqid_base;
2130 uint32_t ulp0_toe_rq_total;
2131 uint32_t ulp0_toe_defrqid_base;
2132 uint32_t ulp0_toe_defrq_total;
2133 uint32_t ulp0_lro_rqid_base;
2134 uint32_t ulp0_lro_rq_total;
2135 uint32_t ulp0_iscsi_icd_base;
2136 uint32_t ulp0_iscsi_icd_total; /* Dword 20 */
2138 uint32_t ulp1_nic_wqid_base;
2139 uint32_t ulp1_nic_wq_total;
2140 uint32_t ulp1_toe_wqid_base;
2141 uint32_t ulp1_toe_wq_total;
2142 uint32_t ulp1_toe_rqid_base;
2143 uint32_t ulp1_toe_rq_total;
2144 uint32_t ulp1_toe_defrqid_base;
2145 uint32_t ulp1_toe_defrq_total;
2146 uint32_t ulp1_lro_rqid_base; /* Dword 30 */
2147 uint32_t ulp1_lro_rq_total;
2148 uint32_t ulp1_iscsi_icd_base;
2149 uint32_t ulp1_iscsi_icd_total;
2150 uint32_t function_capabilities;
2151 uint32_t ulp0_cq_base;
2152 uint32_t ulp0_cq_total;
2153 uint32_t ulp0_eq_base;
2154 uint32_t ulp0_eq_total;
2155 uint32_t ulp0_iscsi_chain_icd_base;
2156 uint32_t ulp0_iscsi_chain_icd_total; /* Dword 40 */
2157 uint32_t ulp1_iscsi_chain_icd_base;
2158 uint32_t ulp1_iscsi_chain_icd_total;
2159 } sli4_res_common_query_fw_config_t;
2162 * @brief COMMON_GET_PORT_NAME
2164 typedef struct sli4_req_common_get_port_name_s {
2166 #if BYTE_ORDER == LITTLE_ENDIAN
2167 uint32_t pt:2, /* only COMMON_GET_PORT_NAME_V1 */
2170 #error big endian version not defined
2172 } sli4_req_common_get_port_name_t;
2174 typedef struct sli4_res_common_get_port_name_s {
2177 } sli4_res_common_get_port_name_t;
2180 * @brief COMMON_WRITE_FLASHROM
2182 typedef struct sli4_req_common_write_flashrom_s {
2184 #if BYTE_ORDER == LITTLE_ENDIAN
2185 uint32_t flash_rom_access_opcode;
2186 uint32_t flash_rom_access_operation_type;
2187 uint32_t data_buffer_size;
2189 uint8_t data_buffer[4];
2191 #error big endian version not defined
2193 } sli4_req_common_write_flashrom_t;
2195 #define SLI4_MGMT_FLASHROM_OPCODE_FLASH 0x01
2196 #define SLI4_MGMT_FLASHROM_OPCODE_SAVE 0x02
2197 #define SLI4_MGMT_FLASHROM_OPCODE_CLEAR 0x03
2198 #define SLI4_MGMT_FLASHROM_OPCODE_REPORT 0x04
2199 #define SLI4_MGMT_FLASHROM_OPCODE_IMAGE_INFO 0x05
2200 #define SLI4_MGMT_FLASHROM_OPCODE_IMAGE_CRC 0x06
2201 #define SLI4_MGMT_FLASHROM_OPCODE_OFFSET_BASED_FLASH 0x07
2202 #define SLI4_MGMT_FLASHROM_OPCODE_OFFSET_BASED_SAVE 0x08
2203 #define SLI4_MGMT_PHY_FLASHROM_OPCODE_FLASH 0x09
2204 #define SLI4_MGMT_PHY_FLASHROM_OPCODE_SAVE 0x0a
2206 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_ISCSI 0x00
2207 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_REDBOOT 0x01
2208 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_BIOS 0x02
2209 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_PXE_BIOS 0x03
2210 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_CODE_CONTROL 0x04
2211 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_IPSEC_CFG 0x05
2212 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_INIT_DATA 0x06
2213 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_ROM_OFFSET 0x07
2214 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_FCOE_BIOS 0x08
2215 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_ISCSI_BAK 0x09
2216 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_FCOE_ACT 0x0a
2217 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_FCOE_BAK 0x0b
2218 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_CODE_CTRL_P 0x0c
2219 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_NCSI 0x0d
2220 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_NIC 0x0e
2221 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_DCBX 0x0f
2222 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_PXE_BIOS_CFG 0x10
2223 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_ALL_CFG_DATA 0x11
2226 * @brief COMMON_MANAGE_FAT
2228 typedef struct sli4_req_common_manage_fat_s {
2230 #if BYTE_ORDER == LITTLE_ENDIAN
2231 uint32_t fat_operation;
2232 uint32_t read_log_offset;
2233 uint32_t read_log_length;
2234 uint32_t data_buffer_size;
2235 uint32_t data_buffer; /* response only */
2237 #error big endian version not defined
2239 } sli4_req_common_manage_fat_t;
2242 * @brief COMMON_GET_EXT_FAT_CAPABILITIES
2244 typedef struct sli4_req_common_get_ext_fat_capabilities_s {
2246 #if BYTE_ORDER == LITTLE_ENDIAN
2247 uint32_t parameter_type;
2249 #error big endian version not defined
2251 } sli4_req_common_get_ext_fat_capabilities_t;
2254 * @brief COMMON_SET_EXT_FAT_CAPABILITIES
2256 typedef struct sli4_req_common_set_ext_fat_capabilities_s {
2258 #if BYTE_ORDER == LITTLE_ENDIAN
2259 uint32_t maximum_log_entries;
2260 uint32_t log_entry_size;
2261 uint32_t logging_type:8,
2262 maximum_logging_functions:8,
2263 maximum_logging_ports:8,
2265 uint32_t supported_modes;
2266 uint32_t number_modules;
2267 uint32_t debug_module[14];
2269 #error big endian version not defined
2271 } sli4_req_common_set_ext_fat_capabilities_t;
2274 * @brief COMMON_EXT_FAT_CONFIGURE_SNAPSHOT
2276 typedef struct sli4_req_common_ext_fat_configure_snapshot_s {
2278 #if BYTE_ORDER == LITTLE_ENDIAN
2279 uint32_t total_log_entries;
2281 #error big endian version not defined
2283 } sli4_req_common_ext_fat_configure_snapshot_t;
2286 * @brief COMMON_EXT_FAT_RETRIEVE_SNAPSHOT
2288 typedef struct sli4_req_common_ext_fat_retrieve_snapshot_s {
2290 #if BYTE_ORDER == LITTLE_ENDIAN
2291 uint32_t snapshot_mode;
2292 uint32_t start_index;
2293 uint32_t number_log_entries;
2295 #error big endian version not defined
2297 } sli4_req_common_ext_fat_retrieve_snapshot_t;
2299 typedef struct sli4_res_common_ext_fat_retrieve_snapshot_s {
2301 #if BYTE_ORDER == LITTLE_ENDIAN
2302 uint32_t number_log_entries;
2306 uint32_t trace_level;
2307 uint32_t module_mask[2];
2308 uint32_t trace_table_index;
2310 uint8_t string_data[16];
2313 #error big endian version not defined
2315 } sli4_res_common_ext_fat_retrieve_snapshot_t;
2318 * @brief COMMON_EXT_FAT_READ_STRING_TABLE
2320 typedef struct sli4_req_common_ext_fat_read_string_table_s {
2322 #if BYTE_ORDER == LITTLE_ENDIAN
2323 uint32_t byte_offset;
2324 uint32_t number_bytes;
2326 #error big endian version not defined
2328 } sli4_req_common_ext_fat_read_string_table_t;
2330 typedef struct sli4_res_common_ext_fat_read_string_table_s {
2332 #if BYTE_ORDER == LITTLE_ENDIAN
2333 uint32_t number_returned_bytes;
2334 uint32_t number_remaining_bytes;
2335 uint32_t table_data0:8,
2337 uint8_t table_data[0];
2339 #error big endian version not defined
2341 } sli4_res_common_ext_fat_read_string_table_t;
2344 * @brief COMMON_READ_TRANSCEIVER_DATA
2346 * This command reads SFF transceiver data(Format is defined
2347 * by the SFF-8472 specification).
2349 typedef struct sli4_req_common_read_transceiver_data_s {
2351 #if BYTE_ORDER == LITTLE_ENDIAN
2352 uint32_t page_number;
2355 #error big endian version not defined
2357 } sli4_req_common_read_transceiver_data_t;
2359 typedef struct sli4_res_common_read_transceiver_data_s {
2361 #if BYTE_ORDER == LITTLE_ENDIAN
2362 uint32_t page_number;
2364 uint32_t page_data[32];
2365 uint32_t page_data_2[32];
2367 #error big endian version not defined
2369 } sli4_res_common_read_transceiver_data_t;
2372 * @brief COMMON_READ_OBJECT
2374 typedef struct sli4_req_common_read_object_s {
2376 #if BYTE_ORDER == LITTLE_ENDIAN
2377 uint32_t desired_read_length:24,
2379 uint32_t read_offset;
2380 uint8_t object_name[104];
2381 uint32_t host_buffer_descriptor_count;
2382 sli4_bde_t host_buffer_descriptor[0];
2384 #error big endian version not defined
2386 } sli4_req_common_read_object_t;
2388 typedef struct sli4_res_common_read_object_s {
2390 #if BYTE_ORDER == LITTLE_ENDIAN
2391 uint32_t actual_read_length;
2395 #error big endian version not defined
2397 } sli4_res_common_read_object_t;
2400 * @brief COMMON_WRITE_OBJECT
2402 typedef struct sli4_req_common_write_object_s {
2404 #if BYTE_ORDER == LITTLE_ENDIAN
2405 uint32_t desired_write_length:24,
2409 uint32_t write_offset;
2410 uint8_t object_name[104];
2411 uint32_t host_buffer_descriptor_count;
2412 sli4_bde_t host_buffer_descriptor[0];
2414 #error big endian version not defined
2416 } sli4_req_common_write_object_t;
2418 typedef struct sli4_res_common_write_object_s {
2420 #if BYTE_ORDER == LITTLE_ENDIAN
2421 uint32_t actual_write_length;
2422 uint32_t change_status:8,
2425 #error big endian version not defined
2427 } sli4_res_common_write_object_t;
2430 * @brief COMMON_DELETE_OBJECT
2432 typedef struct sli4_req_common_delete_object_s {
2434 #if BYTE_ORDER == LITTLE_ENDIAN
2437 uint8_t object_name[104];
2439 #error big endian version not defined
2441 } sli4_req_common_delete_object_t;
2444 * @brief COMMON_READ_OBJECT_LIST
2446 typedef struct sli4_req_common_read_object_list_s {
2448 #if BYTE_ORDER == LITTLE_ENDIAN
2449 uint32_t desired_read_length:24,
2451 uint32_t read_offset;
2452 uint8_t object_name[104];
2453 uint32_t host_buffer_descriptor_count;
2454 sli4_bde_t host_buffer_descriptor[0];
2456 #error big endian version not defined
2458 } sli4_req_common_read_object_list_t;
2461 * @brief COMMON_SET_DUMP_LOCATION
2463 typedef struct sli4_req_common_set_dump_location_s {
2465 #if BYTE_ORDER == LITTLE_ENDIAN
2466 uint32_t buffer_length:24,
2471 uint32_t buf_addr_low;
2472 uint32_t buf_addr_high;
2474 #error big endian version not defined
2476 } sli4_req_common_set_dump_location_t;
2478 typedef struct sli4_res_common_set_dump_location_s {
2480 #if BYTE_ORDER == LITTLE_ENDIAN
2481 uint32_t buffer_length:24,
2484 #error big endian version not defined
2486 }sli4_res_common_set_dump_location_t;
2489 * @brief COMMON_SET_SET_FEATURES
2491 #define SLI4_SET_FEATURES_DIF_SEED 0x01
2492 #define SLI4_SET_FEATURES_XRI_TIMER 0x03
2493 #define SLI4_SET_FEATURES_MAX_PCIE_SPEED 0x04
2494 #define SLI4_SET_FEATURES_FCTL_CHECK 0x05
2495 #define SLI4_SET_FEATURES_FEC 0x06
2496 #define SLI4_SET_FEATURES_PCIE_RECV_DETECT 0x07
2497 #define SLI4_SET_FEATURES_DIF_MEMORY_MODE 0x08
2498 #define SLI4_SET_FEATURES_DISABLE_SLI_PORT_PAUSE_STATE 0x09
2499 #define SLI4_SET_FEATURES_ENABLE_PCIE_OPTIONS 0x0A
2500 #define SLI4_SET_FEATURES_SET_CONFIG_AUTO_XFER_RDY_T10PI 0x0C
2501 #define SLI4_SET_FEATURES_ENABLE_MULTI_RECEIVE_QUEUE 0x0D
2502 #define SLI4_SET_FEATURES_SET_FTD_XFER_HINT 0x0F
2503 #define SLI4_SET_FEATURES_SLI_PORT_HEALTH_CHECK 0x11
2505 typedef struct sli4_req_common_set_features_s {
2507 #if BYTE_ORDER == LITTLE_ENDIAN
2512 #error big endian version not defined
2514 } sli4_req_common_set_features_t;
2516 typedef struct sli4_req_common_set_features_dif_seed_s {
2517 #if BYTE_ORDER == LITTLE_ENDIAN
2521 #error big endian version not defined
2523 } sli4_req_common_set_features_dif_seed_t;
2525 typedef struct sli4_req_common_set_features_t10_pi_mem_model_s {
2526 #if BYTE_ORDER == LITTLE_ENDIAN
2530 #error big endian version not defined
2532 } sli4_req_common_set_features_t10_pi_mem_model_t;
2534 typedef struct sli4_req_common_set_features_multirq_s {
2535 #if BYTE_ORDER == LITTLE_ENDIAN
2536 uint32_t isr:1, /*<< Include Sequence Reporting */
2537 agxfe:1, /*<< Auto Generate XFER-RDY Feature Enabled */
2543 #error big endian version not defined
2545 } sli4_req_common_set_features_multirq_t;
2547 typedef struct sli4_req_common_set_features_xfer_rdy_t10pi_s {
2548 #if BYTE_ORDER == LITTLE_ENDIAN
2556 uint32_t app_tag:16,
2559 #error big endian version not defined
2561 } sli4_req_common_set_features_xfer_rdy_t10pi_t;
2563 typedef struct sli4_req_common_set_features_health_check_s {
2564 #if BYTE_ORDER == LITTLE_ENDIAN
2569 #error big endian version not defined
2571 } sli4_req_common_set_features_health_check_t;
2573 typedef struct sli4_req_common_set_features_set_fdt_xfer_hint_s {
2574 #if BYTE_ORDER == LITTLE_ENDIAN
2575 uint32_t fdt_xfer_hint;
2577 #error big endian version not defined
2579 } sli4_req_common_set_features_set_fdt_xfer_hint_t;
2582 * @brief DMTF_EXEC_CLP_CMD
2584 typedef struct sli4_req_dmtf_exec_clp_cmd_s {
2586 #if BYTE_ORDER == LITTLE_ENDIAN
2587 uint32_t cmd_buf_length;
2588 uint32_t resp_buf_length;
2589 uint32_t cmd_buf_addr_low;
2590 uint32_t cmd_buf_addr_high;
2591 uint32_t resp_buf_addr_low;
2592 uint32_t resp_buf_addr_high;
2594 #error big endian version not defined
2596 } sli4_req_dmtf_exec_clp_cmd_t;
2598 typedef struct sli4_res_dmtf_exec_clp_cmd_s {
2600 #if BYTE_ORDER == LITTLE_ENDIAN
2602 uint32_t resp_length;
2607 uint32_t clp_status;
2608 uint32_t clp_detailed_status;
2610 #error big endian version not defined
2612 } sli4_res_dmtf_exec_clp_cmd_t;
2615 * @brief Resource descriptor
2618 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_PCIE 0x50
2619 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_NIC 0x51
2620 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_ISCSI 0x52
2621 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_FCFCOE 0x53
2622 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_RDMA 0x54
2623 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_PORT 0x55
2624 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_ISAP 0x56
2626 #define SLI4_PROTOCOL_NIC_TOE 0x01
2627 #define SLI4_PROTOCOL_ISCSI 0x02
2628 #define SLI4_PROTOCOL_FCOE 0x04
2629 #define SLI4_PROTOCOL_NIC_TOE_RDMA 0x08
2630 #define SLI4_PROTOCOL_FC 0x10
2631 #define SLI4_PROTOCOL_DEFAULT 0xff
2633 typedef struct sli4_resource_descriptor_v1_s {
2634 uint32_t descriptor_type:8,
2635 descriptor_length:8,
2637 uint32_t type_specific[0];
2638 } sli4_resource_descriptor_v1_t;
2640 typedef struct sli4_pcie_resource_descriptor_v1_s {
2641 uint32_t descriptor_type:8,
2642 descriptor_length:8,
2650 uint32_t sriov_state:8,
2654 uint32_t number_of_vfs:16,
2656 uint32_t mission_roles:8,
2663 } sli4_pcie_resource_descriptor_v1_t;
2665 typedef struct sli4_isap_resource_descriptor_v1_s {
2666 uint32_t descriptor_type:8,
2667 descriptor_length:8,
2669 uint32_t iscsi_tgt:1,
2674 uint32_t fcoe_tgt:1,
2679 uint32_t mc_type0:8,
2684 } sli4_isap_resouce_descriptor_v1_t;
2687 * @brief COMMON_GET_FUNCTION_CONFIG
2689 typedef struct sli4_req_common_get_function_config_s {
2691 } sli4_req_common_get_function_config_t;
2693 typedef struct sli4_res_common_get_function_config_s {
2695 #if BYTE_ORDER == LITTLE_ENDIAN
2696 uint32_t desc_count;
2699 #error big endian version not defined
2701 } sli4_res_common_get_function_config_t;
2704 * @brief COMMON_GET_PROFILE_CONFIG
2706 typedef struct sli4_req_common_get_profile_config_s {
2708 uint32_t profile_id:8,
2711 } sli4_req_common_get_profile_config_t;
2713 typedef struct sli4_res_common_get_profile_config_s {
2715 #if BYTE_ORDER == LITTLE_ENDIAN
2716 uint32_t desc_count;
2719 #error big endian version not defined
2721 } sli4_res_common_get_profile_config_t;
2724 * @brief COMMON_SET_PROFILE_CONFIG
2726 typedef struct sli4_req_common_set_profile_config_s {
2728 uint32_t profile_id:8,
2731 uint32_t desc_count;
2733 } sli4_req_common_set_profile_config_t;
2735 typedef struct sli4_res_common_set_profile_config_s {
2737 #if BYTE_ORDER == LITTLE_ENDIAN
2739 #error big endian version not defined
2741 } sli4_res_common_set_profile_config_t;
2744 * @brief Profile Descriptor for profile functions
2746 typedef struct sli4_profile_descriptor_s {
2747 #if BYTE_ORDER == LITTLE_ENDIAN
2748 uint32_t profile_id:8,
2752 uint32_t profile_description[128];
2754 #error big endian version not defined
2756 } sli4_profile_descriptor_t;
2758 /* We don't know in advance how many descriptors there are. We have
2759 to pick a number that we think will be big enough and ask for that
2762 #define MAX_PRODUCT_DESCRIPTORS 40
2765 * @brief COMMON_GET_PROFILE_LIST
2767 typedef struct sli4_req_common_get_profile_list_s {
2769 #if BYTE_ORDER == LITTLE_ENDIAN
2770 uint32_t start_profile_index:8,
2773 #error big endian version not defined
2775 } sli4_req_common_get_profile_list_t;
2777 typedef struct sli4_res_common_get_profile_list_s {
2779 #if BYTE_ORDER == LITTLE_ENDIAN
2780 uint32_t profile_descriptor_count;
2781 sli4_profile_descriptor_t profile_descriptor[MAX_PRODUCT_DESCRIPTORS];
2783 #error big endian version not defined
2785 } sli4_res_common_get_profile_list_t;
2788 * @brief COMMON_GET_ACTIVE_PROFILE
2790 typedef struct sli4_req_common_get_active_profile_s {
2792 } sli4_req_common_get_active_profile_t;
2794 typedef struct sli4_res_common_get_active_profile_s {
2796 #if BYTE_ORDER == LITTLE_ENDIAN
2797 uint32_t active_profile_id:8,
2802 #error big endian version not defined
2804 } sli4_res_common_get_active_profile_t;
2807 * @brief COMMON_SET_ACTIVE_PROFILE
2809 typedef struct sli4_req_common_set_active_profile_s {
2811 #if BYTE_ORDER == LITTLE_ENDIAN
2812 uint32_t active_profile_id:8,
2816 #error big endian version not defined
2818 } sli4_req_common_set_active_profile_t;
2820 typedef struct sli4_res_common_set_active_profile_s {
2822 } sli4_res_common_set_active_profile_t;
2825 * @brief Link Config Descriptor for link config functions
2827 typedef struct sli4_link_config_descriptor_s {
2828 #if BYTE_ORDER == LITTLE_ENDIAN
2829 uint32_t link_config_id:8,
2831 uint32_t config_description[8];
2833 #error big endian version not defined
2835 } sli4_link_config_descriptor_t;
2837 #define MAX_LINK_CONFIG_DESCRIPTORS 10
2840 * @brief COMMON_GET_RECONFIG_LINK_INFO
2842 typedef struct sli4_req_common_get_reconfig_link_info_s {
2844 #if BYTE_ORDER == LITTLE_ENDIAN
2846 #error big endian version not defined
2848 } sli4_req_common_get_reconfig_link_info_t;
2850 typedef struct sli4_res_common_get_reconfig_link_info_s {
2852 #if BYTE_ORDER == LITTLE_ENDIAN
2853 uint32_t active_link_config_id:8,
2855 next_link_config_id:8,
2857 uint32_t link_configuration_descriptor_count;
2858 sli4_link_config_descriptor_t desc[MAX_LINK_CONFIG_DESCRIPTORS];
2860 #error big endian version not defined
2862 } sli4_res_common_get_reconfig_link_info_t;
2865 * @brief COMMON_SET_RECONFIG_LINK_ID
2867 typedef struct sli4_req_common_set_reconfig_link_id_s {
2869 #if BYTE_ORDER == LITTLE_ENDIAN
2870 uint32_t next_link_config_id:8,
2874 #error big endian version not defined
2876 } sli4_req_common_set_reconfig_link_id_t;
2878 typedef struct sli4_res_common_set_reconfig_link_id_s {
2880 #if BYTE_ORDER == LITTLE_ENDIAN
2882 #error big endian version not defined
2884 } sli4_res_common_set_reconfig_link_id_t;
2887 typedef struct sli4_req_lowlevel_set_watchdog_s {
2889 #if BYTE_ORDER == LITTLE_ENDIAN
2890 uint32_t watchdog_timeout:16,
2893 #error big endian version not defined
2896 } sli4_req_lowlevel_set_watchdog_t;
2899 typedef struct sli4_res_lowlevel_set_watchdog_s {
2901 #if BYTE_ORDER == LITTLE_ENDIAN
2904 #error big endian version not defined
2906 } sli4_res_lowlevel_set_watchdog_t;
2909 * @brief Event Queue Entry
2911 typedef struct sli4_eqe_s {
2912 #if BYTE_ORDER == LITTLE_ENDIAN
2913 uint32_t vld:1, /** valid */
2918 #error big endian version not defined
2922 #define SLI4_MAJOR_CODE_STANDARD 0
2923 #define SLI4_MAJOR_CODE_SENTINEL 1
2926 * @brief Mailbox Completion Queue Entry
2928 * A CQE generated on the completion of a MQE from a MQ.
2930 typedef struct sli4_mcqe_s {
2931 #if BYTE_ORDER == LITTLE_ENDIAN
2932 uint32_t completion_status:16, /** values are protocol specific */
2934 uint32_t mqe_tag_low;
2935 uint32_t mqe_tag_high;
2937 con:1, /** consumed - command now being executed */
2938 cmp:1, /** completed - command still executing if clear */
2940 ae:1, /** async event - this is an ACQE */
2941 val:1; /** valid - contents of CQE are valid */
2943 #error big endian version not defined
2949 * @brief Asynchronous Completion Queue Entry
2951 * A CQE generated asynchronously in response to the link or other internal events.
2953 typedef struct sli4_acqe_s {
2954 #if BYTE_ORDER == LITTLE_ENDIAN
2955 uint32_t event_data[3];
2958 event_type:8, /** values are protocol specific */
2960 ae:1, /** async event - this is an ACQE */
2961 val:1; /** valid - contents of CQE are valid */
2963 #error big endian version not defined
2967 #define SLI4_ACQE_EVENT_CODE_LINK_STATE 0x01
2968 #define SLI4_ACQE_EVENT_CODE_FCOE_FIP 0x02
2969 #define SLI4_ACQE_EVENT_CODE_DCBX 0x03
2970 #define SLI4_ACQE_EVENT_CODE_ISCSI 0x04
2971 #define SLI4_ACQE_EVENT_CODE_GRP_5 0x05
2972 #define SLI4_ACQE_EVENT_CODE_FC_LINK_EVENT 0x10
2973 #define SLI4_ACQE_EVENT_CODE_SLI_PORT_EVENT 0x11
2974 #define SLI4_ACQE_EVENT_CODE_VF_EVENT 0x12
2975 #define SLI4_ACQE_EVENT_CODE_MR_EVENT 0x13
2978 * @brief Register name enums
2982 SLI4_REG_EQCQ_DOORBELL,
2983 SLI4_REG_FCOE_RQ_DOORBELL,
2984 SLI4_REG_IO_WQ_DOORBELL,
2985 SLI4_REG_MQ_DOORBELL,
2986 SLI4_REG_PHYSDEV_CONTROL,
2987 SLI4_REG_SLIPORT_CONTROL,
2988 SLI4_REG_SLIPORT_ERROR1,
2989 SLI4_REG_SLIPORT_ERROR2,
2990 SLI4_REG_SLIPORT_SEMAPHORE,
2991 SLI4_REG_SLIPORT_STATUS,
2992 SLI4_REG_UERR_MASK_HI,
2993 SLI4_REG_UERR_MASK_LO,
2994 SLI4_REG_UERR_STATUS_HI,
2995 SLI4_REG_UERR_STATUS_LO,
2996 SLI4_REG_SW_UE_CSR1,
2997 SLI4_REG_SW_UE_CSR2,
2998 SLI4_REG_MAX /* must be last */
3001 typedef struct sli4_reg_s {
3012 SLI_QTYPE_MAX, /* must be last */
3015 #define SLI_USER_MQ_COUNT 1 /** User specified max mail queues */
3016 #define SLI_MAX_CQ_SET_COUNT 16
3017 #define SLI_MAX_RQ_SET_COUNT 16
3024 SLI_QENTRY_WQ_RELEASE,
3025 SLI_QENTRY_OPT_WRITE_CMD,
3026 SLI_QENTRY_OPT_WRITE_DATA,
3028 SLI_QENTRY_MAX /* must be last */
3031 typedef struct sli4_queue_s {
3032 /* Common to all queue types */
3035 uint32_t index; /** current host entry index */
3036 uint16_t size; /** entry size */
3037 uint16_t length; /** number of entries */
3038 uint16_t n_posted; /** number entries posted */
3039 uint16_t id; /** Port assigned xQ_ID */
3040 uint16_t ulp; /** ULP assigned to this queue */
3041 uint32_t doorbell_offset;/** The offset for the doorbell */
3042 uint16_t doorbell_rset; /** register set for the doorbell */
3043 uint8_t type; /** queue type ie EQ, CQ, ... */
3044 uint32_t proc_limit; /** limit number of CQE processed per iteration */
3045 uint32_t posted_limit; /** number of CQE/EQE to process before ringing doorbell */
3046 uint32_t max_num_processed;
3047 time_t max_process_time;
3049 /* Type specific gunk */
3051 uint32_t r_idx; /** "read" index (MQ only) */
3053 uint32_t is_mq:1,/** CQ contains MQ/Async completions */
3054 is_hdr:1,/** is a RQ for packet headers */
3055 rq_batch:1;/** RQ index incremented by 8 */
3061 sli_queue_lock(sli4_queue_t *q)
3067 sli_queue_unlock(sli4_queue_t *q)
3069 ocs_unlock(&q->lock);
3073 #define SLI4_QUEUE_DEFAULT_CQ UINT16_MAX /** Use the default CQ */
3075 #define SLI4_QUEUE_RQ_BATCH 8
3080 SLI4_CB_MAX /* must be last */
3085 SLI_LINK_STATUS_DOWN,
3086 SLI_LINK_STATUS_NO_ALPA,
3087 SLI_LINK_STATUS_MAX,
3088 } sli4_link_status_e;
3091 SLI_LINK_TOPO_NPORT = 1, /** fabric or point-to-point */
3093 SLI_LINK_TOPO_LOOPBACK_INTERNAL,
3094 SLI_LINK_TOPO_LOOPBACK_EXTERNAL,
3097 } sli4_link_topology_e;
3099 /* TODO do we need both sli4_port_type_e & sli4_link_medium_e */
3101 SLI_LINK_MEDIUM_ETHERNET,
3103 SLI_LINK_MEDIUM_MAX,
3104 } sli4_link_medium_e;
3106 typedef struct sli4_link_event_s {
3107 sli4_link_status_e status; /* link up/down */
3108 sli4_link_topology_e topology;
3109 sli4_link_medium_e medium; /* Ethernet / FC */
3110 uint32_t speed; /* Mbps */
3113 } sli4_link_event_t;
3116 * @brief Fields retrieved from skyhawk that used used to build chained SGL
3118 typedef struct sli4_sgl_chaining_params_s {
3119 uint8_t chaining_capable;
3120 uint16_t frag_num_field_offset;
3121 uint16_t sgl_index_field_offset;
3122 uint64_t frag_num_field_mask;
3123 uint64_t sgl_index_field_mask;
3124 uint32_t chain_sge_initial_value_lo;
3125 uint32_t chain_sge_initial_value_hi;
3126 } sli4_sgl_chaining_params_t;
3128 typedef struct sli4_fip_event_s {
3130 uint32_t index; /* FCF index or UINT32_MAX if invalid */
3139 SLI_RSRC_MAX /* must be last */
3145 SLI4_PORT_TYPE_MAX /* must be last */
3149 SLI4_ASIC_TYPE_BE3 = 1,
3150 SLI4_ASIC_TYPE_SKYHAWK,
3151 SLI4_ASIC_TYPE_LANCER,
3152 SLI4_ASIC_TYPE_CORSAIR,
3153 SLI4_ASIC_TYPE_LANCERG6,
3157 SLI4_ASIC_REV_FPGA = 1,
3168 typedef struct sli4_s {
3170 sli4_port_type_e port_type;
3172 uint32_t sli_rev; /* SLI revision number */
3173 uint32_t sli_family;
3174 uint32_t if_type; /* SLI Interface type */
3176 sli4_asic_type_e asic_type; /*<< ASIC type */
3177 sli4_asic_rev_e asic_rev; /*<< ASIC revision */
3178 uint32_t physical_port;
3183 uint16_t max_qcount[SLI_QTYPE_MAX];
3184 uint32_t max_qentries[SLI_QTYPE_MAX];
3185 uint16_t count_mask[SLI_QTYPE_MAX];
3186 uint16_t count_method[SLI_QTYPE_MAX];
3187 uint32_t qpage_count[SLI_QTYPE_MAX];
3188 uint16_t link_module_type;
3190 uint16_t rq_min_buf_size;
3191 uint32_t rq_max_buf_size;
3196 uint8_t fw_name[2][16];
3199 uint8_t port_number;
3201 char bios_version_string[32];
3202 uint8_t dual_ulp_capable;
3203 uint8_t is_ulp_fc[2];
3205 * Tracks the port resources using extents metaphor. For
3206 * devices that don't implement extents (i.e.
3207 * has_extents == FALSE), the code models each resource as
3208 * a single large extent.
3211 uint32_t number; /* number of extents */
3212 uint32_t size; /* number of elements in each extent */
3213 uint32_t n_alloc;/* number of elements allocated */
3215 ocs_bitmap_t *use_map;/* bitmap showing resources in use */
3216 uint32_t map_size;/* number of bits in bitmap */
3217 } extent[SLI_RSRC_MAX];
3218 sli4_features_t features;
3219 uint32_t has_extents:1,
3224 perf_wq_id_association:1,
3225 cq_create_version:2,
3226 mq_create_version:2,
3228 sgl_pre_registered:1,
3229 sgl_pre_registration_required:1,
3230 t10_dif_inline_capable:1,
3231 t10_dif_separate_capable:1;
3232 uint32_t sge_supported_length;
3233 uint32_t sgl_page_sizes;
3234 uint32_t max_sgl_pages;
3235 sli4_sgl_chaining_params_t sgl_chaining_params;
3240 * Callback functions
3242 int32_t (*link)(void *, void *);
3244 int32_t (*fip)(void *, void *);
3248 #if defined(OCS_INCLUDE_DEBUG)
3249 /* Save pointer to physical memory descriptor for non-embedded SLI_CONFIG
3250 * commands for BMBX dumping purposes */
3251 ocs_dma_t *bmbx_non_emb_pmd;
3261 * Get / set parameter functions
3263 static inline uint32_t
3264 sli_get_max_rsrc(sli4_t *sli4, sli4_resource_e rsrc)
3266 if (rsrc >= SLI_RSRC_MAX) {
3270 return sli4->config.extent[rsrc].size;
3273 static inline uint32_t
3274 sli_get_max_queue(sli4_t *sli4, sli4_qtype_e qtype)
3276 if (qtype >= SLI_QTYPE_MAX) {
3279 return sli4->config.max_qcount[qtype];
3282 static inline uint32_t
3283 sli_get_max_qentries(sli4_t *sli4, sli4_qtype_e qtype)
3286 return sli4->config.max_qentries[qtype];
3289 static inline uint32_t
3290 sli_get_max_sge(sli4_t *sli4)
3292 return sli4->config.sge_supported_length;
3295 static inline uint32_t
3296 sli_get_max_sgl(sli4_t *sli4)
3299 if (sli4->config.sgl_page_sizes != 1) {
3300 ocs_log_test(sli4->os, "unsupported SGL page sizes %#x\n",
3301 sli4->config.sgl_page_sizes);
3305 return ((sli4->config.max_sgl_pages * SLI_PAGE_SIZE) / sizeof(sli4_sge_t));
3308 static inline sli4_link_medium_e
3309 sli_get_medium(sli4_t *sli4)
3311 switch (sli4->config.topology) {
3312 case SLI4_READ_CFG_TOPO_FCOE:
3313 return SLI_LINK_MEDIUM_ETHERNET;
3314 case SLI4_READ_CFG_TOPO_FC:
3315 case SLI4_READ_CFG_TOPO_FC_DA:
3316 case SLI4_READ_CFG_TOPO_FC_AL:
3317 return SLI_LINK_MEDIUM_FC;
3319 return SLI_LINK_MEDIUM_MAX;
3324 sli_skh_chain_sge_build(sli4_t *sli4, sli4_sge_t *sge, uint32_t xri_index, uint32_t frag_num, uint32_t offset)
3326 sli4_sgl_chaining_params_t *cparms = &sli4->config.sgl_chaining_params;
3329 ocs_memset(sge, 0, sizeof(*sge));
3330 sge->sge_type = SLI4_SGE_TYPE_CHAIN;
3331 sge->buffer_address_high = (uint32_t)cparms->chain_sge_initial_value_hi;
3332 sge->buffer_address_low =
3333 (uint32_t)((cparms->chain_sge_initial_value_lo |
3334 (((uintptr_t)(xri_index & cparms->sgl_index_field_mask)) <<
3335 cparms->sgl_index_field_offset) |
3336 (((uintptr_t)(frag_num & cparms->frag_num_field_mask)) <<
3337 cparms->frag_num_field_offset) |
3341 static inline uint32_t
3342 sli_get_sli_rev(sli4_t *sli4)
3344 return sli4->sli_rev;
3347 static inline uint32_t
3348 sli_get_sli_family(sli4_t *sli4)
3350 return sli4->sli_family;
3353 static inline uint32_t
3354 sli_get_if_type(sli4_t *sli4)
3356 return sli4->if_type;
3359 static inline void *
3360 sli_get_wwn_port(sli4_t *sli4)
3362 return sli4->config.wwpn;
3365 static inline void *
3366 sli_get_wwn_node(sli4_t *sli4)
3368 return sli4->config.wwnn;
3371 static inline void *
3372 sli_get_vpd(sli4_t *sli4)
3374 return sli4->vpd.data.virt;
3377 static inline uint32_t
3378 sli_get_vpd_len(sli4_t *sli4)
3380 return sli4->vpd.length;
3383 static inline uint32_t
3384 sli_get_fw_revision(sli4_t *sli4, uint32_t which)
3386 return sli4->config.fw_rev[which];
3389 static inline void *
3390 sli_get_fw_name(sli4_t *sli4, uint32_t which)
3392 return sli4->config.fw_name[which];
3395 static inline char *
3396 sli_get_ipl_name(sli4_t *sli4)
3398 return sli4->config.ipl_name;
3401 static inline uint32_t
3402 sli_get_hw_revision(sli4_t *sli4, uint32_t which)
3404 return sli4->config.hw_rev[which];
3407 static inline uint32_t
3408 sli_get_auto_xfer_rdy_capable(sli4_t *sli4)
3410 return sli4->config.auto_xfer_rdy;
3413 static inline uint32_t
3414 sli_get_dif_capable(sli4_t *sli4)
3416 return sli4->config.features.flag.dif;
3419 static inline uint32_t
3420 sli_is_dif_inline_capable(sli4_t *sli4)
3422 return sli_get_dif_capable(sli4) && sli4->config.t10_dif_inline_capable;
3425 static inline uint32_t
3426 sli_is_dif_separate_capable(sli4_t *sli4)
3428 return sli_get_dif_capable(sli4) && sli4->config.t10_dif_separate_capable;
3431 static inline uint32_t
3432 sli_get_is_dual_ulp_capable(sli4_t *sli4)
3434 return sli4->config.dual_ulp_capable;
3437 static inline uint32_t
3438 sli_get_is_sgl_chaining_capable(sli4_t *sli4)
3440 return sli4->config.sgl_chaining_params.chaining_capable;
3443 static inline uint32_t
3444 sli_get_is_ulp_enabled(sli4_t *sli4, uint16_t ulp)
3446 return sli4->config.is_ulp_fc[ulp];
3449 static inline uint32_t
3450 sli_get_hlm_capable(sli4_t *sli4)
3452 return sli4->config.features.flag.hlm;
3455 static inline int32_t
3456 sli_set_hlm(sli4_t *sli4, uint32_t value)
3458 if (value && !sli4->config.features.flag.hlm) {
3459 ocs_log_test(sli4->os, "HLM not supported\n");
3463 sli4->config.high_login_mode = value != 0 ? TRUE : FALSE;
3468 static inline uint32_t
3469 sli_get_hlm(sli4_t *sli4)
3471 return sli4->config.high_login_mode;
3474 static inline uint32_t
3475 sli_get_sgl_preregister_required(sli4_t *sli4)
3477 return sli4->config.sgl_pre_registration_required;
3480 static inline uint32_t
3481 sli_get_sgl_preregister(sli4_t *sli4)
3483 return sli4->config.sgl_pre_registered;
3486 static inline int32_t
3487 sli_set_sgl_preregister(sli4_t *sli4, uint32_t value)
3489 if ((value == 0) && sli4->config.sgl_pre_registration_required) {
3490 ocs_log_test(sli4->os, "SGL pre-registration required\n");
3494 sli4->config.sgl_pre_registered = value != 0 ? TRUE : FALSE;
3499 static inline sli4_asic_type_e
3500 sli_get_asic_type(sli4_t *sli4)
3502 return sli4->asic_type;
3505 static inline sli4_asic_rev_e
3506 sli_get_asic_rev(sli4_t *sli4)
3508 return sli4->asic_rev;
3511 static inline int32_t
3512 sli_set_topology(sli4_t *sli4, uint32_t value)
3517 case SLI4_READ_CFG_TOPO_FCOE:
3518 case SLI4_READ_CFG_TOPO_FC:
3519 case SLI4_READ_CFG_TOPO_FC_DA:
3520 case SLI4_READ_CFG_TOPO_FC_AL:
3521 sli4->config.topology = value;
3524 ocs_log_test(sli4->os, "unsupported topology %#x\n", value);
3531 static inline uint16_t
3532 sli_get_link_module_type(sli4_t *sli4)
3534 return sli4->config.link_module_type;
3537 static inline char *
3538 sli_get_portnum(sli4_t *sli4)
3540 return sli4->config.port_name;
3543 static inline char *
3544 sli_get_bios_version_string(sli4_t *sli4)
3546 return sli4->config.bios_version_string;
3549 static inline uint32_t
3550 sli_convert_mask_to_count(uint32_t method, uint32_t mask)
3555 count = 1 << ocs_lg2(mask);
3565 * @brief Common Create Queue function prototype
3567 typedef int32_t (*sli4_create_q_fn_t)(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t);
3570 * @brief Common Destroy Queue function prototype
3572 typedef int32_t (*sli4_destroy_q_fn_t)(sli4_t *, void *, size_t, uint16_t);
3575 /****************************************************************************
3576 * Function prototypes
3578 extern int32_t sli_cmd_config_auto_xfer_rdy(sli4_t *, void *, size_t, uint32_t);
3579 extern int32_t sli_cmd_config_auto_xfer_rdy_hp(sli4_t *, void *, size_t, uint32_t, uint32_t, uint32_t);
3580 extern int32_t sli_cmd_config_link(sli4_t *, void *, size_t);
3581 extern int32_t sli_cmd_down_link(sli4_t *, void *, size_t);
3582 extern int32_t sli_cmd_dump_type4(sli4_t *, void *, size_t, uint16_t);
3583 extern int32_t sli_cmd_common_read_transceiver_data(sli4_t *, void *, size_t, uint32_t, ocs_dma_t *);
3584 extern int32_t sli_cmd_read_link_stats(sli4_t *, void *, size_t,uint8_t, uint8_t, uint8_t);
3585 extern int32_t sli_cmd_read_status(sli4_t *sli4, void *buf, size_t size, uint8_t clear_counters);
3586 extern int32_t sli_cmd_init_link(sli4_t *, void *, size_t, uint32_t, uint8_t);
3587 extern int32_t sli_cmd_init_vfi(sli4_t *, void *, size_t, uint16_t, uint16_t, uint16_t);
3588 extern int32_t sli_cmd_init_vpi(sli4_t *, void *, size_t, uint16_t, uint16_t);
3589 extern int32_t sli_cmd_post_xri(sli4_t *, void *, size_t, uint16_t, uint16_t);
3590 extern int32_t sli_cmd_release_xri(sli4_t *, void *, size_t, uint8_t);
3591 extern int32_t sli_cmd_read_sparm64(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t);
3592 extern int32_t sli_cmd_read_topology(sli4_t *, void *, size_t, ocs_dma_t *);
3593 extern int32_t sli_cmd_read_nvparms(sli4_t *, void *, size_t);
3594 extern int32_t sli_cmd_write_nvparms(sli4_t *, void *, size_t, uint8_t *, uint8_t *, uint8_t, uint32_t);
3598 uint8_t r_ctl_match;
3601 } sli4_cmd_rq_cfg_t;
3602 extern int32_t sli_cmd_reg_fcfi(sli4_t *, void *, size_t, uint16_t,
3603 sli4_cmd_rq_cfg_t rq_cfg[SLI4_CMD_REG_FCFI_NUM_RQ_CFG], uint16_t);
3604 extern int32_t sli_cmd_reg_fcfi_mrq(sli4_t *, void *, size_t, uint8_t, uint16_t, uint16_t, uint8_t, uint8_t , uint16_t, sli4_cmd_rq_cfg_t *);
3606 extern int32_t sli_cmd_reg_rpi(sli4_t *, void *, size_t, uint32_t, uint16_t, uint16_t, ocs_dma_t *, uint8_t, uint8_t);
3607 extern int32_t sli_cmd_reg_vfi(sli4_t *, void *, size_t, ocs_domain_t *);
3608 extern int32_t sli_cmd_reg_vpi(sli4_t *, void *, size_t, ocs_sli_port_t *, uint8_t);
3609 extern int32_t sli_cmd_sli_config(sli4_t *, void *, size_t, uint32_t, ocs_dma_t *);
3610 extern int32_t sli_cmd_unreg_fcfi(sli4_t *, void *, size_t, uint16_t);
3611 extern int32_t sli_cmd_unreg_rpi(sli4_t *, void *, size_t, uint16_t, sli4_resource_e, uint32_t);
3612 extern int32_t sli_cmd_unreg_vfi(sli4_t *, void *, size_t, ocs_domain_t *, uint32_t);
3613 extern int32_t sli_cmd_unreg_vpi(sli4_t *, void *, size_t, uint16_t, uint32_t);
3614 extern int32_t sli_cmd_common_nop(sli4_t *, void *, size_t, uint64_t);
3615 extern int32_t sli_cmd_common_get_resource_extent_info(sli4_t *, void *, size_t, uint16_t);
3616 extern int32_t sli_cmd_common_get_sli4_parameters(sli4_t *, void *, size_t);
3617 extern int32_t sli_cmd_common_write_object(sli4_t *, void *, size_t,
3618 uint16_t, uint16_t, uint32_t, uint32_t, char *, ocs_dma_t *);
3619 extern int32_t sli_cmd_common_delete_object(sli4_t *, void *, size_t, char *);
3620 extern int32_t sli_cmd_common_read_object(sli4_t *, void *, size_t, uint32_t,
3621 uint32_t, char *, ocs_dma_t *);
3622 extern int32_t sli_cmd_dmtf_exec_clp_cmd(sli4_t *sli4, void *buf, size_t size,
3625 extern int32_t sli_cmd_common_set_dump_location(sli4_t *sli4, void *buf, size_t size,
3626 uint8_t query, uint8_t is_buffer_list,
3627 ocs_dma_t *buffer, uint8_t fdb);
3628 extern int32_t sli_cmd_common_set_features(sli4_t *, void *, size_t, uint32_t, uint32_t, void*);
3629 extern int32_t sli_cmd_common_get_profile_list(sli4_t *sli4, void *buf,
3630 size_t size, uint32_t start_profile_index, ocs_dma_t *dma);
3631 extern int32_t sli_cmd_common_get_active_profile(sli4_t *sli4, void *buf,
3633 extern int32_t sli_cmd_common_set_active_profile(sli4_t *sli4, void *buf,
3636 uint32_t active_profile_id);
3637 extern int32_t sli_cmd_common_get_reconfig_link_info(sli4_t *sli4, void *buf,
3638 size_t size, ocs_dma_t *dma);
3639 extern int32_t sli_cmd_common_set_reconfig_link_id(sli4_t *sli4, void *buf,
3640 size_t size, ocs_dma_t *dma,
3641 uint32_t fd, uint32_t active_link_config_id);
3642 extern int32_t sli_cmd_common_get_function_config(sli4_t *sli4, void *buf,
3644 extern int32_t sli_cmd_common_get_profile_config(sli4_t *sli4, void *buf,
3645 size_t size, ocs_dma_t *dma);
3646 extern int32_t sli_cmd_common_set_profile_config(sli4_t *sli4, void *buf,
3647 size_t size, ocs_dma_t *dma,
3648 uint8_t profile_id, uint32_t descriptor_count,
3651 extern int32_t sli_cqe_mq(void *);
3652 extern int32_t sli_cqe_async(sli4_t *, void *);
3654 extern int32_t sli_setup(sli4_t *, ocs_os_handle_t, sli4_port_type_e);
3655 extern void sli_calc_max_qentries(sli4_t *sli4);
3656 extern int32_t sli_init(sli4_t *);
3657 extern int32_t sli_reset(sli4_t *);
3658 extern int32_t sli_fw_reset(sli4_t *);
3659 extern int32_t sli_teardown(sli4_t *);
3660 extern int32_t sli_callback(sli4_t *, sli4_callback_e, void *, void *);
3661 extern int32_t sli_bmbx_command(sli4_t *);
3662 extern int32_t __sli_queue_init(sli4_t *, sli4_queue_t *, uint32_t, size_t, uint32_t, uint32_t);
3663 extern int32_t __sli_create_queue(sli4_t *, sli4_queue_t *);
3664 extern int32_t sli_eq_modify_delay(sli4_t *sli4, sli4_queue_t *eq, uint32_t num_eq, uint32_t shift, uint32_t delay_mult);
3665 extern int32_t sli_queue_alloc(sli4_t *, uint32_t, sli4_queue_t *, uint32_t, sli4_queue_t *, uint16_t);
3666 extern int32_t sli_cq_alloc_set(sli4_t *, sli4_queue_t *qs[], uint32_t, uint32_t, sli4_queue_t *eqs[]);
3667 extern int32_t sli_get_queue_entry_size(sli4_t *, uint32_t);
3668 extern int32_t sli_queue_free(sli4_t *, sli4_queue_t *, uint32_t, uint32_t);
3669 extern int32_t sli_queue_reset(sli4_t *, sli4_queue_t *);
3670 extern int32_t sli_queue_is_empty(sli4_t *, sli4_queue_t *);
3671 extern int32_t sli_queue_eq_arm(sli4_t *, sli4_queue_t *, uint8_t);
3672 extern int32_t sli_queue_arm(sli4_t *, sli4_queue_t *, uint8_t);
3673 extern int32_t _sli_queue_write(sli4_t *, sli4_queue_t *, uint8_t *);
3674 extern int32_t sli_queue_write(sli4_t *, sli4_queue_t *, uint8_t *);
3675 extern int32_t sli_queue_read(sli4_t *, sli4_queue_t *, uint8_t *);
3676 extern int32_t sli_queue_index(sli4_t *, sli4_queue_t *);
3677 extern int32_t _sli_queue_poke(sli4_t *, sli4_queue_t *, uint32_t, uint8_t *);
3678 extern int32_t sli_queue_poke(sli4_t *, sli4_queue_t *, uint32_t, uint8_t *);
3679 extern int32_t sli_resource_alloc(sli4_t *, sli4_resource_e, uint32_t *, uint32_t *);
3680 extern int32_t sli_resource_free(sli4_t *, sli4_resource_e, uint32_t);
3681 extern int32_t sli_resource_reset(sli4_t *, sli4_resource_e);
3682 extern int32_t sli_eq_parse(sli4_t *, uint8_t *, uint16_t *);
3683 extern int32_t sli_cq_parse(sli4_t *, sli4_queue_t *, uint8_t *, sli4_qentry_e *, uint16_t *);
3685 extern int32_t sli_raise_ue(sli4_t *, uint8_t);
3686 extern int32_t sli_dump_is_ready(sli4_t *);
3687 extern int32_t sli_dump_is_present(sli4_t *);
3688 extern int32_t sli_reset_required(sli4_t *);
3689 extern int32_t sli_fw_error_status(sli4_t *);
3690 extern int32_t sli_fw_ready(sli4_t *);
3691 extern uint32_t sli_reg_read(sli4_t *, sli4_regname_e);
3692 extern void sli_reg_write(sli4_t *, sli4_regname_e, uint32_t);
3693 extern int32_t sli_link_is_configurable(sli4_t *);
3695 #include "ocs_fcp.h"
3698 * @brief Maximum value for a FCFI
3700 * Note that although most commands provide a 16 bit field for the FCFI,
3701 * the FC/FCoE Asynchronous Recived CQE format only provides 6 bits for
3702 * the returned FCFI. Then effectively, the FCFI cannot be larger than
3705 #define SLI4_MAX_FCFI 64
3708 * @brief Maximum value for FCF index
3710 * The SLI-4 specification uses a 16 bit field in most places for the FCF
3711 * index, but practically, this value will be much smaller. Arbitrarily
3712 * limit the max FCF index to match the max FCFI value.
3714 #define SLI4_MAX_FCF_INDEX SLI4_MAX_FCFI
3716 /*************************************************************************
3717 * SLI-4 FC/FCoE mailbox command formats and definitions.
3721 * FC/FCoE opcode (OPC) values.
3723 #define SLI4_OPC_FCOE_WQ_CREATE 0x1
3724 #define SLI4_OPC_FCOE_WQ_DESTROY 0x2
3725 #define SLI4_OPC_FCOE_POST_SGL_PAGES 0x3
3726 #define SLI4_OPC_FCOE_RQ_CREATE 0x5
3727 #define SLI4_OPC_FCOE_RQ_DESTROY 0x6
3728 #define SLI4_OPC_FCOE_READ_FCF_TABLE 0x8
3729 #define SLI4_OPC_FCOE_POST_HDR_TEMPLATES 0xb
3730 #define SLI4_OPC_FCOE_REDISCOVER_FCF 0x10
3732 /* Use the default CQ associated with the WQ */
3733 #define SLI4_CQ_DEFAULT 0xffff
3735 typedef struct sli4_physical_page_descriptor_s {
3738 } sli4_physical_page_descriptor_t;
3741 * @brief FCOE_WQ_CREATE
3743 * Create a Work Queue for FC/FCoE use.
3745 #define SLI4_FCOE_WQ_CREATE_V0_MAX_PAGES 4
3747 typedef struct sli4_req_fcoe_wq_create_s {
3749 #if BYTE_ORDER == LITTLE_ENDIAN
3750 uint32_t num_pages:8,
3754 sli4_physical_page_descriptor_t page_physical_address[SLI4_FCOE_WQ_CREATE_V0_MAX_PAGES];
3760 #error big endian version not defined
3762 } sli4_req_fcoe_wq_create_t;
3765 * @brief FCOE_WQ_CREATE_V1
3767 * Create a version 1 Work Queue for FC/FCoE use.
3769 typedef struct sli4_req_fcoe_wq_create_v1_s {
3771 #if BYTE_ORDER == LITTLE_ENDIAN
3772 uint32_t num_pages:16,
3774 uint32_t page_size:8,
3779 sli4_physical_page_descriptor_t page_physical_address[8];
3781 #error big endian version not defined
3783 } sli4_req_fcoe_wq_create_v1_t;
3785 #define SLI4_FCOE_WQ_CREATE_V1_MAX_PAGES 8
3788 * @brief FCOE_WQ_DESTROY
3790 * Destroy an FC/FCoE Work Queue.
3792 typedef struct sli4_req_fcoe_wq_destroy_s {
3794 #if BYTE_ORDER == LITTLE_ENDIAN
3798 #error big endian version not defined
3800 } sli4_req_fcoe_wq_destroy_t;
3803 * @brief FCOE_POST_SGL_PAGES
3805 * Register the scatter gather list (SGL) memory and associate it with an XRI.
3807 typedef struct sli4_req_fcoe_post_sgl_pages_s {
3809 #if BYTE_ORDER == LITTLE_ENDIAN
3810 uint32_t xri_start:16,
3814 uint32_t page0_high;
3816 uint32_t page1_high;
3819 #error big endian version not defined
3821 } sli4_req_fcoe_post_sgl_pages_t;
3824 * @brief FCOE_RQ_CREATE
3826 * Create a Receive Queue for FC/FCoE use.
3828 typedef struct sli4_req_fcoe_rq_create_s {
3830 #if BYTE_ORDER == LITTLE_ENDIAN
3831 uint32_t num_pages:16,
3840 uint32_t buffer_size:16,
3843 sli4_physical_page_descriptor_t page_physical_address[8];
3845 #error big endian version not defined
3847 } sli4_req_fcoe_rq_create_t;
3849 #define SLI4_FCOE_RQ_CREATE_V0_MAX_PAGES 8
3850 #define SLI4_FCOE_RQ_CREATE_V0_MIN_BUF_SIZE 128
3851 #define SLI4_FCOE_RQ_CREATE_V0_MAX_BUF_SIZE 2048
3854 * @brief FCOE_RQ_CREATE_V1
3856 * Create a version 1 Receive Queue for FC/FCoE use.
3858 typedef struct sli4_req_fcoe_rq_create_v1_s {
3860 #if BYTE_ORDER == LITTLE_ENDIAN
3861 uint32_t num_pages:16,
3866 uint32_t page_size:8,
3873 uint32_t buffer_size;
3874 sli4_physical_page_descriptor_t page_physical_address[8];
3876 #error big endian version not defined
3878 } sli4_req_fcoe_rq_create_v1_t;
3882 * @brief FCOE_RQ_CREATE_V2
3884 * Create a version 2 Receive Queue for FC/FCoE use.
3886 typedef struct sli4_req_fcoe_rq_create_v2_s {
3888 #if BYTE_ORDER == LITTLE_ENDIAN
3889 uint32_t num_pages:16,
3895 uint32_t page_size:8,
3899 uint32_t hdr_buffer_size:16,
3900 payload_buffer_size:16;
3901 uint32_t base_cq_id:16,
3904 sli4_physical_page_descriptor_t page_physical_address[0];
3906 #error big endian version not defined
3908 } sli4_req_fcoe_rq_create_v2_t;
3911 #define SLI4_FCOE_RQ_CREATE_V1_MAX_PAGES 8
3912 #define SLI4_FCOE_RQ_CREATE_V1_MIN_BUF_SIZE 64
3913 #define SLI4_FCOE_RQ_CREATE_V1_MAX_BUF_SIZE 2048
3915 #define SLI4_FCOE_RQE_SIZE_8 0x2
3916 #define SLI4_FCOE_RQE_SIZE_16 0x3
3917 #define SLI4_FCOE_RQE_SIZE_32 0x4
3918 #define SLI4_FCOE_RQE_SIZE_64 0x5
3919 #define SLI4_FCOE_RQE_SIZE_128 0x6
3921 #define SLI4_FCOE_RQ_PAGE_SIZE_4096 0x1
3922 #define SLI4_FCOE_RQ_PAGE_SIZE_8192 0x2
3923 #define SLI4_FCOE_RQ_PAGE_SIZE_16384 0x4
3924 #define SLI4_FCOE_RQ_PAGE_SIZE_32768 0x8
3925 #define SLI4_FCOE_RQ_PAGE_SIZE_64536 0x10
3927 #define SLI4_FCOE_RQE_SIZE 8
3930 * @brief FCOE_RQ_DESTROY
3932 * Destroy an FC/FCoE Receive Queue.
3934 typedef struct sli4_req_fcoe_rq_destroy_s {
3936 #if BYTE_ORDER == LITTLE_ENDIAN
3940 #error big endian version not defined
3942 } sli4_req_fcoe_rq_destroy_t;
3945 * @brief FCOE_READ_FCF_TABLE
3947 * Retrieve a FCF database (also known as a table) entry created by the SLI Port
3948 * during FIP discovery.
3950 typedef struct sli4_req_fcoe_read_fcf_table_s {
3952 #if BYTE_ORDER == LITTLE_ENDIAN
3953 uint32_t fcf_index:16,
3956 #error big endian version not defined
3958 } sli4_req_fcoe_read_fcf_table_t;
3960 /* A FCF index of -1 on the request means return the first valid entry */
3961 #define SLI4_FCOE_FCF_TABLE_FIRST (UINT16_MAX)
3964 * @brief FCF table entry
3966 * This is the information returned by the FCOE_READ_FCF_TABLE command.
3968 typedef struct sli4_fcf_entry_s {
3969 #if BYTE_ORDER == LITTLE_ENDIAN
3970 uint32_t max_receive_size;
3971 uint32_t fip_keep_alive;
3972 uint32_t fip_priority;
3973 uint8_t fcf_mac_address[6];
3974 uint8_t fcf_available;
3975 uint8_t mac_address_provider;
3976 uint8_t fabric_name_id[8];
3982 uint32_t fcf_index:16,
3984 uint8_t vlan_bitmap[512];
3985 uint8_t switch_name[8];
3987 #error big endian version not defined
3992 * @brief FCOE_READ_FCF_TABLE response.
3994 typedef struct sli4_res_fcoe_read_fcf_table_s {
3996 #if BYTE_ORDER == LITTLE_ENDIAN
3998 uint32_t next_index:16,
4000 sli4_fcf_entry_t fcf_entry;
4002 #error big endian version not defined
4004 } sli4_res_fcoe_read_fcf_table_t;
4006 /* A next FCF index of -1 in the response means this is the last valid entry */
4007 #define SLI4_FCOE_FCF_TABLE_LAST (UINT16_MAX)
4011 * @brief FCOE_POST_HDR_TEMPLATES
4013 typedef struct sli4_req_fcoe_post_hdr_templates_s {
4015 #if BYTE_ORDER == LITTLE_ENDIAN
4016 uint32_t rpi_offset:16,
4018 sli4_physical_page_descriptor_t page_descriptor[0];
4020 #error big endian version not defined
4022 } sli4_req_fcoe_post_hdr_templates_t;
4024 #define SLI4_FCOE_HDR_TEMPLATE_SIZE 64
4027 * @brief FCOE_REDISCOVER_FCF
4029 typedef struct sli4_req_fcoe_rediscover_fcf_s {
4031 #if BYTE_ORDER == LITTLE_ENDIAN
4032 uint32_t fcf_count:16,
4035 uint16_t fcf_index[16];
4037 #error big endian version not defined
4039 } sli4_req_fcoe_rediscover_fcf_t;
4043 * Work Queue Entry (WQE) types.
4045 #define SLI4_WQE_ABORT 0x0f
4046 #define SLI4_WQE_ELS_REQUEST64 0x8a
4047 #define SLI4_WQE_FCP_IBIDIR64 0xac
4048 #define SLI4_WQE_FCP_IREAD64 0x9a
4049 #define SLI4_WQE_FCP_IWRITE64 0x98
4050 #define SLI4_WQE_FCP_ICMND64 0x9c
4051 #define SLI4_WQE_FCP_TRECEIVE64 0xa1
4052 #define SLI4_WQE_FCP_CONT_TRECEIVE64 0xe5
4053 #define SLI4_WQE_FCP_TRSP64 0xa3
4054 #define SLI4_WQE_FCP_TSEND64 0x9f
4055 #define SLI4_WQE_GEN_REQUEST64 0xc2
4056 #define SLI4_WQE_SEND_FRAME 0xe1
4057 #define SLI4_WQE_XMIT_BCAST64 0X84
4058 #define SLI4_WQE_XMIT_BLS_RSP 0x97
4059 #define SLI4_WQE_ELS_RSP64 0x95
4060 #define SLI4_WQE_XMIT_SEQUENCE64 0x82
4061 #define SLI4_WQE_REQUEUE_XRI 0x93
4064 * WQE command types.
4066 #define SLI4_CMD_FCP_IREAD64_WQE 0x00
4067 #define SLI4_CMD_FCP_ICMND64_WQE 0x00
4068 #define SLI4_CMD_FCP_IWRITE64_WQE 0x01
4069 #define SLI4_CMD_FCP_TRECEIVE64_WQE 0x02
4070 #define SLI4_CMD_FCP_TRSP64_WQE 0x03
4071 #define SLI4_CMD_FCP_TSEND64_WQE 0x07
4072 #define SLI4_CMD_GEN_REQUEST64_WQE 0x08
4073 #define SLI4_CMD_XMIT_BCAST64_WQE 0x08
4074 #define SLI4_CMD_XMIT_BLS_RSP64_WQE 0x08
4075 #define SLI4_CMD_ABORT_WQE 0x08
4076 #define SLI4_CMD_XMIT_SEQUENCE64_WQE 0x08
4077 #define SLI4_CMD_REQUEUE_XRI_WQE 0x0A
4078 #define SLI4_CMD_SEND_FRAME_WQE 0x0a
4080 #define SLI4_WQE_SIZE 0x05
4081 #define SLI4_WQE_EXT_SIZE 0x06
4083 #define SLI4_WQE_BYTES (16 * sizeof(uint32_t))
4084 #define SLI4_WQE_EXT_BYTES (32 * sizeof(uint32_t))
4086 /* Mask for ccp (CS_CTL) */
4087 #define SLI4_MASK_CCP 0xfe /* Upper 7 bits of CS_CTL is priority */
4090 * @brief Generic WQE
4092 typedef struct sli4_generic_wqe_s {
4093 #if BYTE_ORDER == LITTLE_ENDIAN
4094 uint32_t cmd_spec0_5[6];
4095 uint32_t xri_tag:16,
4107 uint32_t request_tag:16,
4109 uint32_t ebde_cnt:4,
4126 uint32_t cmd_type:4,
4132 #error big endian version not defined
4134 } sli4_generic_wqe_t;
4137 * @brief WQE used to abort exchanges.
4139 typedef struct sli4_abort_wqe_s {
4140 #if BYTE_ORDER == LITTLE_ENDIAN
4149 uint32_t ext_t_mask;
4151 uint32_t xri_tag:16,
4163 uint32_t request_tag:16,
4165 uint32_t ebde_cnt:4,
4182 uint32_t cmd_type:4,
4188 #error big endian version not defined
4192 #define SLI4_ABORT_CRITERIA_XRI_TAG 0x01
4193 #define SLI4_ABORT_CRITERIA_ABORT_TAG 0x02
4194 #define SLI4_ABORT_CRITERIA_REQUEST_TAG 0x03
4195 #define SLI4_ABORT_CRITERIA_EXT_ABORT_TAG 0x04
4200 SLI_ABORT_REQUEST_ID,
4201 SLI_ABORT_MAX, /* must be last */
4202 } sli4_abort_type_e;
4205 * @brief WQE used to create an ELS request.
4207 typedef struct sli4_els_request64_wqe_s {
4208 sli4_bde_t els_request_payload;
4209 #if BYTE_ORDER == LITTLE_ENDIAN
4210 uint32_t els_request_payload_length;
4214 uint32_t remote_id:24,
4216 uint32_t xri_tag:16,
4228 uint32_t request_tag:16,
4230 uint32_t ebde_cnt:4,
4247 uint32_t cmd_type:4,
4252 sli4_bde_t els_response_payload_bde;
4253 uint32_t max_response_payload_length;
4255 #error big endian version not defined
4257 } sli4_els_request64_wqe_t;
4259 #define SLI4_ELS_REQUEST64_CONTEXT_RPI 0x0
4260 #define SLI4_ELS_REQUEST64_CONTEXT_VPI 0x1
4261 #define SLI4_ELS_REQUEST64_CONTEXT_VFI 0x2
4262 #define SLI4_ELS_REQUEST64_CONTEXT_FCFI 0x3
4264 #define SLI4_ELS_REQUEST64_CLASS_2 0x1
4265 #define SLI4_ELS_REQUEST64_CLASS_3 0x2
4267 #define SLI4_ELS_REQUEST64_DIR_WRITE 0x0
4268 #define SLI4_ELS_REQUEST64_DIR_READ 0x1
4270 #define SLI4_ELS_REQUEST64_OTHER 0x0
4271 #define SLI4_ELS_REQUEST64_LOGO 0x1
4272 #define SLI4_ELS_REQUEST64_FDISC 0x2
4273 #define SLI4_ELS_REQUEST64_FLOGIN 0x3
4274 #define SLI4_ELS_REQUEST64_PLOGI 0x4
4276 #define SLI4_ELS_REQUEST64_CMD_GEN 0x08
4277 #define SLI4_ELS_REQUEST64_CMD_NON_FABRIC 0x0c
4278 #define SLI4_ELS_REQUEST64_CMD_FABRIC 0x0d
4281 * @brief WQE used to create an FCP initiator no data command.
4283 typedef struct sli4_fcp_icmnd64_wqe_s {
4285 #if BYTE_ORDER == LITTLE_ENDIAN
4286 uint32_t payload_offset_length:16,
4287 fcp_cmd_buffer_length:16;
4289 uint32_t remote_n_port_id:24,
4291 uint32_t xri_tag:16,
4305 uint32_t request_tag:16,
4307 uint32_t ebde_cnt:4,
4324 uint32_t cmd_type:4,
4334 #error big endian version not defined
4336 } sli4_fcp_icmnd64_wqe_t;
4339 * @brief WQE used to create an FCP initiator read.
4341 typedef struct sli4_fcp_iread64_wqe_s {
4343 #if BYTE_ORDER == LITTLE_ENDIAN
4344 uint32_t payload_offset_length:16,
4345 fcp_cmd_buffer_length:16;
4346 uint32_t total_transfer_length;
4347 uint32_t remote_n_port_id:24,
4349 uint32_t xri_tag:16,
4363 uint32_t request_tag:16,
4365 uint32_t ebde_cnt:4,
4382 uint32_t cmd_type:4,
4389 #error big endian version not defined
4391 sli4_bde_t first_data_bde; /* reserved if performance hints disabled */
4392 } sli4_fcp_iread64_wqe_t;
4395 * @brief WQE used to create an FCP initiator write.
4397 typedef struct sli4_fcp_iwrite64_wqe_s {
4399 #if BYTE_ORDER == LITTLE_ENDIAN
4400 uint32_t payload_offset_length:16,
4401 fcp_cmd_buffer_length:16;
4402 uint32_t total_transfer_length;
4403 uint32_t initial_transfer_length;
4404 uint32_t xri_tag:16,
4418 uint32_t request_tag:16,
4420 uint32_t ebde_cnt:4,
4437 uint32_t cmd_type:4,
4442 uint32_t remote_n_port_id:24,
4445 #error big endian version not defined
4447 sli4_bde_t first_data_bde;
4448 } sli4_fcp_iwrite64_wqe_t;
4451 typedef struct sli4_fcp_128byte_wqe_s {
4453 } sli4_fcp_128byte_wqe_t;
4456 * @brief WQE used to create an FCP target receive, and FCP target
4459 typedef struct sli4_fcp_treceive64_wqe_s {
4461 #if BYTE_ORDER == LITTLE_ENDIAN
4462 uint32_t payload_offset_length;
4463 uint32_t relative_offset;
4465 * DWord 5 can either be the task retry identifier (HLM=0) or
4466 * the remote N_Port ID (HLM=1), or if implementing the Skyhawk
4467 * T10-PI workaround, the secondary xri tag
4470 uint32_t sec_xri_tag:16,
4474 uint32_t xri_tag:16,
4488 uint32_t request_tag:16,
4490 uint32_t ebde_cnt:4,
4509 uint32_t cmd_type:4,
4514 uint32_t fcp_data_receive_length;
4517 #error big endian version not defined
4519 sli4_bde_t first_data_bde; /* For performance hints */
4521 } sli4_fcp_treceive64_wqe_t;
4524 * @brief WQE used to create an FCP target response.
4526 typedef struct sli4_fcp_trsp64_wqe_s {
4528 #if BYTE_ORDER == LITTLE_ENDIAN
4529 uint32_t fcp_response_length;
4532 * DWord 5 can either be the task retry identifier (HLM=0) or
4533 * the remote N_Port ID (HLM=1)
4536 uint32_t xri_tag:16,
4550 uint32_t request_tag:16,
4552 uint32_t ebde_cnt:4,
4571 uint32_t cmd_type:4,
4581 #error big endian version not defined
4583 } sli4_fcp_trsp64_wqe_t;
4586 * @brief WQE used to create an FCP target send (DATA IN).
4588 typedef struct sli4_fcp_tsend64_wqe_s {
4590 #if BYTE_ORDER == LITTLE_ENDIAN
4591 uint32_t payload_offset_length;
4592 uint32_t relative_offset;
4594 * DWord 5 can either be the task retry identifier (HLM=0) or
4595 * the remote N_Port ID (HLM=1)
4598 uint32_t xri_tag:16,
4612 uint32_t request_tag:16,
4614 uint32_t ebde_cnt:4,
4633 uint32_t cmd_type:4,
4638 uint32_t fcp_data_transmit_length;
4641 #error big endian version not defined
4643 sli4_bde_t first_data_bde; /* For performance hints */
4644 } sli4_fcp_tsend64_wqe_t;
4646 #define SLI4_IO_CONTINUATION BIT(0) /** The XRI associated with this IO is already active */
4647 #define SLI4_IO_AUTO_GOOD_RESPONSE BIT(1) /** Automatically generate a good RSP frame */
4648 #define SLI4_IO_NO_ABORT BIT(2)
4649 #define SLI4_IO_DNRX BIT(3) /** Set the DNRX bit because no auto xref rdy buffer is posted */
4651 /* WQE DIF field contents */
4652 #define SLI4_DIF_DISABLED 0
4653 #define SLI4_DIF_PASS_THROUGH 1
4654 #define SLI4_DIF_STRIP 2
4655 #define SLI4_DIF_INSERT 3
4658 * @brief WQE used to create a general request.
4660 typedef struct sli4_gen_request64_wqe_s {
4662 #if BYTE_ORDER == LITTLE_ENDIAN
4663 uint32_t request_payload_length;
4664 uint32_t relative_offset;
4669 uint32_t xri_tag:16,
4681 uint32_t request_tag:16,
4683 uint32_t ebde_cnt:4,
4700 uint32_t cmd_type:4,
4705 uint32_t remote_n_port_id:24,
4709 uint32_t max_response_payload_length;
4711 #error big endian version not defined
4713 } sli4_gen_request64_wqe_t;
4716 * @brief WQE used to create a send frame request.
4718 typedef struct sli4_send_frame_wqe_s {
4720 #if BYTE_ORDER == LITTLE_ENDIAN
4721 uint32_t frame_length;
4722 uint32_t fc_header_0_1[2];
4723 uint32_t xri_tag:16,
4735 uint32_t request_tag:16,
4738 uint32_t ebde_cnt:4,
4755 uint32_t cmd_type:4,
4760 uint32_t fc_header_2_5[4];
4762 #error big endian version not defined
4764 } sli4_send_frame_wqe_t;
4767 * @brief WQE used to create a transmit sequence.
4769 typedef struct sli4_xmit_sequence64_wqe_s {
4771 #if BYTE_ORDER == LITTLE_ENDIAN
4772 uint32_t remote_n_port_id:24,
4774 uint32_t relative_offset;
4784 uint32_t xri_tag:16,
4797 uint32_t request_tag:16,
4799 uint32_t ebde_cnt:4,
4816 uint32_t cmd_type:4,
4821 uint32_t sequence_payload_len;
4826 #error big endian version not defined
4828 } sli4_xmit_sequence64_wqe_t;
4831 * @brief WQE used unblock the specified XRI and to release it to the SLI Port's free pool.
4833 typedef struct sli4_requeue_xri_wqe_s {
4840 #if BYTE_ORDER == LITTLE_ENDIAN
4841 uint32_t xri_tag:16,
4853 uint32_t request_tag:16,
4855 uint32_t ebde_cnt:4,
4872 uint32_t cmd_type:4,
4882 #error big endian version not defined
4884 } sli4_requeue_xri_wqe_t;
4887 * @brief WQE used to send a single frame sequence to broadcast address
4889 typedef struct sli4_xmit_bcast64_wqe_s {
4890 sli4_bde_t sequence_payload;
4891 #if BYTE_ORDER == LITTLE_ENDIAN
4892 uint32_t sequence_payload_length;
4898 uint32_t xri_tag:16,
4910 uint32_t request_tag:16,
4912 uint32_t ebde_cnt:4,
4929 uint32_t cmd_type:4,
4939 #error big endian version not defined
4941 } sli4_xmit_bcast64_wqe_t;
4944 * @brief WQE used to create a BLS response.
4946 typedef struct sli4_xmit_bls_rsp_wqe_s {
4947 #if BYTE_ORDER == LITTLE_ENDIAN
4948 uint32_t payload_word0;
4951 uint32_t high_seq_cnt:16,
4954 uint32_t local_n_port_id:24,
4956 uint32_t remote_id:24,
4960 uint32_t xri_tag:16,
4972 uint32_t request_tag:16,
4974 uint32_t ebde_cnt:4,
4991 uint32_t cmd_type:4,
4996 uint32_t temporary_rpi:16,
5002 #error big endian version not defined
5004 } sli4_xmit_bls_rsp_wqe_t;
5012 typedef struct sli_bls_payload_s {
5013 sli_bls_type_e type;
5018 uint32_t seq_id_validity:8,
5023 uint16_t low_seq_cnt;
5024 uint16_t high_seq_cnt;
5027 uint32_t vendor_unique:8,
5028 reason_explanation:8,
5033 } sli_bls_payload_t;
5036 * @brief WQE used to create an ELS response.
5038 typedef struct sli4_xmit_els_rsp64_wqe_s {
5039 sli4_bde_t els_response_payload;
5040 #if BYTE_ORDER == LITTLE_ENDIAN
5041 uint32_t els_response_payload_length;
5045 uint32_t remote_id:24,
5047 uint32_t xri_tag:16,
5059 uint32_t request_tag:16,
5061 uint32_t ebde_cnt:4,
5078 uint32_t cmd_type:4,
5083 uint32_t temporary_rpi:16,
5089 #error big endian version not defined
5091 } sli4_xmit_els_rsp64_wqe_t;
5094 * @brief Asynchronouse Event: Link State ACQE.
5096 typedef struct sli4_link_state_s {
5097 #if BYTE_ORDER == LITTLE_ENDIAN
5098 uint32_t link_number:6,
5103 uint32_t port_fault:8,
5105 logical_link_speed:16;
5109 event_type:8, /** values are protocol specific */
5111 ae:1, /** async event - this is an ACQE */
5112 val:1; /** valid - contents of CQE are valid */
5114 #error big endian version not defined
5116 } sli4_link_state_t;
5119 #define SLI4_LINK_ATTN_TYPE_LINK_UP 0x01
5120 #define SLI4_LINK_ATTN_TYPE_LINK_DOWN 0x02
5121 #define SLI4_LINK_ATTN_TYPE_NO_HARD_ALPA 0x03
5123 #define SLI4_LINK_ATTN_P2P 0x01
5124 #define SLI4_LINK_ATTN_FC_AL 0x02
5125 #define SLI4_LINK_ATTN_INTERNAL_LOOPBACK 0x03
5126 #define SLI4_LINK_ATTN_SERDES_LOOPBACK 0x04
5128 #define SLI4_LINK_ATTN_1G 0x01
5129 #define SLI4_LINK_ATTN_2G 0x02
5130 #define SLI4_LINK_ATTN_4G 0x04
5131 #define SLI4_LINK_ATTN_8G 0x08
5132 #define SLI4_LINK_ATTN_10G 0x0a
5133 #define SLI4_LINK_ATTN_16G 0x10
5135 #define SLI4_LINK_TYPE_ETHERNET 0x0
5136 #define SLI4_LINK_TYPE_FC 0x1
5139 * @brief Asynchronouse Event: FC Link Attention Event.
5141 typedef struct sli4_link_attention_s {
5142 #if BYTE_ORDER == LITTLE_ENDIAN
5143 uint32_t link_number:8,
5147 uint32_t port_fault:8,
5148 shared_link_status:8,
5149 logical_link_speed:16;
5153 event_type:8, /** values are protocol specific */
5155 ae:1, /** async event - this is an ACQE */
5156 val:1; /** valid - contents of CQE are valid */
5158 #error big endian version not defined
5160 } sli4_link_attention_t;
5163 * @brief FC/FCoE event types.
5165 #define SLI4_LINK_STATE_PHYSICAL 0x00
5166 #define SLI4_LINK_STATE_LOGICAL 0x01
5168 #define SLI4_FCOE_FIP_FCF_DISCOVERED 0x01
5169 #define SLI4_FCOE_FIP_FCF_TABLE_FULL 0x02
5170 #define SLI4_FCOE_FIP_FCF_DEAD 0x03
5171 #define SLI4_FCOE_FIP_FCF_CLEAR_VLINK 0x04
5172 #define SLI4_FCOE_FIP_FCF_MODIFIED 0x05
5174 #define SLI4_GRP5_QOS_SPEED 0x01
5176 #define SLI4_FC_EVENT_LINK_ATTENTION 0x01
5177 #define SLI4_FC_EVENT_SHARED_LINK_ATTENTION 0x02
5179 #define SLI4_PORT_SPEED_NO_LINK 0x0
5180 #define SLI4_PORT_SPEED_10_MBPS 0x1
5181 #define SLI4_PORT_SPEED_100_MBPS 0x2
5182 #define SLI4_PORT_SPEED_1_GBPS 0x3
5183 #define SLI4_PORT_SPEED_10_GBPS 0x4
5185 #define SLI4_PORT_DUPLEX_NONE 0x0
5186 #define SLI4_PORT_DUPLEX_HWF 0x1
5187 #define SLI4_PORT_DUPLEX_FULL 0x2
5189 #define SLI4_PORT_LINK_STATUS_PHYSICAL_DOWN 0x0
5190 #define SLI4_PORT_LINK_STATUS_PHYSICAL_UP 0x1
5191 #define SLI4_PORT_LINK_STATUS_LOGICAL_DOWN 0x2
5192 #define SLI4_PORT_LINK_STATUS_LOGICAL_UP 0x3
5195 * @brief Asynchronouse Event: FCoE/FIP ACQE.
5197 typedef struct sli4_fcoe_fip_s {
5198 #if BYTE_ORDER == LITTLE_ENDIAN
5199 uint32_t event_information;
5200 uint32_t fcf_count:16,
5205 event_type:8, /** values are protocol specific */
5207 ae:1, /** async event - this is an ACQE */
5208 val:1; /** valid - contents of CQE are valid */
5210 #error big endian version not defined
5215 * @brief FC/FCoE WQ completion queue entry.
5217 typedef struct sli4_fc_wcqe_s {
5218 #if BYTE_ORDER == LITTLE_ENDIAN
5219 uint32_t hw_status:8,
5222 uint32_t wqe_specific_1;
5223 uint32_t wqe_specific_2;
5233 #error big endian version not defined
5238 * @brief FC/FCoE WQ consumed CQ queue entry.
5240 typedef struct sli4_fc_wqec_s {
5241 #if BYTE_ORDER == LITTLE_ENDIAN
5244 uint32_t wqe_index:16,
5251 #error big endian version not defined
5256 * @brief FC/FCoE Completion Status Codes.
5258 #define SLI4_FC_WCQE_STATUS_SUCCESS 0x00
5259 #define SLI4_FC_WCQE_STATUS_FCP_RSP_FAILURE 0x01
5260 #define SLI4_FC_WCQE_STATUS_REMOTE_STOP 0x02
5261 #define SLI4_FC_WCQE_STATUS_LOCAL_REJECT 0x03
5262 #define SLI4_FC_WCQE_STATUS_NPORT_RJT 0x04
5263 #define SLI4_FC_WCQE_STATUS_FABRIC_RJT 0x05
5264 #define SLI4_FC_WCQE_STATUS_NPORT_BSY 0x06
5265 #define SLI4_FC_WCQE_STATUS_FABRIC_BSY 0x07
5266 #define SLI4_FC_WCQE_STATUS_LS_RJT 0x09
5267 #define SLI4_FC_WCQE_STATUS_CMD_REJECT 0x0b
5268 #define SLI4_FC_WCQE_STATUS_FCP_TGT_LENCHECK 0x0c
5269 #define SLI4_FC_WCQE_STATUS_RQ_BUF_LEN_EXCEEDED 0x11
5270 #define SLI4_FC_WCQE_STATUS_RQ_INSUFF_BUF_NEEDED 0x12
5271 #define SLI4_FC_WCQE_STATUS_RQ_INSUFF_FRM_DISC 0x13
5272 #define SLI4_FC_WCQE_STATUS_RQ_DMA_FAILURE 0x14
5273 #define SLI4_FC_WCQE_STATUS_FCP_RSP_TRUNCATE 0x15
5274 #define SLI4_FC_WCQE_STATUS_DI_ERROR 0x16
5275 #define SLI4_FC_WCQE_STATUS_BA_RJT 0x17
5276 #define SLI4_FC_WCQE_STATUS_RQ_INSUFF_XRI_NEEDED 0x18
5277 #define SLI4_FC_WCQE_STATUS_RQ_INSUFF_XRI_DISC 0x19
5278 #define SLI4_FC_WCQE_STATUS_RX_ERROR_DETECT 0x1a
5279 #define SLI4_FC_WCQE_STATUS_RX_ABORT_REQUEST 0x1b
5281 /* driver generated status codes; better not overlap with chip's status codes! */
5282 #define SLI4_FC_WCQE_STATUS_TARGET_WQE_TIMEOUT 0xff
5283 #define SLI4_FC_WCQE_STATUS_SHUTDOWN 0xfe
5284 #define SLI4_FC_WCQE_STATUS_DISPATCH_ERROR 0xfd
5287 * @brief DI_ERROR Extended Status
5289 #define SLI4_FC_DI_ERROR_GE (1 << 0) /* Guard Error */
5290 #define SLI4_FC_DI_ERROR_AE (1 << 1) /* Application Tag Error */
5291 #define SLI4_FC_DI_ERROR_RE (1 << 2) /* Reference Tag Error */
5292 #define SLI4_FC_DI_ERROR_TDPV (1 << 3) /* Total Data Placed Valid */
5293 #define SLI4_FC_DI_ERROR_UDB (1 << 4) /* Uninitialized DIF Block */
5294 #define SLI4_FC_DI_ERROR_EDIR (1 << 5) /* Error direction */
5297 * @brief Local Reject Reason Codes.
5299 #define SLI4_FC_LOCAL_REJECT_MISSING_CONTINUE 0x01
5300 #define SLI4_FC_LOCAL_REJECT_SEQUENCE_TIMEOUT 0x02
5301 #define SLI4_FC_LOCAL_REJECT_INTERNAL_ERROR 0x03
5302 #define SLI4_FC_LOCAL_REJECT_INVALID_RPI 0x04
5303 #define SLI4_FC_LOCAL_REJECT_NO_XRI 0x05
5304 #define SLI4_FC_LOCAL_REJECT_ILLEGAL_COMMAND 0x06
5305 #define SLI4_FC_LOCAL_REJECT_XCHG_DROPPED 0x07
5306 #define SLI4_FC_LOCAL_REJECT_ILLEGAL_FIELD 0x08
5307 #define SLI4_FC_LOCAL_REJECT_NO_ABORT_MATCH 0x0c
5308 #define SLI4_FC_LOCAL_REJECT_TX_DMA_FAILED 0x0d
5309 #define SLI4_FC_LOCAL_REJECT_RX_DMA_FAILED 0x0e
5310 #define SLI4_FC_LOCAL_REJECT_ILLEGAL_FRAME 0x0f
5311 #define SLI4_FC_LOCAL_REJECT_NO_RESOURCES 0x11
5312 #define SLI4_FC_LOCAL_REJECT_FCP_CONF_FAILURE 0x12
5313 #define SLI4_FC_LOCAL_REJECT_ILLEGAL_LENGTH 0x13
5314 #define SLI4_FC_LOCAL_REJECT_UNSUPPORTED_FEATURE 0x14
5315 #define SLI4_FC_LOCAL_REJECT_ABORT_IN_PROGRESS 0x15
5316 #define SLI4_FC_LOCAL_REJECT_ABORT_REQUESTED 0x16
5317 #define SLI4_FC_LOCAL_REJECT_RCV_BUFFER_TIMEOUT 0x17
5318 #define SLI4_FC_LOCAL_REJECT_LOOP_OPEN_FAILURE 0x18
5319 #define SLI4_FC_LOCAL_REJECT_LINK_DOWN 0x1a
5320 #define SLI4_FC_LOCAL_REJECT_CORRUPTED_DATA 0x1b
5321 #define SLI4_FC_LOCAL_REJECT_CORRUPTED_RPI 0x1c
5322 #define SLI4_FC_LOCAL_REJECT_OUT_OF_ORDER_DATA 0x1d
5323 #define SLI4_FC_LOCAL_REJECT_OUT_OF_ORDER_ACK 0x1e
5324 #define SLI4_FC_LOCAL_REJECT_DUP_FRAME 0x1f
5325 #define SLI4_FC_LOCAL_REJECT_LINK_CONTROL_FRAME 0x20
5326 #define SLI4_FC_LOCAL_REJECT_BAD_HOST_ADDRESS 0x21
5327 #define SLI4_FC_LOCAL_REJECT_MISSING_HDR_BUFFER 0x23
5328 #define SLI4_FC_LOCAL_REJECT_MSEQ_CHAIN_CORRUPTED 0x24
5329 #define SLI4_FC_LOCAL_REJECT_ABORTMULT_REQUESTED 0x25
5330 #define SLI4_FC_LOCAL_REJECT_BUFFER_SHORTAGE 0x28
5331 #define SLI4_FC_LOCAL_REJECT_RCV_XRIBUF_WAITING 0x29
5332 #define SLI4_FC_LOCAL_REJECT_INVALID_VPI 0x2e
5333 #define SLI4_FC_LOCAL_REJECT_MISSING_XRIBUF 0x30
5334 #define SLI4_FC_LOCAL_REJECT_INVALID_RELOFFSET 0x40
5335 #define SLI4_FC_LOCAL_REJECT_MISSING_RELOFFSET 0x41
5336 #define SLI4_FC_LOCAL_REJECT_INSUFF_BUFFERSPACE 0x42
5337 #define SLI4_FC_LOCAL_REJECT_MISSING_SI 0x43
5338 #define SLI4_FC_LOCAL_REJECT_MISSING_ES 0x44
5339 #define SLI4_FC_LOCAL_REJECT_INCOMPLETE_XFER 0x45
5340 #define SLI4_FC_LOCAL_REJECT_SLER_FAILURE 0x46
5341 #define SLI4_FC_LOCAL_REJECT_SLER_CMD_RCV_FAILURE 0x47
5342 #define SLI4_FC_LOCAL_REJECT_SLER_REC_RJT_ERR 0x48
5343 #define SLI4_FC_LOCAL_REJECT_SLER_REC_SRR_RETRY_ERR 0x49
5344 #define SLI4_FC_LOCAL_REJECT_SLER_SRR_RJT_ERR 0x4a
5345 #define SLI4_FC_LOCAL_REJECT_SLER_RRQ_RJT_ERR 0x4c
5346 #define SLI4_FC_LOCAL_REJECT_SLER_RRQ_RETRY_ERR 0x4d
5347 #define SLI4_FC_LOCAL_REJECT_SLER_ABTS_ERR 0x4e
5349 typedef struct sli4_fc_async_rcqe_s {
5350 #if BYTE_ORDER == LITTLE_ENDIAN
5353 rq_element_index:12,
5358 payload_data_placement_length:16;
5359 uint32_t sof_byte:8,
5362 header_data_placement_length:6,
5366 #error big endian version not defined
5368 } sli4_fc_async_rcqe_t;
5370 typedef struct sli4_fc_async_rcqe_v1_s {
5371 #if BYTE_ORDER == LITTLE_ENDIAN
5374 rq_element_index:12,
5379 payload_data_placement_length:16;
5380 uint32_t sof_byte:8,
5383 header_data_placement_length:6,
5387 #error big endian version not defined
5389 } sli4_fc_async_rcqe_v1_t;
5391 #define SLI4_FC_ASYNC_RQ_SUCCESS 0x10
5392 #define SLI4_FC_ASYNC_RQ_BUF_LEN_EXCEEDED 0x11
5393 #define SLI4_FC_ASYNC_RQ_INSUFF_BUF_NEEDED 0x12
5394 #define SLI4_FC_ASYNC_RQ_INSUFF_BUF_FRM_DISC 0x13
5395 #define SLI4_FC_ASYNC_RQ_DMA_FAILURE 0x14
5397 typedef struct sli4_fc_coalescing_rcqe_s {
5398 #if BYTE_ORDER == LITTLE_ENDIAN
5401 rq_element_index:12,
5405 sequence_reporting_placement_length:16;
5411 #error big endian version not defined
5413 } sli4_fc_coalescing_rcqe_t;
5415 #define SLI4_FC_COALESCE_RQ_SUCCESS 0x10
5416 #define SLI4_FC_COALESCE_RQ_INSUFF_XRI_NEEDED 0x18
5418 typedef struct sli4_fc_optimized_write_cmd_cqe_s {
5419 #if BYTE_ORDER == LITTLE_ENDIAN
5422 rq_element_index:15,
5430 payload_data_placement_length:16;
5433 header_data_placement_length:6,
5437 #error big endian version not defined
5439 } sli4_fc_optimized_write_cmd_cqe_t;
5441 typedef struct sli4_fc_optimized_write_data_cqe_s {
5442 #if BYTE_ORDER == LITTLE_ENDIAN
5443 uint32_t hw_status:8,
5446 uint32_t total_data_placed;
5447 uint32_t extended_status;
5457 #error big endian version not defined
5459 } sli4_fc_optimized_write_data_cqe_t;
5461 typedef struct sli4_fc_xri_aborted_cqe_s {
5462 #if BYTE_ORDER == LITTLE_ENDIAN
5466 uint32_t extended_status;
5478 #error big endian version not defined
5480 } sli4_fc_xri_aborted_cqe_t;
5483 * Code definitions applicable to all FC/FCoE CQE types.
5485 #define SLI4_CQE_CODE_OFFSET 14
5487 #define SLI4_CQE_CODE_WORK_REQUEST_COMPLETION 0x01
5488 #define SLI4_CQE_CODE_RELEASE_WQE 0x02
5489 #define SLI4_CQE_CODE_RQ_ASYNC 0x04
5490 #define SLI4_CQE_CODE_XRI_ABORTED 0x05
5491 #define SLI4_CQE_CODE_RQ_COALESCING 0x06
5492 #define SLI4_CQE_CODE_RQ_CONSUMPTION 0x07
5493 #define SLI4_CQE_CODE_MEASUREMENT_REPORTING 0x08
5494 #define SLI4_CQE_CODE_RQ_ASYNC_V1 0x09
5495 #define SLI4_CQE_CODE_OPTIMIZED_WRITE_CMD 0x0B
5496 #define SLI4_CQE_CODE_OPTIMIZED_WRITE_DATA 0x0C
5498 extern int32_t sli_fc_process_link_state(sli4_t *, void *);
5499 extern int32_t sli_fc_process_link_attention(sli4_t *, void *);
5500 extern int32_t sli_fc_cqe_parse(sli4_t *, sli4_queue_t *, uint8_t *, sli4_qentry_e *, uint16_t *);
5501 extern uint32_t sli_fc_response_length(sli4_t *, uint8_t *);
5502 extern uint32_t sli_fc_io_length(sli4_t *, uint8_t *);
5503 extern int32_t sli_fc_els_did(sli4_t *, uint8_t *, uint32_t *);
5504 extern uint32_t sli_fc_ext_status(sli4_t *, uint8_t *);
5505 extern int32_t sli_fc_rqe_rqid_and_index(sli4_t *, uint8_t *, uint16_t *, uint32_t *);
5506 extern int32_t sli_fc_process_fcoe(sli4_t *, void *);
5507 extern int32_t sli_cmd_fcoe_wq_create(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t);
5508 extern int32_t sli_cmd_fcoe_wq_create_v1(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t);
5509 extern int32_t sli_cmd_fcoe_wq_destroy(sli4_t *, void *, size_t, uint16_t);
5510 extern int32_t sli_cmd_fcoe_post_sgl_pages(sli4_t *, void *, size_t, uint16_t, uint32_t, ocs_dma_t **, ocs_dma_t **,
5512 extern int32_t sli_cmd_fcoe_rq_create(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t, uint16_t);
5513 extern int32_t sli_cmd_fcoe_rq_create_v1(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t, uint16_t);
5514 extern int32_t sli_cmd_fcoe_rq_destroy(sli4_t *, void *, size_t, uint16_t);
5515 extern int32_t sli_cmd_fcoe_read_fcf_table(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t);
5516 extern int32_t sli_cmd_fcoe_post_hdr_templates(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, ocs_dma_t *);
5517 extern int32_t sli_cmd_fcoe_rediscover_fcf(sli4_t *, void *, size_t, uint16_t);
5518 extern int32_t sli_fc_rq_alloc(sli4_t *, sli4_queue_t *, uint32_t, uint32_t, sli4_queue_t *, uint16_t, uint8_t);
5519 extern int32_t sli_fc_rq_set_alloc(sli4_t *, uint32_t, sli4_queue_t *[], uint32_t, uint32_t, uint32_t, uint32_t, uint16_t);
5520 extern uint32_t sli_fc_get_rpi_requirements(sli4_t *, uint32_t);
5521 extern int32_t sli_abort_wqe(sli4_t *, void *, size_t, sli4_abort_type_e, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t);
5523 extern int32_t sli_els_request64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint8_t, uint32_t, uint32_t, uint8_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *);
5524 extern int32_t sli_fcp_iread64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t);
5525 extern int32_t sli_fcp_iwrite64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t);
5526 extern int32_t sli_fcp_icmnd64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint8_t);
5528 extern int32_t sli_fcp_treceive64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint32_t, uint8_t, uint8_t, uint8_t, uint32_t);
5529 extern int32_t sli_fcp_trsp64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint32_t, uint8_t, uint8_t, uint32_t);
5530 extern int32_t sli_fcp_tsend64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint32_t, uint8_t, uint8_t, uint8_t, uint32_t);
5531 extern int32_t sli_fcp_cont_treceive64_wqe(sli4_t *, void*, size_t, ocs_dma_t *, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint32_t, uint8_t, uint8_t, uint8_t, uint32_t);
5532 extern int32_t sli_gen_request64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t,uint8_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t);
5533 extern int32_t sli_send_frame_wqe(sli4_t *sli4, void *buf, size_t size, uint8_t sof, uint8_t eof, uint32_t *hdr,
5534 ocs_dma_t *payload, uint32_t req_len, uint8_t timeout,
5535 uint16_t xri, uint16_t req_tag);
5536 extern int32_t sli_xmit_sequence64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint8_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t);
5537 extern int32_t sli_xmit_bcast64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint8_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t);
5538 extern int32_t sli_xmit_bls_rsp64_wqe(sli4_t *, void *, size_t, sli_bls_payload_t *, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint32_t);
5539 extern int32_t sli_xmit_els_rsp64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint32_t, uint32_t);
5540 extern int32_t sli_requeue_xri_wqe(sli4_t *, void *, size_t, uint16_t, uint16_t, uint16_t);
5541 extern void sli4_cmd_lowlevel_set_watchdog(sli4_t *sli4, void *buf, size_t size, uint16_t timeout);
5545 * @brief Retrieve the received header and payload length.
5547 * @param sli4 SLI context.
5548 * @param cqe Pointer to the CQ entry.
5549 * @param len_hdr Pointer where the header length is written.
5550 * @param len_data Pointer where the payload length is written.
5552 * @return Returns 0 on success, or a non-zero value on failure.
5554 static inline int32_t
5555 sli_fc_rqe_length(sli4_t *sli4, void *cqe, uint32_t *len_hdr, uint32_t *len_data)
5557 sli4_fc_async_rcqe_t *rcqe = cqe;
5559 *len_hdr = *len_data = 0;
5561 if (SLI4_FC_ASYNC_RQ_SUCCESS == rcqe->status) {
5562 *len_hdr = rcqe->header_data_placement_length;
5563 *len_data = rcqe->payload_data_placement_length;
5572 * @brief Retrieve the received FCFI.
5574 * @param sli4 SLI context.
5575 * @param cqe Pointer to the CQ entry.
5577 * @return Returns the FCFI in the CQE. or UINT8_MAX if invalid CQE code.
5579 static inline uint8_t
5580 sli_fc_rqe_fcfi(sli4_t *sli4, void *cqe)
5582 uint8_t code = ((uint8_t*)cqe)[SLI4_CQE_CODE_OFFSET];
5583 uint8_t fcfi = UINT8_MAX;
5586 case SLI4_CQE_CODE_RQ_ASYNC: {
5587 sli4_fc_async_rcqe_t *rcqe = cqe;
5591 case SLI4_CQE_CODE_RQ_ASYNC_V1: {
5592 sli4_fc_async_rcqe_v1_t *rcqev1 = cqe;
5593 fcfi = rcqev1->fcfi;
5596 case SLI4_CQE_CODE_OPTIMIZED_WRITE_CMD: {
5597 sli4_fc_optimized_write_cmd_cqe_t *opt_wr = cqe;
5598 fcfi = opt_wr->fcfi;
5606 extern const char *sli_fc_get_status_string(uint32_t status);
5608 #endif /* !_SLI4_H */