sys/dev/ocs_fc/sli4.h

   1 /*-
   2  * Copyright (c) 2017 Broadcom. All rights reserved.
   3  * The term "Broadcom" refers to Broadcom Limited and/or its subsidiaries.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright notice,
   9  *    this list of conditions and the following disclaimer.
  10  *
  11  * 2. Redistributions in binary form must reproduce the above copyright notice,
  12  *    this list of conditions and the following disclaimer in the documentation
  13  *    and/or other materials provided with the distribution.
  14  *
  15  * 3. Neither the name of the copyright holder nor the names of its contributors
  16  *    may be used to endorse or promote products derived from this software
  17  *    without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  *
  31  * $FreeBSD$
  32  */
  33
  34 /**
  35  * @file
  36  * Define common SLI-4 structures and function prototypes.
  37  */
  38
  39 #ifndef _SLI4_H
  40 #define _SLI4_H
  41
  42 #include "ocs_os.h"
  43
  44 #define SLI_PAGE_SIZE           (4096)
  45 #define SLI_SUB_PAGE_MASK       (SLI_PAGE_SIZE - 1)
  46 #define SLI_PAGE_SHIFT          12
  47 #define SLI_ROUND_PAGE(b)       (((b) + SLI_SUB_PAGE_MASK) & ~SLI_SUB_PAGE_MASK)
  48
  49 #define SLI4_BMBX_TIMEOUT_MSEC          30000
  50 #define SLI4_FW_READY_TIMEOUT_MSEC      30000
  51
  52 static inline uint32_t
  53 sli_page_count(size_t bytes, uint32_t page_size)
  54 {
  55         uint32_t        mask = page_size - 1;
  56         uint32_t        shift = 0;
  57
  58         switch (page_size) {
  59         case 4096:
  60                 shift = 12;
  61                 break;
  62         case 8192:
  63                 shift = 13;
  64                 break;
  65         case 16384:
  66                 shift = 14;
  67                 break;
  68         case 32768:
  69                 shift = 15;
  70                 break;
  71         case 65536:
  72                 shift = 16;
  73                 break;
  74         default:
  75                 return 0;
  76         }
  77
  78         return (bytes + mask) >> shift;
  79 }
  80
  81 /*************************************************************************
  82  * Common PCI configuration space register definitions
  83  */
  84
  85 #define SLI4_PCI_CLASS_REVISION         0x0008  /** register offset */
  86 #define SLI4_PCI_REV_ID_SHIFT                   0
  87 #define SLI4_PCI_REV_ID_MASK                    0xff
  88 #define SLI4_PCI_CLASS_SHIFT                    8
  89 #define SLI4_PCI_CLASS_MASK                     0xfff
  90
  91 #define SLI4_PCI_SOFT_RESET_CSR         0x005c  /** register offset */
  92 #define SLI4_PCI_SOFT_RESET_MASK                0x0080
  93
  94 /*************************************************************************
  95  * Common SLI-4 register offsets and field definitions
  96  */
  97
  98 /**
  99  * @brief SLI_INTF - SLI Interface Definition Register
 100  */
 101 #define SLI4_INTF_REG                   0x0058  /** register offset */
 102 #define SLI4_INTF_VALID_SHIFT                   29
 103 #define SLI4_INTF_VALID_MASK                    0x7
 104 #define SLI4_INTF_VALID                         0x6
 105 #define SLI4_INTF_IF_TYPE_SHIFT                 12
 106 #define SLI4_INTF_IF_TYPE_MASK                  0xf
 107 #define SLI4_INTF_SLI_FAMILY_SHIFT              8
 108 #define SLI4_INTF_SLI_FAMILY_MASK               0xf
 109 #define SLI4_INTF_SLI_REVISION_SHIFT            4
 110 #define SLI4_INTF_SLI_REVISION_MASK             0xf
 111 #define SLI4_FAMILY_CHECK_ASIC_TYPE             0xf
 112
 113 #define SLI4_IF_TYPE_BE3_SKH_PF         0
 114 #define SLI4_IF_TYPE_BE3_SKH_VF         1
 115 #define SLI4_IF_TYPE_LANCER_FC_ETH      2
 116 #define SLI4_IF_TYPE_LANCER_RDMA        3
 117 #define SLI4_IF_TYPE_LANCER_G7          6
 118 #define SLI4_MAX_IF_TYPES               7
 119
 120 /**
 121  * @brief ASIC_ID - SLI ASIC Type and Revision Register
 122  */
 123 #define SLI4_ASIC_ID_REG                        0x009c /* register offset */
 124 #define SLI4_ASIC_REV_SHIFT                     0
 125 #define SLI4_ASIC_REV_MASK                      0xf
 126 #define SLI4_ASIC_VER_SHIFT                     4
 127 #define SLI4_ASIC_VER_MASK                      0xf
 128 #define SLI4_ASIC_GEN_SHIFT                     8
 129 #define SLI4_ASIC_GEN_MASK                      0xff
 130 #define SLI4_ASIC_GEN_BE2                       0x00
 131 #define SLI4_ASIC_GEN_BE3                       0x03
 132 #define SLI4_ASIC_GEN_SKYHAWK                   0x04
 133 #define SLI4_ASIC_GEN_CORSAIR                   0x05
 134 #define SLI4_ASIC_GEN_LANCER                    0x0b
 135
 136 /**
 137  * @brief BMBX - Bootstrap Mailbox Register
 138  */
 139 #define SLI4_BMBX_REG                   0x0160  /* register offset */
 140 #define SLI4_BMBX_MASK_HI                       0x3
 141 #define SLI4_BMBX_MASK_LO                       0xf
 142 #define SLI4_BMBX_RDY                           BIT(0)
 143 #define SLI4_BMBX_HI                            BIT(1)
 144 #define SLI4_BMBX_WRITE_HI(r)                   ((ocs_addr32_hi(r) & ~SLI4_BMBX_MASK_HI) | \
 145                                                                 SLI4_BMBX_HI)
 146 #define SLI4_BMBX_WRITE_LO(r)                   (((ocs_addr32_hi(r) & SLI4_BMBX_MASK_HI) << 30) | \
 147                                                                 (((r) & ~SLI4_BMBX_MASK_LO) >> 2))
 148
 149 #define SLI4_BMBX_SIZE                  256
 150
 151 /**
 152  * @brief EQCQ_DOORBELL - EQ and CQ Doorbell Register
 153  */
 154 #define SLI4_EQCQ_DOORBELL_REG                  0x120
 155 #define SLI4_EQCQ_DOORBELL_CI                   BIT(9)
 156 #define SLI4_EQCQ_DOORBELL_QT                   BIT(10)
 157 #define SLI4_EQCQ_DOORBELL_ARM                  BIT(29)
 158 #define SLI4_EQCQ_DOORBELL_SE                   BIT(31)
 159 #define SLI4_EQCQ_NUM_SHIFT                     16
 160 #define SLI4_EQCQ_NUM_MASK                      0x01ff
 161 #define SLI4_EQCQ_EQ_ID_MASK                    0x3fff
 162 #define SLI4_EQCQ_CQ_ID_MASK                    0x7fff
 163 #define SLI4_EQCQ_EQ_ID_MASK_LO                 0x01ff
 164 #define SLI4_EQCQ_CQ_ID_MASK_LO                 0x03ff
 165 #define SLI4_EQCQ_EQCQ_ID_MASK_HI               0xf800
 166 #define SLI4_IF6_EQ_DOORBELL_REG                0x120
 167 #define SLI4_IF6_CQ_DOORBELL_REG                0xC0
 168
 169 /**
 170  * @brief SLIPORT_CONTROL - SLI Port Control Register
 171  */
 172 #define SLI4_SLIPORT_CONTROL_REG        0x0408
 173 #define SLI4_SLIPORT_CONTROL_END                BIT(30)
 174 #define SLI4_SLIPORT_CONTROL_LITTLE_ENDIAN      (0)
 175 #define SLI4_SLIPORT_CONTROL_BIG_ENDIAN         BIT(30)
 176 #define SLI4_SLIPORT_CONTROL_IP                 BIT(27)
 177 #define SLI4_SLIPORT_CONTROL_IDIS               BIT(22)
 178 #define SLI4_SLIPORT_CONTROL_FDD                BIT(31)
 179
 180 /**
 181  * @brief SLI4_SLIPORT_ERROR1 - SLI Port Error Register
 182  */
 183 #define SLI4_SLIPORT_ERROR1             0x040c
 184
 185 /**
 186  * @brief SLI4_SLIPORT_ERROR2 - SLI Port Error Register
 187  */
 188 #define SLI4_SLIPORT_ERROR2             0x0410
 189
 190 /**
 191  * @brief User error registers
 192  */
 193 #define SLI4_UERR_STATUS_LOW_REG                0xA0
 194 #define SLI4_UERR_STATUS_HIGH_REG               0xA4
 195 #define SLI4_UERR_MASK_LOW_REG                  0xA8
 196 #define SLI4_UERR_MASK_HIGH_REG                 0xAC
 197
 198 /**
 199  * @brief Registers for generating software UE (BE3)
 200  */
 201 #define SLI4_SW_UE_CSR1                 0x138
 202 #define SLI4_SW_UE_CSR2                 0x1FFFC
 203
 204 /**
 205  * @brief Registers for generating software UE (Skyhawk)
 206  */
 207 #define SLI4_SW_UE_REG                  0x5C    /* register offset */
 208
 209 static inline uint32_t sli_eq_doorbell(uint16_t n_popped, uint16_t id, uint8_t arm)
 210 {
 211         uint32_t        reg = 0;
 212 #if BYTE_ORDER == LITTLE_ENDIAN
 213         struct {
 214                 uint32_t        eq_id_lo:9,
 215                                 ci:1,                   /* clear interrupt */
 216                                 qt:1,                   /* queue type */
 217                                 eq_id_hi:5,
 218                                 number_popped:13,
 219                                 arm:1,
 220                                 :1,
 221                                 se:1;
 222         } * eq_doorbell = (void *)&reg;
 223 #else
 224 #error big endian version not defined
 225 #endif
 226
 227         eq_doorbell->eq_id_lo = id & SLI4_EQCQ_EQ_ID_MASK_LO;
 228         eq_doorbell->qt = 1;    /* EQ is type 1 (section 2.2.3.3 SLI Arch) */
 229         eq_doorbell->eq_id_hi = (id >> 9) & 0x1f;
 230         eq_doorbell->number_popped = n_popped;
 231         eq_doorbell->arm = arm;
 232         eq_doorbell->ci = TRUE;
 233
 234         return reg;
 235 }
 236
 237 static inline uint32_t sli_cq_doorbell(uint16_t n_popped, uint16_t id, uint8_t arm)
 238 {
 239         uint32_t        reg = 0;
 240 #if BYTE_ORDER == LITTLE_ENDIAN
 241         struct {
 242                 uint32_t        cq_id_lo:10,
 243                                 qt:1,                   /* queue type */
 244                                 cq_id_hi:5,
 245                                 number_popped:13,
 246                                 arm:1,
 247                                 :1,
 248                                 se:1;
 249         } * cq_doorbell = (void *)&reg;
 250 #else
 251 #error big endian version not defined
 252 #endif
 253
 254         cq_doorbell->cq_id_lo = id & SLI4_EQCQ_CQ_ID_MASK_LO;
 255         cq_doorbell->qt = 0;    /* CQ is type 0 (section 2.2.3.3 SLI Arch) */
 256         cq_doorbell->cq_id_hi = (id >> 10) & 0x1f;
 257         cq_doorbell->number_popped = n_popped;
 258         cq_doorbell->arm = arm;
 259
 260         return reg;
 261 }
 262
 263 static inline uint32_t sli_iftype6_eq_doorbell(uint16_t n_popped, uint16_t id, uint8_t arm)
 264 {
 265         uint32_t        reg = 0;
 266 #if BYTE_ORDER == LITTLE_ENDIAN
 267         struct {
 268                 uint32_t        eq_id:12,
 269                                 :4,                     /* clear interrupt */
 270                                 number_popped:13,
 271                                 arm:1,
 272                                 :1,
 273                                 io:1;
 274         } * eq_doorbell = (void *)&reg;
 275 #else
 276 #error big endian version not defined
 277 #endif
 278
 279         eq_doorbell->eq_id = id;
 280         eq_doorbell->number_popped = n_popped;
 281         eq_doorbell->arm = arm;
 282
 283         return reg;
 284 }
 285
 286 static inline uint32_t sli_iftype6_cq_doorbell(uint16_t n_popped, uint16_t id, uint8_t arm)
 287 {
 288         uint32_t        reg = 0;
 289 #if BYTE_ORDER == LITTLE_ENDIAN
 290         struct {
 291                 uint32_t        cq_id:16,
 292                                 number_popped:13,
 293                                 arm:1,
 294                                 :1,
 295                                 se:1;
 296         } * cq_doorbell = (void *)&reg;
 297 #else
 298 #error big endian version not defined
 299 #endif
 300
 301         cq_doorbell->cq_id = id;
 302         cq_doorbell->number_popped = n_popped;
 303         cq_doorbell->arm = arm;
 304
 305         return reg;
 306 }
 307
 308 /**
 309  * @brief MQ_DOORBELL - MQ Doorbell Register
 310  */
 311 #define SLI4_MQ_DOORBELL_REG                    0x0140  /* register offset */
 312 #define SLI4_IF6_MQ_DOORBELL_REG                0x0160  /* register offset if_type = 6 */
 313 #define SLI4_MQ_DOORBELL_NUM_SHIFT              16
 314 #define SLI4_MQ_DOORBELL_NUM_MASK               0x3fff
 315 #define SLI4_MQ_DOORBELL_ID_MASK                0xffff
 316 #define SLI4_MQ_DOORBELL(n, i)                  ((((n) & SLI4_MQ_DOORBELL_NUM_MASK) << SLI4_MQ_DOORBELL_NUM_SHIFT) | \
 317                                                   ((i) & SLI4_MQ_DOORBELL_ID_MASK))
 318
 319 /**
 320  * @brief RQ_DOORBELL - RQ Doorbell Register
 321  */
 322 #define SLI4_RQ_DOORBELL_REG                    0x0a0   /* register offset */
 323 #define SLI4_IF6_RQ_DOORBELL_REG        0x0080  /* register offset of if_type = 6 */
 324 #define SLI4_RQ_DOORBELL_NUM_SHIFT              16
 325 #define SLI4_RQ_DOORBELL_NUM_MASK               0x3fff
 326 #define SLI4_RQ_DOORBELL_ID_MASK                0xffff
 327 #define SLI4_RQ_DOORBELL(n, i)                  ((((n) & SLI4_RQ_DOORBELL_NUM_MASK) << SLI4_RQ_DOORBELL_NUM_SHIFT) | \
 328                                                   ((i) & SLI4_RQ_DOORBELL_ID_MASK))
 329
 330 /**
 331  * @brief WQ_DOORBELL - WQ Doorbell Register
 332  */
 333 #define SLI4_IO_WQ_DOORBELL_REG                 0x040   /* register offset */
 334 #define SLI4_IF6_WQ_DOORBELL_REG                0x040   /* register offset for if_type = 6 */
 335 #define SLI4_WQ_DOORBELL_IDX_SHIFT              16
 336 #define SLI4_WQ_DOORBELL_IDX_MASK               0x00ff
 337 #define SLI4_WQ_DOORBELL_NUM_SHIFT              24
 338 #define SLI4_WQ_DOORBELL_NUM_MASK               0x00ff
 339 #define SLI4_WQ_DOORBELL_ID_MASK                0xffff
 340 #define SLI4_WQ_DOORBELL(n, x, i)               ((((n) & SLI4_WQ_DOORBELL_NUM_MASK) << SLI4_WQ_DOORBELL_NUM_SHIFT) | \
 341                                                  (((x) & SLI4_WQ_DOORBELL_IDX_MASK) << SLI4_WQ_DOORBELL_IDX_SHIFT) | \
 342                                                   ((i) & SLI4_WQ_DOORBELL_ID_MASK))
 343
 344 /**
 345  * @brief SLIPORT_SEMAPHORE - SLI Port Host and Port Status Register
 346  */
 347 #define SLI4_PORT_SEMAPHORE_REG_0       0x00ac  /** register offset Interface Type 0 + 1 */
 348 #define SLI4_PORT_SEMAPHORE_REG_1       0x0180  /** register offset Interface Type 0 + 1 */
 349 #define SLI4_PORT_SEMAPHORE_REG_236     0x0400  /** register offset Interface Type 2 + 3 + 6*/
 350 #define SLI4_PORT_SEMAPHORE_PORT_MASK           0x0000ffff
 351 #define SLI4_PORT_SEMAPHORE_PORT(r)             ((r) & SLI4_PORT_SEMAPHORE_PORT_MASK)
 352 #define SLI4_PORT_SEMAPHORE_HOST_MASK           0x00ff0000
 353 #define SLI4_PORT_SEMAPHORE_HOST_SHIFT          16
 354 #define SLI4_PORT_SEMAPHORE_HOST(r)             (((r) & SLI4_PORT_SEMAPHORE_HOST_MASK) >> \
 355                                                                 SLI4_PORT_SEMAPHORE_HOST_SHIFT)
 356 #define SLI4_PORT_SEMAPHORE_SCR2                BIT(26) /** scratch area 2 */
 357 #define SLI4_PORT_SEMAPHORE_SCR1                BIT(27) /** scratch area 1 */
 358 #define SLI4_PORT_SEMAPHORE_IPC                 BIT(28) /** IP conflict */
 359 #define SLI4_PORT_SEMAPHORE_NIP                 BIT(29) /** no IP address */
 360 #define SLI4_PORT_SEMAPHORE_SFI                 BIT(30) /** secondary firmware image used */
 361 #define SLI4_PORT_SEMAPHORE_PERR                BIT(31) /** POST fatal error */
 362
 363 #define SLI4_PORT_SEMAPHORE_STATUS_POST_READY   0xc000
 364 #define SLI4_PORT_SEMAPHORE_STATUS_UNRECOV_ERR  0xf000
 365 #define SLI4_PORT_SEMAPHORE_STATUS_ERR_MASK     0xf000
 366 #define SLI4_PORT_SEMAPHORE_IN_ERR(r)           (SLI4_PORT_SEMAPHORE_STATUS_UNRECOV_ERR == ((r) & \
 367                                                                 SLI4_PORT_SEMAPHORE_STATUS_ERR_MASK))
 368
 369 /**
 370  * @brief SLIPORT_STATUS - SLI Port Status Register
 371  */
 372
 373 #define SLI4_PORT_STATUS_REG_236        0x0404  /** register offset Interface Type 2 + 3 + 6*/
 374 #define SLI4_PORT_STATUS_FDP                    BIT(21) /** function specific dump present */
 375 #define SLI4_PORT_STATUS_RDY                    BIT(23) /** ready */
 376 #define SLI4_PORT_STATUS_RN                     BIT(24) /** reset needed */
 377 #define SLI4_PORT_STATUS_DIP                    BIT(25) /** dump present */
 378 #define SLI4_PORT_STATUS_OTI                    BIT(29) /** over temp indicator */
 379 #define SLI4_PORT_STATUS_END                    BIT(30) /** endianness */
 380 #define SLI4_PORT_STATUS_ERR                    BIT(31) /** SLI port error */
 381 #define SLI4_PORT_STATUS_READY(r)               ((r) & SLI4_PORT_STATUS_RDY)
 382 #define SLI4_PORT_STATUS_ERROR(r)               ((r) & SLI4_PORT_STATUS_ERR)
 383 #define SLI4_PORT_STATUS_DUMP_PRESENT(r)        ((r) & SLI4_PORT_STATUS_DIP)
 384 #define SLI4_PORT_STATUS_FDP_PRESENT(r)         ((r) & SLI4_PORT_STATUS_FDP)
 385
 386 #define SLI4_PHSDEV_CONTROL_REG_236             0x0414  /** register offset Interface Type 2 + 3 + 6*/
 387 #define SLI4_PHYDEV_CONTROL_DRST                BIT(0)  /** physical device reset */
 388 #define SLI4_PHYDEV_CONTROL_FRST                BIT(1)  /** firmware reset */
 389 #define SLI4_PHYDEV_CONTROL_DD                  BIT(2)  /** diagnostic dump */
 390 #define SLI4_PHYDEV_CONTROL_FRL_MASK            0x000000f0
 391 #define SLI4_PHYDEV_CONTROL_FRL_SHIFT           4
 392 #define SLI4_PHYDEV_CONTROL_FRL(r)              (((r) & SLI4_PHYDEV_CONTROL_FRL_MASK) >> \
 393                                                                 SLI4_PHYDEV_CONTROL_FRL_SHIFT_SHIFT)
 394
 395 /*************************************************************************
 396  * SLI-4 mailbox command formats and definitions
 397  */
 398
 399 typedef struct sli4_mbox_command_header_s {
 400 #if BYTE_ORDER == LITTLE_ENDIAN
 401         uint32_t        :8,
 402                         command:8,
 403                         status:16;      /** Port writes to indicate success / fail */
 404 #else
 405 #error big endian version not defined
 406 #endif
 407 } sli4_mbox_command_header_t;
 408
 409 #define SLI4_MBOX_COMMAND_CONFIG_LINK   0x07
 410 #define SLI4_MBOX_COMMAND_DUMP          0x17
 411 #define SLI4_MBOX_COMMAND_DOWN_LINK     0x06
 412 #define SLI4_MBOX_COMMAND_INIT_LINK     0x05
 413 #define SLI4_MBOX_COMMAND_INIT_VFI      0xa3
 414 #define SLI4_MBOX_COMMAND_INIT_VPI      0xa4
 415 #define SLI4_MBOX_COMMAND_POST_XRI      0xa7
 416 #define SLI4_MBOX_COMMAND_RELEASE_XRI   0xac
 417 #define SLI4_MBOX_COMMAND_READ_CONFIG   0x0b
 418 #define SLI4_MBOX_COMMAND_READ_STATUS   0x0e
 419 #define SLI4_MBOX_COMMAND_READ_NVPARMS  0x02
 420 #define SLI4_MBOX_COMMAND_READ_REV      0x11
 421 #define SLI4_MBOX_COMMAND_READ_LNK_STAT 0x12
 422 #define SLI4_MBOX_COMMAND_READ_SPARM64  0x8d
 423 #define SLI4_MBOX_COMMAND_READ_TOPOLOGY 0x95
 424 #define SLI4_MBOX_COMMAND_REG_FCFI      0xa0
 425 #define SLI4_MBOX_COMMAND_REG_FCFI_MRQ  0xaf
 426 #define SLI4_MBOX_COMMAND_REG_RPI       0x93
 427 #define SLI4_MBOX_COMMAND_REG_RX_RQ     0xa6
 428 #define SLI4_MBOX_COMMAND_REG_VFI       0x9f
 429 #define SLI4_MBOX_COMMAND_REG_VPI       0x96
 430 #define SLI4_MBOX_COMMAND_REQUEST_FEATURES 0x9d
 431 #define SLI4_MBOX_COMMAND_SLI_CONFIG    0x9b
 432 #define SLI4_MBOX_COMMAND_UNREG_FCFI    0xa2
 433 #define SLI4_MBOX_COMMAND_UNREG_RPI     0x14
 434 #define SLI4_MBOX_COMMAND_UNREG_VFI     0xa1
 435 #define SLI4_MBOX_COMMAND_UNREG_VPI     0x97
 436 #define SLI4_MBOX_COMMAND_WRITE_NVPARMS 0x03
 437 #define SLI4_MBOX_COMMAND_CONFIG_AUTO_XFER_RDY  0xAD
 438 #define SLI4_MBOX_COMMAND_CONFIG_AUTO_XFER_RDY_HP       0xAE
 439
 440 #define SLI4_MBOX_STATUS_SUCCESS        0x0000
 441 #define SLI4_MBOX_STATUS_FAILURE        0x0001
 442 #define SLI4_MBOX_STATUS_RPI_NOT_REG    0x1400
 443
 444 /**
 445  * @brief Buffer Descriptor Entry (BDE)
 446  */
 447 typedef struct sli4_bde_s {
 448 #if BYTE_ORDER == LITTLE_ENDIAN
 449         uint32_t        buffer_length:24,
 450                         bde_type:8;
 451         union {
 452                 struct {
 453                         uint32_t        buffer_address_low;
 454                         uint32_t        buffer_address_high;
 455                 } data;
 456                 struct {
 457                         uint32_t        offset;
 458                         uint32_t        rsvd2;
 459                 } imm;
 460                 struct {
 461                         uint32_t        sgl_segment_address_low;
 462                         uint32_t        sgl_segment_address_high;
 463                 } blp;
 464         } u;
 465 #else
 466 #error big endian version not defined
 467 #endif
 468 } sli4_bde_t;
 469
 470 #define SLI4_BDE_TYPE_BDE_64            0x00    /** Generic 64-bit data */
 471 #define SLI4_BDE_TYPE_BDE_IMM           0x01    /** Immediate data */
 472 #define SLI4_BDE_TYPE_BLP               0x40    /** Buffer List Pointer */
 473
 474 /**
 475  * @brief Scatter-Gather Entry (SGE)
 476  */
 477 typedef struct sli4_sge_s {
 478 #if BYTE_ORDER == LITTLE_ENDIAN
 479         uint32_t        buffer_address_high;
 480         uint32_t        buffer_address_low;
 481         uint32_t        data_offset:27,
 482                         sge_type:4,
 483                         last:1;
 484         uint32_t        buffer_length;
 485 #else
 486 #error big endian version not defined
 487 #endif
 488 } sli4_sge_t;
 489
 490 /**
 491  * @brief T10 DIF Scatter-Gather Entry (SGE)
 492  */
 493 typedef struct sli4_dif_sge_s {
 494 #if BYTE_ORDER == LITTLE_ENDIAN
 495         uint32_t        buffer_address_high;
 496         uint32_t        buffer_address_low;
 497         uint32_t        :27,
 498                         sge_type:4,
 499                         last:1;
 500         uint32_t        :32;
 501 #else
 502 #error big endian version not defined
 503 #endif
 504 } sli4_dif_sge_t;
 505
 506 /**
 507  * @brief T10 DIF Seed Scatter-Gather Entry (SGE)
 508  */
 509 typedef struct sli4_diseed_sge_s {
 510 #if BYTE_ORDER == LITTLE_ENDIAN
 511         uint32_t        ref_tag_cmp;
 512         uint32_t        ref_tag_repl;
 513         uint32_t        app_tag_repl:16,
 514                         :2,
 515                         hs:1,
 516                         ws:1,
 517                         ic:1,
 518                         ics:1,
 519                         atrt:1,
 520                         at:1,
 521                         fwd_app_tag:1,
 522                         repl_app_tag:1,
 523                         head_insert:1,
 524                         sge_type:4,
 525                         last:1;
 526         uint32_t        app_tag_cmp:16,
 527                         dif_blk_size:3,
 528                         auto_incr_ref_tag:1,
 529                         check_app_tag:1,
 530                         check_ref_tag:1,
 531                         check_crc:1,
 532                         new_ref_tag:1,
 533                         dif_op_rx:4,
 534                         dif_op_tx:4;
 535 #else
 536 #error big endian version not defined
 537 #endif
 538 } sli4_diseed_sge_t;
 539
 540 /**
 541  * @brief List Segment Pointer Scatter-Gather Entry (SGE)
 542  */
 543 typedef struct sli4_lsp_sge_s {
 544 #if BYTE_ORDER == LITTLE_ENDIAN
 545         uint32_t        buffer_address_high;
 546         uint32_t        buffer_address_low;
 547         uint32_t        :27,
 548                         sge_type:4,
 549                         last:1;
 550         uint32_t        segment_length:24,
 551                         :8;
 552 #else
 553 #error big endian version not defined
 554 #endif
 555 } sli4_lsp_sge_t;
 556
 557 #define SLI4_SGE_MAX_RESERVED                   3
 558
 559 #define SLI4_SGE_DIF_OP_IN_NODIF_OUT_CRC     0x00
 560 #define SLI4_SGE_DIF_OP_IN_CRC_OUT_NODIF     0x01
 561 #define SLI4_SGE_DIF_OP_IN_NODIF_OUT_CHKSUM  0x02
 562 #define SLI4_SGE_DIF_OP_IN_CHKSUM_OUT_NODIF  0x03
 563 #define SLI4_SGE_DIF_OP_IN_CRC_OUT_CRC       0x04
 564 #define SLI4_SGE_DIF_OP_IN_CHKSUM_OUT_CHKSUM 0x05
 565 #define SLI4_SGE_DIF_OP_IN_CRC_OUT_CHKSUM    0x06
 566 #define SLI4_SGE_DIF_OP_IN_CHKSUM_OUT_CRC    0x07
 567 #define SLI4_SGE_DIF_OP_IN_RAW_OUT_RAW       0x08
 568
 569 #define SLI4_SGE_TYPE_DATA              0x00
 570 #define SLI4_SGE_TYPE_CHAIN             0x03    /** Skyhawk only */
 571 #define SLI4_SGE_TYPE_DIF               0x04    /** Data Integrity Field */
 572 #define SLI4_SGE_TYPE_LSP               0x05    /** List Segment Pointer */
 573 #define SLI4_SGE_TYPE_PEDIF             0x06    /** Post Encryption Engine DIF */
 574 #define SLI4_SGE_TYPE_PESEED            0x07    /** Post Encryption Engine DIF Seed */
 575 #define SLI4_SGE_TYPE_DISEED            0x08    /** DIF Seed */
 576 #define SLI4_SGE_TYPE_ENC               0x09    /** Encryption */
 577 #define SLI4_SGE_TYPE_ATM               0x0a    /** DIF Application Tag Mask */
 578 #define SLI4_SGE_TYPE_SKIP              0x0c    /** SKIP */
 579
 580 #define OCS_MAX_SGE_SIZE                0x80000000 /* Maximum data allowed in a SGE */
 581
 582 /**
 583  * @brief CONFIG_LINK
 584  */
 585 typedef struct sli4_cmd_config_link_s {
 586         sli4_mbox_command_header_t      hdr;
 587 #if BYTE_ORDER == LITTLE_ENDIAN
 588         uint32_t        maxbbc:8,       /** Max buffer-to-buffer credit */
 589                         :24;
 590         uint32_t        alpa:8,
 591                         n_port_id:16,
 592                         :8;
 593         uint32_t        rsvd3;
 594         uint32_t        e_d_tov;
 595         uint32_t        lp_tov;
 596         uint32_t        r_a_tov;
 597         uint32_t        r_t_tov;
 598         uint32_t        al_tov;
 599         uint32_t        rsvd9;
 600         uint32_t        :8,
 601                         bbscn:4,        /** buffer-to-buffer state change number */
 602                         cscn:1,         /** configure BBSCN */
 603                         :19;
 604 #else
 605 #error big endian version not defined
 606 #endif
 607 } sli4_cmd_config_link_t;
 608
 609 /**
 610  * @brief DUMP Type 4
 611  */
 612 #define SLI4_WKI_TAG_SAT_TEM 0x1040
 613 typedef struct sli4_cmd_dump4_s {
 614         sli4_mbox_command_header_t      hdr;
 615 #if BYTE_ORDER == LITTLE_ENDIAN
 616         uint32_t        type:4,
 617                         :28;
 618         uint32_t        wki_selection:16,
 619                         :16;
 620         uint32_t        resv;
 621         uint32_t        returned_byte_cnt;
 622         uint32_t        resp_data[59];
 623 #else
 624 #error big endian version not defined
 625 #endif
 626 } sli4_cmd_dump4_t;
 627
 628 /**
 629  * @brief FW_INITIALIZE - initialize a SLI port
 630  *
 631  * @note This command uses a different format than all others.
 632  */
 633
 634 extern const uint8_t sli4_fw_initialize[8];
 635
 636 /**
 637  * @brief FW_DEINITIALIZE - deinitialize a SLI port
 638  *
 639  * @note This command uses a different format than all others.
 640  */
 641
 642 extern const uint8_t sli4_fw_deinitialize[8];
 643
 644 /**
 645  * @brief INIT_LINK - initialize the link for a FC/FCoE port
 646  */
 647 typedef struct sli4_cmd_init_link_flags_s {
 648         uint32_t        loopback:1,
 649                         topology:2,
 650                         #define FC_TOPOLOGY_FCAL        0
 651                         #define FC_TOPOLOGY_P2P         1
 652                         :3,
 653                         unfair:1,
 654                         skip_lirp_lilp:1,
 655                         gen_loop_validity_check:1,
 656                         skip_lisa:1,
 657                         enable_topology_failover:1,
 658                         fixed_speed:1,
 659                         :3,
 660                         select_hightest_al_pa:1,
 661                         :16;    /* pad to 32 bits */
 662 } sli4_cmd_init_link_flags_t;
 663
 664 #define SLI4_INIT_LINK_F_LOOP_BACK      BIT(0)
 665 #define SLI4_INIT_LINK_F_UNFAIR         BIT(6)
 666 #define SLI4_INIT_LINK_F_NO_LIRP        BIT(7)
 667 #define SLI4_INIT_LINK_F_LOOP_VALID_CHK BIT(8)
 668 #define SLI4_INIT_LINK_F_NO_LISA        BIT(9)
 669 #define SLI4_INIT_LINK_F_FAIL_OVER      BIT(10)
 670 #define SLI4_INIT_LINK_F_NO_AUTOSPEED   BIT(11)
 671 #define SLI4_INIT_LINK_F_PICK_HI_ALPA   BIT(15)
 672
 673 #define SLI4_INIT_LINK_F_P2P_ONLY       1
 674 #define SLI4_INIT_LINK_F_FCAL_ONLY      2
 675
 676 #define SLI4_INIT_LINK_F_FCAL_FAIL_OVER 0
 677 #define SLI4_INIT_LINK_F_P2P_FAIL_OVER  1
 678
 679 typedef struct sli4_cmd_init_link_s {
 680         sli4_mbox_command_header_t      hdr;
 681 #if BYTE_ORDER == LITTLE_ENDIAN
 682         uint32_t        selective_reset_al_pa:8,
 683                         :24;
 684         sli4_cmd_init_link_flags_t link_flags;
 685         uint32_t        link_speed_selection_code;
 686                         #define FC_LINK_SPEED_1G                1
 687                         #define FC_LINK_SPEED_2G                2
 688                         #define FC_LINK_SPEED_AUTO_1_2          3
 689                         #define FC_LINK_SPEED_4G                4
 690                         #define FC_LINK_SPEED_AUTO_4_1          5
 691                         #define FC_LINK_SPEED_AUTO_4_2          6
 692                         #define FC_LINK_SPEED_AUTO_4_2_1        7
 693                         #define FC_LINK_SPEED_8G                8
 694                         #define FC_LINK_SPEED_AUTO_8_1          9
 695                         #define FC_LINK_SPEED_AUTO_8_2          10
 696                         #define FC_LINK_SPEED_AUTO_8_2_1        11
 697                         #define FC_LINK_SPEED_AUTO_8_4          12
 698                         #define FC_LINK_SPEED_AUTO_8_4_1        13
 699                         #define FC_LINK_SPEED_AUTO_8_4_2        14
 700                         #define FC_LINK_SPEED_10G               16
 701                         #define FC_LINK_SPEED_16G               17
 702                         #define FC_LINK_SPEED_AUTO_16_8_4       18
 703                         #define FC_LINK_SPEED_AUTO_16_8         19
 704                         #define FC_LINK_SPEED_32G               20
 705                         #define FC_LINK_SPEED_AUTO_32_16_8      21
 706                         #define FC_LINK_SPEED_AUTO_32_16        22
 707 #else
 708 #error big endian version not defined
 709 #endif
 710 } sli4_cmd_init_link_t;
 711
 712 /**
 713  * @brief INIT_VFI - initialize the VFI resource
 714  */
 715 typedef struct sli4_cmd_init_vfi_s {
 716         sli4_mbox_command_header_t      hdr;
 717 #if BYTE_ORDER == LITTLE_ENDIAN
 718         uint32_t        vfi:16,
 719                         :12,
 720                         vp:1,
 721                         vf:1,
 722                         vt:1,
 723                         vr:1;
 724         uint32_t        fcfi:16,
 725                         vpi:16;
 726         uint32_t        vf_id:13,
 727                         pri:3,
 728                         :16;
 729         uint32_t        :24,
 730                         hop_count:8;
 731 #else
 732 #error big endian version not defined
 733 #endif
 734 } sli4_cmd_init_vfi_t;
 735
 736 /**
 737  * @brief INIT_VPI - initialize the VPI resource
 738  */
 739 typedef struct sli4_cmd_init_vpi_s {
 740         sli4_mbox_command_header_t      hdr;
 741 #if BYTE_ORDER == LITTLE_ENDIAN
 742         uint32_t        vpi:16,
 743                         vfi:16;
 744 #else
 745 #error big endian version not defined
 746 #endif
 747 } sli4_cmd_init_vpi_t;
 748
 749 /**
 750  * @brief POST_XRI - post XRI resources to the SLI Port
 751  */
 752 typedef struct sli4_cmd_post_xri_s {
 753         sli4_mbox_command_header_t      hdr;
 754 #if BYTE_ORDER == LITTLE_ENDIAN
 755         uint32_t        xri_base:16,
 756                         xri_count:12,
 757                         enx:1,
 758                         dl:1,
 759                         di:1,
 760                         val:1;
 761 #else
 762 #error big endian version not defined
 763 #endif
 764 } sli4_cmd_post_xri_t;
 765
 766 /**
 767  * @brief RELEASE_XRI - Release XRI resources from the SLI Port
 768  */
 769 typedef struct sli4_cmd_release_xri_s {
 770         sli4_mbox_command_header_t      hdr;
 771 #if BYTE_ORDER == LITTLE_ENDIAN
 772         uint32_t        released_xri_count:5,
 773                         :11,
 774                         xri_count:5,
 775                         :11;
 776         struct {
 777                 uint32_t        xri_tag0:16,
 778                                 xri_tag1:16;
 779         } xri_tbl[62];
 780 #else
 781 #error big endian version not defined
 782 #endif
 783 } sli4_cmd_release_xri_t;
 784
 785 /**
 786  * @brief READ_CONFIG - read SLI port configuration parameters
 787  */
 788 typedef struct sli4_cmd_read_config_s {
 789         sli4_mbox_command_header_t      hdr;
 790 } sli4_cmd_read_config_t;
 791
 792 typedef struct sli4_res_read_config_s {
 793         sli4_mbox_command_header_t      hdr;
 794 #if BYTE_ORDER == LITTLE_ENDIAN
 795         uint32_t        :31,
 796                         ext:1;          /** Resource Extents */
 797         uint32_t        :20,
 798                         pt:2,
 799                         tf:1,
 800                         ptv:1,
 801                         topology:8;
 802         uint32_t        rsvd3;
 803         uint32_t        e_d_tov:16,
 804                         :16;
 805         uint32_t        rsvd5;
 806         uint32_t        r_a_tov:16,
 807                         :16;
 808         uint32_t        rsvd7;
 809         uint32_t        rsvd8;
 810         uint32_t        lmt:16,         /** Link Module Type */
 811                         :16;
 812         uint32_t        rsvd10;
 813         uint32_t        rsvd11;
 814         uint32_t        xri_base:16,
 815                         xri_count:16;
 816         uint32_t        rpi_base:16,
 817                         rpi_count:16;
 818         uint32_t        vpi_base:16,
 819                         vpi_count:16;
 820         uint32_t        vfi_base:16,
 821                         vfi_count:16;
 822         uint32_t        :16,
 823                         fcfi_count:16;
 824         uint32_t        rq_count:16,
 825                         eq_count:16;
 826         uint32_t        wq_count:16,
 827                         cq_count:16;
 828         uint32_t        pad[45];
 829 #else
 830 #error big endian version not defined
 831 #endif
 832 } sli4_res_read_config_t;
 833
 834 #define SLI4_READ_CFG_TOPO_FCOE                 0x0     /** FCoE topology */
 835 #define SLI4_READ_CFG_TOPO_FC                   0x1     /** FC topology unknown */
 836 #define SLI4_READ_CFG_TOPO_FC_DA                0x2     /** FC Direct Attach (non FC-AL) topology */
 837 #define SLI4_READ_CFG_TOPO_FC_AL                0x3     /** FC-AL topology */
 838
 839 /**
 840  * @brief READ_NVPARMS - read SLI port configuration parameters
 841  */
 842 typedef struct sli4_cmd_read_nvparms_s {
 843         sli4_mbox_command_header_t      hdr;
 844 #if BYTE_ORDER == LITTLE_ENDIAN
 845         uint32_t        rsvd1;
 846         uint32_t        rsvd2;
 847         uint32_t        rsvd3;
 848         uint32_t        rsvd4;
 849         uint8_t         wwpn[8];
 850         uint8_t         wwnn[8];
 851         uint32_t        hard_alpa:8,
 852                         preferred_d_id:24;
 853 #else
 854 #error big endian version not defined
 855 #endif
 856 } sli4_cmd_read_nvparms_t;
 857
 858 /**
 859  * @brief WRITE_NVPARMS - write SLI port configuration parameters
 860  */
 861 typedef struct sli4_cmd_write_nvparms_s {
 862         sli4_mbox_command_header_t      hdr;
 863 #if BYTE_ORDER == LITTLE_ENDIAN
 864         uint32_t        rsvd1;
 865         uint32_t        rsvd2;
 866         uint32_t        rsvd3;
 867         uint32_t        rsvd4;
 868         uint8_t         wwpn[8];
 869         uint8_t         wwnn[8];
 870         uint32_t        hard_alpa:8,
 871                         preferred_d_id:24;
 872 #else
 873 #error big endian version not defined
 874 #endif
 875 } sli4_cmd_write_nvparms_t;
 876
 877 /**
 878  * @brief READ_REV - read the Port revision levels
 879  */
 880 typedef struct sli4_cmd_read_rev_s {
 881         sli4_mbox_command_header_t      hdr;
 882 #if BYTE_ORDER == LITTLE_ENDIAN
 883         uint32_t        :16,
 884                         sli_level:4,
 885                         fcoem:1,
 886                         ceev:2,
 887                         :6,
 888                         vpd:1,
 889                         :2;
 890         uint32_t        first_hw_revision;
 891         uint32_t        second_hw_revision;
 892         uint32_t        rsvd4;
 893         uint32_t        third_hw_revision;
 894         uint32_t        fc_ph_low:8,
 895                         fc_ph_high:8,
 896                         feature_level_low:8,
 897                         feature_level_high:8;
 898         uint32_t        rsvd7;
 899         uint32_t        first_fw_id;
 900         char            first_fw_name[16];
 901         uint32_t        second_fw_id;
 902         char            second_fw_name[16];
 903         uint32_t        rsvd18[30];
 904         uint32_t        available_length:24,
 905                         :8;
 906         uint32_t        physical_address_low;
 907         uint32_t        physical_address_high;
 908         uint32_t        returned_vpd_length;
 909         uint32_t        actual_vpd_length;
 910 #else
 911 #error big endian version not defined
 912 #endif
 913 } sli4_cmd_read_rev_t;
 914
 915 /**
 916  * @brief READ_SPARM64 - read the Port service parameters
 917  */
 918 typedef struct sli4_cmd_read_sparm64_s {
 919         sli4_mbox_command_header_t      hdr;
 920 #if BYTE_ORDER == LITTLE_ENDIAN
 921         uint32_t        rsvd1;
 922         uint32_t        rsvd2;
 923         sli4_bde_t      bde_64;
 924         uint32_t        vpi:16,
 925                         :16;
 926         uint32_t        port_name_start:16,
 927                         port_name_length:16;
 928         uint32_t        node_name_start:16,
 929                         node_name_length:16;
 930 #else
 931 #error big endian version not defined
 932 #endif
 933 } sli4_cmd_read_sparm64_t;
 934
 935 #define SLI4_READ_SPARM64_VPI_DEFAULT   0
 936 #define SLI4_READ_SPARM64_VPI_SPECIAL   UINT16_MAX
 937
 938 #define SLI4_READ_SPARM64_WWPN_OFFSET   (4 * sizeof(uint32_t))
 939 #define SLI4_READ_SPARM64_WWNN_OFFSET   (SLI4_READ_SPARM64_WWPN_OFFSET + sizeof(uint64_t))
 940
 941 typedef struct sli4_port_state_s {
 942 #if BYTE_ORDER == LITTLE_ENDIAN
 943         uint32_t        nx_port_recv_state:2,
 944                         nx_port_trans_state:2,
 945                         nx_port_state_machine:4,
 946                         link_speed:8,
 947                         :14,
 948                         tf:1,
 949                         lu:1;
 950 #else
 951 #error big endian version not defined
 952 #endif
 953 } sli4_port_state_t;
 954
 955 /**
 956  * @brief READ_TOPOLOGY - read the link event information
 957  */
 958 typedef struct sli4_cmd_read_topology_s {
 959         sli4_mbox_command_header_t      hdr;
 960 #if BYTE_ORDER == LITTLE_ENDIAN
 961         uint32_t        event_tag;
 962         uint32_t        attention_type:8,
 963                         il:1,
 964                         pb_recvd:1,
 965                         :22;
 966         uint32_t        topology:8,
 967                         lip_type:8,
 968                         lip_al_ps:8,
 969                         al_pa_granted:8;
 970         sli4_bde_t      bde_loop_map;
 971         sli4_port_state_t link_down;
 972         sli4_port_state_t link_current;
 973         uint32_t        max_bbc:8,
 974                         init_bbc:8,
 975                         bbscn:4,
 976                         cbbscn:4,
 977                         :8;
 978         uint32_t        r_t_tov:9,
 979                         :3,
 980                         al_tov:4,
 981                         lp_tov:16;
 982         uint32_t        acquired_al_pa:8,
 983                         :7,
 984                         pb:1,
 985                         specified_al_pa:16;
 986         uint32_t        initial_n_port_id:24,
 987                         :8;
 988 #else
 989 #error big endian version not defined
 990 #endif
 991 } sli4_cmd_read_topology_t;
 992
 993 #define SLI4_MIN_LOOP_MAP_BYTES 128
 994
 995 #define SLI4_READ_TOPOLOGY_LINK_UP      0x1
 996 #define SLI4_READ_TOPOLOGY_LINK_DOWN    0x2
 997 #define SLI4_READ_TOPOLOGY_LINK_NO_ALPA 0x3
 998
 999 #define SLI4_READ_TOPOLOGY_UNKNOWN      0x0
1000 #define SLI4_READ_TOPOLOGY_NPORT        0x1
1001 #define SLI4_READ_TOPOLOGY_FC_AL        0x2
1002
1003 #define SLI4_READ_TOPOLOGY_SPEED_NONE   0x00
1004 #define SLI4_READ_TOPOLOGY_SPEED_1G     0x04
1005 #define SLI4_READ_TOPOLOGY_SPEED_2G     0x08
1006 #define SLI4_READ_TOPOLOGY_SPEED_4G     0x10
1007 #define SLI4_READ_TOPOLOGY_SPEED_8G     0x20
1008 #define SLI4_READ_TOPOLOGY_SPEED_10G    0x40
1009 #define SLI4_READ_TOPOLOGY_SPEED_16G    0x80
1010 #define SLI4_READ_TOPOLOGY_SPEED_32G    0x90
1011
1012 /**
1013  * @brief REG_FCFI - activate a FC Forwarder
1014  */
1015 #define SLI4_CMD_REG_FCFI_NUM_RQ_CFG    4
1016 typedef struct sli4_cmd_reg_fcfi_s {
1017         sli4_mbox_command_header_t      hdr;
1018 #if BYTE_ORDER == LITTLE_ENDIAN
1019         uint32_t        fcf_index:16,
1020                         fcfi:16;
1021         uint32_t        rq_id_1:16,
1022                         rq_id_0:16;
1023         uint32_t        rq_id_3:16,
1024                         rq_id_2:16;
1025         struct {
1026                 uint32_t        r_ctl_mask:8,
1027                                 r_ctl_match:8,
1028                                 type_mask:8,
1029                                 type_match:8;
1030         } rq_cfg[SLI4_CMD_REG_FCFI_NUM_RQ_CFG];
1031         uint32_t        vlan_tag:12,
1032                         vv:1,
1033                         :19;
1034 #else
1035 #error big endian version not defined
1036 #endif
1037 } sli4_cmd_reg_fcfi_t;
1038
1039 #define SLI4_CMD_REG_FCFI_MRQ_NUM_RQ_CFG        4
1040 #define SLI4_CMD_REG_FCFI_MRQ_MAX_NUM_RQ        32
1041 #define SLI4_CMD_REG_FCFI_SET_FCFI_MODE         0
1042 #define SLI4_CMD_REG_FCFI_SET_MRQ_MODE          1
1043
1044 typedef struct sli4_cmd_reg_fcfi_mrq_s {
1045         sli4_mbox_command_header_t      hdr;
1046 #if BYTE_ORDER == LITTLE_ENDIAN
1047         uint32_t        fcf_index:16,
1048                         fcfi:16;
1049
1050         uint32_t        rq_id_1:16,
1051                         rq_id_0:16;
1052
1053         uint32_t        rq_id_3:16,
1054                         rq_id_2:16;
1055
1056         struct {
1057                 uint32_t        r_ctl_mask:8,
1058                                 r_ctl_match:8,
1059                                 type_mask:8,
1060                                 type_match:8;
1061         } rq_cfg[SLI4_CMD_REG_FCFI_MRQ_NUM_RQ_CFG];
1062
1063         uint32_t        vlan_tag:12,
1064                         vv:1,
1065                         mode:1,
1066                         :18;
1067
1068         uint32_t        num_mrq_pairs:8,
1069                         mrq_filter_bitmask:4,
1070                         rq_selection_policy:4,
1071                         :16;
1072 #endif
1073 } sli4_cmd_reg_fcfi_mrq_t;
1074
1075 /**
1076  * @brief REG_RPI - register a Remote Port Indicator
1077  */
1078 typedef struct sli4_cmd_reg_rpi_s {
1079         sli4_mbox_command_header_t      hdr;
1080 #if BYTE_ORDER == LITTLE_ENDIAN
1081         uint32_t        rpi:16,
1082                         :16;
1083         uint32_t        remote_n_port_id:24,
1084                         upd:1,
1085                         :2,
1086                         etow:1,
1087                         :1,
1088                         terp:1,
1089                         :1,
1090                         ci:1;
1091         sli4_bde_t      bde_64;
1092         uint32_t        vpi:16,
1093                         :16;
1094 #else
1095 #error big endian version not defined
1096 #endif
1097 } sli4_cmd_reg_rpi_t;
1098 #define SLI4_REG_RPI_BUF_LEN                    0x70
1099
1100 /**
1101  * @brief REG_VFI - register a Virtual Fabric Indicator
1102  */
1103 typedef struct sli4_cmd_reg_vfi_s {
1104         sli4_mbox_command_header_t      hdr;
1105 #if BYTE_ORDER == LITTLE_ENDIAN
1106         uint32_t        vfi:16,
1107                         :12,
1108                         vp:1,
1109                         upd:1,
1110                         :2;
1111         uint32_t        fcfi:16,
1112                         vpi:16;                 /* vp=TRUE */
1113         uint8_t         wwpn[8];                /* vp=TRUE */
1114         sli4_bde_t      sparm;                  /* either FLOGI or PLOGI */
1115         uint32_t        e_d_tov;
1116         uint32_t        r_a_tov;
1117         uint32_t        local_n_port_id:24,     /* vp=TRUE */
1118                         :8;
1119 #else
1120 #error big endian version not defined
1121 #endif
1122 } sli4_cmd_reg_vfi_t;
1123
1124 /**
1125  * @brief REG_VPI - register a Virtual Port Indicator
1126  */
1127 typedef struct sli4_cmd_reg_vpi_s {
1128         sli4_mbox_command_header_t      hdr;
1129 #if BYTE_ORDER == LITTLE_ENDIAN
1130         uint32_t        rsvd1;
1131         uint32_t        local_n_port_id:24,
1132                         upd:1,
1133                         :7;
1134         uint8_t         wwpn[8];
1135         uint32_t        rsvd5;
1136         uint32_t        vpi:16,
1137                         vfi:16;
1138 #else
1139 #error big endian version not defined
1140 #endif
1141 } sli4_cmd_reg_vpi_t;
1142
1143 /**
1144  * @brief REQUEST_FEATURES - request / query SLI features
1145  */
1146 typedef union {
1147 #if BYTE_ORDER == LITTLE_ENDIAN
1148         struct {
1149                 uint32_t        iaab:1,         /** inhibit auto-ABTS originator */
1150                                 npiv:1,         /** NPIV support */
1151                                 dif:1,          /** DIF/DIX support */
1152                                 vf:1,           /** virtual fabric support */
1153                                 fcpi:1,         /** FCP initiator support */
1154                                 fcpt:1,         /** FCP target support */
1155                                 fcpc:1,         /** combined FCP initiator/target */
1156                                 :1,
1157                                 rqd:1,          /** recovery qualified delay */
1158                                 iaar:1,         /** inhibit auto-ABTS responder */
1159                                 hlm:1,          /** High Login Mode */
1160                                 perfh:1,        /** performance hints */
1161                                 rxseq:1,        /** RX Sequence Coalescing */
1162                                 rxri:1,         /** Release XRI variant of Coalescing */
1163                                 dcl2:1,         /** Disable Class 2 */
1164                                 rsco:1,         /** Receive Sequence Coalescing Optimizations */
1165                                 mrqp:1,         /** Multi RQ Pair Mode Support */
1166                                 :15;
1167         } flag;
1168         uint32_t        dword;
1169 #else
1170 #error big endian version not defined
1171 #endif
1172 } sli4_features_t;
1173
1174 typedef struct sli4_cmd_request_features_s {
1175         sli4_mbox_command_header_t      hdr;
1176 #if BYTE_ORDER == LITTLE_ENDIAN
1177         uint32_t        qry:1,
1178                         :31;
1179 #else
1180 #error big endian version not defined
1181 #endif
1182         sli4_features_t command;
1183         sli4_features_t response;
1184 } sli4_cmd_request_features_t;
1185
1186 /**
1187  * @brief SLI_CONFIG - submit a configuration command to Port
1188  *
1189  * Command is either embedded as part of the payload (embed) or located
1190  * in a separate memory buffer (mem)
1191  */
1192
1193 typedef struct sli4_sli_config_pmd_s {
1194         uint32_t        address_low;
1195         uint32_t        address_high;
1196         uint32_t        length:24,
1197                         :8;
1198 } sli4_sli_config_pmd_t;
1199
1200 typedef struct sli4_cmd_sli_config_s {
1201         sli4_mbox_command_header_t      hdr;
1202 #if BYTE_ORDER == LITTLE_ENDIAN
1203         uint32_t        emb:1,
1204                         :2,
1205                         pmd_count:5,
1206                         :24;
1207         uint32_t        payload_length;
1208         uint32_t        rsvd3;
1209         uint32_t        rsvd4;
1210         uint32_t        rsvd5;
1211         union {
1212                 uint8_t                 embed[58 * sizeof(uint32_t)];
1213                 sli4_sli_config_pmd_t   mem;
1214         } payload;
1215 #else
1216 #error big endian version not defined
1217 #endif
1218 } sli4_cmd_sli_config_t;
1219
1220 /**
1221  * @brief READ_STATUS - read tx/rx status of a particular port
1222  *
1223  */
1224
1225 typedef struct sli4_cmd_read_status_s {
1226         sli4_mbox_command_header_t      hdr;
1227 #if BYTE_ORDER == LITTLE_ENDIAN
1228         uint32_t        cc:1,
1229                         :31;
1230         uint32_t        rsvd2;
1231         uint32_t        transmit_kbyte_count;
1232         uint32_t        receive_kbyte_count;
1233         uint32_t        transmit_frame_count;
1234         uint32_t        receive_frame_count;
1235         uint32_t        transmit_sequence_count;
1236         uint32_t        receive_sequence_count;
1237         uint32_t        total_exchanges_originator;
1238         uint32_t        total_exchanges_responder;
1239         uint32_t        receive_p_bsy_count;
1240         uint32_t        receive_f_bsy_count;
1241         uint32_t        dropped_frames_due_to_no_rq_buffer_count;
1242         uint32_t        empty_rq_timeout_count;
1243         uint32_t        dropped_frames_due_to_no_xri_count;
1244         uint32_t        empty_xri_pool_count;
1245
1246 #else
1247 #error big endian version not defined
1248 #endif
1249 } sli4_cmd_read_status_t;
1250
1251 /**
1252  * @brief READ_LNK_STAT - read link status of a particular port
1253  *
1254  */
1255
1256 typedef struct sli4_cmd_read_link_stats_s {
1257         sli4_mbox_command_header_t      hdr;
1258 #if BYTE_ORDER == LITTLE_ENDIAN
1259         uint32_t        rec:1,
1260                         gec:1,
1261                         w02of:1,
1262                         w03of:1,
1263                         w04of:1,
1264                         w05of:1,
1265                         w06of:1,
1266                         w07of:1,
1267                         w08of:1,
1268                         w09of:1,
1269                         w10of:1,
1270                         w11of:1,
1271                         w12of:1,
1272                         w13of:1,
1273                         w14of:1,
1274                         w15of:1,
1275                         w16of:1,
1276                         w17of:1,
1277                         w18of:1,
1278                         w19of:1,
1279                         w20of:1,
1280                         w21of:1,
1281                         resv0:8,
1282                         clrc:1,
1283                         clof:1;
1284         uint32_t        link_failure_error_count;
1285         uint32_t        loss_of_sync_error_count;
1286         uint32_t        loss_of_signal_error_count;
1287         uint32_t        primitive_sequence_error_count;
1288         uint32_t        invalid_transmission_word_error_count;
1289         uint32_t        crc_error_count;
1290         uint32_t        primitive_sequence_event_timeout_count;
1291         uint32_t        elastic_buffer_overrun_error_count;
1292         uint32_t        arbitration_fc_al_timout_count;
1293         uint32_t        advertised_receive_bufftor_to_buffer_credit;
1294         uint32_t        current_receive_buffer_to_buffer_credit;
1295         uint32_t        advertised_transmit_buffer_to_buffer_credit;
1296         uint32_t        current_transmit_buffer_to_buffer_credit;
1297         uint32_t        received_eofa_count;
1298         uint32_t        received_eofdti_count;
1299         uint32_t        received_eofni_count;
1300         uint32_t        received_soff_count;
1301         uint32_t        received_dropped_no_aer_count;
1302         uint32_t        received_dropped_no_available_rpi_resources_count;
1303         uint32_t        received_dropped_no_available_xri_resources_count;
1304
1305 #else
1306 #error big endian version not defined
1307 #endif
1308 } sli4_cmd_read_link_stats_t;
1309
1310 /**
1311  * @brief Format a WQE with WQ_ID Association performance hint
1312  *
1313  * @par Description
1314  * PHWQ works by over-writing part of Word 10 in the WQE with the WQ ID.
1315  *
1316  * @param entry Pointer to the WQE.
1317  * @param q_id Queue ID.
1318  *
1319  * @return None.
1320  */
1321 static inline void
1322 sli_set_wq_id_association(void *entry, uint16_t q_id)
1323 {
1324         uint32_t *wqe = entry;
1325
1326         /*
1327          * Set Word 10, bit 0 to zero
1328          * Set Word 10, bits 15:1 to the WQ ID
1329          */
1330 #if BYTE_ORDER == LITTLE_ENDIAN
1331         wqe[10] &= ~0xffff;
1332         wqe[10] |= q_id << 1;
1333 #else
1334 #error big endian version not defined
1335 #endif
1336 }
1337
1338 /**
1339  * @brief UNREG_FCFI - unregister a FCFI
1340  */
1341 typedef struct sli4_cmd_unreg_fcfi_s {
1342         sli4_mbox_command_header_t      hdr;
1343         uint32_t        rsvd1;
1344 #if BYTE_ORDER == LITTLE_ENDIAN
1345         uint32_t        fcfi:16,
1346                         :16;
1347 #else
1348 #error big endian version not defined
1349 #endif
1350 } sli4_cmd_unreg_fcfi_t;
1351
1352 /**
1353  * @brief UNREG_RPI - unregister one or more RPI
1354  */
1355 typedef struct sli4_cmd_unreg_rpi_s {
1356         sli4_mbox_command_header_t      hdr;
1357 #if BYTE_ORDER == LITTLE_ENDIAN
1358         uint32_t        index:16,
1359                         :13,
1360                         dp:1,
1361                         ii:2;
1362         uint32_t        destination_n_port_id:24,
1363                         :8;
1364 #else
1365 #error big endian version not defined
1366 #endif
1367 } sli4_cmd_unreg_rpi_t;
1368
1369 #define SLI4_UNREG_RPI_II_RPI                   0x0
1370 #define SLI4_UNREG_RPI_II_VPI                   0x1
1371 #define SLI4_UNREG_RPI_II_VFI                   0x2
1372 #define SLI4_UNREG_RPI_II_FCFI                  0x3
1373
1374 /**
1375  * @brief UNREG_VFI - unregister one or more VFI
1376  */
1377 typedef struct sli4_cmd_unreg_vfi_s {
1378         sli4_mbox_command_header_t      hdr;
1379 #if BYTE_ORDER == LITTLE_ENDIAN
1380         uint32_t        rsvd1;
1381         uint32_t        index:16,
1382                         :14,
1383                         ii:2;
1384 #else
1385 #error big endian version not defined
1386 #endif
1387 } sli4_cmd_unreg_vfi_t;
1388
1389 #define SLI4_UNREG_VFI_II_VFI                   0x0
1390 #define SLI4_UNREG_VFI_II_FCFI                  0x3
1391
1392 enum {
1393         SLI4_UNREG_TYPE_PORT,
1394         SLI4_UNREG_TYPE_DOMAIN,
1395         SLI4_UNREG_TYPE_FCF,
1396         SLI4_UNREG_TYPE_ALL
1397 };
1398
1399 /**
1400  * @brief UNREG_VPI - unregister one or more VPI
1401  */
1402 typedef struct sli4_cmd_unreg_vpi_s {
1403         sli4_mbox_command_header_t      hdr;
1404 #if BYTE_ORDER == LITTLE_ENDIAN
1405         uint32_t        rsvd1;
1406         uint32_t        index:16,
1407                         :14,
1408                         ii:2;
1409 #else
1410 #error big endian version not defined
1411 #endif
1412 } sli4_cmd_unreg_vpi_t;
1413
1414 #define SLI4_UNREG_VPI_II_VPI                   0x0
1415 #define SLI4_UNREG_VPI_II_VFI                   0x2
1416 #define SLI4_UNREG_VPI_II_FCFI                  0x3
1417
1418 /**
1419  * @brief AUTO_XFER_RDY - Configure the auto-generate XFER-RDY feature.
1420  */
1421 typedef struct sli4_cmd_config_auto_xfer_rdy_s {
1422         sli4_mbox_command_header_t      hdr;
1423 #if BYTE_ORDER == LITTLE_ENDIAN
1424         uint32_t        resv;
1425         uint32_t        max_burst_len;
1426 #else
1427 #error big endian version not defined
1428 #endif
1429 } sli4_cmd_config_auto_xfer_rdy_t;
1430
1431 typedef struct sli4_cmd_config_auto_xfer_rdy_hp_s {
1432         sli4_mbox_command_header_t      hdr;
1433 #if BYTE_ORDER == LITTLE_ENDIAN
1434         uint32_t        resv;
1435         uint32_t        max_burst_len;
1436         uint32_t        esoc:1,
1437                         :31;
1438         uint32_t        block_size:16,
1439                         :16;
1440 #else
1441 #error big endian version not defined
1442 #endif
1443 } sli4_cmd_config_auto_xfer_rdy_hp_t;
1444
1445 /*************************************************************************
1446  * SLI-4 common configuration command formats and definitions
1447  */
1448
1449 #define SLI4_CFG_STATUS_SUCCESS                 0x00
1450 #define SLI4_CFG_STATUS_FAILED                  0x01
1451 #define SLI4_CFG_STATUS_ILLEGAL_REQUEST         0x02
1452 #define SLI4_CFG_STATUS_ILLEGAL_FIELD           0x03
1453
1454 #define SLI4_MGMT_STATUS_FLASHROM_READ_FAILED   0xcb
1455
1456 #define SLI4_CFG_ADD_STATUS_NO_STATUS           0x00
1457 #define SLI4_CFG_ADD_STATUS_INVALID_OPCODE      0x1e
1458
1459 /**
1460  * Subsystem values.
1461  */
1462 #define SLI4_SUBSYSTEM_COMMON                   0x01
1463 #define SLI4_SUBSYSTEM_LOWLEVEL                 0x0B
1464 #define SLI4_SUBSYSTEM_FCFCOE                   0x0c
1465 #define SLI4_SUBSYSTEM_DMTF                     0x11
1466
1467 #define SLI4_OPC_LOWLEVEL_SET_WATCHDOG          0X36
1468
1469 /**
1470  * Common opcode (OPC) values.
1471  */
1472 #define SLI4_OPC_COMMON_FUNCTION_RESET                  0x3d
1473 #define SLI4_OPC_COMMON_CREATE_CQ                       0x0c
1474 #define SLI4_OPC_COMMON_CREATE_CQ_SET                   0x1d
1475 #define SLI4_OPC_COMMON_DESTROY_CQ                      0x36
1476 #define SLI4_OPC_COMMON_MODIFY_EQ_DELAY                 0x29
1477 #define SLI4_OPC_COMMON_CREATE_EQ                       0x0d
1478 #define SLI4_OPC_COMMON_DESTROY_EQ                      0x37
1479 #define SLI4_OPC_COMMON_CREATE_MQ_EXT                   0x5a
1480 #define SLI4_OPC_COMMON_DESTROY_MQ                      0x35
1481 #define SLI4_OPC_COMMON_GET_CNTL_ATTRIBUTES             0x20
1482 #define SLI4_OPC_COMMON_NOP                             0x21
1483 #define SLI4_OPC_COMMON_GET_RESOURCE_EXTENT_INFO        0x9a
1484 #define SLI4_OPC_COMMON_GET_SLI4_PARAMETERS             0xb5
1485 #define SLI4_OPC_COMMON_QUERY_FW_CONFIG                 0x3a
1486 #define SLI4_OPC_COMMON_GET_PORT_NAME                   0x4d
1487
1488 #define SLI4_OPC_COMMON_WRITE_FLASHROM                  0x07
1489 #define SLI4_OPC_COMMON_MANAGE_FAT                      0x44
1490 #define SLI4_OPC_COMMON_READ_TRANSCEIVER_DATA           0x49
1491 #define SLI4_OPC_COMMON_GET_CNTL_ADDL_ATTRIBUTES        0x79
1492 #define SLI4_OPC_COMMON_GET_EXT_FAT_CAPABILITIES        0x7d
1493 #define SLI4_OPC_COMMON_SET_EXT_FAT_CAPABILITIES        0x7e
1494 #define SLI4_OPC_COMMON_EXT_FAT_CONFIGURE_SNAPSHOT      0x7f
1495 #define SLI4_OPC_COMMON_EXT_FAT_RETRIEVE_SNAPSHOT       0x80
1496 #define SLI4_OPC_COMMON_EXT_FAT_READ_STRING_TABLE       0x82
1497 #define SLI4_OPC_COMMON_GET_FUNCTION_CONFIG             0xa0
1498 #define SLI4_OPC_COMMON_GET_PROFILE_CONFIG              0xa4
1499 #define SLI4_OPC_COMMON_SET_PROFILE_CONFIG              0xa5
1500 #define SLI4_OPC_COMMON_GET_PROFILE_LIST                0xa6
1501 #define SLI4_OPC_COMMON_GET_ACTIVE_PROFILE              0xa7
1502 #define SLI4_OPC_COMMON_SET_ACTIVE_PROFILE              0xa8
1503 #define SLI4_OPC_COMMON_READ_OBJECT                     0xab
1504 #define SLI4_OPC_COMMON_WRITE_OBJECT                    0xac
1505 #define SLI4_OPC_COMMON_DELETE_OBJECT                   0xae
1506 #define SLI4_OPC_COMMON_READ_OBJECT_LIST                0xad
1507 #define SLI4_OPC_COMMON_SET_DUMP_LOCATION               0xb8
1508 #define SLI4_OPC_COMMON_SET_FEATURES                    0xbf
1509 #define SLI4_OPC_COMMON_GET_RECONFIG_LINK_INFO          0xc9
1510 #define SLI4_OPC_COMMON_SET_RECONFIG_LINK_ID            0xca
1511
1512 /**
1513  * DMTF opcode (OPC) values.
1514  */
1515 #define SLI4_OPC_DMTF_EXEC_CLP_CMD                      0x01
1516
1517 /**
1518  * @brief Generic Command Request header
1519  */
1520 typedef struct sli4_req_hdr_s {
1521 #if BYTE_ORDER == LITTLE_ENDIAN
1522         uint32_t        opcode:8,
1523                         subsystem:8,
1524                         :16;
1525         uint32_t        timeout;
1526         uint32_t        request_length;
1527         uint32_t        version:8,
1528                         :24;
1529 #else
1530 #error big endian version not defined
1531 #endif
1532 } sli4_req_hdr_t;
1533
1534 /**
1535  * @brief Generic Command Response header
1536  */
1537 typedef struct sli4_res_hdr_s {
1538 #if BYTE_ORDER == LITTLE_ENDIAN
1539         uint32_t        opcode:8,
1540                         subsystem:8,
1541                         :16;
1542         uint32_t        status:8,
1543                         additional_status:8,
1544                         :16;
1545         uint32_t        response_length;
1546         uint32_t        actual_response_length;
1547 #else
1548 #error big endian version not defined
1549 #endif
1550 } sli4_res_hdr_t;
1551
1552 /**
1553  * @brief COMMON_FUNCTION_RESET
1554  *
1555  * Resets the Port, returning it to a power-on state. This configuration
1556  * command does not have a payload and should set/expect the lengths to
1557  * be zero.
1558  */
1559 typedef struct sli4_req_common_function_reset_s {
1560         sli4_req_hdr_t  hdr;
1561 } sli4_req_common_function_reset_t;
1562
1563 typedef struct sli4_res_common_function_reset_s {
1564         sli4_res_hdr_t  hdr;
1565 } sli4_res_common_function_reset_t;
1566
1567 /**
1568  * @brief COMMON_CREATE_CQ_V0
1569  *
1570  * Create a Completion Queue.
1571  */
1572 typedef struct sli4_req_common_create_cq_v0_s {
1573         sli4_req_hdr_t  hdr;
1574 #if BYTE_ORDER == LITTLE_ENDIAN
1575         uint32_t        num_pages:16,
1576                         :16;
1577         uint32_t        :12,
1578                         clswm:2,
1579                         nodelay:1,
1580                         :12,
1581                         cqecnt:2,
1582                         valid:1,
1583                         :1,
1584                         evt:1;
1585         uint32_t        :22,
1586                         eq_id:8,
1587                         :1,
1588                         arm:1;
1589         uint32_t        rsvd[2];
1590         struct {
1591                 uint32_t        low;
1592                 uint32_t        high;
1593         } page_physical_address[0];
1594 #else
1595 #error big endian version not defined
1596 #endif
1597 } sli4_req_common_create_cq_v0_t;
1598
1599 /**
1600  * @brief COMMON_CREATE_CQ_V2
1601  *
1602  * Create a Completion Queue.
1603  */
1604 typedef struct sli4_req_common_create_cq_v2_s {
1605         sli4_req_hdr_t  hdr;
1606 #if BYTE_ORDER == LITTLE_ENDIAN
1607         uint32_t        num_pages:16,
1608                         page_size:8,
1609                         :8,
1610         uint32_t        :12,
1611                         clswm:2,
1612                         nodelay:1,
1613                         autovalid:1,
1614                         :9,
1615                         cqe_size:2,
1616                         cqecnt:2,
1617                         valid:1,
1618                         :1,
1619                         evt:1;
1620         uint32_t        eq_id:16,
1621                         :15,
1622                         arm:1;
1623         uint32_t        cqe_count:16,
1624                         :16;
1625         uint32_t        rsvd[1];
1626         struct {
1627                 uint32_t        low;
1628                 uint32_t        high;
1629         } page_physical_address[0];
1630 #else
1631 #error big endian version not defined
1632 #endif
1633 } sli4_req_common_create_cq_v2_t;
1634
1635 /**
1636  * @brief COMMON_CREATE_CQ_SET_V0
1637  *
1638  * Create a set of Completion Queues.
1639  */
1640 typedef struct sli4_req_common_create_cq_set_v0_s {
1641         sli4_req_hdr_t  hdr;
1642 #if BYTE_ORDER == LITTLE_ENDIAN
1643         uint32_t        num_pages:16,
1644                         page_size:8,
1645                         :8;
1646         uint32_t        :12,
1647                         clswm:2,
1648                         nodelay:1,
1649                         autovalid:1,
1650                         rsvd:11,
1651                         cqecnt:2,
1652                         valid:1,
1653                         :1,
1654                         evt:1;
1655         uint32_t        num_cq_req:16,
1656                         cqe_count:15,
1657                         arm:1;
1658         uint16_t        eq_id[16];
1659         struct {
1660                 uint32_t        low;
1661                 uint32_t        high;
1662         } page_physical_address[0];
1663 #else
1664 #error big endian version not defined
1665 #endif
1666 } sli4_req_common_create_cq_set_v0_t;
1667
1668 /**
1669  * CQE count.
1670  */
1671 #define SLI4_CQ_CNT_256                 0
1672 #define SLI4_CQ_CNT_512                 1
1673 #define SLI4_CQ_CNT_1024                2
1674 #define SLI4_CQ_CNT_LARGE               3
1675
1676 #define SLI4_CQE_BYTES                  (4 * sizeof(uint32_t))
1677
1678 #define SLI4_COMMON_CREATE_CQ_V2_MAX_PAGES 8
1679
1680 /**
1681  * @brief Generic Common Create EQ/CQ/MQ/WQ/RQ Queue completion
1682  */
1683 typedef struct sli4_res_common_create_queue_s {
1684         sli4_res_hdr_t  hdr;
1685 #if BYTE_ORDER == LITTLE_ENDIAN
1686         uint32_t q_id:16,
1687                 :8,
1688                 ulp:8;
1689         uint32_t db_offset;
1690         uint32_t db_rs:16,
1691                  db_fmt:16;
1692 #else
1693 #error big endian version not defined
1694 #endif
1695 } sli4_res_common_create_queue_t;
1696
1697 typedef struct sli4_res_common_create_queue_set_s {
1698         sli4_res_hdr_t  hdr;
1699 #if BYTE_ORDER == LITTLE_ENDIAN
1700         uint32_t q_id:16,
1701                 num_q_allocated:16;
1702 #else
1703 #error big endian version not defined
1704 #endif
1705 } sli4_res_common_create_queue_set_t;
1706
1707 /**
1708  * @brief Common Destroy CQ
1709  */
1710 typedef struct sli4_req_common_destroy_cq_s {
1711         sli4_req_hdr_t  hdr;
1712 #if BYTE_ORDER == LITTLE_ENDIAN
1713         uint32_t        cq_id:16,
1714                         :16;
1715 #else
1716 #error big endian version not defined
1717 #endif
1718 } sli4_req_common_destroy_cq_t;
1719
1720 /**
1721  * @brief COMMON_MODIFY_EQ_DELAY
1722  *
1723  * Modify the delay multiplier for EQs
1724  */
1725 typedef struct sli4_req_common_modify_eq_delay_s {
1726         sli4_req_hdr_t  hdr;
1727 #if BYTE_ORDER == LITTLE_ENDIAN
1728         uint32_t        num_eq;
1729         struct {
1730                 uint32_t        eq_id;
1731                 uint32_t        phase;
1732                 uint32_t        delay_multiplier;
1733         } eq_delay_record[8];
1734 #else
1735 #error big endian version not defined
1736 #endif
1737 } sli4_req_common_modify_eq_delay_t;
1738
1739 /**
1740  * @brief COMMON_CREATE_EQ
1741  *
1742  * Create an Event Queue.
1743  */
1744 typedef struct sli4_req_common_create_eq_s {
1745         sli4_req_hdr_t  hdr;
1746 #if BYTE_ORDER == LITTLE_ENDIAN
1747         uint32_t        num_pages:16,
1748                         :16;
1749         uint32_t        :28,
1750                         autovalid:1,
1751                         valid:1,
1752                         :1,
1753                         eqesz:1;
1754         uint32_t        :26,
1755                         count:3,
1756                         :2,
1757                         arm:1;
1758         uint32_t        :13,
1759                         delay_multiplier:10,
1760                         :9;
1761         uint32_t        rsvd;
1762         struct {
1763                 uint32_t        low;
1764                 uint32_t        high;
1765         } page_address[8];
1766 #else
1767 #error big endian version not defined
1768 #endif
1769 } sli4_req_common_create_eq_t;
1770
1771 #define SLI4_EQ_CNT_256                 0
1772 #define SLI4_EQ_CNT_512                 1
1773 #define SLI4_EQ_CNT_1024                2
1774 #define SLI4_EQ_CNT_2048                3
1775 #define SLI4_EQ_CNT_4096                4
1776
1777 #define SLI4_EQE_SIZE_4                 0
1778 #define SLI4_EQE_SIZE_16                1
1779
1780 /**
1781  * @brief Common Destroy EQ
1782  */
1783 typedef struct sli4_req_common_destroy_eq_s {
1784         sli4_req_hdr_t  hdr;
1785 #if BYTE_ORDER == LITTLE_ENDIAN
1786         uint32_t        eq_id:16,
1787                         :16;
1788 #else
1789 #error big endian version not defined
1790 #endif
1791 } sli4_req_common_destroy_eq_t;
1792
1793 /**
1794  * @brief COMMON_CREATE_MQ_EXT
1795  *
1796  * Create a Mailbox Queue; accommodate v0 and v1 forms.
1797  */
1798 typedef struct sli4_req_common_create_mq_ext_s {
1799         sli4_req_hdr_t  hdr;
1800 #if BYTE_ORDER == LITTLE_ENDIAN
1801         uint32_t        num_pages:16,
1802                         cq_id_v1:16;
1803         uint32_t        async_event_bitmap;
1804         uint32_t        async_cq_id_v1:16,
1805                         ring_size:4,
1806                         :2,
1807                         cq_id_v0:10;
1808         uint32_t        :31,
1809                         val:1;
1810         uint32_t        acqv:1,
1811                         async_cq_id_v0:10,
1812                         :21;
1813         uint32_t        rsvd9;
1814         struct {
1815                 uint32_t        low;
1816                 uint32_t        high;
1817         } page_physical_address[8];
1818 #else
1819 #error big endian version not defined
1820 #endif
1821 } sli4_req_common_create_mq_ext_t;
1822
1823 #define SLI4_MQE_SIZE_16                0x05
1824 #define SLI4_MQE_SIZE_32                0x06
1825 #define SLI4_MQE_SIZE_64                0x07
1826 #define SLI4_MQE_SIZE_128               0x08
1827
1828 #define SLI4_ASYNC_EVT_LINK_STATE       BIT(1)
1829 #define SLI4_ASYNC_EVT_FCOE_FIP         BIT(2)
1830 #define SLI4_ASYNC_EVT_DCBX             BIT(3)
1831 #define SLI4_ASYNC_EVT_ISCSI            BIT(4)
1832 #define SLI4_ASYNC_EVT_GRP5             BIT(5)
1833 #define SLI4_ASYNC_EVT_FC               BIT(16)
1834 #define SLI4_ASYNC_EVT_SLI_PORT         BIT(17)
1835 #define SLI4_ASYNC_EVT_VF               BIT(18)
1836 #define SLI4_ASYNC_EVT_MR               BIT(19)
1837
1838 #define SLI4_ASYNC_EVT_ALL      \
1839                 SLI4_ASYNC_EVT_LINK_STATE       | \
1840                 SLI4_ASYNC_EVT_FCOE_FIP         | \
1841                 SLI4_ASYNC_EVT_DCBX             | \
1842                 SLI4_ASYNC_EVT_ISCSI            | \
1843                 SLI4_ASYNC_EVT_GRP5             | \
1844                 SLI4_ASYNC_EVT_FC               | \
1845                 SLI4_ASYNC_EVT_SLI_PORT         | \
1846                 SLI4_ASYNC_EVT_VF               |\
1847                 SLI4_ASYNC_EVT_MR
1848
1849 #define SLI4_ASYNC_EVT_FC_FCOE \
1850                 SLI4_ASYNC_EVT_LINK_STATE       | \
1851                 SLI4_ASYNC_EVT_FCOE_FIP         | \
1852                 SLI4_ASYNC_EVT_GRP5             | \
1853                 SLI4_ASYNC_EVT_FC               | \
1854                 SLI4_ASYNC_EVT_SLI_PORT
1855
1856 /**
1857  * @brief Common Destroy MQ
1858  */
1859 typedef struct sli4_req_common_destroy_mq_s {
1860         sli4_req_hdr_t  hdr;
1861 #if BYTE_ORDER == LITTLE_ENDIAN
1862         uint32_t        mq_id:16,
1863                         :16;
1864 #else
1865 #error big endian version not defined
1866 #endif
1867 } sli4_req_common_destroy_mq_t;
1868
1869 /**
1870  * @brief COMMON_GET_CNTL_ATTRIBUTES
1871  *
1872  * Query for information about the SLI Port
1873  */
1874 typedef struct sli4_res_common_get_cntl_attributes_s {
1875         sli4_res_hdr_t  hdr;
1876 #if BYTE_ORDER == LITTLE_ENDIAN
1877         uint8_t         version_string[32];
1878         uint8_t         manufacturer_name[32];
1879         uint32_t        supported_modes;
1880         uint32_t        eprom_version_lo:8,
1881                         eprom_version_hi:8,
1882                         :16;
1883         uint32_t        mbx_data_structure_version;
1884         uint32_t        ep_firmware_data_structure_version;
1885         uint8_t         ncsi_version_string[12];
1886         uint32_t        default_extended_timeout;
1887         uint8_t         model_number[32];
1888         uint8_t         description[64];
1889         uint8_t         serial_number[32];
1890         uint8_t         ip_version_string[32];
1891         uint8_t         fw_version_string[32];
1892         uint8_t         bios_version_string[32];
1893         uint8_t         redboot_version_string[32];
1894         uint8_t         driver_version_string[32];
1895         uint8_t         fw_on_flash_version_string[32];
1896         uint32_t        functionalities_supported;
1897         uint32_t        max_cdb_length:16,
1898                         asic_revision:8,
1899                         generational_guid0:8;
1900         uint32_t        generational_guid1_12[3];
1901         uint32_t        generational_guid13:24,
1902                         hba_port_count:8;
1903         uint32_t        default_link_down_timeout:16,
1904                         iscsi_version_min_max:8,
1905                         multifunctional_device:8;
1906         uint32_t        cache_valid:8,
1907                         hba_status:8,
1908                         max_domains_supported:8,
1909                         port_number:6,
1910                         port_type:2;
1911         uint32_t        firmware_post_status;
1912         uint32_t        hba_mtu;
1913         uint32_t        iscsi_features:8,
1914                         rsvd121:24;
1915         uint32_t        pci_vendor_id:16,
1916                         pci_device_id:16;
1917         uint32_t        pci_sub_vendor_id:16,
1918                         pci_sub_system_id:16;
1919         uint32_t        pci_bus_number:8,
1920                         pci_device_number:8,
1921                         pci_function_number:8,
1922                         interface_type:8;
1923         uint64_t        unique_identifier;
1924         uint32_t        number_of_netfilters:8,
1925                         rsvd130:24;
1926 #else
1927 #error big endian version not defined
1928 #endif
1929 } sli4_res_common_get_cntl_attributes_t;
1930
1931 /**
1932  * @brief COMMON_GET_CNTL_ATTRIBUTES
1933  *
1934  * This command queries the controller information from the Flash ROM.
1935  */
1936 typedef struct sli4_req_common_get_cntl_addl_attributes_s {
1937         sli4_req_hdr_t  hdr;
1938 } sli4_req_common_get_cntl_addl_attributes_t;
1939
1940 typedef struct sli4_res_common_get_cntl_addl_attributes_s {
1941         sli4_res_hdr_t  hdr;
1942         uint16_t        ipl_file_number;
1943         uint8_t         ipl_file_version;
1944         uint8_t         rsvd0;
1945         uint8_t         on_die_temperature;
1946         uint8_t         rsvd1[3];
1947         uint32_t        driver_advanced_features_supported;
1948         uint32_t        rsvd2[4];
1949         char            fcoe_universal_bios_version[32];
1950         char            fcoe_x86_bios_version[32];
1951         char            fcoe_efi_bios_version[32];
1952         char            fcoe_fcode_version[32];
1953         char            uefi_bios_version[32];
1954         char            uefi_nic_version[32];
1955         char            uefi_fcode_version[32];
1956         char            uefi_iscsi_version[32];
1957         char            iscsi_x86_bios_version[32];
1958         char            pxe_x86_bios_version[32];
1959         uint8_t         fcoe_default_wwpn[8];
1960         uint8_t         ext_phy_version[32];
1961         uint8_t         fc_universal_bios_version[32];
1962         uint8_t         fc_x86_bios_version[32];
1963         uint8_t         fc_efi_bios_version[32];
1964         uint8_t         fc_fcode_version[32];
1965         uint8_t         ext_phy_crc_label[8];
1966         uint8_t         ipl_file_name[16];
1967         uint8_t         rsvd3[72];
1968 } sli4_res_common_get_cntl_addl_attributes_t;
1969
1970 /**
1971  * @brief COMMON_NOP
1972  *
1973  * This command does not do anything; it only returns the payload in the completion.
1974  */
1975 typedef struct sli4_req_common_nop_s {
1976         sli4_req_hdr_t  hdr;
1977 #if BYTE_ORDER == LITTLE_ENDIAN
1978         uint32_t        context[2];
1979 #else
1980 #error big endian version not defined
1981 #endif
1982 } sli4_req_common_nop_t;
1983
1984 typedef struct sli4_res_common_nop_s {
1985         sli4_res_hdr_t  hdr;
1986 #if BYTE_ORDER == LITTLE_ENDIAN
1987         uint32_t        context[2];
1988 #else
1989 #error big endian version not defined
1990 #endif
1991 } sli4_res_common_nop_t;
1992
1993 /**
1994  * @brief COMMON_GET_RESOURCE_EXTENT_INFO
1995  */
1996 typedef struct sli4_req_common_get_resource_extent_info_s {
1997         sli4_req_hdr_t  hdr;
1998 #if BYTE_ORDER == LITTLE_ENDIAN
1999         uint32_t        resource_type:16,
2000                         :16;
2001 #else
2002 #error big endian version not defined
2003 #endif
2004 } sli4_req_common_get_resource_extent_info_t;
2005
2006 #define SLI4_RSC_TYPE_ISCSI_INI_XRI     0x0c
2007 #define SLI4_RSC_TYPE_FCOE_VFI          0x20
2008 #define SLI4_RSC_TYPE_FCOE_VPI          0x21
2009 #define SLI4_RSC_TYPE_FCOE_RPI          0x22
2010 #define SLI4_RSC_TYPE_FCOE_XRI          0x23
2011
2012 typedef struct sli4_res_common_get_resource_extent_info_s {
2013         sli4_res_hdr_t  hdr;
2014 #if BYTE_ORDER == LITTLE_ENDIAN
2015         uint32_t        resource_extent_count:16,
2016                         resource_extent_size:16;
2017 #else
2018 #error big endian version not defined
2019 #endif
2020 } sli4_res_common_get_resource_extent_info_t;
2021
2022 #define SLI4_128BYTE_WQE_SUPPORT        0x02
2023 /**
2024  * @brief COMMON_GET_SLI4_PARAMETERS
2025  */
2026 typedef struct sli4_res_common_get_sli4_parameters_s {
2027         sli4_res_hdr_t  hdr;
2028 #if BYTE_ORDER == LITTLE_ENDIAN
2029         uint32_t        protocol_type:8,
2030                         :24;
2031         uint32_t        ft:1,
2032                         :3,
2033                         sli_revision:4,
2034                         sli_family:4,
2035                         if_type:4,
2036                         sli_hint_1:8,
2037                         sli_hint_2:5,
2038                         :3;
2039         uint32_t        eq_page_cnt:4,
2040                         :4,
2041                         eqe_sizes:4,
2042                         :4,
2043                         eq_page_sizes:8,
2044                         eqe_count_method:4,
2045                         :4;
2046         uint32_t        eqe_count_mask:16,
2047                         :16;
2048         uint32_t        cq_page_cnt:4,
2049                         :4,
2050                         cqe_sizes:4,
2051                         :2,
2052                         cqv:2,
2053                         cq_page_sizes:8,
2054                         cqe_count_method:4,
2055                         :4;
2056         uint32_t        cqe_count_mask:16,
2057                         :16;
2058         uint32_t        mq_page_cnt:4,
2059                         :10,
2060                         mqv:2,
2061                         mq_page_sizes:8,
2062                         mqe_count_method:4,
2063                         :4;
2064         uint32_t        mqe_count_mask:16,
2065                         :16;
2066         uint32_t        wq_page_cnt:4,
2067                         :4,
2068                         wqe_sizes:4,
2069                         :2,
2070                         wqv:2,
2071                         wq_page_sizes:8,
2072                         wqe_count_method:4,
2073                         :4;
2074         uint32_t        wqe_count_mask:16,
2075                         :16;
2076         uint32_t        rq_page_cnt:4,
2077                         :4,
2078                         rqe_sizes:4,
2079                         :2,
2080                         rqv:2,
2081                         rq_page_sizes:8,
2082                         rqe_count_method:4,
2083                         :4;
2084         uint32_t        rqe_count_mask:16,
2085                         :12,
2086                         rq_db_window:4;
2087         uint32_t        fcoe:1,
2088                         ext:1,
2089                         hdrr:1,
2090                         sglr:1,
2091                         fbrr:1,
2092                         areg:1,
2093                         tgt:1,
2094                         terp:1,
2095                         assi:1,
2096                         wchn:1,
2097                         tcca:1,
2098                         trty:1,
2099                         trir:1,
2100                         phoff:1,
2101                         phon:1,
2102                         phwq:1,                 /** Performance Hint WQ_ID Association */
2103                         boundary_4ga:1,
2104                         rxc:1,
2105                         hlm:1,
2106                         ipr:1,
2107                         rxri:1,
2108                         sglc:1,
2109                         timm:1,
2110                         tsmm:1,
2111                         :1,
2112                         oas:1,
2113                         lc:1,
2114                         agxf:1,
2115                         loopback_scope:4;
2116         uint32_t        sge_supported_length;
2117         uint32_t        sgl_page_cnt:4,
2118                         :4,
2119                         sgl_page_sizes:8,
2120                         sgl_pp_align:8,
2121                         :8;
2122         uint32_t        min_rq_buffer_size:16,
2123                         :16;
2124         uint32_t        max_rq_buffer_size;
2125         uint32_t        physical_xri_max:16,
2126                         physical_rpi_max:16;
2127         uint32_t        physical_vpi_max:16,
2128                         physical_vfi_max:16;
2129         uint32_t        rsvd19;
2130         uint32_t        frag_num_field_offset:16,       /* dword 20 */
2131                         frag_num_field_size:16;
2132         uint32_t        sgl_index_field_offset:16,      /* dword 21 */
2133                         sgl_index_field_size:16;
2134         uint32_t        chain_sge_initial_value_lo;     /* dword 22 */
2135         uint32_t        chain_sge_initial_value_hi;     /* dword 23 */
2136 #else
2137 #error big endian version not defined
2138 #endif
2139 } sli4_res_common_get_sli4_parameters_t;
2140
2141 /**
2142  * @brief COMMON_QUERY_FW_CONFIG
2143  *
2144  * This command retrieves firmware configuration parameters and adapter
2145  * resources available to the driver.
2146  */
2147 typedef struct sli4_req_common_query_fw_config_s {
2148         sli4_req_hdr_t  hdr;
2149 } sli4_req_common_query_fw_config_t;
2150
2151 #define SLI4_FUNCTION_MODE_FCOE_INI_MODE 0x40
2152 #define SLI4_FUNCTION_MODE_FCOE_TGT_MODE 0x80
2153 #define SLI4_FUNCTION_MODE_DUA_MODE      0x800
2154
2155 #define SLI4_ULP_MODE_FCOE_INI           0x40
2156 #define SLI4_ULP_MODE_FCOE_TGT           0x80
2157
2158 typedef struct sli4_res_common_query_fw_config_s {
2159         sli4_res_hdr_t  hdr;
2160         uint32_t        config_number;
2161         uint32_t        asic_rev;
2162         uint32_t        physical_port;
2163         uint32_t        function_mode;
2164         uint32_t        ulp0_mode;
2165         uint32_t        ulp0_nic_wqid_base;
2166         uint32_t        ulp0_nic_wq_total; /* Dword 10 */
2167         uint32_t        ulp0_toe_wqid_base;
2168         uint32_t        ulp0_toe_wq_total;
2169         uint32_t        ulp0_toe_rqid_base;
2170         uint32_t        ulp0_toe_rq_total;
2171         uint32_t        ulp0_toe_defrqid_base;
2172         uint32_t        ulp0_toe_defrq_total;
2173         uint32_t        ulp0_lro_rqid_base;
2174         uint32_t        ulp0_lro_rq_total;
2175         uint32_t        ulp0_iscsi_icd_base;
2176         uint32_t        ulp0_iscsi_icd_total; /* Dword 20 */
2177         uint32_t        ulp1_mode;
2178         uint32_t        ulp1_nic_wqid_base;
2179         uint32_t        ulp1_nic_wq_total;
2180         uint32_t        ulp1_toe_wqid_base;
2181         uint32_t        ulp1_toe_wq_total;
2182         uint32_t        ulp1_toe_rqid_base;
2183         uint32_t        ulp1_toe_rq_total;
2184         uint32_t        ulp1_toe_defrqid_base;
2185         uint32_t        ulp1_toe_defrq_total;
2186         uint32_t        ulp1_lro_rqid_base;  /* Dword 30 */
2187         uint32_t        ulp1_lro_rq_total;
2188         uint32_t        ulp1_iscsi_icd_base;
2189         uint32_t        ulp1_iscsi_icd_total;
2190         uint32_t        function_capabilities;
2191         uint32_t        ulp0_cq_base;
2192         uint32_t        ulp0_cq_total;
2193         uint32_t        ulp0_eq_base;
2194         uint32_t        ulp0_eq_total;
2195         uint32_t        ulp0_iscsi_chain_icd_base;
2196         uint32_t        ulp0_iscsi_chain_icd_total;  /* Dword 40 */
2197         uint32_t        ulp1_iscsi_chain_icd_base;
2198         uint32_t        ulp1_iscsi_chain_icd_total;
2199 } sli4_res_common_query_fw_config_t;
2200
2201 /**
2202  * @brief COMMON_GET_PORT_NAME
2203  */
2204 typedef struct sli4_req_common_get_port_name_s {
2205         sli4_req_hdr_t  hdr;
2206 #if BYTE_ORDER == LITTLE_ENDIAN
2207         uint32_t        pt:2,           /* only COMMON_GET_PORT_NAME_V1 */
2208                         :30;
2209 #else
2210 #error big endian version not defined
2211 #endif
2212 } sli4_req_common_get_port_name_t;
2213
2214 typedef struct sli4_res_common_get_port_name_s {
2215         sli4_res_hdr_t  hdr;
2216         char            port_name[4];
2217 } sli4_res_common_get_port_name_t;
2218
2219 /**
2220  * @brief COMMON_WRITE_FLASHROM
2221  */
2222 typedef struct sli4_req_common_write_flashrom_s {
2223         sli4_req_hdr_t  hdr;
2224 #if BYTE_ORDER == LITTLE_ENDIAN
2225         uint32_t        flash_rom_access_opcode;
2226         uint32_t        flash_rom_access_operation_type;
2227         uint32_t        data_buffer_size;
2228         uint32_t        offset;
2229         uint8_t         data_buffer[4];
2230 #else
2231 #error big endian version not defined
2232 #endif
2233 } sli4_req_common_write_flashrom_t;
2234
2235 #define SLI4_MGMT_FLASHROM_OPCODE_FLASH                 0x01
2236 #define SLI4_MGMT_FLASHROM_OPCODE_SAVE                  0x02
2237 #define SLI4_MGMT_FLASHROM_OPCODE_CLEAR                 0x03
2238 #define SLI4_MGMT_FLASHROM_OPCODE_REPORT                0x04
2239 #define SLI4_MGMT_FLASHROM_OPCODE_IMAGE_INFO            0x05
2240 #define SLI4_MGMT_FLASHROM_OPCODE_IMAGE_CRC             0x06
2241 #define SLI4_MGMT_FLASHROM_OPCODE_OFFSET_BASED_FLASH    0x07
2242 #define SLI4_MGMT_FLASHROM_OPCODE_OFFSET_BASED_SAVE     0x08
2243 #define SLI4_MGMT_PHY_FLASHROM_OPCODE_FLASH             0x09
2244 #define SLI4_MGMT_PHY_FLASHROM_OPCODE_SAVE              0x0a
2245
2246 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_ISCSI             0x00
2247 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_REDBOOT           0x01
2248 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_BIOS              0x02
2249 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_PXE_BIOS          0x03
2250 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_CODE_CONTROL      0x04
2251 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_IPSEC_CFG         0x05
2252 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_INIT_DATA         0x06
2253 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_ROM_OFFSET        0x07
2254 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_FCOE_BIOS         0x08
2255 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_ISCSI_BAK         0x09
2256 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_FCOE_ACT          0x0a
2257 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_FCOE_BAK          0x0b
2258 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_CODE_CTRL_P       0x0c
2259 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_NCSI              0x0d
2260 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_NIC               0x0e
2261 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_DCBX              0x0f
2262 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_PXE_BIOS_CFG      0x10
2263 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_ALL_CFG_DATA      0x11
2264
2265 /**
2266  * @brief COMMON_MANAGE_FAT
2267  */
2268 typedef struct sli4_req_common_manage_fat_s {
2269         sli4_req_hdr_t  hdr;
2270 #if BYTE_ORDER == LITTLE_ENDIAN
2271         uint32_t        fat_operation;
2272         uint32_t        read_log_offset;
2273         uint32_t        read_log_length;
2274         uint32_t        data_buffer_size;
2275         uint32_t        data_buffer;            /* response only */
2276 #else
2277 #error big endian version not defined
2278 #endif
2279 } sli4_req_common_manage_fat_t;
2280
2281 /**
2282  * @brief COMMON_GET_EXT_FAT_CAPABILITIES
2283  */
2284 typedef struct sli4_req_common_get_ext_fat_capabilities_s {
2285         sli4_req_hdr_t  hdr;
2286 #if BYTE_ORDER == LITTLE_ENDIAN
2287         uint32_t        parameter_type;
2288 #else
2289 #error big endian version not defined
2290 #endif
2291 } sli4_req_common_get_ext_fat_capabilities_t;
2292
2293 /**
2294  * @brief COMMON_SET_EXT_FAT_CAPABILITIES
2295  */
2296 typedef struct sli4_req_common_set_ext_fat_capabilities_s {
2297         sli4_req_hdr_t  hdr;
2298 #if BYTE_ORDER == LITTLE_ENDIAN
2299         uint32_t        maximum_log_entries;
2300         uint32_t        log_entry_size;
2301         uint32_t        logging_type:8,
2302                         maximum_logging_functions:8,
2303                         maximum_logging_ports:8,
2304                         :8;
2305         uint32_t        supported_modes;
2306         uint32_t        number_modules;
2307         uint32_t        debug_module[14];
2308 #else
2309 #error big endian version not defined
2310 #endif
2311 } sli4_req_common_set_ext_fat_capabilities_t;
2312
2313 /**
2314  * @brief COMMON_EXT_FAT_CONFIGURE_SNAPSHOT
2315  */
2316 typedef struct sli4_req_common_ext_fat_configure_snapshot_s {
2317         sli4_req_hdr_t  hdr;
2318 #if BYTE_ORDER == LITTLE_ENDIAN
2319         uint32_t        total_log_entries;
2320 #else
2321 #error big endian version not defined
2322 #endif
2323 } sli4_req_common_ext_fat_configure_snapshot_t;
2324
2325 /**
2326  * @brief COMMON_EXT_FAT_RETRIEVE_SNAPSHOT
2327  */
2328 typedef struct sli4_req_common_ext_fat_retrieve_snapshot_s {
2329         sli4_req_hdr_t  hdr;
2330 #if BYTE_ORDER == LITTLE_ENDIAN
2331         uint32_t        snapshot_mode;
2332         uint32_t        start_index;
2333         uint32_t        number_log_entries;
2334 #else
2335 #error big endian version not defined
2336 #endif
2337 } sli4_req_common_ext_fat_retrieve_snapshot_t;
2338
2339 typedef struct sli4_res_common_ext_fat_retrieve_snapshot_s {
2340         sli4_res_hdr_t  hdr;
2341 #if BYTE_ORDER == LITTLE_ENDIAN
2342         uint32_t        number_log_entries;
2343         uint32_t        version:8,
2344                         physical_port:8,
2345                         function_id:16;
2346         uint32_t        trace_level;
2347         uint32_t        module_mask[2];
2348         uint32_t        trace_table_index;
2349         uint32_t        timestamp;
2350         uint8_t         string_data[16];
2351         uint32_t        data[6];
2352 #else
2353 #error big endian version not defined
2354 #endif
2355 } sli4_res_common_ext_fat_retrieve_snapshot_t;
2356
2357 /**
2358  * @brief COMMON_EXT_FAT_READ_STRING_TABLE
2359  */
2360 typedef struct sli4_req_common_ext_fat_read_string_table_s {
2361         sli4_req_hdr_t  hdr;
2362 #if BYTE_ORDER == LITTLE_ENDIAN
2363         uint32_t        byte_offset;
2364         uint32_t        number_bytes;
2365 #else
2366 #error big endian version not defined
2367 #endif
2368 } sli4_req_common_ext_fat_read_string_table_t;
2369
2370 typedef struct sli4_res_common_ext_fat_read_string_table_s {
2371         sli4_res_hdr_t  hdr;
2372 #if BYTE_ORDER == LITTLE_ENDIAN
2373         uint32_t        number_returned_bytes;
2374         uint32_t        number_remaining_bytes;
2375         uint32_t        table_data0:8,
2376                         :24;
2377         uint8_t         table_data[0];
2378 #else
2379 #error big endian version not defined
2380 #endif
2381 } sli4_res_common_ext_fat_read_string_table_t;
2382
2383 /**
2384  * @brief COMMON_READ_TRANSCEIVER_DATA
2385  *
2386  * This command reads SFF transceiver data(Format is defined
2387  * by the SFF-8472 specification).
2388  */
2389 typedef struct sli4_req_common_read_transceiver_data_s {
2390         sli4_req_hdr_t  hdr;
2391 #if BYTE_ORDER == LITTLE_ENDIAN
2392         uint32_t        page_number;
2393         uint32_t        port;
2394 #else
2395 #error big endian version not defined
2396 #endif
2397 } sli4_req_common_read_transceiver_data_t;
2398
2399 typedef struct sli4_res_common_read_transceiver_data_s {
2400         sli4_res_hdr_t  hdr;
2401 #if BYTE_ORDER == LITTLE_ENDIAN
2402         uint32_t        page_number;
2403         uint32_t        port;
2404         uint32_t        page_data[32];
2405         uint32_t        page_data_2[32];
2406 #else
2407 #error big endian version not defined
2408 #endif
2409 } sli4_res_common_read_transceiver_data_t;
2410
2411 /**
2412  * @brief COMMON_READ_OBJECT
2413  */
2414 typedef struct sli4_req_common_read_object_s {
2415         sli4_req_hdr_t  hdr;
2416 #if BYTE_ORDER == LITTLE_ENDIAN
2417         uint32_t        desired_read_length:24,
2418                         :8;
2419         uint32_t        read_offset;
2420         uint8_t         object_name[104];
2421         uint32_t        host_buffer_descriptor_count;
2422         sli4_bde_t      host_buffer_descriptor[0];
2423 #else
2424 #error big endian version not defined
2425 #endif
2426 } sli4_req_common_read_object_t;
2427
2428 typedef struct sli4_res_common_read_object_s {
2429         sli4_res_hdr_t  hdr;
2430 #if BYTE_ORDER == LITTLE_ENDIAN
2431         uint32_t        actual_read_length;
2432         uint32_t        resv:31,
2433                         eof:1;
2434 #else
2435 #error big endian version not defined
2436 #endif
2437 } sli4_res_common_read_object_t;
2438
2439 /**
2440  * @brief COMMON_WRITE_OBJECT
2441  */
2442 typedef struct sli4_req_common_write_object_s {
2443         sli4_req_hdr_t  hdr;
2444 #if BYTE_ORDER == LITTLE_ENDIAN
2445         uint32_t        desired_write_length:24,
2446                         :6,
2447                         noc:1,
2448                         eof:1;
2449         uint32_t        write_offset;
2450         uint8_t         object_name[104];
2451         uint32_t        host_buffer_descriptor_count;
2452         sli4_bde_t      host_buffer_descriptor[0];
2453 #else
2454 #error big endian version not defined
2455 #endif
2456 } sli4_req_common_write_object_t;
2457
2458 typedef struct sli4_res_common_write_object_s {
2459         sli4_res_hdr_t  hdr;
2460 #if BYTE_ORDER == LITTLE_ENDIAN
2461         uint32_t        actual_write_length;
2462         uint32_t        change_status:8,
2463                         :24;
2464 #else
2465 #error big endian version not defined
2466 #endif
2467 } sli4_res_common_write_object_t;
2468
2469 /**
2470  * @brief COMMON_DELETE_OBJECT
2471  */
2472 typedef struct sli4_req_common_delete_object_s {
2473         sli4_req_hdr_t  hdr;
2474 #if BYTE_ORDER == LITTLE_ENDIAN
2475         uint32_t        rsvd4;
2476         uint32_t        rsvd5;
2477         uint8_t         object_name[104];
2478 #else
2479 #error big endian version not defined
2480 #endif
2481 } sli4_req_common_delete_object_t;
2482
2483 /**
2484  * @brief COMMON_READ_OBJECT_LIST
2485  */
2486 typedef struct sli4_req_common_read_object_list_s {
2487         sli4_req_hdr_t  hdr;
2488 #if BYTE_ORDER == LITTLE_ENDIAN
2489         uint32_t        desired_read_length:24,
2490                         :8;
2491         uint32_t        read_offset;
2492         uint8_t         object_name[104];
2493         uint32_t        host_buffer_descriptor_count;
2494         sli4_bde_t      host_buffer_descriptor[0];
2495 #else
2496 #error big endian version not defined
2497 #endif
2498 } sli4_req_common_read_object_list_t;
2499
2500 /**
2501  * @brief COMMON_SET_DUMP_LOCATION
2502  */
2503 typedef struct sli4_req_common_set_dump_location_s {
2504         sli4_req_hdr_t  hdr;
2505 #if BYTE_ORDER == LITTLE_ENDIAN
2506         uint32_t        buffer_length:24,
2507                         :5,
2508                         fdb:1,
2509                         blp:1,
2510                         qry:1;
2511         uint32_t        buf_addr_low;
2512         uint32_t        buf_addr_high;
2513 #else
2514 #error big endian version not defined
2515 #endif
2516 } sli4_req_common_set_dump_location_t;
2517
2518 typedef struct sli4_res_common_set_dump_location_s {
2519         sli4_res_hdr_t  hdr;
2520 #if BYTE_ORDER == LITTLE_ENDIAN
2521         uint32_t        buffer_length:24,
2522                         :8;
2523 #else
2524 #error big endian version not defined
2525 #endif
2526 }sli4_res_common_set_dump_location_t;
2527
2528 /**
2529  * @brief COMMON_SET_SET_FEATURES
2530  */
2531 #define SLI4_SET_FEATURES_DIF_SEED                      0x01
2532 #define SLI4_SET_FEATURES_XRI_TIMER                     0x03
2533 #define SLI4_SET_FEATURES_MAX_PCIE_SPEED                0x04
2534 #define SLI4_SET_FEATURES_FCTL_CHECK                    0x05
2535 #define SLI4_SET_FEATURES_FEC                           0x06
2536 #define SLI4_SET_FEATURES_PCIE_RECV_DETECT              0x07
2537 #define SLI4_SET_FEATURES_DIF_MEMORY_MODE               0x08
2538 #define SLI4_SET_FEATURES_DISABLE_SLI_PORT_PAUSE_STATE  0x09
2539 #define SLI4_SET_FEATURES_ENABLE_PCIE_OPTIONS           0x0A
2540 #define SLI4_SET_FEATURES_SET_CONFIG_AUTO_XFER_RDY_T10PI        0x0C
2541 #define SLI4_SET_FEATURES_ENABLE_MULTI_RECEIVE_QUEUE    0x0D
2542 #define SLI4_SET_FEATURES_SET_FTD_XFER_HINT             0x0F
2543 #define SLI4_SET_FEATURES_SLI_PORT_HEALTH_CHECK         0x11
2544 #define SLI4_SET_FEATURES_PERSISTENT_TOPOLOGY          0x20
2545
2546 typedef struct sli4_req_common_set_features_s {
2547         sli4_req_hdr_t  hdr;
2548 #if BYTE_ORDER == LITTLE_ENDIAN
2549         uint32_t        feature;
2550         uint32_t        param_len;
2551         uint32_t        params[8];
2552 #else
2553 #error big endian version not defined
2554 #endif
2555 } sli4_req_common_set_features_t;
2556
2557 typedef struct sli4_req_common_set_features_dif_seed_s {
2558 #if BYTE_ORDER == LITTLE_ENDIAN
2559         uint32_t        seed:16,
2560                 :16;
2561 #else
2562 #error big endian version not defined
2563 #endif
2564 } sli4_req_common_set_features_dif_seed_t;
2565
2566 typedef struct sli4_req_common_set_features_t10_pi_mem_model_s {
2567 #if BYTE_ORDER == LITTLE_ENDIAN
2568         uint32_t        tmm:1,
2569                 :31;
2570 #else
2571 #error big endian version not defined
2572 #endif
2573 } sli4_req_common_set_features_t10_pi_mem_model_t;
2574
2575 typedef struct sli4_req_common_set_features_multirq_s {
2576 #if BYTE_ORDER == LITTLE_ENDIAN
2577         uint32_t        isr:1,                  /*<< Include Sequence Reporting */
2578                         agxfe:1,                /*<< Auto Generate XFER-RDY Feature Enabled */
2579                         :30;
2580         uint32_t        num_rqs:8,
2581                         rq_select_policy:4,
2582                         :20;
2583 #else
2584 #error big endian version not defined
2585 #endif
2586 } sli4_req_common_set_features_multirq_t;
2587
2588 typedef struct sli4_req_common_set_features_xfer_rdy_t10pi_s {
2589 #if BYTE_ORDER == LITTLE_ENDIAN
2590         uint32_t        rtc:1,
2591                         atv:1,
2592                         tmm:1,
2593                         :1,
2594                         p_type:3,
2595                         blk_size:3,
2596                         :22;
2597         uint32_t        app_tag:16,
2598                         :16;
2599 #else
2600 #error big endian version not defined
2601 #endif
2602 } sli4_req_common_set_features_xfer_rdy_t10pi_t;
2603
2604 typedef struct sli4_req_common_set_features_health_check_s {
2605 #if BYTE_ORDER == LITTLE_ENDIAN
2606         uint32_t        hck:1,
2607                         qry:1,
2608                         :30;
2609 #else
2610 #error big endian version not defined
2611 #endif
2612 } sli4_req_common_set_features_health_check_t;
2613
2614 typedef struct sli4_req_common_set_features_set_fdt_xfer_hint_s {
2615 #if BYTE_ORDER == LITTLE_ENDIAN
2616         uint32_t        fdt_xfer_hint;
2617 #else
2618 #error big endian version not defined
2619 #endif
2620 } sli4_req_common_set_features_set_fdt_xfer_hint_t;
2621
2622 typedef struct sli4_req_common_set_features_persistent_topo_param_s {
2623 #if BYTE_ORDER == LITTLE_ENDIAN
2624        uint32_t        persistent_topo:2,
2625                        topo_failover:1,
2626                        :29;
2627 #else
2628 #error big endian version not defined
2629 #endif
2630 } sli4_req_common_set_features_persistent_topo_param_t;
2631
2632 /**
2633  * @brief DMTF_EXEC_CLP_CMD
2634  */
2635 typedef struct sli4_req_dmtf_exec_clp_cmd_s {
2636         sli4_req_hdr_t  hdr;
2637 #if BYTE_ORDER == LITTLE_ENDIAN
2638         uint32_t        cmd_buf_length;
2639         uint32_t        resp_buf_length;
2640         uint32_t        cmd_buf_addr_low;
2641         uint32_t        cmd_buf_addr_high;
2642         uint32_t        resp_buf_addr_low;
2643         uint32_t        resp_buf_addr_high;
2644 #else
2645 #error big endian version not defined
2646 #endif
2647 } sli4_req_dmtf_exec_clp_cmd_t;
2648
2649 typedef struct sli4_res_dmtf_exec_clp_cmd_s {
2650         sli4_res_hdr_t  hdr;
2651 #if BYTE_ORDER == LITTLE_ENDIAN
2652         uint32_t        :32;
2653         uint32_t        resp_length;
2654         uint32_t        :32;
2655         uint32_t        :32;
2656         uint32_t        :32;
2657         uint32_t        :32;
2658         uint32_t        clp_status;
2659         uint32_t        clp_detailed_status;
2660 #else
2661 #error big endian version not defined
2662 #endif
2663 } sli4_res_dmtf_exec_clp_cmd_t;
2664
2665 /**
2666  * @brief Resource descriptor
2667  */
2668
2669 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_PCIE      0x50
2670 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_NIC       0x51
2671 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_ISCSI     0x52
2672 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_FCFCOE    0x53
2673 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_RDMA      0x54
2674 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_PORT      0x55
2675 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_ISAP      0x56
2676
2677 #define SLI4_PROTOCOL_NIC_TOE                   0x01
2678 #define SLI4_PROTOCOL_ISCSI                     0x02
2679 #define SLI4_PROTOCOL_FCOE                      0x04
2680 #define SLI4_PROTOCOL_NIC_TOE_RDMA              0x08
2681 #define SLI4_PROTOCOL_FC                        0x10
2682 #define SLI4_PROTOCOL_DEFAULT                   0xff
2683
2684 typedef struct sli4_resource_descriptor_v1_s {
2685         uint32_t        descriptor_type:8,
2686                         descriptor_length:8,
2687                         :16;
2688         uint32_t        type_specific[0];
2689 } sli4_resource_descriptor_v1_t;
2690
2691 typedef struct sli4_pcie_resource_descriptor_v1_s {
2692         uint32_t        descriptor_type:8,
2693                         descriptor_length:8,
2694                         :14,
2695                         imm:1,
2696                         nosv:1;
2697         uint32_t        :16,
2698                         pf_number:10,
2699                         :6;
2700         uint32_t        rsvd1;
2701         uint32_t        sriov_state:8,
2702                         pf_state:8,
2703                         pf_type:8,
2704                         :8;
2705         uint32_t        number_of_vfs:16,
2706                         :16;
2707         uint32_t        mission_roles:8,
2708                         :19,
2709                         pchg:1,
2710                         schg:1,
2711                         xchg:1,
2712                         xrom:2;
2713         uint32_t        rsvd2[16];
2714 } sli4_pcie_resource_descriptor_v1_t;
2715
2716 typedef struct sli4_isap_resource_descriptor_v1_s {
2717         uint32_t        descriptor_type:8,
2718                         descriptor_length:8,
2719                         :16;
2720         uint32_t        iscsi_tgt:1,
2721                         iscsi_ini:1,
2722                         iscsi_dif:1,
2723                         :29;
2724         uint32_t        rsvd1[3];
2725         uint32_t        fcoe_tgt:1,
2726                         fcoe_ini:1,
2727                         fcoe_dif:1,
2728                         :29;
2729         uint32_t        rsvd2[7];
2730         uint32_t        mc_type0:8,
2731                         mc_type1:8,
2732                         mc_type2:8,
2733                         mc_type3:8;
2734         uint32_t        rsvd3[3];
2735 } sli4_isap_resouce_descriptor_v1_t;
2736
2737 /**
2738  * @brief COMMON_GET_FUNCTION_CONFIG
2739  */
2740 typedef struct sli4_req_common_get_function_config_s {
2741         sli4_req_hdr_t  hdr;
2742 } sli4_req_common_get_function_config_t;
2743
2744 typedef struct sli4_res_common_get_function_config_s {
2745         sli4_res_hdr_t  hdr;
2746 #if BYTE_ORDER == LITTLE_ENDIAN
2747         uint32_t        desc_count;
2748         uint32_t        desc[54];
2749 #else
2750 #error big endian version not defined
2751 #endif
2752 } sli4_res_common_get_function_config_t;
2753
2754 /**
2755  * @brief COMMON_GET_PROFILE_CONFIG
2756  */
2757 typedef struct sli4_req_common_get_profile_config_s {
2758         sli4_req_hdr_t  hdr;
2759         uint32_t        profile_id:8,
2760                         typ:2,
2761                         :22;
2762 } sli4_req_common_get_profile_config_t;
2763
2764 typedef struct sli4_res_common_get_profile_config_s {
2765         sli4_res_hdr_t  hdr;
2766 #if BYTE_ORDER == LITTLE_ENDIAN
2767         uint32_t        desc_count;
2768         uint32_t        desc[0];
2769 #else
2770 #error big endian version not defined
2771 #endif
2772 } sli4_res_common_get_profile_config_t;
2773
2774 /**
2775  * @brief COMMON_SET_PROFILE_CONFIG
2776  */
2777 typedef struct sli4_req_common_set_profile_config_s {
2778         sli4_req_hdr_t  hdr;
2779         uint32_t        profile_id:8,
2780                         :23,
2781                         isap:1;
2782         uint32_t        desc_count;
2783         uint32_t        desc[0];
2784 } sli4_req_common_set_profile_config_t;
2785
2786 typedef struct sli4_res_common_set_profile_config_s {
2787         sli4_res_hdr_t  hdr;
2788 #if BYTE_ORDER == LITTLE_ENDIAN
2789 #else
2790 #error big endian version not defined
2791 #endif
2792 } sli4_res_common_set_profile_config_t;
2793
2794 /**
2795  * @brief Profile Descriptor for profile functions
2796  */
2797 typedef struct sli4_profile_descriptor_s {
2798 #if BYTE_ORDER == LITTLE_ENDIAN
2799         uint32_t        profile_id:8,
2800                         :8,
2801                         profile_index:8,
2802                         :8;
2803         uint32_t        profile_description[128];
2804 #else
2805 #error big endian version not defined
2806 #endif
2807 } sli4_profile_descriptor_t;
2808
2809 /* We don't know in advance how many descriptors there are.  We have
2810    to pick a number that we think will be big enough and ask for that
2811    many. */
2812
2813 #define MAX_PRODUCT_DESCRIPTORS 40
2814
2815 /**
2816  * @brief COMMON_GET_PROFILE_LIST
2817  */
2818 typedef struct sli4_req_common_get_profile_list_s {
2819         sli4_req_hdr_t  hdr;
2820 #if BYTE_ORDER == LITTLE_ENDIAN
2821         uint32_t        start_profile_index:8,
2822                         :24;
2823 #else
2824 #error big endian version not defined
2825 #endif
2826 } sli4_req_common_get_profile_list_t;
2827
2828 typedef struct sli4_res_common_get_profile_list_s {
2829         sli4_res_hdr_t  hdr;
2830 #if BYTE_ORDER == LITTLE_ENDIAN
2831         uint32_t        profile_descriptor_count;
2832         sli4_profile_descriptor_t profile_descriptor[MAX_PRODUCT_DESCRIPTORS];
2833 #else
2834 #error big endian version not defined
2835 #endif
2836 } sli4_res_common_get_profile_list_t;
2837
2838 /**
2839  * @brief COMMON_GET_ACTIVE_PROFILE
2840  */
2841 typedef struct sli4_req_common_get_active_profile_s {
2842         sli4_req_hdr_t  hdr;
2843 } sli4_req_common_get_active_profile_t;
2844
2845 typedef struct sli4_res_common_get_active_profile_s {
2846         sli4_res_hdr_t  hdr;
2847 #if BYTE_ORDER == LITTLE_ENDIAN
2848         uint32_t        active_profile_id:8,
2849                         :8,
2850                         next_profile_id:8,
2851                         :8;
2852 #else
2853 #error big endian version not defined
2854 #endif
2855 } sli4_res_common_get_active_profile_t;
2856
2857 /**
2858  * @brief COMMON_SET_ACTIVE_PROFILE
2859  */
2860 typedef struct sli4_req_common_set_active_profile_s {
2861         sli4_req_hdr_t  hdr;
2862 #if BYTE_ORDER == LITTLE_ENDIAN
2863         uint32_t        active_profile_id:8,
2864                         :23,
2865                         fd:1;
2866 #else
2867 #error big endian version not defined
2868 #endif
2869 } sli4_req_common_set_active_profile_t;
2870
2871 typedef struct sli4_res_common_set_active_profile_s {
2872         sli4_res_hdr_t  hdr;
2873 } sli4_res_common_set_active_profile_t;
2874
2875 /**
2876  * @brief Link Config Descriptor for link config functions
2877  */
2878 typedef struct sli4_link_config_descriptor_s {
2879 #if BYTE_ORDER == LITTLE_ENDIAN
2880         uint32_t        link_config_id:8,
2881                         :24;
2882         uint32_t        config_description[8];
2883 #else
2884 #error big endian version not defined
2885 #endif
2886 } sli4_link_config_descriptor_t;
2887
2888 #define MAX_LINK_CONFIG_DESCRIPTORS 10
2889
2890 /**
2891  * @brief COMMON_GET_RECONFIG_LINK_INFO
2892  */
2893 typedef struct sli4_req_common_get_reconfig_link_info_s {
2894         sli4_req_hdr_t  hdr;
2895 #if BYTE_ORDER == LITTLE_ENDIAN
2896 #else
2897 #error big endian version not defined
2898 #endif
2899 } sli4_req_common_get_reconfig_link_info_t;
2900
2901 typedef struct sli4_res_common_get_reconfig_link_info_s {
2902         sli4_res_hdr_t  hdr;
2903 #if BYTE_ORDER == LITTLE_ENDIAN
2904         uint32_t        active_link_config_id:8,
2905                         :8,
2906                         next_link_config_id:8,
2907                         :8;
2908         uint32_t        link_configuration_descriptor_count;
2909         sli4_link_config_descriptor_t   desc[MAX_LINK_CONFIG_DESCRIPTORS];
2910 #else
2911 #error big endian version not defined
2912 #endif
2913 } sli4_res_common_get_reconfig_link_info_t;
2914
2915 /**
2916  * @brief COMMON_SET_RECONFIG_LINK_ID
2917  */
2918 typedef struct sli4_req_common_set_reconfig_link_id_s {
2919         sli4_req_hdr_t  hdr;
2920 #if BYTE_ORDER == LITTLE_ENDIAN
2921         uint32_t        next_link_config_id:8,
2922                         :23,
2923                         fd:1;
2924 #else
2925 #error big endian version not defined
2926 #endif
2927 } sli4_req_common_set_reconfig_link_id_t;
2928
2929 typedef struct sli4_res_common_set_reconfig_link_id_s {
2930         sli4_res_hdr_t  hdr;
2931 #if BYTE_ORDER == LITTLE_ENDIAN
2932 #else
2933 #error big endian version not defined
2934 #endif
2935 } sli4_res_common_set_reconfig_link_id_t;
2936
2937 typedef struct sli4_req_lowlevel_set_watchdog_s {
2938         sli4_req_hdr_t  hdr;
2939 #if BYTE_ORDER == LITTLE_ENDIAN
2940         uint32_t        watchdog_timeout:16,
2941                         :16;
2942 #else
2943 #error big endian version not defined
2944 #endif
2945
2946 } sli4_req_lowlevel_set_watchdog_t;
2947
2948 typedef struct sli4_res_lowlevel_set_watchdog_s {
2949         sli4_res_hdr_t  hdr;
2950 #if BYTE_ORDER == LITTLE_ENDIAN
2951         uint32_t        rsvd;
2952 #else
2953 #error big endian version not defined
2954 #endif
2955 } sli4_res_lowlevel_set_watchdog_t;
2956
2957 /**
2958  * @brief Event Queue Entry
2959  */
2960 typedef struct sli4_eqe_s {
2961 #if BYTE_ORDER == LITTLE_ENDIAN
2962         uint32_t        vld:1,          /** valid */
2963                         major_code:3,
2964                         minor_code:12,
2965                         resource_id:16;
2966 #else
2967 #error big endian version not defined
2968 #endif
2969 } sli4_eqe_t;
2970
2971 #define SLI4_MAJOR_CODE_STANDARD        0
2972 #define SLI4_MAJOR_CODE_SENTINEL        1
2973
2974 /**
2975  * @brief Mailbox Completion Queue Entry
2976  *
2977  * A CQE generated on the completion of a MQE from a MQ.
2978  */
2979 typedef struct sli4_mcqe_s {
2980 #if BYTE_ORDER == LITTLE_ENDIAN
2981         uint32_t        completion_status:16, /** values are protocol specific */
2982                         extended_status:16;
2983         uint32_t        mqe_tag_low;
2984         uint32_t        mqe_tag_high;
2985         uint32_t        :27,
2986                         con:1,          /** consumed - command now being executed */
2987                         cmp:1,          /** completed - command still executing if clear */
2988                         :1,
2989                         ae:1,           /** async event - this is an ACQE */
2990                         val:1;          /** valid - contents of CQE are valid */
2991 #else
2992 #error big endian version not defined
2993 #endif
2994 } sli4_mcqe_t;
2995
2996 /**
2997  * @brief Asynchronous Completion Queue Entry
2998  *
2999  * A CQE generated asynchronously in response to the link or other internal events.
3000  */
3001 typedef struct sli4_acqe_s {
3002 #if BYTE_ORDER == LITTLE_ENDIAN
3003         uint32_t        event_data[3];
3004         uint32_t        :8,
3005                         event_code:8,
3006                         event_type:8,   /** values are protocol specific */
3007                         :6,
3008                         ae:1,           /** async event - this is an ACQE */
3009                         val:1;          /** valid - contents of CQE are valid */
3010 #else
3011 #error big endian version not defined
3012 #endif
3013 } sli4_acqe_t;
3014
3015 #define SLI4_ACQE_EVENT_CODE_LINK_STATE         0x01
3016 #define SLI4_ACQE_EVENT_CODE_FCOE_FIP           0x02
3017 #define SLI4_ACQE_EVENT_CODE_DCBX               0x03
3018 #define SLI4_ACQE_EVENT_CODE_ISCSI              0x04
3019 #define SLI4_ACQE_EVENT_CODE_GRP_5              0x05
3020 #define SLI4_ACQE_EVENT_CODE_FC_LINK_EVENT      0x10
3021 #define SLI4_ACQE_EVENT_CODE_SLI_PORT_EVENT     0x11
3022 #define SLI4_ACQE_EVENT_CODE_VF_EVENT           0x12
3023 #define SLI4_ACQE_EVENT_CODE_MR_EVENT           0x13
3024
3025 /**
3026  * @brief Register name enums
3027  */
3028 typedef enum {
3029         SLI4_REG_BMBX,
3030         SLI4_REG_EQ_DOORBELL,
3031         SLI4_REG_CQ_DOORBELL,
3032         SLI4_REG_FCOE_RQ_DOORBELL,
3033         SLI4_REG_IO_WQ_DOORBELL,
3034         SLI4_REG_MQ_DOORBELL,
3035         SLI4_REG_PHYSDEV_CONTROL,
3036         SLI4_REG_SLIPORT_CONTROL,
3037         SLI4_REG_SLIPORT_ERROR1,
3038         SLI4_REG_SLIPORT_ERROR2,
3039         SLI4_REG_SLIPORT_SEMAPHORE,
3040         SLI4_REG_SLIPORT_STATUS,
3041         SLI4_REG_UERR_MASK_HI,
3042         SLI4_REG_UERR_MASK_LO,
3043         SLI4_REG_UERR_STATUS_HI,
3044         SLI4_REG_UERR_STATUS_LO,
3045         SLI4_REG_SW_UE_CSR1,
3046         SLI4_REG_SW_UE_CSR2,
3047         SLI4_REG_MAX                    /* must be last */
3048 } sli4_regname_e;
3049
3050 typedef struct sli4_reg_s {
3051         uint32_t        rset;
3052         uint32_t        off;
3053 } sli4_reg_t;
3054
3055 typedef enum {
3056         SLI_QTYPE_EQ,
3057         SLI_QTYPE_CQ,
3058         SLI_QTYPE_MQ,
3059         SLI_QTYPE_WQ,
3060         SLI_QTYPE_RQ,
3061         SLI_QTYPE_MAX,                  /* must be last */
3062 } sli4_qtype_e;
3063
3064 #define SLI_USER_MQ_COUNT       1       /** User specified max mail queues */
3065 #define SLI_MAX_CQ_SET_COUNT    16
3066 #define SLI_MAX_RQ_SET_COUNT    16
3067
3068 typedef enum {
3069         SLI_QENTRY_ASYNC,
3070         SLI_QENTRY_MQ,
3071         SLI_QENTRY_RQ,
3072         SLI_QENTRY_WQ,
3073         SLI_QENTRY_WQ_RELEASE,
3074         SLI_QENTRY_OPT_WRITE_CMD,
3075         SLI_QENTRY_OPT_WRITE_DATA,
3076         SLI_QENTRY_XABT,
3077         SLI_QENTRY_MAX                  /* must be last */
3078 } sli4_qentry_e;
3079
3080 typedef struct sli4_queue_s {
3081         /* Common to all queue types */
3082         ocs_dma_t       dma;
3083         ocs_lock_t      lock;
3084         uint32_t        index;          /** current host entry index */
3085         uint16_t        size;           /** entry size */
3086         uint16_t        length;         /** number of entries */
3087         uint16_t        n_posted;       /** number entries posted */
3088         uint16_t        id;             /** Port assigned xQ_ID */
3089         uint16_t        ulp;            /** ULP assigned to this queue */
3090         uint32_t        doorbell_offset;/** The offset for the doorbell */
3091         uint16_t        doorbell_rset;  /** register set for the doorbell */
3092         uint8_t         type;           /** queue type ie EQ, CQ, ... */
3093         uint32_t        proc_limit;     /** limit number of CQE processed per iteration */
3094         uint32_t        posted_limit;   /** number of CQE/EQE to process before ringing doorbell */
3095         uint32_t        max_num_processed;
3096         time_t          max_process_time;
3097
3098         uint16_t        phase;          /** For if_type = 6, this value toggle for each iteration
3099                                             of the queue, a queue entry is valid when a cqe valid
3100                                             bit matches this value */
3101         /* Type specific gunk */
3102         union {
3103                 uint32_t        r_idx;  /** "read" index (MQ only) */
3104                 struct {
3105                         uint32_t        is_mq:1,/** CQ contains MQ/Async completions */
3106                                         is_hdr:1,/** is a RQ for packet headers */
3107                                         rq_batch:1;/** RQ index incremented by 8 */
3108                 } flag;
3109         } u;
3110 } sli4_queue_t;
3111
3112 static inline void
3113 sli_queue_lock(sli4_queue_t *q)
3114 {
3115         ocs_lock(&q->lock);
3116 }
3117
3118 static inline void
3119 sli_queue_unlock(sli4_queue_t *q)
3120 {
3121         ocs_unlock(&q->lock);
3122 }
3123
3124 #define SLI4_QUEUE_DEFAULT_CQ   UINT16_MAX /** Use the default CQ */
3125
3126 #define SLI4_QUEUE_RQ_BATCH     8
3127
3128 typedef enum {
3129         SLI4_CB_LINK,
3130         SLI4_CB_FIP,
3131         SLI4_CB_MAX                     /* must be last */
3132 } sli4_callback_e;
3133
3134 typedef enum {
3135         SLI_LINK_STATUS_UP,
3136         SLI_LINK_STATUS_DOWN,
3137         SLI_LINK_STATUS_NO_ALPA,
3138         SLI_LINK_STATUS_MAX,
3139 } sli4_link_status_e;
3140
3141 typedef enum {
3142         SLI_LINK_TOPO_NPORT = 1,        /** fabric or point-to-point */
3143         SLI_LINK_TOPO_LOOP,
3144         SLI_LINK_TOPO_LOOPBACK_INTERNAL,
3145         SLI_LINK_TOPO_LOOPBACK_EXTERNAL,
3146         SLI_LINK_TOPO_NONE,
3147         SLI_LINK_TOPO_MAX,
3148 } sli4_link_topology_e;
3149
3150 /* TODO do we need both sli4_port_type_e & sli4_link_medium_e */
3151 typedef enum {
3152         SLI_LINK_MEDIUM_ETHERNET,
3153         SLI_LINK_MEDIUM_FC,
3154         SLI_LINK_MEDIUM_MAX,
3155 } sli4_link_medium_e;
3156
3157 typedef struct sli4_link_event_s {
3158         sli4_link_status_e      status;         /* link up/down */
3159         sli4_link_topology_e    topology;
3160         sli4_link_medium_e      medium;         /* Ethernet / FC */
3161         uint32_t                speed;          /* Mbps */
3162         uint8_t                 *loop_map;
3163         uint32_t                fc_id;
3164 } sli4_link_event_t;
3165
3166 /**
3167  * @brief Fields retrieved from skyhawk that used used to build chained SGL
3168  */
3169 typedef struct sli4_sgl_chaining_params_s {
3170         uint8_t         chaining_capable;
3171         uint16_t        frag_num_field_offset;
3172         uint16_t        sgl_index_field_offset;
3173         uint64_t        frag_num_field_mask;
3174         uint64_t        sgl_index_field_mask;
3175         uint32_t        chain_sge_initial_value_lo;
3176         uint32_t        chain_sge_initial_value_hi;
3177 } sli4_sgl_chaining_params_t;
3178
3179 typedef struct sli4_fip_event_s {
3180         uint32_t        type;
3181         uint32_t        index;          /* FCF index or UINT32_MAX if invalid */
3182 } sli4_fip_event_t;
3183
3184 typedef enum {
3185         SLI_RSRC_FCOE_VFI,
3186         SLI_RSRC_FCOE_VPI,
3187         SLI_RSRC_FCOE_RPI,
3188         SLI_RSRC_FCOE_XRI,
3189         SLI_RSRC_FCOE_FCFI,
3190         SLI_RSRC_MAX                    /* must be last */
3191 } sli4_resource_e;
3192
3193 typedef enum {
3194         SLI4_PORT_TYPE_FC,
3195         SLI4_PORT_TYPE_NIC,
3196         SLI4_PORT_TYPE_MAX              /* must be last */
3197 } sli4_port_type_e;
3198
3199 typedef enum {
3200         SLI4_ASIC_TYPE_BE3 = 1,
3201         SLI4_ASIC_TYPE_SKYHAWK,
3202         SLI4_ASIC_TYPE_LANCER,
3203         SLI4_ASIC_TYPE_CORSAIR,
3204         SLI4_ASIC_TYPE_LANCERG6,
3205         SLI4_ASIC_TYPE_LANCERG7
3206 } sli4_asic_type_e;
3207
3208 typedef enum {
3209         SLI4_ASIC_REV_FPGA = 1,
3210         SLI4_ASIC_REV_A0,
3211         SLI4_ASIC_REV_A1,
3212         SLI4_ASIC_REV_A2,
3213         SLI4_ASIC_REV_A3,
3214         SLI4_ASIC_REV_B0,
3215         SLI4_ASIC_REV_B1,
3216         SLI4_ASIC_REV_C0,
3217         SLI4_ASIC_REV_D0,
3218 } sli4_asic_rev_e;
3219
3220 typedef struct sli4_s {
3221         ocs_os_handle_t os;
3222         sli4_port_type_e port_type;
3223
3224         uint32_t        sli_rev;        /* SLI revision number */
3225         uint32_t        sli_family;
3226         uint32_t        if_type;        /* SLI Interface type */
3227
3228         sli4_asic_type_e asic_type;     /*<< ASIC type */
3229         sli4_asic_rev_e asic_rev;       /*<< ASIC revision */
3230         uint32_t        physical_port;
3231
3232         struct {
3233                 uint16_t                e_d_tov;
3234                 uint16_t                r_a_tov;
3235                 uint16_t                max_qcount[SLI_QTYPE_MAX];
3236                 uint32_t                max_qentries[SLI_QTYPE_MAX];
3237                 uint16_t                count_mask[SLI_QTYPE_MAX];
3238                 uint16_t                count_method[SLI_QTYPE_MAX];
3239                 uint32_t                qpage_count[SLI_QTYPE_MAX];
3240                 uint16_t                link_module_type;
3241                 uint8_t                 rq_batch;
3242                 uint16_t                rq_min_buf_size;
3243                 uint32_t                rq_max_buf_size;
3244                 uint8_t                 topology;
3245                 uint8_t                 pt:4,
3246                                         tf:1,
3247                                         ptv:1,
3248                                         :2;
3249                 uint8_t                 wwpn[8];
3250                 uint8_t                 wwnn[8];
3251                 uint32_t                fw_rev[2];
3252                 uint8_t                 fw_name[2][16];
3253                 char                    ipl_name[16];
3254                 uint32_t                hw_rev[3];
3255                 uint8_t                 port_number;
3256                 char                    port_name[2];
3257                 char                    bios_version_string[32];
3258                 uint8_t                 dual_ulp_capable;
3259                 uint8_t                 is_ulp_fc[2];
3260                 /*
3261                  * Tracks the port resources using extents metaphor. For
3262                  * devices that don't implement extents (i.e.
3263                  * has_extents == FALSE), the code models each resource as
3264                  * a single large extent.
3265                  */
3266                 struct {
3267                         uint32_t        number; /* number of extents */
3268                         uint32_t        size;   /* number of elements in each extent */
3269                         uint32_t        n_alloc;/* number of elements allocated */
3270                         uint32_t        *base;
3271                         ocs_bitmap_t    *use_map;/* bitmap showing resources in use */
3272                         uint32_t        map_size;/* number of bits in bitmap */
3273                 } extent[SLI_RSRC_MAX];
3274                 sli4_features_t         features;
3275                 uint32_t                has_extents:1,
3276                                         auto_reg:1,
3277                                         auto_xfer_rdy:1,
3278                                         hdr_template_req:1,
3279                                         perf_hint:1,
3280                                         perf_wq_id_association:1,
3281                                         cq_create_version:2,
3282                                         mq_create_version:2,
3283                                         high_login_mode:1,
3284                                         sgl_pre_registered:1,
3285                                         sgl_pre_registration_required:1,
3286                                         t10_dif_inline_capable:1,
3287                                         t10_dif_separate_capable:1;
3288                 uint32_t                sge_supported_length;
3289                 uint32_t                sgl_page_sizes;
3290                 uint32_t                max_sgl_pages;
3291                 sli4_sgl_chaining_params_t sgl_chaining_params;
3292                 size_t                  wqe_size;
3293         } config;
3294
3295         /*
3296          * Callback functions
3297          */
3298         int32_t         (*link)(void *, void *);
3299         void            *link_arg;
3300         int32_t         (*fip)(void *, void *);
3301         void            *fip_arg;
3302
3303         ocs_dma_t       bmbx;
3304 #if defined(OCS_INCLUDE_DEBUG)
3305         /* Save pointer to physical memory descriptor for non-embedded SLI_CONFIG
3306          * commands for BMBX dumping purposes */
3307         ocs_dma_t       *bmbx_non_emb_pmd;
3308 #endif
3309
3310         struct {
3311                 ocs_dma_t       data;
3312                 uint32_t        length;
3313         } vpd;
3314 } sli4_t;
3315
3316 /**
3317  * Get / set parameter functions
3318  */
3319 static inline uint32_t
3320 sli_get_max_rsrc(sli4_t *sli4, sli4_resource_e rsrc)
3321 {
3322         if (rsrc >= SLI_RSRC_MAX) {
3323                 return 0;
3324         }
3325
3326         return sli4->config.extent[rsrc].size;
3327 }
3328
3329 static inline uint32_t
3330 sli_get_max_queue(sli4_t *sli4, sli4_qtype_e qtype)
3331 {
3332         if (qtype >= SLI_QTYPE_MAX) {
3333                 return 0;
3334         }
3335         return sli4->config.max_qcount[qtype];
3336 }
3337
3338 static inline uint32_t
3339 sli_get_max_qentries(sli4_t *sli4, sli4_qtype_e qtype)
3340 {
3341
3342         return sli4->config.max_qentries[qtype];
3343 }
3344
3345 static inline uint32_t
3346 sli_get_max_sge(sli4_t *sli4)
3347 {
3348         return sli4->config.sge_supported_length;
3349 }
3350
3351 static inline uint32_t
3352 sli_get_max_sgl(sli4_t *sli4)
3353 {
3354
3355         if (sli4->config.sgl_page_sizes != 1) {
3356                 ocs_log_test(sli4->os, "unsupported SGL page sizes %#x\n",
3357                                 sli4->config.sgl_page_sizes);
3358                 return 0;
3359         }
3360
3361         return ((sli4->config.max_sgl_pages * SLI_PAGE_SIZE) / sizeof(sli4_sge_t));
3362 }
3363
3364 static inline sli4_link_medium_e
3365 sli_get_medium(sli4_t *sli4)
3366 {
3367         switch (sli4->config.topology) {
3368         case SLI4_READ_CFG_TOPO_FCOE:
3369                 return SLI_LINK_MEDIUM_ETHERNET;
3370         case SLI4_READ_CFG_TOPO_FC:
3371         case SLI4_READ_CFG_TOPO_FC_DA:
3372         case SLI4_READ_CFG_TOPO_FC_AL:
3373                 return SLI_LINK_MEDIUM_FC;
3374         default:
3375                 return SLI_LINK_MEDIUM_MAX;
3376         }
3377 }
3378
3379 static inline void
3380 sli_skh_chain_sge_build(sli4_t *sli4, sli4_sge_t *sge, uint32_t xri_index, uint32_t frag_num, uint32_t offset)
3381 {
3382         sli4_sgl_chaining_params_t *cparms = &sli4->config.sgl_chaining_params;
3383
3384         ocs_memset(sge, 0, sizeof(*sge));
3385         sge->sge_type = SLI4_SGE_TYPE_CHAIN;
3386         sge->buffer_address_high = (uint32_t)cparms->chain_sge_initial_value_hi;
3387         sge->buffer_address_low =
3388                 (uint32_t)((cparms->chain_sge_initial_value_lo |
3389                             (((uintptr_t)(xri_index & cparms->sgl_index_field_mask)) <<
3390                              cparms->sgl_index_field_offset) |
3391                             (((uintptr_t)(frag_num & cparms->frag_num_field_mask)) <<
3392                              cparms->frag_num_field_offset)  |
3393                             offset) >> 3);
3394 }
3395
3396 static inline uint32_t
3397 sli_get_sli_rev(sli4_t *sli4)
3398 {
3399         return sli4->sli_rev;
3400 }
3401
3402 static inline uint32_t
3403 sli_get_sli_family(sli4_t *sli4)
3404 {
3405         return sli4->sli_family;
3406 }
3407
3408 static inline uint32_t
3409 sli_get_if_type(sli4_t *sli4)
3410 {
3411         return sli4->if_type;
3412 }
3413
3414 static inline void *
3415 sli_get_wwn_port(sli4_t *sli4)
3416 {
3417         return sli4->config.wwpn;
3418 }
3419
3420 static inline void *
3421 sli_get_wwn_node(sli4_t *sli4)
3422 {
3423         return sli4->config.wwnn;
3424 }
3425
3426 static inline void *
3427 sli_get_vpd(sli4_t *sli4)
3428 {
3429         return sli4->vpd.data.virt;
3430 }
3431
3432 static inline uint32_t
3433 sli_get_vpd_len(sli4_t *sli4)
3434 {
3435         return sli4->vpd.length;
3436 }
3437
3438 static inline uint32_t
3439 sli_get_fw_revision(sli4_t *sli4, uint32_t which)
3440 {
3441         return sli4->config.fw_rev[which];
3442 }
3443
3444 static inline void *
3445 sli_get_fw_name(sli4_t *sli4, uint32_t which)
3446 {
3447         return sli4->config.fw_name[which];
3448 }
3449
3450 static inline char *
3451 sli_get_ipl_name(sli4_t *sli4)
3452 {
3453         return sli4->config.ipl_name;
3454 }
3455
3456 static inline uint32_t
3457 sli_get_hw_revision(sli4_t *sli4, uint32_t which)
3458 {
3459         return sli4->config.hw_rev[which];
3460 }
3461
3462 static inline uint32_t
3463 sli_get_auto_xfer_rdy_capable(sli4_t *sli4)
3464 {
3465         return sli4->config.auto_xfer_rdy;
3466 }
3467
3468 static inline uint32_t
3469 sli_get_dif_capable(sli4_t *sli4)
3470 {
3471         return sli4->config.features.flag.dif;
3472 }
3473
3474 static inline uint32_t
3475 sli_is_dif_inline_capable(sli4_t *sli4)
3476 {
3477         return sli_get_dif_capable(sli4) && sli4->config.t10_dif_inline_capable;
3478 }
3479
3480 static inline uint32_t
3481 sli_is_dif_separate_capable(sli4_t *sli4)
3482 {
3483         return sli_get_dif_capable(sli4) && sli4->config.t10_dif_separate_capable;
3484 }
3485
3486 static inline uint32_t
3487 sli_get_is_dual_ulp_capable(sli4_t *sli4)
3488 {
3489         return sli4->config.dual_ulp_capable;
3490 }
3491
3492 static inline uint32_t
3493 sli_get_is_sgl_chaining_capable(sli4_t *sli4)
3494 {
3495         return sli4->config.sgl_chaining_params.chaining_capable;
3496 }
3497
3498 static inline uint32_t
3499 sli_get_is_ulp_enabled(sli4_t *sli4, uint16_t ulp)
3500 {
3501         return sli4->config.is_ulp_fc[ulp];
3502 }
3503
3504 static inline uint32_t
3505 sli_get_hlm_capable(sli4_t *sli4)
3506 {
3507         return sli4->config.features.flag.hlm;
3508 }
3509
3510 static inline int32_t
3511 sli_set_hlm(sli4_t *sli4, uint32_t value)
3512 {
3513         if (value && !sli4->config.features.flag.hlm) {
3514                 ocs_log_test(sli4->os, "HLM not supported\n");
3515                 return -1;
3516         }
3517
3518         sli4->config.high_login_mode = value != 0 ? TRUE : FALSE;
3519
3520         return 0;
3521 }
3522
3523 static inline uint32_t
3524 sli_get_hlm(sli4_t *sli4)
3525 {
3526         return sli4->config.high_login_mode;
3527 }
3528
3529 static inline uint32_t
3530 sli_get_sgl_preregister_required(sli4_t *sli4)
3531 {
3532         return sli4->config.sgl_pre_registration_required;
3533 }
3534
3535 static inline uint32_t
3536 sli_get_sgl_preregister(sli4_t *sli4)
3537 {
3538         return sli4->config.sgl_pre_registered;
3539 }
3540
3541 static inline int32_t
3542 sli_set_sgl_preregister(sli4_t *sli4, uint32_t value)
3543 {
3544         if ((value == 0) && sli4->config.sgl_pre_registration_required) {
3545                 ocs_log_test(sli4->os, "SGL pre-registration required\n");
3546                 return -1;
3547         }
3548
3549         sli4->config.sgl_pre_registered = value != 0 ? TRUE : FALSE;
3550
3551         return 0;
3552 }
3553
3554 static inline sli4_asic_type_e
3555 sli_get_asic_type(sli4_t *sli4)
3556 {
3557         return sli4->asic_type;
3558 }
3559
3560 static inline sli4_asic_rev_e
3561 sli_get_asic_rev(sli4_t *sli4)
3562 {
3563         return sli4->asic_rev;
3564 }
3565
3566 static inline int32_t
3567 sli_set_topology(sli4_t *sli4, uint32_t value)
3568 {
3569         int32_t rc = 0;
3570
3571         switch (value) {
3572         case SLI4_READ_CFG_TOPO_FCOE:
3573         case SLI4_READ_CFG_TOPO_FC:
3574         case SLI4_READ_CFG_TOPO_FC_DA:
3575         case SLI4_READ_CFG_TOPO_FC_AL:
3576                 sli4->config.topology = value;
3577                 break;
3578         default:
3579                 ocs_log_test(sli4->os, "unsupported topology %#x\n", value);
3580                 rc = -1;
3581         }
3582
3583         return rc;
3584 }
3585
3586 static inline void
3587 sli_config_persistent_topology(sli4_t *sli4, sli4_req_common_set_features_persistent_topo_param_t *req)
3588 {
3589         sli4->config.pt = req->persistent_topo;
3590         sli4->config.tf = req->topo_failover;
3591 }
3592
3593 static inline uint16_t
3594 sli_get_link_module_type(sli4_t *sli4)
3595 {
3596         return sli4->config.link_module_type;
3597 }
3598
3599 static inline char *
3600 sli_get_portnum(sli4_t *sli4)
3601 {
3602         return sli4->config.port_name;
3603 }
3604
3605 static inline char *
3606 sli_get_bios_version_string(sli4_t *sli4)
3607 {
3608         return sli4->config.bios_version_string;
3609 }
3610
3611 static inline uint32_t
3612 sli_convert_mask_to_count(uint32_t method, uint32_t mask)
3613 {
3614         uint32_t count = 0;
3615
3616         if (method) {
3617                 count = 1 << ocs_lg2(mask);
3618                 count *= 16;
3619         } else {
3620                 count = mask;
3621         }
3622
3623         return count;
3624 }
3625
3626 static inline bool
3627 sli_fcal_is_speed_supported(uint32_t link_speed)
3628 {
3629         if ((link_speed == FC_LINK_SPEED_16G) ||
3630             (link_speed == FC_LINK_SPEED_32G) ||
3631             (link_speed >= FC_LINK_SPEED_AUTO_32_16)) {
3632                 ocs_log_err(NULL, "unsupported FC-AL speed (speed_code: %d)\n", link_speed);
3633                 return FALSE;
3634         }
3635
3636         return TRUE;
3637 }
3638
3639 /**
3640  * @brief Common Create Queue function prototype
3641  */
3642 typedef int32_t (*sli4_create_q_fn_t)(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t);
3643
3644 /**
3645  * @brief Common Destroy Queue function prototype
3646  */
3647 typedef int32_t (*sli4_destroy_q_fn_t)(sli4_t *, void *, size_t, uint16_t);
3648
3649 /****************************************************************************
3650  * Function prototypes
3651  */
3652 extern int32_t sli_cmd_config_auto_xfer_rdy(sli4_t *, void *, size_t, uint32_t);
3653 extern int32_t sli_cmd_config_auto_xfer_rdy_hp(sli4_t *, void *, size_t, uint32_t, uint32_t, uint32_t);
3654 extern int32_t sli_cmd_config_link(sli4_t *, void *, size_t);
3655 extern int32_t sli_cmd_down_link(sli4_t *, void *, size_t);
3656 extern int32_t sli_cmd_dump_type4(sli4_t *, void *, size_t, uint16_t);
3657 extern int32_t sli_cmd_common_read_transceiver_data(sli4_t *, void *, size_t, uint32_t, ocs_dma_t *);
3658 extern int32_t sli_cmd_read_link_stats(sli4_t *, void *, size_t,uint8_t, uint8_t, uint8_t);
3659 extern int32_t sli_cmd_read_status(sli4_t *sli4, void *buf, size_t size, uint8_t clear_counters);
3660 extern int32_t sli_cmd_init_link(sli4_t *, void *, size_t, uint32_t, uint8_t);
3661 extern int32_t sli_cmd_init_vfi(sli4_t *, void *, size_t, uint16_t, uint16_t, uint16_t);
3662 extern int32_t sli_cmd_init_vpi(sli4_t *, void *, size_t, uint16_t, uint16_t);
3663 extern int32_t sli_cmd_post_xri(sli4_t *, void *, size_t,  uint16_t, uint16_t);
3664 extern int32_t sli_cmd_release_xri(sli4_t *, void *, size_t,  uint8_t);
3665 extern int32_t sli_cmd_read_sparm64(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t);
3666 extern int32_t sli_cmd_read_topology(sli4_t *, void *, size_t, ocs_dma_t *);
3667 extern int32_t sli_cmd_read_nvparms(sli4_t *, void *, size_t);
3668 extern int32_t sli_cmd_write_nvparms(sli4_t *, void *, size_t, uint8_t *, uint8_t *, uint8_t, uint32_t);
3669 typedef struct {
3670         uint16_t rq_id;
3671         uint8_t r_ctl_mask;
3672         uint8_t r_ctl_match;
3673         uint8_t type_mask;
3674         uint8_t type_match;
3675 } sli4_cmd_rq_cfg_t;
3676 extern int32_t sli_cmd_reg_fcfi(sli4_t *, void *, size_t, uint16_t,
3677                                 sli4_cmd_rq_cfg_t rq_cfg[SLI4_CMD_REG_FCFI_NUM_RQ_CFG], uint16_t);
3678 extern int32_t sli_cmd_reg_fcfi_mrq(sli4_t *, void *, size_t, uint8_t, uint16_t, uint16_t, uint8_t, uint8_t , uint16_t, sli4_cmd_rq_cfg_t *);
3679
3680 extern int32_t sli_cmd_reg_rpi(sli4_t *, void *, size_t, uint32_t, uint16_t, uint16_t, ocs_dma_t *, uint8_t, uint8_t);
3681 extern int32_t sli_cmd_reg_vfi(sli4_t *, void *, size_t, ocs_domain_t *);
3682 extern int32_t sli_cmd_reg_vpi(sli4_t *, void *, size_t, ocs_sli_port_t *, uint8_t);
3683 extern int32_t sli_cmd_sli_config(sli4_t *, void *, size_t, uint32_t, ocs_dma_t *);
3684 extern int32_t sli_cmd_unreg_fcfi(sli4_t *, void *, size_t, uint16_t);
3685 extern int32_t sli_cmd_unreg_rpi(sli4_t *, void *, size_t, uint16_t, sli4_resource_e, uint32_t);
3686 extern int32_t sli_cmd_unreg_vfi(sli4_t *, void *, size_t, ocs_domain_t *, uint32_t);
3687 extern int32_t sli_cmd_unreg_vpi(sli4_t *, void *, size_t, uint16_t, uint32_t);
3688 extern int32_t sli_cmd_common_nop(sli4_t *, void *, size_t, uint64_t);
3689 extern int32_t sli_cmd_common_get_resource_extent_info(sli4_t *, void *, size_t, uint16_t);
3690 extern int32_t sli_cmd_common_get_sli4_parameters(sli4_t *, void *, size_t);
3691 extern int32_t sli_cmd_common_write_object(sli4_t *, void *, size_t,
3692                 uint16_t, uint16_t, uint32_t, uint32_t, char *, ocs_dma_t *);
3693 extern int32_t sli_cmd_common_delete_object(sli4_t *, void *, size_t, char *);
3694 extern int32_t sli_cmd_common_read_object(sli4_t *, void *, size_t, uint32_t,
3695                 uint32_t, char *, ocs_dma_t *);
3696 extern int32_t sli_cmd_dmtf_exec_clp_cmd(sli4_t *sli4, void *buf, size_t size,
3697                 ocs_dma_t *cmd,
3698                 ocs_dma_t *resp);
3699 extern int32_t sli_cmd_common_set_dump_location(sli4_t *sli4, void *buf, size_t size,
3700                                                 uint8_t query, uint8_t is_buffer_list,
3701                                                 ocs_dma_t *buffer, uint8_t fdb);
3702 extern int32_t sli_cmd_common_set_features(sli4_t *, void *, size_t, uint32_t, uint32_t, void*);
3703 extern int32_t sli_cmd_common_get_profile_list(sli4_t *sli4, void *buf,
3704                 size_t size, uint32_t start_profile_index, ocs_dma_t *dma);
3705 extern int32_t sli_cmd_common_get_active_profile(sli4_t *sli4, void *buf,
3706                 size_t size);
3707 extern int32_t sli_cmd_common_set_active_profile(sli4_t *sli4, void *buf,
3708                 size_t size,
3709                 uint32_t fd,
3710                 uint32_t active_profile_id);
3711 extern int32_t sli_cmd_common_get_reconfig_link_info(sli4_t *sli4, void *buf,
3712                 size_t size, ocs_dma_t *dma);
3713 extern int32_t sli_cmd_common_set_reconfig_link_id(sli4_t *sli4, void *buf,
3714                 size_t size, ocs_dma_t *dma,
3715                 uint32_t fd, uint32_t active_link_config_id);
3716 extern int32_t sli_cmd_common_get_function_config(sli4_t *sli4, void *buf,
3717                 size_t size);
3718 extern int32_t sli_cmd_common_get_profile_config(sli4_t *sli4, void *buf,
3719                 size_t size, ocs_dma_t *dma);
3720 extern int32_t sli_cmd_common_set_profile_config(sli4_t *sli4, void *buf,
3721                 size_t size, ocs_dma_t *dma,
3722                 uint8_t profile_id, uint32_t descriptor_count,
3723                 uint8_t isap);
3724
3725 extern int32_t sli_cqe_mq(void *);
3726 extern int32_t sli_cqe_async(sli4_t *, void *);
3727
3728 extern int32_t sli_setup(sli4_t *, ocs_os_handle_t, sli4_port_type_e);
3729 extern void sli_calc_max_qentries(sli4_t *sli4);
3730 extern int32_t sli_init(sli4_t *);
3731 extern int32_t sli_reset(sli4_t *);
3732 extern int32_t sli_fw_reset(sli4_t *);
3733 extern int32_t sli_teardown(sli4_t *);
3734 extern int32_t sli_callback(sli4_t *, sli4_callback_e, void *, void *);
3735 extern int32_t sli_bmbx_command(sli4_t *);
3736 extern int32_t __sli_queue_init(sli4_t *, sli4_queue_t *, uint32_t, size_t, uint32_t, uint32_t);
3737 extern int32_t __sli_create_queue(sli4_t *, sli4_queue_t *);
3738 extern int32_t sli_eq_modify_delay(sli4_t *sli4, sli4_queue_t *eq, uint32_t num_eq, uint32_t shift, uint32_t delay_mult);
3739 extern int32_t sli_queue_alloc(sli4_t *, uint32_t, sli4_queue_t *, uint32_t, sli4_queue_t *, uint16_t);
3740 extern int32_t sli_cq_alloc_set(sli4_t *, sli4_queue_t *qs[], uint32_t, uint32_t, sli4_queue_t *eqs[]);
3741 extern int32_t sli_get_queue_entry_size(sli4_t *, uint32_t);
3742 extern int32_t sli_queue_free(sli4_t *, sli4_queue_t *, uint32_t, uint32_t);
3743 extern int32_t sli_queue_reset(sli4_t *, sli4_queue_t *);
3744 extern int32_t sli_queue_is_empty(sli4_t *, sli4_queue_t *);
3745 extern int32_t sli_queue_eq_arm(sli4_t *, sli4_queue_t *, uint8_t);
3746 extern int32_t sli_queue_arm(sli4_t *, sli4_queue_t *, uint8_t);
3747 extern int32_t _sli_queue_write(sli4_t *, sli4_queue_t *, uint8_t *);
3748 extern int32_t sli_queue_write(sli4_t *, sli4_queue_t *, uint8_t *);
3749 extern int32_t sli_queue_read(sli4_t *, sli4_queue_t *, uint8_t *);
3750 extern int32_t sli_queue_index(sli4_t *, sli4_queue_t *);
3751 extern int32_t _sli_queue_poke(sli4_t *, sli4_queue_t *, uint32_t, uint8_t *);
3752 extern int32_t sli_queue_poke(sli4_t *, sli4_queue_t *, uint32_t, uint8_t *);
3753 extern int32_t sli_resource_alloc(sli4_t *, sli4_resource_e, uint32_t *, uint32_t *);
3754 extern int32_t sli_resource_free(sli4_t *, sli4_resource_e, uint32_t);
3755 extern int32_t sli_resource_reset(sli4_t *, sli4_resource_e);
3756 extern int32_t sli_eq_parse(sli4_t *, uint8_t *, uint16_t *);
3757 extern int32_t sli_cq_parse(sli4_t *, sli4_queue_t *, uint8_t *, sli4_qentry_e *, uint16_t *);
3758
3759 extern int32_t sli_raise_ue(sli4_t *, uint8_t);
3760 extern int32_t sli_dump_is_ready(sli4_t *);
3761 extern int32_t sli_dump_is_present(sli4_t *);
3762 extern int32_t sli_reset_required(sli4_t *);
3763 extern int32_t sli_fw_error_status(sli4_t *);
3764 extern int32_t sli_fw_ready(sli4_t *);
3765 extern uint32_t sli_reg_read(sli4_t *, sli4_regname_e);
3766 extern void sli_reg_write(sli4_t *, sli4_regname_e, uint32_t);
3767 extern int32_t sli_link_is_configurable(sli4_t *);
3768
3769 #include "ocs_fcp.h"
3770
3771 /**
3772  * @brief Maximum value for a FCFI
3773  *
3774  * Note that although most commands provide a 16 bit field for the FCFI,
3775  * the FC/FCoE Asynchronous Recived CQE format only provides 6 bits for
3776  * the returned FCFI. Then effectively, the FCFI cannot be larger than
3777  * 1 << 6 or 64.
3778  */
3779 #define SLI4_MAX_FCFI   64
3780
3781 /**
3782  * @brief Maximum value for FCF index
3783  *
3784  * The SLI-4 specification uses a 16 bit field in most places for the FCF
3785  * index, but practically, this value will be much smaller. Arbitrarily
3786  * limit the max FCF index to match the max FCFI value.
3787  */
3788 #define SLI4_MAX_FCF_INDEX      SLI4_MAX_FCFI
3789
3790 /*************************************************************************
3791  * SLI-4 FC/FCoE mailbox command formats and definitions.
3792  */
3793
3794 /**
3795  * FC/FCoE opcode (OPC) values.
3796  */
3797 #define SLI4_OPC_FCOE_WQ_CREATE                 0x1
3798 #define SLI4_OPC_FCOE_WQ_DESTROY                0x2
3799 #define SLI4_OPC_FCOE_POST_SGL_PAGES            0x3
3800 #define SLI4_OPC_FCOE_RQ_CREATE                 0x5
3801 #define SLI4_OPC_FCOE_RQ_DESTROY                0x6
3802 #define SLI4_OPC_FCOE_READ_FCF_TABLE            0x8
3803 #define SLI4_OPC_FCOE_POST_HDR_TEMPLATES        0xb
3804 #define SLI4_OPC_FCOE_REDISCOVER_FCF            0x10
3805
3806 /* Use the default CQ associated with the WQ */
3807 #define SLI4_CQ_DEFAULT 0xffff
3808
3809 typedef struct sli4_physical_page_descriptor_s {
3810         uint32_t        low;
3811         uint32_t        high;
3812 } sli4_physical_page_descriptor_t;
3813
3814 /**
3815  * @brief FCOE_WQ_CREATE
3816  *
3817  * Create a Work Queue for FC/FCoE use.
3818  */
3819 #define SLI4_FCOE_WQ_CREATE_V0_MAX_PAGES        4
3820
3821 typedef struct sli4_req_fcoe_wq_create_s {
3822         sli4_req_hdr_t  hdr;
3823 #if BYTE_ORDER == LITTLE_ENDIAN
3824         uint32_t        num_pages:8,
3825                         dua:1,
3826                         :7,
3827                         cq_id:16;
3828         sli4_physical_page_descriptor_t page_physical_address[SLI4_FCOE_WQ_CREATE_V0_MAX_PAGES];
3829         uint32_t        bqu:1,
3830                         :7,
3831                         ulp:8,
3832                         :16;
3833 #else
3834 #error big endian version not defined
3835 #endif
3836 } sli4_req_fcoe_wq_create_t;
3837
3838 /**
3839  * @brief FCOE_WQ_CREATE_V1
3840  *
3841  * Create a version 1 Work Queue for FC/FCoE use.
3842  */
3843 typedef struct sli4_req_fcoe_wq_create_v1_s {
3844         sli4_req_hdr_t  hdr;
3845 #if BYTE_ORDER == LITTLE_ENDIAN
3846         uint32_t        num_pages:16,
3847                         cq_id:16;
3848         uint32_t        page_size:8,
3849                         wqe_size:4,
3850                         :4,
3851                         wqe_count:16;
3852         uint32_t        rsvd6;
3853         sli4_physical_page_descriptor_t page_physical_address[8];
3854 #else
3855 #error big endian version not defined
3856 #endif
3857 } sli4_req_fcoe_wq_create_v1_t;
3858
3859 #define SLI4_FCOE_WQ_CREATE_V1_MAX_PAGES        8
3860
3861 /**
3862  * @brief FCOE_WQ_DESTROY
3863  *
3864  * Destroy an FC/FCoE Work Queue.
3865  */
3866 typedef struct sli4_req_fcoe_wq_destroy_s {
3867         sli4_req_hdr_t  hdr;
3868 #if BYTE_ORDER == LITTLE_ENDIAN
3869         uint32_t        wq_id:16,
3870                         :16;
3871 #else
3872 #error big endian version not defined
3873 #endif
3874 } sli4_req_fcoe_wq_destroy_t;
3875
3876 /**
3877  * @brief FCOE_POST_SGL_PAGES
3878  *
3879  * Register the scatter gather list (SGL) memory and associate it with an XRI.
3880  */
3881 typedef struct sli4_req_fcoe_post_sgl_pages_s {
3882         sli4_req_hdr_t  hdr;
3883 #if BYTE_ORDER == LITTLE_ENDIAN
3884         uint32_t        xri_start:16,
3885                         xri_count:16;
3886         struct {
3887                 uint32_t        page0_low;
3888                 uint32_t        page0_high;
3889                 uint32_t        page1_low;
3890                 uint32_t        page1_high;
3891         } page_set[10];
3892 #else
3893 #error big endian version not defined
3894 #endif
3895 } sli4_req_fcoe_post_sgl_pages_t;
3896
3897 /**
3898  * @brief FCOE_RQ_CREATE
3899  *
3900  * Create a Receive Queue for FC/FCoE use.
3901  */
3902 typedef struct sli4_req_fcoe_rq_create_s {
3903         sli4_req_hdr_t  hdr;
3904 #if BYTE_ORDER == LITTLE_ENDIAN
3905         uint32_t        num_pages:16,
3906                         dua:1,
3907                         bqu:1,
3908                         :6,
3909                         ulp:8;
3910         uint32_t        :16,
3911                         rqe_count:4,
3912                         :12;
3913         uint32_t        rsvd6;
3914         uint32_t        buffer_size:16,
3915                         cq_id:16;
3916         uint32_t        rsvd8;
3917         sli4_physical_page_descriptor_t page_physical_address[8];
3918 #else
3919 #error big endian version not defined
3920 #endif
3921 } sli4_req_fcoe_rq_create_t;
3922
3923 #define SLI4_FCOE_RQ_CREATE_V0_MAX_PAGES        8
3924 #define SLI4_FCOE_RQ_CREATE_V0_MIN_BUF_SIZE     128
3925 #define SLI4_FCOE_RQ_CREATE_V0_MAX_BUF_SIZE     2048
3926
3927 /**
3928  * @brief FCOE_RQ_CREATE_V1
3929  *
3930  * Create a version 1 Receive Queue for FC/FCoE use.
3931  */
3932 typedef struct sli4_req_fcoe_rq_create_v1_s {
3933         sli4_req_hdr_t  hdr;
3934 #if BYTE_ORDER == LITTLE_ENDIAN
3935         uint32_t        num_pages:16,
3936                         :13,
3937                         dim:1,
3938                         dfd:1,
3939                         dnb:1;
3940         uint32_t        page_size:8,
3941                         rqe_size:4,
3942                         :4,
3943                         rqe_count:16;
3944         uint32_t        rsvd6;
3945         uint32_t        :16,
3946                         cq_id:16;
3947         uint32_t        buffer_size;
3948         sli4_physical_page_descriptor_t page_physical_address[8];
3949 #else
3950 #error big endian version not defined
3951 #endif
3952 } sli4_req_fcoe_rq_create_v1_t;
3953
3954 /**
3955  * @brief FCOE_RQ_CREATE_V2
3956  *
3957  * Create a version 2 Receive Queue for FC/FCoE use.
3958  */
3959 typedef struct sli4_req_fcoe_rq_create_v2_s {
3960         sli4_req_hdr_t  hdr;
3961 #if BYTE_ORDER == LITTLE_ENDIAN
3962         uint32_t        num_pages:16,
3963                         rq_count:8,
3964                         :5,
3965                         dim:1,
3966                         dfd:1,
3967                         dnb:1;
3968         uint32_t        page_size:8,
3969                         rqe_size:4,
3970                         :4,
3971                         rqe_count:16;
3972         uint32_t        hdr_buffer_size:16,
3973                         payload_buffer_size:16;
3974         uint32_t        base_cq_id:16,
3975                         :16;
3976         uint32_t        rsvd;
3977         sli4_physical_page_descriptor_t page_physical_address[0];
3978 #else
3979 #error big endian version not defined
3980 #endif
3981 } sli4_req_fcoe_rq_create_v2_t;
3982
3983 #define SLI4_FCOE_RQ_CREATE_V1_MAX_PAGES        8
3984 #define SLI4_FCOE_RQ_CREATE_V1_MIN_BUF_SIZE     64
3985 #define SLI4_FCOE_RQ_CREATE_V1_MAX_BUF_SIZE     2048
3986
3987 #define SLI4_FCOE_RQE_SIZE_8                    0x2
3988 #define SLI4_FCOE_RQE_SIZE_16                   0x3
3989 #define SLI4_FCOE_RQE_SIZE_32                   0x4
3990 #define SLI4_FCOE_RQE_SIZE_64                   0x5
3991 #define SLI4_FCOE_RQE_SIZE_128                  0x6
3992
3993 #define SLI4_FCOE_RQ_PAGE_SIZE_4096             0x1
3994 #define SLI4_FCOE_RQ_PAGE_SIZE_8192             0x2
3995 #define SLI4_FCOE_RQ_PAGE_SIZE_16384            0x4
3996 #define SLI4_FCOE_RQ_PAGE_SIZE_32768            0x8
3997 #define SLI4_FCOE_RQ_PAGE_SIZE_64536            0x10
3998
3999 #define SLI4_FCOE_RQE_SIZE                      8
4000
4001 /**
4002  * @brief FCOE_RQ_DESTROY
4003  *
4004  * Destroy an FC/FCoE Receive Queue.
4005  */
4006 typedef struct sli4_req_fcoe_rq_destroy_s {
4007         sli4_req_hdr_t  hdr;
4008 #if BYTE_ORDER == LITTLE_ENDIAN
4009         uint32_t        rq_id:16,
4010                         :16;
4011 #else
4012 #error big endian version not defined
4013 #endif
4014 } sli4_req_fcoe_rq_destroy_t;
4015
4016 /**
4017  * @brief FCOE_READ_FCF_TABLE
4018  *
4019  * Retrieve a FCF database (also known as a table) entry created by the SLI Port
4020  * during FIP discovery.
4021  */
4022 typedef struct sli4_req_fcoe_read_fcf_table_s {
4023         sli4_req_hdr_t  hdr;
4024 #if BYTE_ORDER == LITTLE_ENDIAN
4025         uint32_t        fcf_index:16,
4026                         :16;
4027 #else
4028 #error big endian version not defined
4029 #endif
4030 } sli4_req_fcoe_read_fcf_table_t;
4031
4032 /* A FCF index of -1 on the request means return the first valid entry */
4033 #define SLI4_FCOE_FCF_TABLE_FIRST               (UINT16_MAX)
4034
4035 /**
4036  * @brief FCF table entry
4037  *
4038  * This is the information returned by the FCOE_READ_FCF_TABLE command.
4039  */
4040 typedef struct sli4_fcf_entry_s {
4041 #if BYTE_ORDER == LITTLE_ENDIAN
4042         uint32_t        max_receive_size;
4043         uint32_t        fip_keep_alive;
4044         uint32_t        fip_priority;
4045         uint8_t         fcf_mac_address[6];
4046         uint8_t         fcf_available;
4047         uint8_t         mac_address_provider;
4048         uint8_t         fabric_name_id[8];
4049         uint8_t         fc_map[3];
4050         uint8_t         val:1,
4051                         fc:1,
4052                         :5,
4053                         sol:1;
4054         uint32_t        fcf_index:16,
4055                         fcf_state:16;
4056         uint8_t         vlan_bitmap[512];
4057         uint8_t         switch_name[8];
4058 #else
4059 #error big endian version not defined
4060 #endif
4061 } sli4_fcf_entry_t;
4062
4063 /**
4064  * @brief FCOE_READ_FCF_TABLE response.
4065  */
4066 typedef struct sli4_res_fcoe_read_fcf_table_s {
4067         sli4_res_hdr_t  hdr;
4068 #if BYTE_ORDER == LITTLE_ENDIAN
4069         uint32_t        event_tag;
4070         uint32_t        next_index:16,
4071                         :16;
4072         sli4_fcf_entry_t fcf_entry;
4073 #else
4074 #error big endian version not defined
4075 #endif
4076 } sli4_res_fcoe_read_fcf_table_t;
4077
4078 /* A next FCF index of -1 in the response means this is the last valid entry */
4079 #define SLI4_FCOE_FCF_TABLE_LAST                (UINT16_MAX)
4080
4081 /**
4082  * @brief FCOE_POST_HDR_TEMPLATES
4083  */
4084 typedef struct sli4_req_fcoe_post_hdr_templates_s {
4085         sli4_req_hdr_t  hdr;
4086 #if BYTE_ORDER == LITTLE_ENDIAN
4087         uint32_t        rpi_offset:16,
4088                         page_count:16;
4089         sli4_physical_page_descriptor_t page_descriptor[0];
4090 #else
4091 #error big endian version not defined
4092 #endif
4093 } sli4_req_fcoe_post_hdr_templates_t;
4094
4095 #define SLI4_FCOE_HDR_TEMPLATE_SIZE     64
4096
4097 /**
4098  * @brief FCOE_REDISCOVER_FCF
4099  */
4100 typedef struct sli4_req_fcoe_rediscover_fcf_s {
4101         sli4_req_hdr_t  hdr;
4102 #if BYTE_ORDER == LITTLE_ENDIAN
4103         uint32_t        fcf_count:16,
4104                         :16;
4105         uint32_t        rsvd5;
4106         uint16_t        fcf_index[16];
4107 #else
4108 #error big endian version not defined
4109 #endif
4110 } sli4_req_fcoe_rediscover_fcf_t;
4111
4112 /**
4113  * Work Queue Entry (WQE) types.
4114  */
4115 #define SLI4_WQE_ABORT                  0x0f
4116 #define SLI4_WQE_ELS_REQUEST64          0x8a
4117 #define SLI4_WQE_FCP_IBIDIR64           0xac
4118 #define SLI4_WQE_FCP_IREAD64            0x9a
4119 #define SLI4_WQE_FCP_IWRITE64           0x98
4120 #define SLI4_WQE_FCP_ICMND64            0x9c
4121 #define SLI4_WQE_FCP_TRECEIVE64         0xa1
4122 #define SLI4_WQE_FCP_CONT_TRECEIVE64    0xe5
4123 #define SLI4_WQE_FCP_TRSP64             0xa3
4124 #define SLI4_WQE_FCP_TSEND64            0x9f
4125 #define SLI4_WQE_GEN_REQUEST64          0xc2
4126 #define SLI4_WQE_SEND_FRAME             0xe1
4127 #define SLI4_WQE_XMIT_BCAST64           0X84
4128 #define SLI4_WQE_XMIT_BLS_RSP           0x97
4129 #define SLI4_WQE_ELS_RSP64              0x95
4130 #define SLI4_WQE_XMIT_SEQUENCE64        0x82
4131 #define SLI4_WQE_REQUEUE_XRI            0x93
4132
4133 /**
4134  * WQE command types.
4135  */
4136 #define SLI4_CMD_FCP_IREAD64_WQE        0x00
4137 #define SLI4_CMD_FCP_ICMND64_WQE        0x00
4138 #define SLI4_CMD_FCP_IWRITE64_WQE       0x01
4139 #define SLI4_CMD_FCP_TRECEIVE64_WQE     0x02
4140 #define SLI4_CMD_FCP_TRSP64_WQE         0x03
4141 #define SLI4_CMD_FCP_TSEND64_WQE        0x07
4142 #define SLI4_CMD_GEN_REQUEST64_WQE      0x08
4143 #define SLI4_CMD_XMIT_BCAST64_WQE       0x08
4144 #define SLI4_CMD_XMIT_BLS_RSP64_WQE     0x08
4145 #define SLI4_CMD_ABORT_WQE              0x08
4146 #define SLI4_CMD_XMIT_SEQUENCE64_WQE    0x08
4147 #define SLI4_CMD_REQUEUE_XRI_WQE        0x0A
4148 #define SLI4_CMD_SEND_FRAME_WQE         0x0a
4149
4150 #define SLI4_WQE_SIZE                   0x05
4151 #define SLI4_WQE_EXT_SIZE               0x06
4152
4153 #define SLI4_WQE_BYTES                  (16 * sizeof(uint32_t))
4154 #define SLI4_WQE_EXT_BYTES              (32 * sizeof(uint32_t))
4155
4156 /* Mask for ccp (CS_CTL) */
4157 #define SLI4_MASK_CCP   0xfe /* Upper 7 bits of CS_CTL is priority */
4158
4159 /**
4160  * @brief Generic WQE
4161  */
4162 typedef struct sli4_generic_wqe_s {
4163 #if BYTE_ORDER == LITTLE_ENDIAN
4164         uint32_t        cmd_spec0_5[6];
4165         uint32_t        xri_tag:16,
4166                         context_tag:16;
4167         uint32_t        :2,
4168                         ct:2,
4169                         :4,
4170                         command:8,
4171                         class:3,
4172                         :1,
4173                         pu:2,
4174                         :2,
4175                         timer:8;
4176         uint32_t        abort_tag;
4177         uint32_t        request_tag:16,
4178                         :16;
4179         uint32_t        ebde_cnt:4,
4180                         :3,
4181                         len_loc:2,
4182                         qosd:1,
4183                         :1,
4184                         xbl:1,
4185                         hlm:1,
4186                         iod:1,
4187                         dbde:1,
4188                         wqes:1,
4189                         pri:3,
4190                         pv:1,
4191                         eat:1,
4192                         xc:1,
4193                         :1,
4194                         ccpe:1,
4195                         ccp:8;
4196         uint32_t        cmd_type:4,
4197                         :3,
4198                         wqec:1,
4199                         :8,
4200                         cq_id:16;
4201 #else
4202 #error big endian version not defined
4203 #endif
4204 } sli4_generic_wqe_t;
4205
4206 /**
4207  * @brief WQE used to abort exchanges.
4208  */
4209 typedef struct sli4_abort_wqe_s {
4210 #if BYTE_ORDER == LITTLE_ENDIAN
4211         uint32_t        rsvd0;
4212         uint32_t        rsvd1;
4213         uint32_t        ext_t_tag;
4214         uint32_t        ia:1,
4215                         ir:1,
4216                         :6,
4217                         criteria:8,
4218                         :16;
4219         uint32_t        ext_t_mask;
4220         uint32_t        t_mask;
4221         uint32_t        xri_tag:16,
4222                         context_tag:16;
4223         uint32_t        :2,
4224                         ct:2,
4225                         :4,
4226                         command:8,
4227                         class:3,
4228                         :1,
4229                         pu:2,
4230                         :2,
4231                         timer:8;
4232         uint32_t        t_tag;
4233         uint32_t        request_tag:16,
4234                         :16;
4235         uint32_t        ebde_cnt:4,
4236                         :3,
4237                         len_loc:2,
4238                         qosd:1,
4239                         :1,
4240                         xbl:1,
4241                         :1,
4242                         iod:1,
4243                         dbde:1,
4244                         wqes:1,
4245                         pri:3,
4246                         pv:1,
4247                         eat:1,
4248                         xc:1,
4249                         :1,
4250                         ccpe:1,
4251                         ccp:8;
4252         uint32_t        cmd_type:4,
4253                         :3,
4254                         wqec:1,
4255                         :8,
4256                         cq_id:16;
4257 #else
4258 #error big endian version not defined
4259 #endif
4260 } sli4_abort_wqe_t;
4261
4262 #define SLI4_ABORT_CRITERIA_XRI_TAG             0x01
4263 #define SLI4_ABORT_CRITERIA_ABORT_TAG           0x02
4264 #define SLI4_ABORT_CRITERIA_REQUEST_TAG         0x03
4265 #define SLI4_ABORT_CRITERIA_EXT_ABORT_TAG       0x04
4266
4267 typedef enum {
4268         SLI_ABORT_XRI,
4269         SLI_ABORT_ABORT_ID,
4270         SLI_ABORT_REQUEST_ID,
4271         SLI_ABORT_MAX,          /* must be last */
4272 } sli4_abort_type_e;
4273
4274 /**
4275  * @brief WQE used to create an ELS request.
4276  */
4277 typedef struct sli4_els_request64_wqe_s {
4278         sli4_bde_t      els_request_payload;
4279 #if BYTE_ORDER == LITTLE_ENDIAN
4280         uint32_t        els_request_payload_length;
4281         uint32_t        sid:24,
4282                         sp:1,
4283                         :7;
4284         uint32_t        remote_id:24,
4285                         :8;
4286         uint32_t        xri_tag:16,
4287                         context_tag:16;
4288         uint32_t        :2,
4289                         ct:2,
4290                         :4,
4291                         command:8,
4292                         class:3,
4293                         ar:1,
4294                         pu:2,
4295                         :2,
4296                         timer:8;
4297         uint32_t        abort_tag;
4298         uint32_t        request_tag:16,
4299                         temporary_rpi:16;
4300         uint32_t        ebde_cnt:4,
4301                         :3,
4302                         len_loc:2,
4303                         qosd:1,
4304                         :1,
4305                         xbl:1,
4306                         hlm:1,
4307                         iod:1,
4308                         dbde:1,
4309                         wqes:1,
4310                         pri:3,
4311                         pv:1,
4312                         eat:1,
4313                         xc:1,
4314                         :1,
4315                         ccpe:1,
4316                         ccp:8;
4317         uint32_t        cmd_type:4,
4318                         els_id:3,
4319                         wqec:1,
4320                         :8,
4321                         cq_id:16;
4322         sli4_bde_t      els_response_payload_bde;
4323         uint32_t        max_response_payload_length;
4324 #else
4325 #error big endian version not defined
4326 #endif
4327 } sli4_els_request64_wqe_t;
4328
4329 #define SLI4_ELS_REQUEST64_CONTEXT_RPI  0x0
4330 #define SLI4_ELS_REQUEST64_CONTEXT_VPI  0x1
4331 #define SLI4_ELS_REQUEST64_CONTEXT_VFI  0x2
4332 #define SLI4_ELS_REQUEST64_CONTEXT_FCFI 0x3
4333
4334 #define SLI4_ELS_REQUEST64_CLASS_2      0x1
4335 #define SLI4_ELS_REQUEST64_CLASS_3      0x2
4336
4337 #define SLI4_ELS_REQUEST64_DIR_WRITE    0x0
4338 #define SLI4_ELS_REQUEST64_DIR_READ     0x1
4339
4340 #define SLI4_ELS_REQUEST64_OTHER        0x0
4341 #define SLI4_ELS_REQUEST64_LOGO         0x1
4342 #define SLI4_ELS_REQUEST64_FDISC        0x2
4343 #define SLI4_ELS_REQUEST64_FLOGIN       0x3
4344 #define SLI4_ELS_REQUEST64_PLOGI        0x4
4345
4346 #define SLI4_ELS_REQUEST64_CMD_GEN              0x08
4347 #define SLI4_ELS_REQUEST64_CMD_NON_FABRIC       0x0c
4348 #define SLI4_ELS_REQUEST64_CMD_FABRIC           0x0d
4349
4350 /**
4351  * @brief WQE used to create an FCP initiator no data command.
4352  */
4353 typedef struct sli4_fcp_icmnd64_wqe_s {
4354         sli4_bde_t      bde;
4355 #if BYTE_ORDER == LITTLE_ENDIAN
4356         uint32_t        payload_offset_length:16,
4357                         fcp_cmd_buffer_length:16;
4358         uint32_t        rsvd4;
4359         uint32_t        remote_n_port_id:24,
4360                         :8;
4361         uint32_t        xri_tag:16,
4362                         context_tag:16;
4363         uint32_t        dif:2,
4364                         ct:2,
4365                         bs:3,
4366                         :1,
4367                         command:8,
4368                         class:3,
4369                         :1,
4370                         pu:2,
4371                         erp:1,
4372                         lnk:1,
4373                         timer:8;
4374         uint32_t        abort_tag;
4375         uint32_t        request_tag:16,
4376                         :16;
4377         uint32_t        ebde_cnt:4,
4378                         :3,
4379                         len_loc:2,
4380                         qosd:1,
4381                         :1,
4382                         xbl:1,
4383                         hlm:1,
4384                         iod:1,
4385                         dbde:1,
4386                         wqes:1,
4387                         pri:3,
4388                         pv:1,
4389                         eat:1,
4390                         xc:1,
4391                         :1,
4392                         ccpe:1,
4393                         ccp:8;
4394         uint32_t        cmd_type:4,
4395                         :3,
4396                         wqec:1,
4397                         :8,
4398                         cq_id:16;
4399         uint32_t        rsvd12;
4400         uint32_t        rsvd13;
4401         uint32_t        rsvd14;
4402         uint32_t        rsvd15;
4403 #else
4404 #error big endian version not defined
4405 #endif
4406 } sli4_fcp_icmnd64_wqe_t;
4407
4408 /**
4409  * @brief WQE used to create an FCP initiator read.
4410  */
4411 typedef struct sli4_fcp_iread64_wqe_s {
4412         sli4_bde_t      bde;
4413 #if BYTE_ORDER == LITTLE_ENDIAN
4414         uint32_t        payload_offset_length:16,
4415                         fcp_cmd_buffer_length:16;
4416         uint32_t        total_transfer_length;
4417         uint32_t        remote_n_port_id:24,
4418                         :8;
4419         uint32_t        xri_tag:16,
4420                         context_tag:16;
4421         uint32_t        dif:2,
4422                         ct:2,
4423                         bs:3,
4424                         :1,
4425                         command:8,
4426                         class:3,
4427                         :1,
4428                         pu:2,
4429                         erp:1,
4430                         lnk:1,
4431                         timer:8;
4432         uint32_t        abort_tag;
4433         uint32_t        request_tag:16,
4434                         :16;
4435         uint32_t        ebde_cnt:4,
4436                         :3,
4437                         len_loc:2,
4438                         qosd:1,
4439                         :1,
4440                         xbl:1,
4441                         hlm:1,
4442                         iod:1,
4443                         dbde:1,
4444                         wqes:1,
4445                         pri:3,
4446                         pv:1,
4447                         eat:1,
4448                         xc:1,
4449                         :1,
4450                         ccpe:1,
4451                         ccp:8;
4452         uint32_t        cmd_type:4,
4453                         :3,
4454                         wqec:1,
4455                         :8,
4456                         cq_id:16;
4457         uint32_t        rsvd12;
4458 #else
4459 #error big endian version not defined
4460 #endif
4461         sli4_bde_t      first_data_bde; /* reserved if performance hints disabled */
4462 } sli4_fcp_iread64_wqe_t;
4463
4464 /**
4465  * @brief WQE used to create an FCP initiator write.
4466  */
4467 typedef struct sli4_fcp_iwrite64_wqe_s {
4468         sli4_bde_t      bde;
4469 #if BYTE_ORDER == LITTLE_ENDIAN
4470         uint32_t        payload_offset_length:16,
4471                         fcp_cmd_buffer_length:16;
4472         uint32_t        total_transfer_length;
4473         uint32_t        initial_transfer_length;
4474         uint32_t        xri_tag:16,
4475                         context_tag:16;
4476         uint32_t        dif:2,
4477                         ct:2,
4478                         bs:3,
4479                         :1,
4480                         command:8,
4481                         class:3,
4482                         :1,
4483                         pu:2,
4484                         erp:1,
4485                         lnk:1,
4486                         timer:8;
4487         uint32_t        abort_tag;
4488         uint32_t        request_tag:16,
4489                         :16;
4490         uint32_t        ebde_cnt:4,
4491                         :3,
4492                         len_loc:2,
4493                         qosd:1,
4494                         :1,
4495                         xbl:1,
4496                         hlm:1,
4497                         iod:1,
4498                         dbde:1,
4499                         wqes:1,
4500                         pri:3,
4501                         pv:1,
4502                         eat:1,
4503                         xc:1,
4504                         :1,
4505                         ccpe:1,
4506                         ccp:8;
4507         uint32_t        cmd_type:4,
4508                         :3,
4509                         wqec:1,
4510                         :8,
4511                         cq_id:16;
4512         uint32_t        remote_n_port_id:24,
4513                         :8;
4514 #else
4515 #error big endian version not defined
4516 #endif
4517         sli4_bde_t      first_data_bde;
4518 } sli4_fcp_iwrite64_wqe_t;
4519
4520 typedef struct sli4_fcp_128byte_wqe_s {
4521         uint32_t dw[32];
4522 } sli4_fcp_128byte_wqe_t;
4523
4524 /**
4525  * @brief WQE used to create an FCP target receive, and FCP target
4526  * receive continue.
4527  */
4528 typedef struct sli4_fcp_treceive64_wqe_s {
4529         sli4_bde_t      bde;
4530 #if BYTE_ORDER == LITTLE_ENDIAN
4531         uint32_t        payload_offset_length;
4532         uint32_t        relative_offset;
4533         /**
4534          * DWord 5 can either be the task retry identifier (HLM=0) or
4535          * the remote N_Port ID (HLM=1), or if implementing the Skyhawk
4536          * T10-PI workaround, the secondary xri tag
4537          */
4538         union {
4539                 uint32_t        sec_xri_tag:16,
4540                                 :16;
4541                 uint32_t        dword;
4542         } dword5;
4543         uint32_t        xri_tag:16,
4544                         context_tag:16;
4545         uint32_t        dif:2,
4546                         ct:2,
4547                         bs:3,
4548                         :1,
4549                         command:8,
4550                         class:3,
4551                         ar:1,
4552                         pu:2,
4553                         conf:1,
4554                         lnk:1,
4555                         timer:8;
4556         uint32_t        abort_tag;
4557         uint32_t        request_tag:16,
4558                         remote_xid:16;
4559         uint32_t        ebde_cnt:4,
4560                         :1,
4561                         app_id_valid:1,
4562                         :1,
4563                         len_loc:2,
4564                         qosd:1,
4565                         wchn:1,
4566                         xbl:1,
4567                         hlm:1,
4568                         iod:1,
4569                         dbde:1,
4570                         wqes:1,
4571                         pri:3,
4572                         pv:1,
4573                         eat:1,
4574                         xc:1,
4575                         sr:1,
4576                         ccpe:1,
4577                         ccp:8;
4578         uint32_t        cmd_type:4,
4579                         :3,
4580                         wqec:1,
4581                         :8,
4582                         cq_id:16;
4583         uint32_t        fcp_data_receive_length;
4584
4585 #else
4586 #error big endian version not defined
4587 #endif
4588         sli4_bde_t      first_data_bde; /* For performance hints */
4589
4590 } sli4_fcp_treceive64_wqe_t;
4591
4592 /**
4593  * @brief WQE used to create an FCP target response.
4594  */
4595 typedef struct sli4_fcp_trsp64_wqe_s {
4596         sli4_bde_t      bde;
4597 #if BYTE_ORDER == LITTLE_ENDIAN
4598         uint32_t        fcp_response_length;
4599         uint32_t        rsvd4;
4600         /**
4601          * DWord 5 can either be the task retry identifier (HLM=0) or
4602          * the remote N_Port ID (HLM=1)
4603          */
4604         uint32_t        dword5;
4605         uint32_t        xri_tag:16,
4606                         rpi:16;
4607         uint32_t        :2,
4608                         ct:2,
4609                         dnrx:1,
4610                         :3,
4611                         command:8,
4612                         class:3,
4613                         ag:1,
4614                         pu:2,
4615                         conf:1,
4616                         lnk:1,
4617                         timer:8;
4618         uint32_t        abort_tag;
4619         uint32_t        request_tag:16,
4620                         remote_xid:16;
4621         uint32_t        ebde_cnt:4,
4622                         :1,
4623                         app_id_valid:1,
4624                         :1,
4625                         len_loc:2,
4626                         qosd:1,
4627                         wchn:1,
4628                         xbl:1,
4629                         hlm:1,
4630                         iod:1,
4631                         dbde:1,
4632                         wqes:1,
4633                         pri:3,
4634                         pv:1,
4635                         eat:1,
4636                         xc:1,
4637                         sr:1,
4638                         ccpe:1,
4639                         ccp:8;
4640         uint32_t        cmd_type:4,
4641                         :3,
4642                         wqec:1,
4643                         :8,
4644                         cq_id:16;
4645         uint32_t        rsvd12;
4646         uint32_t        rsvd13;
4647         uint32_t        rsvd14;
4648         uint32_t        rsvd15;
4649 #else
4650 #error big endian version not defined
4651 #endif
4652 } sli4_fcp_trsp64_wqe_t;
4653
4654 /**
4655  * @brief WQE used to create an FCP target send (DATA IN).
4656  */
4657 typedef struct sli4_fcp_tsend64_wqe_s {
4658         sli4_bde_t      bde;
4659 #if BYTE_ORDER == LITTLE_ENDIAN
4660         uint32_t        payload_offset_length;
4661         uint32_t        relative_offset;
4662         /**
4663          * DWord 5 can either be the task retry identifier (HLM=0) or
4664          * the remote N_Port ID (HLM=1)
4665          */
4666         uint32_t        dword5;
4667         uint32_t        xri_tag:16,
4668                         rpi:16;
4669         uint32_t        dif:2,
4670                         ct:2,
4671                         bs:3,
4672                         :1,
4673                         command:8,
4674                         class:3,
4675                         ar:1,
4676                         pu:2,
4677                         conf:1,
4678                         lnk:1,
4679                         timer:8;
4680         uint32_t        abort_tag;
4681         uint32_t        request_tag:16,
4682                         remote_xid:16;
4683         uint32_t        ebde_cnt:4,
4684                         :1,
4685                         app_id_valid:1,
4686                         :1,
4687                         len_loc:2,
4688                         qosd:1,
4689                         wchn:1,
4690                         xbl:1,
4691                         hlm:1,
4692                         iod:1,
4693                         dbde:1,
4694                         wqes:1,
4695                         pri:3,
4696                         pv:1,
4697                         eat:1,
4698                         xc:1,
4699                         sr:1,
4700                         ccpe:1,
4701                         ccp:8;
4702         uint32_t        cmd_type:4,
4703                         :3,
4704                         wqec:1,
4705                         :8,
4706                         cq_id:16;
4707         uint32_t        fcp_data_transmit_length;
4708
4709 #else
4710 #error big endian version not defined
4711 #endif
4712         sli4_bde_t      first_data_bde; /* For performance hints */
4713 } sli4_fcp_tsend64_wqe_t;
4714
4715 #define SLI4_IO_CONTINUATION            BIT(0)  /** The XRI associated with this IO is already active */
4716 #define SLI4_IO_AUTO_GOOD_RESPONSE      BIT(1)  /** Automatically generate a good RSP frame */
4717 #define SLI4_IO_NO_ABORT                BIT(2)
4718 #define SLI4_IO_DNRX                    BIT(3)  /** Set the DNRX bit because no auto xref rdy buffer is posted */
4719
4720 /* WQE DIF field contents */
4721 #define SLI4_DIF_DISABLED               0
4722 #define SLI4_DIF_PASS_THROUGH           1
4723 #define SLI4_DIF_STRIP                  2
4724 #define SLI4_DIF_INSERT                 3
4725
4726 /**
4727  * @brief WQE used to create a general request.
4728  */
4729 typedef struct sli4_gen_request64_wqe_s {
4730         sli4_bde_t      bde;
4731 #if BYTE_ORDER == LITTLE_ENDIAN
4732         uint32_t        request_payload_length;
4733         uint32_t        relative_offset;
4734         uint32_t        :8,
4735                         df_ctl:8,
4736                         type:8,
4737                         r_ctl:8;
4738         uint32_t        xri_tag:16,
4739                         context_tag:16;
4740         uint32_t        :2,
4741                         ct:2,
4742                         :4,
4743                         command:8,
4744                         class:3,
4745                         :1,
4746                         pu:2,
4747                         :2,
4748                         timer:8;
4749         uint32_t        abort_tag;
4750         uint32_t        request_tag:16,
4751                         :16;
4752         uint32_t        ebde_cnt:4,
4753                         :3,
4754                         len_loc:2,
4755                         qosd:1,
4756                         :1,
4757                         xbl:1,
4758                         hlm:1,
4759                         iod:1,
4760                         dbde:1,
4761                         wqes:1,
4762                         pri:3,
4763                         pv:1,
4764                         eat:1,
4765                         xc:1,
4766                         :1,
4767                         ccpe:1,
4768                         ccp:8;
4769         uint32_t        cmd_type:4,
4770                         :3,
4771                         wqec:1,
4772                         :8,
4773                         cq_id:16;
4774         uint32_t        remote_n_port_id:24,
4775                         :8;
4776         uint32_t        rsvd13;
4777         uint32_t        rsvd14;
4778         uint32_t        max_response_payload_length;
4779 #else
4780 #error big endian version not defined
4781 #endif
4782 } sli4_gen_request64_wqe_t;
4783
4784 /**
4785  * @brief WQE used to create a send frame request.
4786  */
4787 typedef struct sli4_send_frame_wqe_s {
4788         sli4_bde_t      bde;
4789 #if BYTE_ORDER == LITTLE_ENDIAN
4790         uint32_t        frame_length;
4791         uint32_t        fc_header_0_1[2];
4792         uint32_t        xri_tag:16,
4793                         context_tag:16;
4794         uint32_t        :2,
4795                         ct:2,
4796                         :4,
4797                         command:8,
4798                         class:3,
4799                         :1,
4800                         pu:2,
4801                         :2,
4802                         timer:8;
4803         uint32_t        abort_tag;
4804         uint32_t        request_tag:16,
4805                         eof:8,
4806                         sof:8;
4807         uint32_t        ebde_cnt:4,
4808                         :3,
4809                         lenloc:2,
4810                         qosd:1,
4811                         wchn:1,
4812                         xbl:1,
4813                         hlm:1,
4814                         iod:1,
4815                         dbde:1,
4816                         wqes:1,
4817                         pri:3,
4818                         pv:1,
4819                         eat:1,
4820                         xc:1,
4821                         :1,
4822                         ccpe:1,
4823                         ccp:8;
4824         uint32_t        cmd_type:4,
4825                         :3,
4826                         wqec:1,
4827                         :8,
4828                         cq_id:16;
4829         uint32_t        fc_header_2_5[4];
4830 #else
4831 #error big endian version not defined
4832 #endif
4833 } sli4_send_frame_wqe_t;
4834
4835 /**
4836  * @brief WQE used to create a transmit sequence.
4837  */
4838 typedef struct sli4_xmit_sequence64_wqe_s {
4839         sli4_bde_t      bde;
4840 #if BYTE_ORDER == LITTLE_ENDIAN
4841         uint32_t        remote_n_port_id:24,
4842                         :8;
4843         uint32_t        relative_offset;
4844         uint32_t        :2,
4845                         si:1,
4846                         ft:1,
4847                         :2,
4848                         xo:1,
4849                         ls:1,
4850                         df_ctl:8,
4851                         type:8,
4852                         r_ctl:8;
4853         uint32_t        xri_tag:16,
4854                         context_tag:16;
4855         uint32_t        dif:2,
4856                         ct:2,
4857                         bs:3,
4858                         :1,
4859                         command:8,
4860                         class:3,
4861                         :1,
4862                         pu:2,
4863                         :2,
4864                         timer:8;
4865         uint32_t        abort_tag;
4866         uint32_t        request_tag:16,
4867                         remote_xid:16;
4868         uint32_t        ebde_cnt:4,
4869                         :3,
4870                         len_loc:2,
4871                         qosd:1,
4872                         :1,
4873                         xbl:1,
4874                         hlm:1,
4875                         iod:1,
4876                         dbde:1,
4877                         wqes:1,
4878                         pri:3,
4879                         pv:1,
4880                         eat:1,
4881                         xc:1,
4882                         sr:1,
4883                         ccpe:1,
4884                         ccp:8;
4885         uint32_t        cmd_type:4,
4886                         :3,
4887                         wqec:1,
4888                         :8,
4889                         cq_id:16;
4890         uint32_t        sequence_payload_len;
4891         uint32_t        rsvd13;
4892         uint32_t        rsvd14;
4893         uint32_t        rsvd15;
4894 #else
4895 #error big endian version not defined
4896 #endif
4897 } sli4_xmit_sequence64_wqe_t;
4898
4899 /**
4900  * @brief WQE used unblock the specified XRI and to release it to the SLI Port's free pool.
4901  */
4902 typedef struct sli4_requeue_xri_wqe_s {
4903         uint32_t        rsvd0;
4904         uint32_t        rsvd1;
4905         uint32_t        rsvd2;
4906         uint32_t        rsvd3;
4907         uint32_t        rsvd4;
4908         uint32_t        rsvd5;
4909 #if BYTE_ORDER == LITTLE_ENDIAN
4910         uint32_t        xri_tag:16,
4911                         context_tag:16;
4912         uint32_t        :2,
4913                         ct:2,
4914                         :4,
4915                         command:8,
4916                         class:3,
4917                         :1,
4918                         pu:2,
4919                         :2,
4920                         timer:8;
4921         uint32_t        rsvd8;
4922         uint32_t        request_tag:16,
4923                         :16;
4924         uint32_t        ebde_cnt:4,
4925                         :3,
4926                         len_loc:2,
4927                         qosd:1,
4928                         wchn:1,
4929                         xbl:1,
4930                         hlm:1,
4931                         iod:1,
4932                         dbde:1,
4933                         wqes:1,
4934                         pri:3,
4935                         pv:1,
4936                         eat:1,
4937                         xc:1,
4938                         :1,
4939                         ccpe:1,
4940                         ccp:8;
4941         uint32_t        cmd_type:4,
4942                         :3,
4943                         wqec:1,
4944                         :8,
4945                         cq_id:16;
4946         uint32_t        rsvd12;
4947         uint32_t        rsvd13;
4948         uint32_t        rsvd14;
4949         uint32_t        rsvd15;
4950 #else
4951 #error big endian version not defined
4952 #endif
4953 } sli4_requeue_xri_wqe_t;
4954
4955 /**
4956  * @brief WQE used to send a single frame sequence to broadcast address
4957  */
4958 typedef struct sli4_xmit_bcast64_wqe_s {
4959         sli4_bde_t      sequence_payload;
4960 #if BYTE_ORDER == LITTLE_ENDIAN
4961         uint32_t        sequence_payload_length;
4962         uint32_t        rsvd4;
4963         uint32_t        :8,
4964                         df_ctl:8,
4965                         type:8,
4966                         r_ctl:8;
4967         uint32_t        xri_tag:16,
4968                         context_tag:16;
4969         uint32_t        :2,
4970                         ct:2,
4971                         :4,
4972                         command:8,
4973                         class:3,
4974                         :1,
4975                         pu:2,
4976                         :2,
4977                         timer:8;
4978         uint32_t        abort_tag;
4979         uint32_t        request_tag:16,
4980                         temporary_rpi:16;
4981         uint32_t        ebde_cnt:4,
4982                         :3,
4983                         len_loc:2,
4984                         qosd:1,
4985                         :1,
4986                         xbl:1,
4987                         hlm:1,
4988                         iod:1,
4989                         dbde:1,
4990                         wqes:1,
4991                         pri:3,
4992                         pv:1,
4993                         eat:1,
4994                         xc:1,
4995                         :1,
4996                         ccpe:1,
4997                         ccp:8;
4998         uint32_t        cmd_type:4,
4999                         :3,
5000                         wqec:1,
5001                         :8,
5002                         cq_id:16;
5003         uint32_t        rsvd12;
5004         uint32_t        rsvd13;
5005         uint32_t        rsvd14;
5006         uint32_t        rsvd15;
5007 #else
5008 #error big endian version not defined
5009 #endif
5010 } sli4_xmit_bcast64_wqe_t;
5011
5012 /**
5013  * @brief WQE used to create a BLS response.
5014  */
5015 typedef struct sli4_xmit_bls_rsp_wqe_s {
5016 #if BYTE_ORDER == LITTLE_ENDIAN
5017         uint32_t        payload_word0;
5018         uint32_t        rx_id:16,
5019                         ox_id:16;
5020         uint32_t        high_seq_cnt:16,
5021                         low_seq_cnt:16;
5022         uint32_t        rsvd3;
5023         uint32_t        local_n_port_id:24,
5024                         :8;
5025         uint32_t        remote_id:24,
5026                         :6,
5027                         ar:1,
5028                         xo:1;
5029         uint32_t        xri_tag:16,
5030                         context_tag:16;
5031         uint32_t        :2,
5032                         ct:2,
5033                         :4,
5034                         command:8,
5035                         class:3,
5036                         :1,
5037                         pu:2,
5038                         :2,
5039                         timer:8;
5040         uint32_t        abort_tag;
5041         uint32_t        request_tag:16,
5042                         :16;
5043         uint32_t        ebde_cnt:4,
5044                         :3,
5045                         len_loc:2,
5046                         qosd:1,
5047                         :1,
5048                         xbl:1,
5049                         hlm:1,
5050                         iod:1,
5051                         dbde:1,
5052                         wqes:1,
5053                         pri:3,
5054                         pv:1,
5055                         eat:1,
5056                         xc:1,
5057                         :1,
5058                         ccpe:1,
5059                         ccp:8;
5060         uint32_t        cmd_type:4,
5061                         :3,
5062                         wqec:1,
5063                         :8,
5064                         cq_id:16;
5065         uint32_t        temporary_rpi:16,
5066                         :16;
5067         uint32_t        rsvd13;
5068         uint32_t        rsvd14;
5069         uint32_t        rsvd15;
5070 #else
5071 #error big endian version not defined
5072 #endif
5073 } sli4_xmit_bls_rsp_wqe_t;
5074
5075 typedef enum {
5076         SLI_BLS_ACC,
5077         SLI_BLS_RJT,
5078         SLI_BLS_MAX
5079 } sli_bls_type_e;
5080
5081 typedef struct sli_bls_payload_s {
5082         sli_bls_type_e  type;
5083         uint16_t        ox_id;
5084         uint16_t        rx_id;
5085         union {
5086                 struct {
5087                         uint32_t        seq_id_validity:8,
5088                                         seq_id_last:8,
5089                                         :16;
5090                         uint16_t        ox_id;
5091                         uint16_t        rx_id;
5092                         uint16_t        low_seq_cnt;
5093                         uint16_t        high_seq_cnt;
5094                 } acc;
5095                 struct {
5096                         uint32_t        vendor_unique:8,
5097                                         reason_explanation:8,
5098                                         reason_code:8,
5099                                         :8;
5100                 } rjt;
5101         } u;
5102 } sli_bls_payload_t;
5103
5104 /**
5105  * @brief WQE used to create an ELS response.
5106  */
5107 typedef struct sli4_xmit_els_rsp64_wqe_s {
5108         sli4_bde_t      els_response_payload;
5109 #if BYTE_ORDER == LITTLE_ENDIAN
5110         uint32_t        els_response_payload_length;
5111         uint32_t        s_id:24,
5112                         sp:1,
5113                         :7;
5114         uint32_t        remote_id:24,
5115                         :8;
5116         uint32_t        xri_tag:16,
5117                         context_tag:16;
5118         uint32_t        :2,
5119                         ct:2,
5120                         :4,
5121                         command:8,
5122                         class:3,
5123                         :1,
5124                         pu:2,
5125                         :2,
5126                         timer:8;
5127         uint32_t        abort_tag;
5128         uint32_t        request_tag:16,
5129                         ox_id:16;
5130         uint32_t        ebde_cnt:4,
5131                         :3,
5132                         len_loc:2,
5133                         qosd:1,
5134                         :1,
5135                         xbl:1,
5136                         hlm:1,
5137                         iod:1,
5138                         dbde:1,
5139                         wqes:1,
5140                         pri:3,
5141                         pv:1,
5142                         eat:1,
5143                         xc:1,
5144                         :1,
5145                         ccpe:1,
5146                         ccp:8;
5147         uint32_t        cmd_type:4,
5148                         :3,
5149                         wqec:1,
5150                         :8,
5151                         cq_id:16;
5152         uint32_t        temporary_rpi:16,
5153                         :16;
5154         uint32_t        rsvd13;
5155         uint32_t        rsvd14;
5156         uint32_t        rsvd15;
5157 #else
5158 #error big endian version not defined
5159 #endif
5160 } sli4_xmit_els_rsp64_wqe_t;
5161
5162 /**
5163  * @brief Asynchronouse Event: Link State ACQE.
5164  */
5165 typedef struct sli4_link_state_s {
5166 #if BYTE_ORDER == LITTLE_ENDIAN
5167         uint32_t        link_number:6,
5168                         link_type:2,
5169                         port_link_status:8,
5170                         port_duplex:8,
5171                         port_speed:8;
5172         uint32_t        port_fault:8,
5173                         :8,
5174                         logical_link_speed:16;
5175         uint32_t        event_tag;
5176         uint32_t        :8,
5177                         event_code:8,
5178                         event_type:8,   /** values are protocol specific */
5179                         :6,
5180                         ae:1,           /** async event - this is an ACQE */
5181                         val:1;          /** valid - contents of CQE are valid */
5182 #else
5183 #error big endian version not defined
5184 #endif
5185 } sli4_link_state_t;
5186
5187 #define SLI4_LINK_ATTN_TYPE_LINK_UP             0x01
5188 #define SLI4_LINK_ATTN_TYPE_LINK_DOWN           0x02
5189 #define SLI4_LINK_ATTN_TYPE_NO_HARD_ALPA        0x03
5190
5191 #define SLI4_LINK_ATTN_P2P                      0x01
5192 #define SLI4_LINK_ATTN_FC_AL                    0x02
5193 #define SLI4_LINK_ATTN_INTERNAL_LOOPBACK        0x03
5194 #define SLI4_LINK_ATTN_SERDES_LOOPBACK          0x04
5195
5196 #define SLI4_LINK_ATTN_1G                       0x01
5197 #define SLI4_LINK_ATTN_2G                       0x02
5198 #define SLI4_LINK_ATTN_4G                       0x04
5199 #define SLI4_LINK_ATTN_8G                       0x08
5200 #define SLI4_LINK_ATTN_10G                      0x0a
5201 #define SLI4_LINK_ATTN_16G                      0x10
5202
5203 #define SLI4_LINK_TYPE_ETHERNET                 0x0
5204 #define SLI4_LINK_TYPE_FC                       0x1
5205
5206 /**
5207  * @brief Asynchronouse Event: FC Link Attention Event.
5208  */
5209 typedef struct sli4_link_attention_s {
5210 #if BYTE_ORDER == LITTLE_ENDIAN
5211         uint32_t        link_number:8,
5212                         attn_type:8,
5213                         topology:8,
5214                         port_speed:8;
5215         uint32_t        port_fault:8,
5216                         shared_link_status:8,
5217                         logical_link_speed:16;
5218         uint32_t        event_tag;
5219         uint32_t        :8,
5220                         event_code:8,
5221                         event_type:8,   /** values are protocol specific */
5222                         :6,
5223                         ae:1,           /** async event - this is an ACQE */
5224                         val:1;          /** valid - contents of CQE are valid */
5225 #else
5226 #error big endian version not defined
5227 #endif
5228 } sli4_link_attention_t;
5229
5230 /**
5231  * @brief FC/FCoE event types.
5232  */
5233 #define SLI4_LINK_STATE_PHYSICAL                0x00
5234 #define SLI4_LINK_STATE_LOGICAL                 0x01
5235
5236 #define SLI4_FCOE_FIP_FCF_DISCOVERED            0x01
5237 #define SLI4_FCOE_FIP_FCF_TABLE_FULL            0x02
5238 #define SLI4_FCOE_FIP_FCF_DEAD                  0x03
5239 #define SLI4_FCOE_FIP_FCF_CLEAR_VLINK           0x04
5240 #define SLI4_FCOE_FIP_FCF_MODIFIED              0x05
5241
5242 #define SLI4_GRP5_QOS_SPEED                     0x01
5243
5244 #define SLI4_FC_EVENT_LINK_ATTENTION            0x01
5245 #define SLI4_FC_EVENT_SHARED_LINK_ATTENTION     0x02
5246
5247 #define SLI4_PORT_SPEED_NO_LINK                 0x0
5248 #define SLI4_PORT_SPEED_10_MBPS                 0x1
5249 #define SLI4_PORT_SPEED_100_MBPS                0x2
5250 #define SLI4_PORT_SPEED_1_GBPS                  0x3
5251 #define SLI4_PORT_SPEED_10_GBPS                 0x4
5252
5253 #define SLI4_PORT_DUPLEX_NONE                   0x0
5254 #define SLI4_PORT_DUPLEX_HWF                    0x1
5255 #define SLI4_PORT_DUPLEX_FULL                   0x2
5256
5257 #define SLI4_PORT_LINK_STATUS_PHYSICAL_DOWN     0x0
5258 #define SLI4_PORT_LINK_STATUS_PHYSICAL_UP       0x1
5259 #define SLI4_PORT_LINK_STATUS_LOGICAL_DOWN      0x2
5260 #define SLI4_PORT_LINK_STATUS_LOGICAL_UP        0x3
5261
5262 /**
5263  * @brief Asynchronouse Event: FCoE/FIP ACQE.
5264  */
5265 typedef struct sli4_fcoe_fip_s {
5266 #if BYTE_ORDER == LITTLE_ENDIAN
5267         uint32_t        event_information;
5268         uint32_t        fcf_count:16,
5269                         fcoe_event_type:16;
5270         uint32_t        event_tag;
5271         uint32_t        :8,
5272                         event_code:8,
5273                         event_type:8,   /** values are protocol specific */
5274                         :6,
5275                         ae:1,           /** async event - this is an ACQE */
5276                         val:1;          /** valid - contents of CQE are valid */
5277 #else
5278 #error big endian version not defined
5279 #endif
5280 } sli4_fcoe_fip_t;
5281
5282 /**
5283  * @brief FC/FCoE WQ completion queue entry.
5284  */
5285 typedef struct sli4_fc_wcqe_s {
5286 #if BYTE_ORDER == LITTLE_ENDIAN
5287         uint32_t        hw_status:8,
5288                         status:8,
5289                         request_tag:16;
5290         uint32_t        wqe_specific_1;
5291         uint32_t        wqe_specific_2;
5292         uint32_t        :15,
5293                         qx:1,
5294                         code:8,
5295                         pri:3,
5296                         pv:1,
5297                         xb:1,
5298                         :2,
5299                         vld:1;
5300 #else
5301 #error big endian version not defined
5302 #endif
5303 } sli4_fc_wcqe_t;
5304
5305 /**
5306  * @brief FC/FCoE WQ consumed CQ queue entry.
5307  */
5308 typedef struct sli4_fc_wqec_s {
5309 #if BYTE_ORDER == LITTLE_ENDIAN
5310         uint32_t        :32;
5311         uint32_t        :32;
5312         uint32_t        wqe_index:16,
5313                         wq_id:16;
5314         uint32_t        :16,
5315                         code:8,
5316                         :7,
5317                         vld:1;
5318 #else
5319 #error big endian version not defined
5320 #endif
5321 } sli4_fc_wqec_t;
5322
5323 /**
5324  * @brief FC/FCoE Completion Status Codes.
5325  */
5326 #define SLI4_FC_WCQE_STATUS_SUCCESS             0x00
5327 #define SLI4_FC_WCQE_STATUS_FCP_RSP_FAILURE     0x01
5328 #define SLI4_FC_WCQE_STATUS_REMOTE_STOP         0x02
5329 #define SLI4_FC_WCQE_STATUS_LOCAL_REJECT        0x03
5330 #define SLI4_FC_WCQE_STATUS_NPORT_RJT           0x04
5331 #define SLI4_FC_WCQE_STATUS_FABRIC_RJT          0x05
5332 #define SLI4_FC_WCQE_STATUS_NPORT_BSY           0x06
5333 #define SLI4_FC_WCQE_STATUS_FABRIC_BSY          0x07
5334 #define SLI4_FC_WCQE_STATUS_LS_RJT              0x09
5335 #define SLI4_FC_WCQE_STATUS_CMD_REJECT          0x0b
5336 #define SLI4_FC_WCQE_STATUS_FCP_TGT_LENCHECK    0x0c
5337 #define SLI4_FC_WCQE_STATUS_RQ_BUF_LEN_EXCEEDED 0x11
5338 #define SLI4_FC_WCQE_STATUS_RQ_INSUFF_BUF_NEEDED 0x12
5339 #define SLI4_FC_WCQE_STATUS_RQ_INSUFF_FRM_DISC  0x13
5340 #define SLI4_FC_WCQE_STATUS_RQ_DMA_FAILURE      0x14
5341 #define SLI4_FC_WCQE_STATUS_FCP_RSP_TRUNCATE    0x15
5342 #define SLI4_FC_WCQE_STATUS_DI_ERROR            0x16
5343 #define SLI4_FC_WCQE_STATUS_BA_RJT              0x17
5344 #define SLI4_FC_WCQE_STATUS_RQ_INSUFF_XRI_NEEDED 0x18
5345 #define SLI4_FC_WCQE_STATUS_RQ_INSUFF_XRI_DISC  0x19
5346 #define SLI4_FC_WCQE_STATUS_RX_ERROR_DETECT     0x1a
5347 #define SLI4_FC_WCQE_STATUS_RX_ABORT_REQUEST    0x1b
5348
5349 /* driver generated status codes; better not overlap with chip's status codes! */
5350 #define SLI4_FC_WCQE_STATUS_TARGET_WQE_TIMEOUT  0xff
5351 #define SLI4_FC_WCQE_STATUS_SHUTDOWN            0xfe
5352 #define SLI4_FC_WCQE_STATUS_DISPATCH_ERROR      0xfd
5353
5354 /**
5355  * @brief DI_ERROR Extended Status
5356  */
5357 #define SLI4_FC_DI_ERROR_GE     (1 << 0) /* Guard Error */
5358 #define SLI4_FC_DI_ERROR_AE     (1 << 1) /* Application Tag Error */
5359 #define SLI4_FC_DI_ERROR_RE     (1 << 2) /* Reference Tag Error */
5360 #define SLI4_FC_DI_ERROR_TDPV   (1 << 3) /* Total Data Placed Valid */
5361 #define SLI4_FC_DI_ERROR_UDB    (1 << 4) /* Uninitialized DIF Block */
5362 #define SLI4_FC_DI_ERROR_EDIR   (1 << 5) /* Error direction */
5363
5364 /**
5365  * @brief Local Reject Reason Codes.
5366  */
5367 #define SLI4_FC_LOCAL_REJECT_MISSING_CONTINUE   0x01
5368 #define SLI4_FC_LOCAL_REJECT_SEQUENCE_TIMEOUT   0x02
5369 #define SLI4_FC_LOCAL_REJECT_INTERNAL_ERROR     0x03
5370 #define SLI4_FC_LOCAL_REJECT_INVALID_RPI        0x04
5371 #define SLI4_FC_LOCAL_REJECT_NO_XRI             0x05
5372 #define SLI4_FC_LOCAL_REJECT_ILLEGAL_COMMAND    0x06
5373 #define SLI4_FC_LOCAL_REJECT_XCHG_DROPPED       0x07
5374 #define SLI4_FC_LOCAL_REJECT_ILLEGAL_FIELD      0x08
5375 #define SLI4_FC_LOCAL_REJECT_NO_ABORT_MATCH     0x0c
5376 #define SLI4_FC_LOCAL_REJECT_TX_DMA_FAILED      0x0d
5377 #define SLI4_FC_LOCAL_REJECT_RX_DMA_FAILED      0x0e
5378 #define SLI4_FC_LOCAL_REJECT_ILLEGAL_FRAME      0x0f
5379 #define SLI4_FC_LOCAL_REJECT_NO_RESOURCES       0x11
5380 #define SLI4_FC_LOCAL_REJECT_FCP_CONF_FAILURE   0x12
5381 #define SLI4_FC_LOCAL_REJECT_ILLEGAL_LENGTH     0x13
5382 #define SLI4_FC_LOCAL_REJECT_UNSUPPORTED_FEATURE 0x14
5383 #define SLI4_FC_LOCAL_REJECT_ABORT_IN_PROGRESS  0x15
5384 #define SLI4_FC_LOCAL_REJECT_ABORT_REQUESTED    0x16
5385 #define SLI4_FC_LOCAL_REJECT_RCV_BUFFER_TIMEOUT 0x17
5386 #define SLI4_FC_LOCAL_REJECT_LOOP_OPEN_FAILURE  0x18
5387 #define SLI4_FC_LOCAL_REJECT_LINK_DOWN          0x1a
5388 #define SLI4_FC_LOCAL_REJECT_CORRUPTED_DATA     0x1b
5389 #define SLI4_FC_LOCAL_REJECT_CORRUPTED_RPI      0x1c
5390 #define SLI4_FC_LOCAL_REJECT_OUT_OF_ORDER_DATA  0x1d
5391 #define SLI4_FC_LOCAL_REJECT_OUT_OF_ORDER_ACK   0x1e
5392 #define SLI4_FC_LOCAL_REJECT_DUP_FRAME          0x1f
5393 #define SLI4_FC_LOCAL_REJECT_LINK_CONTROL_FRAME 0x20
5394 #define SLI4_FC_LOCAL_REJECT_BAD_HOST_ADDRESS   0x21
5395 #define SLI4_FC_LOCAL_REJECT_MISSING_HDR_BUFFER 0x23
5396 #define SLI4_FC_LOCAL_REJECT_MSEQ_CHAIN_CORRUPTED 0x24
5397 #define SLI4_FC_LOCAL_REJECT_ABORTMULT_REQUESTED 0x25
5398 #define SLI4_FC_LOCAL_REJECT_BUFFER_SHORTAGE    0x28
5399 #define SLI4_FC_LOCAL_REJECT_RCV_XRIBUF_WAITING 0x29
5400 #define SLI4_FC_LOCAL_REJECT_INVALID_VPI        0x2e
5401 #define SLI4_FC_LOCAL_REJECT_MISSING_XRIBUF     0x30
5402 #define SLI4_FC_LOCAL_REJECT_INVALID_RELOFFSET  0x40
5403 #define SLI4_FC_LOCAL_REJECT_MISSING_RELOFFSET  0x41
5404 #define SLI4_FC_LOCAL_REJECT_INSUFF_BUFFERSPACE 0x42
5405 #define SLI4_FC_LOCAL_REJECT_MISSING_SI         0x43
5406 #define SLI4_FC_LOCAL_REJECT_MISSING_ES         0x44
5407 #define SLI4_FC_LOCAL_REJECT_INCOMPLETE_XFER    0x45
5408 #define SLI4_FC_LOCAL_REJECT_SLER_FAILURE       0x46
5409 #define SLI4_FC_LOCAL_REJECT_SLER_CMD_RCV_FAILURE 0x47
5410 #define SLI4_FC_LOCAL_REJECT_SLER_REC_RJT_ERR   0x48
5411 #define SLI4_FC_LOCAL_REJECT_SLER_REC_SRR_RETRY_ERR 0x49
5412 #define SLI4_FC_LOCAL_REJECT_SLER_SRR_RJT_ERR   0x4a
5413 #define SLI4_FC_LOCAL_REJECT_SLER_RRQ_RJT_ERR   0x4c
5414 #define SLI4_FC_LOCAL_REJECT_SLER_RRQ_RETRY_ERR 0x4d
5415 #define SLI4_FC_LOCAL_REJECT_SLER_ABTS_ERR      0x4e
5416
5417 typedef struct sli4_fc_async_rcqe_s {
5418 #if BYTE_ORDER == LITTLE_ENDIAN
5419         uint32_t        :8,
5420                         status:8,
5421                         rq_element_index:12,
5422                         :4;
5423         uint32_t        rsvd1;
5424         uint32_t        fcfi:6,
5425                         rq_id:10,
5426                         payload_data_placement_length:16;
5427         uint32_t        sof_byte:8,
5428                         eof_byte:8,
5429                         code:8,
5430                         header_data_placement_length:6,
5431                         :1,
5432                         vld:1;
5433 #else
5434 #error big endian version not defined
5435 #endif
5436 } sli4_fc_async_rcqe_t;
5437
5438 typedef struct sli4_fc_async_rcqe_v1_s {
5439 #if BYTE_ORDER == LITTLE_ENDIAN
5440         uint32_t        :8,
5441                         status:8,
5442                         rq_element_index:12,
5443                         :4;
5444         uint32_t        fcfi:6,
5445                         :26;
5446         uint32_t        rq_id:16,
5447                         payload_data_placement_length:16;
5448         uint32_t        sof_byte:8,
5449                         eof_byte:8,
5450                         code:8,
5451                         header_data_placement_length:6,
5452                         :1,
5453                         vld:1;
5454 #else
5455 #error big endian version not defined
5456 #endif
5457 } sli4_fc_async_rcqe_v1_t;
5458
5459 #define SLI4_FC_ASYNC_RQ_SUCCESS                0x10
5460 #define SLI4_FC_ASYNC_RQ_BUF_LEN_EXCEEDED       0x11
5461 #define SLI4_FC_ASYNC_RQ_INSUFF_BUF_NEEDED      0x12
5462 #define SLI4_FC_ASYNC_RQ_INSUFF_BUF_FRM_DISC    0x13
5463 #define SLI4_FC_ASYNC_RQ_DMA_FAILURE            0x14
5464
5465 typedef struct sli4_fc_coalescing_rcqe_s {
5466 #if BYTE_ORDER == LITTLE_ENDIAN
5467         uint32_t        :8,
5468                         status:8,
5469                         rq_element_index:12,
5470                         :4;
5471         uint32_t        rsvd1;
5472         uint32_t        rq_id:16,
5473                         sequence_reporting_placement_length:16;
5474         uint32_t        :16,
5475                         code:8,
5476                         :7,
5477                         vld:1;
5478 #else
5479 #error big endian version not defined
5480 #endif
5481 } sli4_fc_coalescing_rcqe_t;
5482
5483 #define SLI4_FC_COALESCE_RQ_SUCCESS             0x10
5484 #define SLI4_FC_COALESCE_RQ_INSUFF_XRI_NEEDED   0x18
5485
5486 typedef struct sli4_fc_optimized_write_cmd_cqe_s {
5487 #if BYTE_ORDER == LITTLE_ENDIAN
5488         uint32_t        :8,
5489                         status:8,
5490                         rq_element_index:15,
5491                         iv:1;
5492         uint32_t        fcfi:6,
5493                         :8,
5494                         oox:1,
5495                         agxr:1,
5496                         xri:16;
5497         uint32_t        rq_id:16,
5498                         payload_data_placement_length:16;
5499         uint32_t        rpi:16,
5500                         code:8,
5501                         header_data_placement_length:6,
5502                         :1,
5503                         vld:1;
5504 #else
5505 #error big endian version not defined
5506 #endif
5507 } sli4_fc_optimized_write_cmd_cqe_t;
5508
5509 typedef struct sli4_fc_optimized_write_data_cqe_s {
5510 #if BYTE_ORDER == LITTLE_ENDIAN
5511         uint32_t        hw_status:8,
5512                         status:8,
5513                         xri:16;
5514         uint32_t        total_data_placed;
5515         uint32_t        extended_status;
5516         uint32_t        :16,
5517                         code:8,
5518                         pri:3,
5519                         pv:1,
5520                         xb:1,
5521                         rha:1,
5522                         :1,
5523                         vld:1;
5524 #else
5525 #error big endian version not defined
5526 #endif
5527 } sli4_fc_optimized_write_data_cqe_t;
5528
5529 typedef struct sli4_fc_xri_aborted_cqe_s {
5530 #if BYTE_ORDER == LITTLE_ENDIAN
5531         uint32_t        :8,
5532                         status:8,
5533                         :16;
5534         uint32_t        extended_status;
5535         uint32_t        xri:16,
5536                         remote_xid:16;
5537         uint32_t        :16,
5538                         code:8,
5539                         xr:1,
5540                         :3,
5541                         eo:1,
5542                         br:1,
5543                         ia:1,
5544                         vld:1;
5545 #else
5546 #error big endian version not defined
5547 #endif
5548 } sli4_fc_xri_aborted_cqe_t;
5549
5550 /**
5551  * Code definitions applicable to all FC/FCoE CQE types.
5552  */
5553 #define SLI4_CQE_CODE_OFFSET            14
5554
5555 #define SLI4_CQE_CODE_WORK_REQUEST_COMPLETION   0x01
5556 #define SLI4_CQE_CODE_RELEASE_WQE               0x02
5557 #define SLI4_CQE_CODE_RQ_ASYNC                  0x04
5558 #define SLI4_CQE_CODE_XRI_ABORTED               0x05
5559 #define SLI4_CQE_CODE_RQ_COALESCING             0x06
5560 #define SLI4_CQE_CODE_RQ_CONSUMPTION            0x07
5561 #define SLI4_CQE_CODE_MEASUREMENT_REPORTING     0x08
5562 #define SLI4_CQE_CODE_RQ_ASYNC_V1               0x09
5563 #define SLI4_CQE_CODE_OPTIMIZED_WRITE_CMD       0x0B
5564 #define SLI4_CQE_CODE_OPTIMIZED_WRITE_DATA      0x0C
5565
5566 extern int32_t sli_fc_process_link_state(sli4_t *, void *);
5567 extern int32_t sli_fc_process_link_attention(sli4_t *, void *);
5568 extern int32_t sli_fc_cqe_parse(sli4_t *, sli4_queue_t *, uint8_t *, sli4_qentry_e *, uint16_t *);
5569 extern uint32_t sli_fc_response_length(sli4_t *, uint8_t *);
5570 extern uint32_t sli_fc_io_length(sli4_t *, uint8_t *);
5571 extern int32_t sli_fc_els_did(sli4_t *, uint8_t *, uint32_t *);
5572 extern uint32_t sli_fc_ext_status(sli4_t *, uint8_t *);
5573 extern int32_t sli_fc_rqe_rqid_and_index(sli4_t *, uint8_t *, uint16_t *, uint32_t *);
5574 extern int32_t sli_fc_process_fcoe(sli4_t *, void *);
5575 extern int32_t sli_cmd_fcoe_wq_create(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t);
5576 extern int32_t sli_cmd_fcoe_wq_create_v1(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t);
5577 extern int32_t sli_cmd_fcoe_wq_destroy(sli4_t *, void *, size_t, uint16_t);
5578 extern int32_t sli_cmd_fcoe_post_sgl_pages(sli4_t *, void *, size_t, uint16_t, uint32_t, ocs_dma_t **, ocs_dma_t **,
5579 ocs_dma_t *);
5580 extern int32_t sli_cmd_fcoe_rq_create(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t, uint16_t);
5581 extern int32_t sli_cmd_fcoe_rq_create_v1(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t, uint16_t);
5582 extern int32_t sli_cmd_fcoe_rq_destroy(sli4_t *, void *, size_t, uint16_t);
5583 extern int32_t sli_cmd_fcoe_read_fcf_table(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t);
5584 extern int32_t sli_cmd_fcoe_post_hdr_templates(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, ocs_dma_t *);
5585 extern int32_t sli_cmd_fcoe_rediscover_fcf(sli4_t *, void *, size_t, uint16_t);
5586 extern int32_t sli_fc_rq_alloc(sli4_t *, sli4_queue_t *, uint32_t, uint32_t, sli4_queue_t *, uint16_t, uint8_t);
5587 extern int32_t sli_fc_rq_set_alloc(sli4_t *, uint32_t, sli4_queue_t *[], uint32_t, uint32_t, uint32_t, uint32_t, uint16_t);
5588 extern uint32_t sli_fc_get_rpi_requirements(sli4_t *, uint32_t);
5589 extern int32_t sli_abort_wqe(sli4_t *, void *, size_t, sli4_abort_type_e, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t);
5590
5591 extern int32_t sli_els_request64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint8_t, uint32_t, uint32_t, uint8_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *);
5592 extern int32_t sli_fcp_iread64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t);
5593 extern int32_t sli_fcp_iwrite64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t);
5594 extern int32_t sli_fcp_icmnd64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint8_t);
5595
5596 extern int32_t sli_fcp_treceive64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint32_t, uint8_t, uint8_t, uint8_t, uint32_t);
5597 extern int32_t sli_fcp_trsp64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint32_t, uint8_t, uint8_t, uint32_t);
5598 extern int32_t sli_fcp_tsend64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint32_t, uint8_t, uint8_t, uint8_t, uint32_t);
5599 extern int32_t sli_fcp_cont_treceive64_wqe(sli4_t *, void*, size_t, ocs_dma_t *, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint32_t, uint8_t, uint8_t, uint8_t, uint32_t);
5600 extern int32_t sli_gen_request64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t,uint8_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t);
5601 extern int32_t sli_send_frame_wqe(sli4_t *sli4, void *buf, size_t size, uint8_t sof, uint8_t eof, uint32_t *hdr,
5602                                   ocs_dma_t *payload, uint32_t req_len, uint8_t timeout,
5603                                   uint16_t xri, uint16_t req_tag);
5604 extern int32_t sli_xmit_sequence64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint8_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t);
5605 extern int32_t sli_xmit_bcast64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint8_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t);
5606 extern int32_t sli_xmit_bls_rsp64_wqe(sli4_t *, void *, size_t, sli_bls_payload_t *, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint32_t);
5607 extern int32_t sli_xmit_els_rsp64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint32_t, uint32_t);
5608 extern int32_t sli_requeue_xri_wqe(sli4_t *, void *, size_t, uint16_t, uint16_t, uint16_t);
5609 extern void sli4_cmd_lowlevel_set_watchdog(sli4_t *sli4, void *buf, size_t size, uint16_t timeout);
5610 extern bool sli_persist_topology_enabled(sli4_t *sli4);
5611
5612
5613 /**
5614  * @ingroup sli_fc
5615  * @brief Retrieve the received header and payload length.
5616  *
5617  * @param sli4 SLI context.
5618  * @param cqe Pointer to the CQ entry.
5619  * @param len_hdr Pointer where the header length is written.
5620  * @param len_data Pointer where the payload length is written.
5621  *
5622  * @return Returns 0 on success, or a non-zero value on failure.
5623  */
5624 static inline int32_t
5625 sli_fc_rqe_length(sli4_t *sli4, void *cqe, uint32_t *len_hdr, uint32_t *len_data)
5626 {
5627         sli4_fc_async_rcqe_t    *rcqe = cqe;
5628
5629         *len_hdr = *len_data = 0;
5630
5631         if (SLI4_FC_ASYNC_RQ_SUCCESS == rcqe->status) {
5632                 *len_hdr  = rcqe->header_data_placement_length;
5633                 *len_data = rcqe->payload_data_placement_length;
5634                 return 0;
5635         } else {
5636                 return -1;
5637         }
5638 }
5639
5640 /**
5641  * @ingroup sli_fc
5642  * @brief Retrieve the received FCFI.
5643  *
5644  * @param sli4 SLI context.
5645  * @param cqe Pointer to the CQ entry.
5646  *
5647  * @return Returns the FCFI in the CQE. or UINT8_MAX if invalid CQE code.
5648  */
5649 static inline uint8_t
5650 sli_fc_rqe_fcfi(sli4_t *sli4, void *cqe)
5651 {
5652         uint8_t code = ((uint8_t*)cqe)[SLI4_CQE_CODE_OFFSET];
5653         uint8_t fcfi = UINT8_MAX;
5654
5655         switch(code) {
5656         case SLI4_CQE_CODE_RQ_ASYNC: {
5657                 sli4_fc_async_rcqe_t *rcqe = cqe;
5658                 fcfi = rcqe->fcfi;
5659                 break;
5660         }
5661         case SLI4_CQE_CODE_RQ_ASYNC_V1: {
5662                 sli4_fc_async_rcqe_v1_t *rcqev1 = cqe;
5663                 fcfi = rcqev1->fcfi;
5664                 break;
5665         }
5666         case SLI4_CQE_CODE_OPTIMIZED_WRITE_CMD: {
5667                 sli4_fc_optimized_write_cmd_cqe_t *opt_wr = cqe;
5668                 fcfi = opt_wr->fcfi;
5669                 break;
5670         }
5671         }
5672
5673         return fcfi;
5674 }
5675
5676 extern const char *sli_fc_get_status_string(uint32_t status);
5677
5678 #endif /* !_SLI4_H */