2 * Copyright (c) 2002-2004 M. Warner Losh.
3 * Copyright (c) 2000-2001 Jonathan Chen.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * Copyright (c) 1998, 1999 and 2000
31 * HAYAKAWA Koichi. All rights reserved.
33 * Redistribution and use in source and binary forms, with or without
34 * modification, are permitted provided that the following conditions
36 * 1. Redistributions of source code must retain the above copyright
37 * notice, this list of conditions and the following disclaimer.
38 * 2. Redistributions in binary form must reproduce the above copyright
39 * notice, this list of conditions and the following disclaimer in the
40 * documentation and/or other materials provided with the distribution.
41 * 3. All advertising materials mentioning features or use of this software
42 * must display the following acknowledgement:
43 * This product includes software developed by HAYAKAWA Koichi.
44 * 4. The name of the author may not be used to endorse or promote products
45 * derived from this software without specific prior written permission.
47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
50 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
60 * Driver for PCI to CardBus Bridge chips
64 * http://www-s.ti.com/cgi-bin/sc/generic2.cgi?family=PCI+CARDBUS+CONTROLLERS
66 * Written by Jonathan Chen <jon@freebsd.org>
67 * The author would like to acknowledge:
68 * * HAYAKAWA Koichi: Author of the NetBSD code for the same thing
69 * * Warner Losh: Newbus/newcard guru and author of the pccard side of things
70 * * YAMAMOTO Shigeru: Author of another FreeBSD cardbus driver
71 * * David Cross: Author of the initial ugly hack for a specific cardbus card
74 #include <sys/cdefs.h>
75 __FBSDID("$FreeBSD$");
77 #include <sys/param.h>
78 #include <sys/systm.h>
80 #include <sys/condvar.h>
81 #include <sys/errno.h>
82 #include <sys/kernel.h>
84 #include <sys/malloc.h>
85 #include <sys/mutex.h>
86 #include <sys/sysctl.h>
87 #include <sys/kthread.h>
89 #include <machine/bus.h>
91 #include <machine/resource.h>
92 #include <sys/module.h>
94 #include <dev/pci/pcireg.h>
95 #include <dev/pci/pcivar.h>
97 #include <dev/pccard/pccardreg.h>
98 #include <dev/pccard/pccardvar.h>
100 #include <dev/exca/excareg.h>
101 #include <dev/exca/excavar.h>
103 #include <dev/pccbb/pccbbreg.h>
104 #include <dev/pccbb/pccbbvar.h>
106 #include "power_if.h"
110 #define DPRINTF(x) do { if (cbb_debug) printf x; } while (0)
111 #define DEVPRINTF(x) do { if (cbb_debug) device_printf x; } while (0)
113 #define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \
114 pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE)
115 #define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \
116 pci_write_config(DEV, REG, ( \
117 pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE)
119 static void cbb_chipinit(struct cbb_softc *sc);
120 static void cbb_pci_intr(void *arg);
122 static struct yenta_chipinfo {
127 /* Texas Instruments chips */
128 {PCIC_ID_TI1031, "TI1031 PCI-PC Card Bridge", CB_TI113X},
129 {PCIC_ID_TI1130, "TI1130 PCI-CardBus Bridge", CB_TI113X},
130 {PCIC_ID_TI1131, "TI1131 PCI-CardBus Bridge", CB_TI113X},
132 {PCIC_ID_TI1210, "TI1210 PCI-CardBus Bridge", CB_TI12XX},
133 {PCIC_ID_TI1211, "TI1211 PCI-CardBus Bridge", CB_TI12XX},
134 {PCIC_ID_TI1220, "TI1220 PCI-CardBus Bridge", CB_TI12XX},
135 {PCIC_ID_TI1221, "TI1221 PCI-CardBus Bridge", CB_TI12XX},
136 {PCIC_ID_TI1225, "TI1225 PCI-CardBus Bridge", CB_TI12XX},
137 {PCIC_ID_TI1250, "TI1250 PCI-CardBus Bridge", CB_TI125X},
138 {PCIC_ID_TI1251, "TI1251 PCI-CardBus Bridge", CB_TI125X},
139 {PCIC_ID_TI1251B,"TI1251B PCI-CardBus Bridge",CB_TI125X},
140 {PCIC_ID_TI1260, "TI1260 PCI-CardBus Bridge", CB_TI12XX},
141 {PCIC_ID_TI1260B,"TI1260B PCI-CardBus Bridge",CB_TI12XX},
142 {PCIC_ID_TI1410, "TI1410 PCI-CardBus Bridge", CB_TI12XX},
143 {PCIC_ID_TI1420, "TI1420 PCI-CardBus Bridge", CB_TI12XX},
144 {PCIC_ID_TI1421, "TI1421 PCI-CardBus Bridge", CB_TI12XX},
145 {PCIC_ID_TI1450, "TI1450 PCI-CardBus Bridge", CB_TI125X}, /*SIC!*/
146 {PCIC_ID_TI1451, "TI1451 PCI-CardBus Bridge", CB_TI12XX},
147 {PCIC_ID_TI1510, "TI1510 PCI-CardBus Bridge", CB_TI12XX},
148 {PCIC_ID_TI1520, "TI1520 PCI-CardBus Bridge", CB_TI12XX},
149 {PCIC_ID_TI4410, "TI4410 PCI-CardBus Bridge", CB_TI12XX},
150 {PCIC_ID_TI4450, "TI4450 PCI-CardBus Bridge", CB_TI12XX},
151 {PCIC_ID_TI4451, "TI4451 PCI-CardBus Bridge", CB_TI12XX},
152 {PCIC_ID_TI4510, "TI4510 PCI-CardBus Bridge", CB_TI12XX},
153 {PCIC_ID_TI6411, "TI6411 PCI-CardBus Bridge", CB_TI12XX},
154 {PCIC_ID_TI6420, "TI6420 PCI-CardBus Bridge", CB_TI12XX},
155 {PCIC_ID_TI6420SC, "TI6420 PCI-CardBus Bridge", CB_TI12XX},
156 {PCIC_ID_TI7410, "TI7410 PCI-CardBus Bridge", CB_TI12XX},
157 {PCIC_ID_TI7510, "TI7510 PCI-CardBus Bridge", CB_TI12XX},
158 {PCIC_ID_TI7610, "TI7610 PCI-CardBus Bridge", CB_TI12XX},
159 {PCIC_ID_TI7610M, "TI7610 PCI-CardBus Bridge", CB_TI12XX},
160 {PCIC_ID_TI7610SD, "TI7610 PCI-CardBus Bridge", CB_TI12XX},
161 {PCIC_ID_TI7610MS, "TI7610 PCI-CardBus Bridge", CB_TI12XX},
164 {PCIC_ID_ENE_CB710, "ENE CB710 PCI-CardBus Bridge", CB_TI12XX},
165 {PCIC_ID_ENE_CB720, "ENE CB720 PCI-CardBus Bridge", CB_TI12XX},
166 {PCIC_ID_ENE_CB1211, "ENE CB1211 PCI-CardBus Bridge", CB_TI12XX},
167 {PCIC_ID_ENE_CB1225, "ENE CB1225 PCI-CardBus Bridge", CB_TI12XX},
168 {PCIC_ID_ENE_CB1410, "ENE CB1410 PCI-CardBus Bridge", CB_TI12XX},
169 {PCIC_ID_ENE_CB1420, "ENE CB1420 PCI-CardBus Bridge", CB_TI12XX},
172 {PCIC_ID_RICOH_RL5C465, "RF5C465 PCI-CardBus Bridge", CB_RF5C46X},
173 {PCIC_ID_RICOH_RL5C466, "RF5C466 PCI-CardBus Bridge", CB_RF5C46X},
174 {PCIC_ID_RICOH_RL5C475, "RF5C475 PCI-CardBus Bridge", CB_RF5C47X},
175 {PCIC_ID_RICOH_RL5C476, "RF5C476 PCI-CardBus Bridge", CB_RF5C47X},
176 {PCIC_ID_RICOH_RL5C477, "RF5C477 PCI-CardBus Bridge", CB_RF5C47X},
177 {PCIC_ID_RICOH_RL5C478, "RF5C478 PCI-CardBus Bridge", CB_RF5C47X},
179 /* Toshiba products */
180 {PCIC_ID_TOPIC95, "ToPIC95 PCI-CardBus Bridge", CB_TOPIC95},
181 {PCIC_ID_TOPIC95B, "ToPIC95B PCI-CardBus Bridge", CB_TOPIC95},
182 {PCIC_ID_TOPIC97, "ToPIC97 PCI-CardBus Bridge", CB_TOPIC97},
183 {PCIC_ID_TOPIC100, "ToPIC100 PCI-CardBus Bridge", CB_TOPIC97},
186 {PCIC_ID_CLPD6832, "CLPD6832 PCI-CardBus Bridge", CB_CIRRUS},
187 {PCIC_ID_CLPD6833, "CLPD6833 PCI-CardBus Bridge", CB_CIRRUS},
188 {PCIC_ID_CLPD6834, "CLPD6834 PCI-CardBus Bridge", CB_CIRRUS},
191 {PCIC_ID_OZ6832, "O2Micro OZ6832/6833 PCI-CardBus Bridge", CB_O2MICRO},
192 {PCIC_ID_OZ6860, "O2Micro OZ6836/6860 PCI-CardBus Bridge", CB_O2MICRO},
193 {PCIC_ID_OZ6872, "O2Micro OZ6812/6872 PCI-CardBus Bridge", CB_O2MICRO},
194 {PCIC_ID_OZ6912, "O2Micro OZ6912/6972 PCI-CardBus Bridge", CB_O2MICRO},
195 {PCIC_ID_OZ6922, "O2Micro OZ6922 PCI-CardBus Bridge", CB_O2MICRO},
196 {PCIC_ID_OZ6933, "O2Micro OZ6933 PCI-CardBus Bridge", CB_O2MICRO},
197 {PCIC_ID_OZ711E1, "O2Micro OZ711E1 PCI-CardBus Bridge", CB_O2MICRO},
198 {PCIC_ID_OZ711EC1, "O2Micro OZ711EC1/M1 PCI-CardBus Bridge", CB_O2MICRO},
199 {PCIC_ID_OZ711E2, "O2Micro OZ711E2 PCI-CardBus Bridge", CB_O2MICRO},
200 {PCIC_ID_OZ711M1, "O2Micro OZ711M1 PCI-CardBus Bridge", CB_O2MICRO},
201 {PCIC_ID_OZ711M2, "O2Micro OZ711M2 PCI-CardBus Bridge", CB_O2MICRO},
202 {PCIC_ID_OZ711M3, "O2Micro OZ711M3 PCI-CardBus Bridge", CB_O2MICRO},
205 {PCIC_ID_SMC_34C90, "SMC 34C90 PCI-CardBus Bridge", CB_CIRRUS},
208 {0 /* null id */, "unknown", CB_UNKNOWN},
211 /************************************************************************/
213 /************************************************************************/
216 cbb_chipset(uint32_t pci_id, const char **namep)
218 struct yenta_chipinfo *ycp;
220 for (ycp = yc_chipsets; ycp->yc_id != 0 && pci_id != ycp->yc_id; ++ycp)
223 *namep = ycp->yc_name;
224 return (ycp->yc_chiptype);
228 cbb_pci_probe(device_t brdev)
236 * Do we know that we support the chipset? If so, then we
239 if (cbb_chipset(pci_get_devid(brdev), &name) != CB_UNKNOWN) {
240 device_set_desc(brdev, name);
241 return (BUS_PROBE_DEFAULT);
245 * We do support generic CardBus bridges. All that we've seen
246 * to date have progif 0 (the Yenta spec, and successors mandate
249 baseclass = pci_get_class(brdev);
250 subclass = pci_get_subclass(brdev);
251 progif = pci_get_progif(brdev);
252 if (baseclass == PCIC_BRIDGE &&
253 subclass == PCIS_BRIDGE_CARDBUS && progif == 0) {
254 device_set_desc(brdev, "PCI-CardBus Bridge");
255 return (BUS_PROBE_GENERIC);
261 * Still need this because the pci code only does power for type 0
265 cbb_powerstate_d0(device_t dev)
267 u_int32_t membase, irq;
269 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
270 /* Save important PCI config data. */
271 membase = pci_read_config(dev, CBBR_SOCKBASE, 4);
272 irq = pci_read_config(dev, PCIR_INTLINE, 4);
274 /* Reset the power state. */
275 device_printf(dev, "chip is in D%d power mode "
276 "-- setting to D0\n", pci_get_powerstate(dev));
278 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
280 /* Restore PCI config data. */
281 pci_write_config(dev, CBBR_SOCKBASE, membase, 4);
282 pci_write_config(dev, PCIR_INTLINE, irq, 4);
287 * Print out the config space
290 cbb_print_config(device_t dev)
294 device_printf(dev, "PCI Configuration space:");
295 for (i = 0; i < 256; i += 4) {
297 printf("\n 0x%02x: ", i);
298 printf("0x%08x ", pci_read_config(dev, i, 4));
304 cbb_pci_attach(device_t brdev)
306 static int curr_bus_number = 2; /* XXX EVILE BAD (see below) */
307 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev);
308 struct sysctl_ctx_list *sctx;
309 struct sysctl_oid *soid;
314 parent = device_get_parent(brdev);
315 mtx_init(&sc->mtx, device_get_nameunit(brdev), "cbb", MTX_DEF);
316 cv_init(&sc->cv, "cbb cv");
317 cv_init(&sc->powercv, "cbb cv");
318 sc->chipset = cbb_chipset(pci_get_devid(brdev), NULL);
321 sc->exca[0].pccarddev = NULL;
322 sc->domain = pci_get_domain(brdev);
323 sc->secbus = pci_read_config(brdev, PCIR_SECBUS_2, 1);
324 sc->subbus = pci_read_config(brdev, PCIR_SUBBUS_2, 1);
325 sc->pribus = pcib_get_bus(parent);
327 cbb_powerstate_d0(brdev);
330 sc->base_res = bus_alloc_resource_any(brdev, SYS_RES_MEMORY, &rid,
333 device_printf(brdev, "Could not map register memory\n");
334 mtx_destroy(&sc->mtx);
338 DEVPRINTF((brdev, "Found memory at %08lx\n",
339 rman_get_start(sc->base_res)));
342 sc->bst = rman_get_bustag(sc->base_res);
343 sc->bsh = rman_get_bushandle(sc->base_res);
344 exca_init(&sc->exca[0], brdev, sc->bst, sc->bsh, CBB_EXCA_OFFSET);
345 sc->exca[0].flags |= EXCA_HAS_MEMREG_WIN;
346 sc->exca[0].chipset = EXCA_CARDBUS;
347 sc->chipinit = cbb_chipinit;
351 sctx = device_get_sysctl_ctx(brdev);
352 soid = device_get_sysctl_tree(brdev);
353 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain",
354 CTLFLAG_RD, &sc->domain, 0, "Domain number");
355 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus",
356 CTLFLAG_RD, &sc->pribus, 0, "Primary bus number");
357 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus",
358 CTLFLAG_RD, &sc->secbus, 0, "Secondary bus number");
359 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus",
360 CTLFLAG_RD, &sc->subbus, 0, "Subordinate bus number");
362 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "memory",
363 CTLFLAG_RD, &sc->subbus, 0, "Memory window open");
364 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "premem",
365 CTLFLAG_RD, &sc->subbus, 0, "Prefetch memroy window open");
366 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "io1",
367 CTLFLAG_RD, &sc->subbus, 0, "io range 1 open");
368 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "io2",
369 CTLFLAG_RD, &sc->subbus, 0, "io range 2 open");
373 * This is a gross hack. We should be scanning the entire pci
374 * tree, assigning bus numbers in a way such that we (1) can
375 * reserve 1 extra bus just in case and (2) all sub busses
376 * are in an appropriate range.
378 DEVPRINTF((brdev, "Secondary bus is %d\n", sc->secbus));
379 pribus = pci_read_config(brdev, PCIR_PRIBUS_2, 1);
380 if (sc->secbus == 0 || sc->pribus != pribus) {
381 if (curr_bus_number <= sc->pribus)
382 curr_bus_number = sc->pribus + 1;
383 if (pribus != sc->pribus) {
384 DEVPRINTF((brdev, "Setting primary bus to %d\n",
386 pci_write_config(brdev, PCIR_PRIBUS_2, sc->pribus, 1);
388 sc->secbus = curr_bus_number++;
389 sc->subbus = curr_bus_number++;
390 DEVPRINTF((brdev, "Secondary bus set to %d subbus %d\n",
391 sc->secbus, sc->subbus));
392 pci_write_config(brdev, PCIR_SECBUS_2, sc->secbus, 1);
393 pci_write_config(brdev, PCIR_SUBBUS_2, sc->subbus, 1);
396 /* attach children */
397 sc->cbdev = device_add_child(brdev, "cardbus", -1);
398 if (sc->cbdev == NULL)
399 DEVPRINTF((brdev, "WARNING: cannot add cardbus bus.\n"));
400 else if (device_probe_and_attach(sc->cbdev) != 0)
401 DEVPRINTF((brdev, "WARNING: cannot attach cardbus bus!\n"));
403 sc->exca[0].pccarddev = device_add_child(brdev, "pccard", -1);
404 if (sc->exca[0].pccarddev == NULL)
405 DEVPRINTF((brdev, "WARNING: cannot add pccard bus.\n"));
406 else if (device_probe_and_attach(sc->exca[0].pccarddev) != 0)
407 DEVPRINTF((brdev, "WARNING: cannot attach pccard bus.\n"));
409 /* Map and establish the interrupt. */
411 sc->irq_res = bus_alloc_resource_any(brdev, SYS_RES_IRQ, &rid,
412 RF_SHAREABLE | RF_ACTIVE);
413 if (sc->irq_res == NULL) {
414 device_printf(brdev, "Unable to map IRQ...\n");
418 if (bus_setup_intr(brdev, sc->irq_res, INTR_TYPE_AV | INTR_MPSAFE,
419 NULL, cbb_pci_intr, sc, &sc->intrhand)) {
420 device_printf(brdev, "couldn't establish interrupt\n");
424 /* reset 16-bit pcmcia bus */
425 exca_clrb(&sc->exca[0], EXCA_INTR, EXCA_INTR_RESET);
428 cbb_power(brdev, CARD_OFF);
430 /* CSC Interrupt: Card detect interrupt on */
431 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD);
433 /* reset interrupt */
434 cbb_set(sc, CBB_SOCKET_EVENT, cbb_get(sc, CBB_SOCKET_EVENT));
437 cbb_print_config(brdev);
439 /* Start the thread */
440 if (kproc_create(cbb_event_thread, sc, &sc->event_thread, 0, 0,
441 "%s event thread", device_get_nameunit(brdev))) {
442 device_printf(brdev, "unable to create event thread.\n");
443 panic("cbb_create_event_thread");
448 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res);
450 bus_release_resource(brdev, SYS_RES_MEMORY, CBBR_SOCKBASE,
453 mtx_destroy(&sc->mtx);
459 cbb_chipinit(struct cbb_softc *sc)
461 uint32_t mux, sysctrl, reg;
463 /* Set CardBus latency timer */
464 if (pci_read_config(sc->dev, PCIR_SECLAT_1, 1) < 0x20)
465 pci_write_config(sc->dev, PCIR_SECLAT_1, 0x20, 1);
467 /* Set PCI latency timer */
468 if (pci_read_config(sc->dev, PCIR_LATTIMER, 1) < 0x20)
469 pci_write_config(sc->dev, PCIR_LATTIMER, 0x20, 1);
471 /* Enable memory access */
472 PCI_MASK_CONFIG(sc->dev, PCIR_COMMAND,
475 | PCIM_CMD_BUSMASTEREN, 2);
477 /* disable Legacy IO */
478 switch (sc->chipset) {
480 PCI_MASK_CONFIG(sc->dev, CBBR_BRIDGECTRL,
481 & ~(CBBM_BRIDGECTRL_RL_3E0_EN |
482 CBBM_BRIDGECTRL_RL_3E2_EN), 2);
485 pci_write_config(sc->dev, CBBR_LEGACY, 0x0, 4);
489 /* Use PCI interrupt for interrupt routing */
490 PCI_MASK2_CONFIG(sc->dev, CBBR_BRIDGECTRL,
491 & ~(CBBM_BRIDGECTRL_MASTER_ABORT |
492 CBBM_BRIDGECTRL_INTR_IREQ_ISA_EN),
493 | CBBM_BRIDGECTRL_WRITE_POST_EN,
497 * XXX this should be a function table, ala OLDCARD. This means
498 * that we could more easily support ISA interrupts for pccard
499 * cards if we had to.
501 switch (sc->chipset) {
504 * The TI 1031, TI 1130 and TI 1131 all require another bit
505 * be set to enable PCI routing of interrupts, and then
506 * a bit for each of the CSC and Function interrupts we
509 PCI_MASK_CONFIG(sc->dev, CBBR_CBCTRL,
510 | CBBM_CBCTRL_113X_PCI_INTR |
511 CBBM_CBCTRL_113X_PCI_CSC | CBBM_CBCTRL_113X_PCI_IRQ_EN,
513 PCI_MASK_CONFIG(sc->dev, CBBR_DEVCTRL,
514 & ~(CBBM_DEVCTRL_INT_SERIAL |
515 CBBM_DEVCTRL_INT_PCI), 1);
519 * Some TI 12xx (and [14][45]xx) based pci cards
520 * sometimes have issues with the MFUNC register not
521 * being initialized due to a bad EEPROM on board.
522 * Laptops that this matters on have this register
523 * properly initialized.
525 * The TI125X parts have a different register.
527 mux = pci_read_config(sc->dev, CBBR_MFUNC, 4);
528 sysctrl = pci_read_config(sc->dev, CBBR_SYSCTRL, 4);
530 mux = (mux & ~CBBM_MFUNC_PIN0) |
531 CBBM_MFUNC_PIN0_INTA;
532 if ((sysctrl & CBBM_SYSCTRL_INTRTIE) == 0)
533 mux = (mux & ~CBBM_MFUNC_PIN1) |
534 CBBM_MFUNC_PIN1_INTB;
535 pci_write_config(sc->dev, CBBR_MFUNC, mux, 4);
540 * Disable zoom video. Some machines initialize this
541 * improperly and exerpience has shown that this helps
542 * prevent strange behavior.
544 pci_write_config(sc->dev, CBBR_MMCTRL, 0, 4);
548 * Issue #1: INT# generated at the same time as
549 * selected ISA IRQ. When IREQ# or STSCHG# is active,
550 * in addition to the ISA IRQ being generated, INT#
551 * will also be generated at the same time.
553 * Some of the older controllers have an issue in
554 * which the slot's PCI INT# will be asserted whenever
555 * IREQ# or STSCGH# is asserted even if ExCA registers
556 * 03h or 05h have an ISA IRQ selected.
558 * The fix for this issue, which will work for any
559 * controller (old or new), is to set ExCA registers
560 * 3Ah (slot 0) & 7Ah (slot 1) bits 7:4 = 1010b.
561 * These bits are undocumented. By setting this
562 * register (of each slot) to '1010xxxxb' a routing of
563 * IREQ# to INTC# and STSCHG# to INTC# is selected.
564 * Since INTC# isn't connected there will be no
565 * unexpected PCI INT when IREQ# or STSCHG# is active.
566 * However, INTA# (slot 0) or INTB# (slot 1) will
567 * still be correctly generated if NO ISA IRQ is
568 * selected (ExCA regs 03h or 05h are cleared).
570 reg = exca_getb(&sc->exca[0], EXCA_O2MICRO_CTRL_C);
572 EXCA_O2CC_IREQ_INTC | EXCA_O2CC_STSCHG_INTC;
573 exca_putb(&sc->exca[0], EXCA_O2MICRO_CTRL_C, reg);
577 * Disable Zoom Video, ToPIC 97, 100.
579 pci_write_config(sc->dev, TOPIC97_ZV_CONTROL, 0, 1);
582 * At offset 0xa1: INTERRUPT CONTROL register
583 * 0x1: Turn on INT interrupts.
585 PCI_MASK_CONFIG(sc->dev, TOPIC_INTCTRL,
586 | TOPIC97_INTCTRL_INTIRQSEL, 1);
589 * Need to assert support for low voltage cards
591 exca_setb(&sc->exca[0], EXCA_TOPIC97_CTRL,
592 EXCA_TOPIC97_CTRL_LV_MASK);
596 * SOCKETCTRL appears to be TOPIC 95/B specific
598 PCI_MASK_CONFIG(sc->dev, TOPIC95_SOCKETCTRL,
599 | TOPIC95_SOCKETCTRL_SCR_IRQSEL, 4);
603 * At offset 0xa0: SLOT CONTROL
604 * 0x80 Enable CardBus Functionality
605 * 0x40 Enable CardBus and PC Card registers
606 * 0x20 Lock ID in exca regs
607 * 0x10 Write protect ID in config regs
608 * Clear the rest of the bits, which defaults the slot
609 * in legacy mode to 0x3e0 and offset 0. (legacy
610 * mode is determined elsewhere)
612 pci_write_config(sc->dev, TOPIC_SLOTCTRL,
613 TOPIC_SLOTCTRL_SLOTON |
614 TOPIC_SLOTCTRL_SLOTEN |
615 TOPIC_SLOTCTRL_ID_LOCK |
616 TOPIC_SLOTCTRL_ID_WP, 1);
619 * At offset 0xa3 Card Detect Control Register
620 * 0x80 CARDBUS enbale
621 * 0x01 Cleared for hardware change detect
623 PCI_MASK2_CONFIG(sc->dev, TOPIC_CDC,
624 | TOPIC_CDC_CARDBUS, & ~TOPIC_CDC_SWDETECT, 4);
629 * Need to tell ExCA registers to CSC interrupts route via PCI
630 * interrupts. There are two ways to do this. One is to set
631 * INTR_ENABLE and the other is to set CSC to 0. Since both
632 * methods are mutually compatible, we do both.
634 exca_putb(&sc->exca[0], EXCA_INTR, EXCA_INTR_ENABLE);
635 exca_putb(&sc->exca[0], EXCA_CSC_INTR, 0);
637 cbb_disable_func_intr(sc);
639 /* close all memory and io windows */
640 pci_write_config(sc->dev, CBBR_MEMBASE0, 0xffffffff, 4);
641 pci_write_config(sc->dev, CBBR_MEMLIMIT0, 0, 4);
642 pci_write_config(sc->dev, CBBR_MEMBASE1, 0xffffffff, 4);
643 pci_write_config(sc->dev, CBBR_MEMLIMIT1, 0, 4);
644 pci_write_config(sc->dev, CBBR_IOBASE0, 0xffffffff, 4);
645 pci_write_config(sc->dev, CBBR_IOLIMIT0, 0, 4);
646 pci_write_config(sc->dev, CBBR_IOBASE1, 0xffffffff, 4);
647 pci_write_config(sc->dev, CBBR_IOLIMIT1, 0, 4);
651 cbb_route_interrupt(device_t pcib, device_t dev, int pin)
653 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(pcib);
655 return (rman_get_start(sc->irq_res));
659 cbb_pci_shutdown(device_t brdev)
661 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev);
664 * Place the cards in reset, turn off the interrupts and power
667 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2);
668 exca_clrb(&sc->exca[0], EXCA_INTR, EXCA_INTR_RESET);
669 cbb_set(sc, CBB_SOCKET_MASK, 0);
670 cbb_set(sc, CBB_SOCKET_EVENT, 0xffffffff);
671 cbb_power(brdev, CARD_OFF);
674 * For paranoia, turn off all address decoding. Really not needed,
675 * it seems, but it can't hurt
677 exca_putb(&sc->exca[0], EXCA_ADDRWIN_ENABLE, 0);
678 pci_write_config(brdev, CBBR_MEMBASE0, 0, 4);
679 pci_write_config(brdev, CBBR_MEMLIMIT0, 0, 4);
680 pci_write_config(brdev, CBBR_MEMBASE1, 0, 4);
681 pci_write_config(brdev, CBBR_MEMLIMIT1, 0, 4);
682 pci_write_config(brdev, CBBR_IOBASE0, 0, 4);
683 pci_write_config(brdev, CBBR_IOLIMIT0, 0, 4);
684 pci_write_config(brdev, CBBR_IOBASE1, 0, 4);
685 pci_write_config(brdev, CBBR_IOLIMIT1, 0, 4);
690 cbb_pci_intr(void *arg)
692 struct cbb_softc *sc = arg;
696 * Read the socket event. Sometimes, the theory goes, the PCI
697 * bus is so loaded that it cannot satisfy the read request, so
698 * we get garbage back from the following read. We have to filter
699 * out the garbage so that we don't spontaneously reset the card
700 * under high load. PCI isn't supposed to act like this. No doubt
701 * this is a bug in the PCI bridge chipset (or cbb brige) that's being
702 * used in certain amd64 laptops today. Work around the issue by
703 * assuming that any bits we don't know about being set means that
706 sockevent = cbb_get(sc, CBB_SOCKET_EVENT);
707 if (sockevent != 0 && (sockevent & ~CBB_SOCKET_EVENT_VALID_MASK) == 0) {
708 /* ack the interrupt */
709 cbb_set(sc, CBB_SOCKET_EVENT, sockevent);
712 * If anything has happened to the socket, we assume that
713 * the card is no longer OK, and we shouldn't call its
714 * ISR. We set cardok as soon as we've attached the
715 * card. This helps in a noisy eject, which happens
716 * all too often when users are ejecting their PC Cards.
718 * We use this method in preference to checking to see if
719 * the card is still there because the check suffers from
720 * a race condition in the bouncing case. Prior versions
721 * of the pccard software used a similar trick and achieved
724 if (sockevent & CBB_SOCKET_EVENT_CD) {
726 cbb_clrb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD);
728 cbb_disable_func_intr(sc);
730 mtx_unlock(&sc->mtx);
733 * If we get a power interrupt, wakeup anybody that might
734 * be waiting for one.
736 if (sockevent & CBB_SOCKET_EVENT_POWER) {
739 cv_signal(&sc->powercv);
740 mtx_unlock(&sc->mtx);
744 * Some chips also require us to read the old ExCA registe for
745 * card status change when we route CSC vis PCI. This isn't supposed
746 * to be required, but it clears the interrupt state on some chipsets.
747 * Maybe there's a setting that would obviate its need. Maybe we
748 * should test the status bits and deal with them, but so far we've
749 * not found any machines that don't also give us the socket status
752 * We have to call this unconditionally because some bridges deliver
753 * the event independent of the CBB_SOCKET_EVENT_CD above.
755 exca_getb(&sc->exca[0], EXCA_CSC);
758 /************************************************************************/
759 /* PCI compat methods */
760 /************************************************************************/
763 cbb_maxslots(device_t brdev)
769 cbb_read_config(device_t brdev, int b, int s, int f, int reg, int width)
774 * Pass through to the next ppb up the chain (i.e. our grandparent).
776 rv = PCIB_READ_CONFIG(device_get_parent(device_get_parent(brdev)),
777 b, s, f, reg, width);
782 cbb_write_config(device_t brdev, int b, int s, int f, int reg, uint32_t val,
786 * Pass through to the next ppb up the chain (i.e. our grandparent).
788 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(brdev)),
789 b, s, f, reg, val, width);
792 static device_method_t cbb_methods[] = {
793 /* Device interface */
794 DEVMETHOD(device_probe, cbb_pci_probe),
795 DEVMETHOD(device_attach, cbb_pci_attach),
796 DEVMETHOD(device_detach, cbb_detach),
797 DEVMETHOD(device_shutdown, cbb_pci_shutdown),
798 DEVMETHOD(device_suspend, cbb_suspend),
799 DEVMETHOD(device_resume, cbb_resume),
802 DEVMETHOD(bus_print_child, bus_generic_print_child),
803 DEVMETHOD(bus_read_ivar, cbb_read_ivar),
804 DEVMETHOD(bus_write_ivar, cbb_write_ivar),
805 DEVMETHOD(bus_alloc_resource, cbb_alloc_resource),
806 DEVMETHOD(bus_release_resource, cbb_release_resource),
807 DEVMETHOD(bus_activate_resource, cbb_activate_resource),
808 DEVMETHOD(bus_deactivate_resource, cbb_deactivate_resource),
809 DEVMETHOD(bus_driver_added, cbb_driver_added),
810 DEVMETHOD(bus_child_detached, cbb_child_detached),
811 DEVMETHOD(bus_setup_intr, cbb_setup_intr),
812 DEVMETHOD(bus_teardown_intr, cbb_teardown_intr),
813 DEVMETHOD(bus_child_present, cbb_child_present),
815 /* 16-bit card interface */
816 DEVMETHOD(card_set_res_flags, cbb_pcic_set_res_flags),
817 DEVMETHOD(card_set_memory_offset, cbb_pcic_set_memory_offset),
819 /* power interface */
820 DEVMETHOD(power_enable_socket, cbb_power_enable_socket),
821 DEVMETHOD(power_disable_socket, cbb_power_disable_socket),
823 /* pcib compatibility interface */
824 DEVMETHOD(pcib_maxslots, cbb_maxslots),
825 DEVMETHOD(pcib_read_config, cbb_read_config),
826 DEVMETHOD(pcib_write_config, cbb_write_config),
827 DEVMETHOD(pcib_route_interrupt, cbb_route_interrupt),
832 static driver_t cbb_driver = {
835 sizeof(struct cbb_softc)
838 DRIVER_MODULE(cbb, pci, cbb_driver, cbb_devclass, 0, 0);
839 MODULE_DEPEND(cbb, exca, 1, 1, 1);