2 * Copyright (c) 2000,2001 Jonathan Chen.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * Copyright (c) 1998, 1999 and 2000
31 * HAYAKAWA Koichi. All rights reserved.
33 * Redistribution and use in source and binary forms, with or without
34 * modification, are permitted provided that the following conditions
36 * 1. Redistributions of source code must retain the above copyright
37 * notice, this list of conditions and the following disclaimer.
38 * 2. Redistributions in binary form must reproduce the above copyright
39 * notice, this list of conditions and the following disclaimer in the
40 * documentation and/or other materials provided with the distribution.
41 * 3. All advertising materials mentioning features or use of this software
42 * must display the following acknowledgement:
43 * This product includes software developed by HAYAKAWA Koichi.
44 * 4. The name of the author may not be used to endorse or promote products
45 * derived from this software without specific prior written permission.
47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
50 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
60 * Register definitions for PCI to Cardbus Bridge chips
64 /* PCI header registers */
65 #define CBBR_SOCKBASE 0x10 /* len=4 */
67 #define CBBR_MEMBASE0 0x1c /* len=4 */
68 #define CBBR_MEMLIMIT0 0x20 /* len=4 */
69 #define CBBR_MEMBASE1 0x24 /* len=4 */
70 #define CBBR_MEMLIMIT1 0x28 /* len=4 */
71 #define CBBR_IOBASE0 0x2c /* len=4 */
72 #define CBBR_IOLIMIT0 0x30 /* len=4 */
73 #define CBBR_IOBASE1 0x34 /* len=4 */
74 #define CBBR_IOLIMIT1 0x38 /* len=4 */
75 #define CBB_MEMALIGN 4096
76 #define CBB_MEMALIGN_BITS 12
78 #define CBB_IOALIGN_BITS 2
80 #define CBBR_INTRLINE 0x3c /* len=1 */
81 #define CBBR_INTRPIN 0x3d /* len=1 */
82 #define CBBR_BRIDGECTRL 0x3e /* len=2 */
83 # define CBBM_BRIDGECTRL_MASTER_ABORT 0x0020
84 # define CBBM_BRIDGECTRL_RESET 0x0040
85 # define CBBM_BRIDGECTRL_INTR_IREQ_ISA_EN 0x0080
86 # define CBBM_BRIDGECTRL_PREFETCH_0 0x0100
87 # define CBBM_BRIDGECTRL_PREFETCH_1 0x0200
88 # define CBBM_BRIDGECTRL_WRITE_POST_EN 0x0400
89 /* additional bit for RF5C46[567] */
90 # define CBBM_BRIDGECTRL_RL_3E0_EN 0x0800
91 # define CBBM_BRIDGECTRL_RL_3E2_EN 0x1000
93 #define CBBR_LEGACY 0x44 /* len=4 */
96 #define CBBR_SYSCTRL 0x80 /* len=4 */
97 # define CBBM_SYSCTRL_INTRTIE 0x20000000u
100 #define CBBR_MMCTRL 0x84 /* len=4 */
102 /* TI 12xx/14xx/15xx (except 1250/1251/1251B/1450) */
103 #define CBBR_MFUNC 0x8c /* len=4 */
104 # define CBBM_MFUNC_PIN0 0x0000000f
105 # define CBBM_MFUNC_PIN0_INTA 0x02
106 # define CBBM_MFUNC_PIN1 0x000000f0
107 # define CBBM_MFUNC_PIN1_INTB 0x20
108 # define CBBM_MFUNC_PIN2 0x00000f00
109 # define CBBM_MFUNC_PIN3 0x0000f000
110 # define CBBM_MFUNC_PIN4 0x000f0000
111 # define CBBM_MFUNC_PIN5 0x00f00000
112 # define CBBM_MFUNC_PIN6 0x0f000000
114 #define CBBR_CBCTRL 0x91 /* len=1 */
115 /* bits for TI 113X */
116 # define CBBM_CBCTRL_113X_RI_EN 0x80
117 # define CBBM_CBCTRL_113X_ZV_EN 0x40
118 # define CBBM_CBCTRL_113X_PCI_IRQ_EN 0x20
119 # define CBBM_CBCTRL_113X_PCI_INTR 0x10
120 # define CBBM_CBCTRL_113X_PCI_CSC 0x08
121 # define CBBM_CBCTRL_113X_PCI_CSC_D 0x04
122 # define CBBM_CBCTRL_113X_SPEAKER_EN 0x02
123 # define CBBM_CBCTRL_113X_INTR_DET 0x01
125 # define CBBM_CBCTRL_12XX_RI_EN 0x80
126 # define CBBM_CBCTRL_12XX_ZV_EN 0x40
127 # define CBBM_CBCTRL_12XX_AUD2MUX 0x04
128 # define CBBM_CBCTRL_12XX_SPEAKER_EN 0x02
129 # define CBBM_CBCTRL_12XX_INTR_DET 0x01
130 #define CBBR_DEVCTRL 0x92 /* len=1 */
131 # define CBBM_DEVCTRL_INT_SERIAL 0x04
132 # define CBBM_DEVCTRL_INT_PCI 0x02
135 #define TOPIC95_SOCKETCTRL 0x90
136 # define TOPIC95_SOCKETCTRL_SCR_IRQSEL 0x00000001 /* PCI intr */
138 #define TOPIC97_ZV_CONTROL 0x9c /* 1 byte */
139 # define TOPIC97_ZVC_ENABLE 0x1
142 #define TOPIC_SLOTCTRL 0xa0 /* 1 byte */
143 # define TOPIC_SLOTCTRL_SLOTON 0x80
144 # define TOPIC_SLOTCTRL_SLOTEN 0x40
145 # define TOPIC_SLOTCTRL_ID_LOCK 0x20
146 # define TOPIC_SLOTCTRL_ID_WP 0x10
147 # define TOPIC_SLOTCTRL_PORT_MASK 0x0c
148 # define TOPIC_SLOTCTRL_PORT_SHIFT 2
149 # define TOPIC_SLOTCTRL_OSF_MASK 0x03
150 # define TOPIC_SLOTCTRL_OSF_SHIFT 0
153 #define TOPIC_INTCTRL 0xa1 /* 1 byte */
154 # define TOPIC_INTCTRL_INTB 0x20
155 # define TOPIC_INTCTRL_INTA 0x10
156 # define TOPIC_INTCTRL_INT_MASK 0x30
157 /* The following bits may be for ToPIC 95 only */
158 # define TOPIC95_INTCTRL_CLOCK_MASK 0x0c
159 # define TOPIC95_INTCTRL_CLOCK_2 0x08 /* PCI Clk/2 */
160 # define TOPIC95_INTCTRL_CLOCK_1 0x04 /* PCI Clk */
161 # define TOPIC95_INTCTRL_CLOCK_0 0x00 /* no clock */
162 /* ToPIC97, 100 defines the following bits */
163 # define TOPIC97_INTCTRL_STSIRQNP 0x04
164 # define TOPIC97_INTCTRL_IRQNP 0x02
165 # define TOPIC97_INTCTRL_INTIRQSEL 0x01
168 #define TOPIC_CDC 0xa3 /* 1 byte */
169 # define TOPIC_CDC_CARDBUS 0x80
170 # define TOPIC_CDC_VS1 0x04
171 # define TOPIC_CDC_VS2 0x02
172 # define TOPIC_CDC_SWDETECT 0x01
175 #define TOPIC_REG_CTRL 0xa4 /* 4 bytes */
176 # define TOPIC_REG_CTRL_RESUME_RESET 0x80000000
177 # define TOPIC_REG_CTRL_REMOVE_RESET 0x40000000
178 # define TOPIC97_REG_CTRL_CLKRUN_ENA 0x20000000
179 # define TOPIC97_REG_CTRL_TESTMODE 0x10000000
180 # define TOPIC97_REG_CTRL_IOPLUP 0x08000000
181 # define TOPIC_REG_CTRL_BUFOFF_PWROFF 0x02000000
182 # define TOPIC_REG_CTRL_BUFOFF_SIGOFF 0x01000000
183 # define TOPIC97_REG_CTRL_CB_DEV_MASK 0x0000f800
184 # define TOPIC97_REG_CTRL_CB_DEV_SHIFT 11
185 # define TOPIC97_REG_CTRL_RI_DISABLE 0x00000004
186 # define TOPIC97_REG_CTRL_CAUDIO_OFF 0x00000002
187 # define TOPIC_REG_CTRL_CAUDIO_INVERT 0x00000001
190 /* Socket definitions */
191 #define CBB_SOCKET_EVENT_CSTS 0x01 /* Card Status Change */
192 #define CBB_SOCKET_EVENT_CD1 0x02 /* Card Detect 1 */
193 #define CBB_SOCKET_EVENT_CD2 0x04 /* Card Detect 2 */
194 #define CBB_SOCKET_EVENT_CD 0x06 /* Card Detect all */
195 #define CBB_SOCKET_EVENT_POWER 0x08 /* Power Cycle */
196 #define CBB_SOCKET_EVENT_VALID_MASK 0x0f /* All socket events */
198 #define CBB_SOCKET_MASK_CSTS 0x01 /* Card Status Change */
199 #define CBB_SOCKET_MASK_CD 0x06 /* Card Detect */
200 #define CBB_SOCKET_MASK_POWER 0x08 /* Power Cycle */
201 #define CBB_SOCKET_MASK_ALL 0x0F /* all of the above */
203 #define CBB_STATE_CSTCHG (1UL << 0) /* Card Status Change */
204 #define CBB_STATE_CD1_CHANGE (1UL << 1) /* Card Detect 1 */
205 #define CBB_STATE_CD2_CHANGE (1UL << 2) /* Card Detect 2 */
206 #define CBB_STATE_CD (3UL << 1) /* Card Detect all */
207 #define CBB_STATE_POWER_CYCLE (1UL << 3) /* Power Cycle */
208 #define CBB_STATE_R2_CARD (1UL << 4) /* 16-bit Card */
209 #define CBB_STATE_CB_CARD (1UL << 5) /* Cardbus Card */
210 #define CBB_STATE_IREQ (1UL << 6) /* Ready */
211 #define CBB_STATE_NOT_A_CARD (1UL << 7) /* Unrecognized Card */
212 #define CBB_STATE_DATA_LOST (1UL << 8) /* Data Lost */
213 #define CBB_STATE_BAD_VCC_REQ (1UL << 9) /* Bad VccRequest */
214 #define CBB_STATE_5VCARD (1UL << 10) /* 5 V Card */
215 #define CBB_STATE_3VCARD (1UL << 11) /* 3.3 V Card */
216 #define CBB_STATE_XVCARD (1UL << 12) /* X.X V Card */
217 #define CBB_STATE_YVCARD (1UL << 13) /* Y.Y V Card */
218 #define CBB_STATE_5VSOCK (1UL << 28) /* 5 V Socket */
219 #define CBB_STATE_3VSOCK (1UL << 29) /* 3.3 V Socket */
220 #define CBB_STATE_XVSOCK (1UL << 30) /* X.X V Socket */
221 #define CBB_STATE_YVSOCK (1UL << 31) /* Y.Y V Socket */
223 #define CBB_SOCKET_CTRL_VPPMASK 0x07
224 #define CBB_SOCKET_CTRL_VPP_OFF 0x00
225 #define CBB_SOCKET_CTRL_VPP_12V 0x01
226 #define CBB_SOCKET_CTRL_VPP_5V 0x02
227 #define CBB_SOCKET_CTRL_VPP_3V 0x03
228 #define CBB_SOCKET_CTRL_VPP_XV 0x04
229 #define CBB_SOCKET_CTRL_VPP_YV 0x05
231 #define CBB_SOCKET_CTRL_VCCMASK 0x70
232 #define CBB_SOCKET_CTRL_VCC_OFF 0x00
233 #define CBB_SOCKET_CTRL_VCC_5V 0x20
234 #define CBB_SOCKET_CTRL_VCC_3V 0x30
235 #define CBB_SOCKET_CTRL_VCC_XV 0x40
236 #define CBB_SOCKET_CTRL_VCC_YV 0x50
238 #define CBB_SOCKET_CTRL_STOPCLK 0x80
240 #define CBB_FORCE_CV_TEST (1UL << 14)
241 #define CBB_FORCE_3VCARD (1UL << 11)
242 #define CBB_FORCE_5VCARD (1UL << 10)
243 #define CBB_FORCE_BAD_VCC_REQ (1UL << 9)
244 #define CBB_FORCE_DATA_LOST (1UL << 8)
245 #define CBB_FORCE_NOT_A_CARD (1UL << 7)
246 #define CBB_FORCE_CB_CARD (1UL << 5)
247 #define CBB_FORCE_R2_CARD (1UL << 4)
248 #define CBB_FORCE_POWER_CYCLE (1UL << 3)
249 #define CBB_FORCE_CD2_CHANGE (1UL << 2)
250 #define CBB_FORCE_CD1_CHANGE (1UL << 1)
251 #define CBB_FORCE_CSTCHG (1UL << 0)
253 #include <dev/pccbb/pccbbdevid.h>
255 #define CBB_SOCKET_EVENT 0x00
256 #define CBB_SOCKET_MASK 0x04
257 #define CBB_SOCKET_STATE 0x08
258 #define CBB_SOCKET_FORCE 0x0c
259 #define CBB_SOCKET_CONTROL 0x10
260 #define CBB_SOCKET_POWER 0x14
262 #define CBB_EXCA_OFFSET 0x800 /* offset for exca regs */