2 * Copyright (c) 1998 Nicolas Souchu, Marc Bouget
3 * Copyright (c) 2004 Joerg Wunsch
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 #define TIMEOUT 9999 /* XXX */
37 /* Status bits of S1 register (read only) */
38 #define nBB 0x01 /* busy when low set/reset by STOP/START*/
39 #define LAB 0x02 /* lost arbitration bit in multi-master mode */
40 #define AAS 0x04 /* addressed as slave */
41 #define LRB 0x08 /* last received byte when not AAS */
42 #define AD0 0x08 /* general call received when AAS */
43 #define BER 0x10 /* bus error, misplaced START or STOP */
44 #define STS 0x20 /* STOP detected in slave receiver mode */
45 #define PIN 0x80 /* pending interrupt not (r/w) */
47 /* Control bits of S1 register (write only) */
58 #define SLAVE_TRANSMITTER 0x1
59 #define SLAVE_RECEIVER 0x2
61 #define PCF_DEFAULT_ADDR 0xaa
64 u_char pcf_addr; /* interface I2C address */
65 int pcf_flags; /* IIC_POLLED? */
66 int pcf_slave_mode; /* receiver or transmitter */
67 int pcf_started; /* 1 if start condition sent */
70 device_t iicbus; /* the corresponding iicbus */
72 /* Resource handling stuff. */
73 struct resource *res_ioport;
75 struct resource *res_irq;
79 #define DEVTOSOFTC(dev) ((struct pcf_softc *)device_get_softc(dev))
81 #define PCF_LOCK(sc) mtx_lock(&(sc)->pcf_lock)
82 #define PCF_UNLOCK(sc) mtx_unlock(&(sc)->pcf_lock)
83 #define PCF_ASSERT_LOCKED(sc) mtx_assert(&(sc)->pcf_lock, MA_OWNED)
86 * PCF8584 datasheet : when operate at 8 MHz or more, a minimun time of
87 * 6 clocks cycles must be left between two consecutives access
89 #define pcf_nops() DELAY(10)
91 #define dummy_read(sc) pcf_get_S0(sc)
92 #define dummy_write(sc) pcf_set_S0(sc, 0)
95 * Specific register access to PCF8584
98 pcf_set_S0(struct pcf_softc *sc, int data)
101 bus_write_1(sc->res_ioport, 0, data);
106 pcf_set_S1(struct pcf_softc *sc, int data)
109 bus_write_1(sc->res_ioport, 1, data);
114 pcf_get_S0(struct pcf_softc *sc)
118 data = bus_read_1(sc->res_ioport, 0);
125 pcf_get_S1(struct pcf_softc *sc)
129 data = bus_read_1(sc->res_ioport, 1);
135 extern int pcf_repeated_start(device_t, u_char, int);
136 extern int pcf_start(device_t, u_char, int);
137 extern int pcf_stop(device_t);
138 extern int pcf_write(device_t, const char *, int, int *, int);
139 extern int pcf_read(device_t, char *, int, int *, int, int);
140 extern int pcf_rst_card(device_t, u_char, u_char, u_char *);
141 extern driver_intr_t pcf_intr;
146 #define PCF_PREFVER PCF_MODVER
148 #endif /* !__PCFVAR_H__ */