2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 #include "opt_simos.h"
33 #include "opt_compat_oldpci.h"
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/malloc.h>
38 #include <sys/module.h>
39 #include <sys/fcntl.h>
41 #include <sys/kernel.h>
42 #include <sys/queue.h>
43 #include <sys/types.h>
47 #include <vm/vm_extern.h>
50 #include <machine/bus.h>
52 #include <machine/resource.h>
53 #include <machine/md_var.h> /* For the Alpha */
55 #include <pci/pcireg.h>
56 #include <pci/pcivar.h>
57 #include <sys/pciio.h>
60 #include <machine/rpb.h>
64 #include <machine/smp.h>
68 u_int32_t devid; /* Vendor/device of the card */
70 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in wierd place */
75 struct pci_quirk pci_quirks[] = {
77 * The Intel 82371AB has a map register at offset 0x90.
79 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
84 /* map register information */
85 #define PCI_MAPMEM 0x01 /* memory map */
86 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
87 #define PCI_MAPPORT 0x04 /* port map */
90 STAILQ_ENTRY(struct pci_devinfo) pci_links;
91 struct resource_list resources;
96 static STAILQ_HEAD(devlist, struct pci_devinfo) pci_devq;
97 u_int32_t pci_numdevs = 0;
98 static u_int32_t pci_generation = 0;
100 /* return base address of memory or port map */
103 pci_mapbase(unsigned mapreg)
106 if ((mapreg & 0x01) == 0)
108 return (mapreg & ~mask);
111 /* return map type of memory or port map */
114 pci_maptype(unsigned mapreg)
116 static u_int8_t maptype[0x10] = {
117 PCI_MAPMEM, PCI_MAPPORT,
119 PCI_MAPMEM, PCI_MAPPORT,
121 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
122 PCI_MAPMEM|PCI_MAPMEMP, 0,
123 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
127 return maptype[mapreg & 0x0f];
130 /* return log2 of map size decoded for memory or port map */
133 pci_mapsize(unsigned testval)
137 testval = pci_mapbase(testval);
140 while ((testval & 1) == 0)
149 /* return log2 of address range supported by map register */
152 pci_maprange(unsigned mapreg)
155 switch (mapreg & 0x07) {
171 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
174 pci_fixancient(pcicfgregs *cfg)
176 if (cfg->hdrtype != 0)
179 /* PCI to PCI bridges use header type 1 */
180 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
184 /* read config data specific to header type 1 device (PCI to PCI bridge) */
187 pci_readppb(pcicfgregs *cfg)
191 p = malloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK);
197 p->secstat = pci_cfgread(cfg, PCIR_SECSTAT_1, 2);
198 p->bridgectl = pci_cfgread(cfg, PCIR_BRIDGECTL_1, 2);
200 p->seclat = pci_cfgread(cfg, PCIR_SECLAT_1, 1);
202 p->iobase = PCI_PPBIOBASE (pci_cfgread(cfg, PCIR_IOBASEH_1, 2),
203 pci_cfgread(cfg, PCIR_IOBASEL_1, 1));
204 p->iolimit = PCI_PPBIOLIMIT (pci_cfgread(cfg, PCIR_IOLIMITH_1, 2),
205 pci_cfgread(cfg, PCIR_IOLIMITL_1, 1));
207 p->membase = PCI_PPBMEMBASE (0,
208 pci_cfgread(cfg, PCIR_MEMBASE_1, 2));
209 p->memlimit = PCI_PPBMEMLIMIT (0,
210 pci_cfgread(cfg, PCIR_MEMLIMIT_1, 2));
212 p->pmembase = PCI_PPBMEMBASE (
213 (pci_addr_t)pci_cfgread(cfg, PCIR_PMBASEH_1, 4),
214 pci_cfgread(cfg, PCIR_PMBASEL_1, 2));
216 p->pmemlimit = PCI_PPBMEMLIMIT (
217 (pci_addr_t)pci_cfgread(cfg, PCIR_PMLIMITH_1, 4),
218 pci_cfgread(cfg, PCIR_PMLIMITL_1, 2));
222 /* read config data specific to header type 2 device (PCI to CardBus bridge) */
225 pci_readpcb(pcicfgregs *cfg)
229 p = malloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK);
235 p->secstat = pci_cfgread(cfg, PCIR_SECSTAT_2, 2);
236 p->bridgectl = pci_cfgread(cfg, PCIR_BRIDGECTL_2, 2);
238 p->seclat = pci_cfgread(cfg, PCIR_SECLAT_2, 1);
240 p->membase0 = pci_cfgread(cfg, PCIR_MEMBASE0_2, 4);
241 p->memlimit0 = pci_cfgread(cfg, PCIR_MEMLIMIT0_2, 4);
242 p->membase1 = pci_cfgread(cfg, PCIR_MEMBASE1_2, 4);
243 p->memlimit1 = pci_cfgread(cfg, PCIR_MEMLIMIT1_2, 4);
245 p->iobase0 = pci_cfgread(cfg, PCIR_IOBASE0_2, 4);
246 p->iolimit0 = pci_cfgread(cfg, PCIR_IOLIMIT0_2, 4);
247 p->iobase1 = pci_cfgread(cfg, PCIR_IOBASE1_2, 4);
248 p->iolimit1 = pci_cfgread(cfg, PCIR_IOLIMIT1_2, 4);
250 p->pccardif = pci_cfgread(cfg, PCIR_PCCARDIF_2, 4);
254 /* extract header type specific config data */
257 pci_hdrtypedata(pcicfgregs *cfg)
259 switch (cfg->hdrtype) {
261 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_0, 2);
262 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_0, 2);
263 cfg->nummaps = PCI_MAXMAPS_0;
266 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_1, 2);
267 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_1, 2);
268 cfg->secondarybus = pci_cfgread(cfg, PCIR_SECBUS_1, 1);
269 cfg->subordinatebus = pci_cfgread(cfg, PCIR_SUBBUS_1, 1);
270 cfg->nummaps = PCI_MAXMAPS_1;
271 cfg->hdrspec = pci_readppb(cfg);
274 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_2, 2);
275 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_2, 2);
276 cfg->secondarybus = pci_cfgread(cfg, PCIR_SECBUS_2, 1);
277 cfg->subordinatebus = pci_cfgread(cfg, PCIR_SUBBUS_2, 1);
278 cfg->nummaps = PCI_MAXMAPS_2;
279 cfg->hdrspec = pci_readpcb(cfg);
284 /* read configuration header into pcicfgrect structure */
286 static struct pci_devinfo *
287 pci_readcfg(pcicfgregs *probe)
289 pcicfgregs *cfg = NULL;
290 struct pci_devinfo *devlist_entry;
291 struct devlist *devlist_head;
293 devlist_head = &pci_devq;
295 devlist_entry = NULL;
297 if (pci_cfgread(probe, PCIR_DEVVENDOR, 4) != -1) {
299 devlist_entry = malloc(sizeof(struct pci_devinfo),
301 if (devlist_entry == NULL)
303 bzero(devlist_entry, sizeof *devlist_entry);
305 cfg = &devlist_entry->cfg;
307 cfg->hose = probe->hose;
308 cfg->bus = probe->bus;
309 cfg->slot = probe->slot;
310 cfg->func = probe->func;
311 cfg->vendor = pci_cfgread(cfg, PCIR_VENDOR, 2);
312 cfg->device = pci_cfgread(cfg, PCIR_DEVICE, 2);
313 cfg->cmdreg = pci_cfgread(cfg, PCIR_COMMAND, 2);
314 cfg->statreg = pci_cfgread(cfg, PCIR_STATUS, 2);
315 cfg->baseclass = pci_cfgread(cfg, PCIR_CLASS, 1);
316 cfg->subclass = pci_cfgread(cfg, PCIR_SUBCLASS, 1);
317 cfg->progif = pci_cfgread(cfg, PCIR_PROGIF, 1);
318 cfg->revid = pci_cfgread(cfg, PCIR_REVID, 1);
319 cfg->hdrtype = pci_cfgread(cfg, PCIR_HEADERTYPE, 1);
320 cfg->cachelnsz = pci_cfgread(cfg, PCIR_CACHELNSZ, 1);
321 cfg->lattimer = pci_cfgread(cfg, PCIR_LATTIMER, 1);
322 cfg->intpin = pci_cfgread(cfg, PCIR_INTPIN, 1);
323 cfg->intline = pci_cfgread(cfg, PCIR_INTLINE, 1);
325 alpha_platform_assign_pciintr(cfg);
329 if (cfg->intpin != 0) {
332 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin);
334 /* PCI specific entry found in MP table */
335 if (airq != cfg->intline) {
336 undirect_pci_irq(cfg->intline);
341 * PCI interrupts might be redirected to the
342 * ISA bus according to some MP tables. Use the
343 * same methods as used by the ISA devices
344 * devices to find the proper IOAPIC int pin.
346 airq = isa_apic_irq(cfg->intline);
347 if ((airq >= 0) && (airq != cfg->intline)) {
348 /* XXX: undirect_pci_irq() ? */
349 undirect_isa_irq(cfg->intline);
356 cfg->mingnt = pci_cfgread(cfg, PCIR_MINGNT, 1);
357 cfg->maxlat = pci_cfgread(cfg, PCIR_MAXLAT, 1);
359 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
360 cfg->hdrtype &= ~PCIM_MFDEV;
363 pci_hdrtypedata(cfg);
365 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
367 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
368 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
369 devlist_entry->conf.pc_sel.pc_func = cfg->func;
370 devlist_entry->conf.pc_hdr = cfg->hdrtype;
372 devlist_entry->conf.pc_subvendor = cfg->subvendor;
373 devlist_entry->conf.pc_subdevice = cfg->subdevice;
374 devlist_entry->conf.pc_vendor = cfg->vendor;
375 devlist_entry->conf.pc_device = cfg->device;
377 devlist_entry->conf.pc_class = cfg->baseclass;
378 devlist_entry->conf.pc_subclass = cfg->subclass;
379 devlist_entry->conf.pc_progif = cfg->progif;
380 devlist_entry->conf.pc_revid = cfg->revid;
385 return (devlist_entry);
389 /* free pcicfgregs structure and all depending data structures */
392 pci_freecfg(struct pci_devinfo *dinfo)
394 struct devlist *devlist_head;
396 devlist_head = &pci_devq;
398 if (dinfo->cfg.hdrspec != NULL)
399 free(dinfo->cfg.hdrspec, M_DEVBUF);
400 if (dinfo->cfg.map != NULL)
401 free(dinfo->cfg.map, M_DEVBUF);
402 /* XXX this hasn't been tested */
403 STAILQ_REMOVE(devlist_head, dinfo, struct pci_devinfo, pci_links);
404 free(dinfo, M_DEVBUF);
406 /* increment the generation count */
409 /* we're losing one device */
417 * This is the user interface to PCI configuration space.
421 pci_open(dev_t dev, int oflags, int devtype, struct proc *p)
423 if ((oflags & FWRITE) && securelevel > 0) {
430 pci_close(dev_t dev, int flag, int devtype, struct proc *p)
436 * Match a single pci_conf structure against an array of pci_match_conf
437 * structures. The first argument, 'matches', is an array of num_matches
438 * pci_match_conf structures. match_buf is a pointer to the pci_conf
439 * structure that will be compared to every entry in the matches array.
440 * This function returns 1 on failure, 0 on success.
443 pci_conf_match(struct pci_match_conf *matches, int num_matches,
444 struct pci_conf *match_buf)
448 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0))
451 for (i = 0; i < num_matches; i++) {
453 * I'm not sure why someone would do this...but...
455 if (matches[i].flags == PCI_GETCONF_NO_MATCH)
459 * Look at each of the match flags. If it's set, do the
460 * comparison. If the comparison fails, we don't have a
461 * match, go on to the next item if there is one.
463 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0)
464 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus))
467 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0)
468 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev))
471 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0)
472 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func))
475 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0)
476 && (match_buf->pc_vendor != matches[i].pc_vendor))
479 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0)
480 && (match_buf->pc_device != matches[i].pc_device))
483 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0)
484 && (match_buf->pc_class != matches[i].pc_class))
487 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0)
488 && (match_buf->pd_unit != matches[i].pd_unit))
491 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0)
492 && (strncmp(matches[i].pd_name, match_buf->pd_name,
493 sizeof(match_buf->pd_name)) != 0))
503 * Locate the parent of a PCI device by scanning the PCI devlist
504 * and return the entry for the parent.
505 * For devices on PCI Bus 0 (the host bus), this is the PCI Host.
506 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge.
510 pci_devlist_get_parent(pcicfgregs *cfg)
512 struct devlist *devlist_head;
513 struct pci_devinfo *dinfo;
514 pcicfgregs *bridge_cfg;
517 dinfo = STAILQ_FIRST(devlist_head = &pci_devq);
519 /* If the device is on PCI bus 0, look for the host */
521 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
522 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
523 bridge_cfg = &dinfo->cfg;
524 if (bridge_cfg->baseclass == PCIC_BRIDGE
525 && bridge_cfg->subclass == PCIS_BRIDGE_HOST
526 && bridge_cfg->bus == cfg->bus) {
532 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */
534 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
535 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
536 bridge_cfg = &dinfo->cfg;
537 if (bridge_cfg->baseclass == PCIC_BRIDGE
538 && bridge_cfg->subclass == PCIS_BRIDGE_PCI
539 && bridge_cfg->secondarybus == cfg->bus) {
549 pci_ioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p)
555 if (!(flag & FWRITE))
562 struct pci_devinfo *dinfo;
563 struct pci_conf_io *cio;
564 struct devlist *devlist_head;
565 struct pci_match_conf *pattern_buf;
570 cio = (struct pci_conf_io *)data;
576 * Hopefully the user won't pass in a null pointer, but it
577 * can't hurt to check.
585 * If the user specified an offset into the device list,
586 * but the list has changed since they last called this
587 * ioctl, tell them that the list has changed. They will
588 * have to get the list from the beginning.
590 if ((cio->offset != 0)
591 && (cio->generation != pci_generation)){
592 cio->num_matches = 0;
593 cio->status = PCI_GETCONF_LIST_CHANGED;
599 * Check to see whether the user has asked for an offset
600 * past the end of our list.
602 if (cio->offset >= pci_numdevs) {
603 cio->num_matches = 0;
604 cio->status = PCI_GETCONF_LAST_DEVICE;
609 /* get the head of the device queue */
610 devlist_head = &pci_devq;
613 * Determine how much room we have for pci_conf structures.
614 * Round the user's buffer size down to the nearest
615 * multiple of sizeof(struct pci_conf) in case the user
616 * didn't specify a multiple of that size.
618 iolen = min(cio->match_buf_len -
619 (cio->match_buf_len % sizeof(struct pci_conf)),
620 pci_numdevs * sizeof(struct pci_conf));
623 * Since we know that iolen is a multiple of the size of
624 * the pciconf union, it's okay to do this.
626 ionum = iolen / sizeof(struct pci_conf);
629 * If this test is true, the user wants the pci_conf
630 * structures returned to match the supplied entries.
632 if ((cio->num_patterns > 0)
633 && (cio->pat_buf_len > 0)) {
635 * pat_buf_len needs to be:
636 * num_patterns * sizeof(struct pci_match_conf)
637 * While it is certainly possible the user just
638 * allocated a large buffer, but set the number of
639 * matches correctly, it is far more likely that
640 * their kernel doesn't match the userland utility
641 * they're using. It's also possible that the user
642 * forgot to initialize some variables. Yes, this
643 * may be overly picky, but I hazard to guess that
644 * it's far more likely to just catch folks that
645 * updated their kernel but not their userland.
647 if ((cio->num_patterns *
648 sizeof(struct pci_match_conf)) != cio->pat_buf_len){
649 /* The user made a mistake, return an error*/
650 cio->status = PCI_GETCONF_ERROR;
651 printf("pci_ioctl: pat_buf_len %d != "
652 "num_patterns (%d) * sizeof(struct "
653 "pci_match_conf) (%d)\npci_ioctl: "
654 "pat_buf_len should be = %d\n",
655 cio->pat_buf_len, cio->num_patterns,
656 (int)sizeof(struct pci_match_conf),
657 (int)sizeof(struct pci_match_conf) *
659 printf("pci_ioctl: do your headers match your "
661 cio->num_matches = 0;
667 * Check the user's buffer to make sure it's readable.
669 if (!useracc((caddr_t)cio->patterns,
670 cio->pat_buf_len, VM_PROT_READ)) {
671 printf("pci_ioctl: pattern buffer %p, "
672 "length %u isn't user accessible for"
673 " READ\n", cio->patterns,
679 * Allocate a buffer to hold the patterns.
681 pattern_buf = malloc(cio->pat_buf_len, M_TEMP,
683 error = copyin(cio->patterns, pattern_buf,
687 num_patterns = cio->num_patterns;
689 } else if ((cio->num_patterns > 0)
690 || (cio->pat_buf_len > 0)) {
692 * The user made a mistake, spit out an error.
694 cio->status = PCI_GETCONF_ERROR;
695 cio->num_matches = 0;
696 printf("pci_ioctl: invalid GETCONF arguments\n");
703 * Make sure we can write to the match buffer.
705 if (!useracc((caddr_t)cio->matches,
706 cio->match_buf_len, VM_PROT_WRITE)) {
707 printf("pci_ioctl: match buffer %p, length %u "
708 "isn't user accessible for WRITE\n",
709 cio->matches, cio->match_buf_len);
715 * Go through the list of devices and copy out the devices
716 * that match the user's criteria.
718 for (cio->num_matches = 0, error = 0, i = 0,
719 dinfo = STAILQ_FIRST(devlist_head);
720 (dinfo != NULL) && (cio->num_matches < ionum)
721 && (error == 0) && (i < pci_numdevs);
722 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
727 /* Populate pd_name and pd_unit */
729 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0')
730 name = device_get_name(dinfo->cfg.dev);
732 strncpy(dinfo->conf.pd_name, name,
733 sizeof(dinfo->conf.pd_name));
734 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0;
735 dinfo->conf.pd_unit =
736 device_get_unit(dinfo->cfg.dev);
739 if ((pattern_buf == NULL) ||
740 (pci_conf_match(pattern_buf, num_patterns,
741 &dinfo->conf) == 0)) {
744 * If we've filled up the user's buffer,
745 * break out at this point. Since we've
746 * got a match here, we'll pick right back
747 * up at the matching entry. We can also
748 * tell the user that there are more matches
751 if (cio->num_matches >= ionum)
754 error = copyout(&dinfo->conf,
755 &cio->matches[cio->num_matches],
756 sizeof(struct pci_conf));
762 * Set the pointer into the list, so if the user is getting
763 * n records at a time, where n < pci_numdevs,
768 * Set the generation, the user will need this if they make
769 * another ioctl call with offset != 0.
771 cio->generation = pci_generation;
774 * If this is the last device, inform the user so he won't
775 * bother asking for more devices. If dinfo isn't NULL, we
776 * know that there are more matches in the list because of
777 * the way the traversal is done.
780 cio->status = PCI_GETCONF_LAST_DEVICE;
782 cio->status = PCI_GETCONF_MORE_DEVS;
784 if (pattern_buf != NULL)
785 free(pattern_buf, M_TEMP);
790 io = (struct pci_io *)data;
791 switch(io->pi_width) {
797 probe.bus = io->pi_sel.pc_bus;
798 probe.slot = io->pi_sel.pc_dev;
799 probe.func = io->pi_sel.pc_func;
800 io->pi_data = pci_cfgread(&probe,
801 io->pi_reg, io->pi_width);
811 io = (struct pci_io *)data;
812 switch(io->pi_width) {
818 probe.bus = io->pi_sel.pc_bus;
819 probe.slot = io->pi_sel.pc_dev;
820 probe.func = io->pi_sel.pc_func;
822 io->pi_reg, io->pi_data, io->pi_width);
841 static struct cdevsw pcicdev = {
843 /* close */ pci_close,
846 /* ioctl */ pci_ioctl,
849 /* strategy */ nostrategy,
860 static devclass_t pci_devclass;
864 * A simple driver to wrap the old pci driver mechanism for back-compat.
868 pci_compat_probe(device_t dev)
870 struct pci_device *dvp;
871 struct pci_devinfo *dinfo;
876 dinfo = device_get_ivars(dev);
878 dvp = device_get_driver(dev)->priv;
881 * Do the wrapped probe.
884 if (dvp && dvp->pd_probe) {
885 name = dvp->pd_probe(cfg, (cfg->device << 16) + cfg->vendor);
887 device_set_desc_copy(dev, name);
888 /* Allow newbus drivers to match "better" */
897 pci_compat_attach(device_t dev)
899 struct pci_device *dvp;
900 struct pci_devinfo *dinfo;
904 dinfo = device_get_ivars(dev);
906 dvp = device_get_driver(dev)->priv;
908 unit = device_get_unit(dev);
909 if (unit > *dvp->pd_count)
910 *dvp->pd_count = unit;
912 dvp->pd_attach(cfg, unit);
913 device_printf(dev, "driver is using old-style compatability shims\n");
917 static device_method_t pci_compat_methods[] = {
918 /* Device interface */
919 DEVMETHOD(device_probe, pci_compat_probe),
920 DEVMETHOD(device_attach, pci_compat_attach),
926 * Create a new style driver around each old pci driver.
929 compat_pci_handler(module_t mod, int type, void *data)
931 struct pci_device *dvp = (struct pci_device *)data;
936 driver = malloc(sizeof(driver_t), M_DEVBUF, M_NOWAIT);
939 bzero(driver, sizeof(driver_t));
940 driver->name = dvp->pd_name;
941 driver->methods = pci_compat_methods;
942 driver->size = sizeof(struct pci_devinfo *);
944 devclass_add_driver(pci_devclass, driver);
947 printf("%s: module unload not supported!\n", dvp->pd_name);
957 * New style pci driver. Parent device is either a pci-host-bridge or a
958 * pci-pci-bridge. Both kinds are represented by instances of pcib.
962 pci_print_verbose(struct pci_devinfo *dinfo)
965 pcicfgregs *cfg = &dinfo->cfg;
967 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
968 cfg->vendor, cfg->device, cfg->revid);
969 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
970 cfg->baseclass, cfg->subclass, cfg->progif,
971 cfg->hdrtype, cfg->mfdev);
972 printf("\tsubordinatebus=%x \tsecondarybus=%x\n",
973 cfg->subordinatebus, cfg->secondarybus);
975 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
976 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
977 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
978 cfg->lattimer, cfg->lattimer * 30,
979 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
980 #endif /* PCI_DEBUG */
982 printf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline);
987 pci_porten(pcicfgregs *cfg)
989 return ((cfg->cmdreg & PCIM_CMD_PORTEN) != 0);
993 pci_memen(pcicfgregs *cfg)
995 return ((cfg->cmdreg & PCIM_CMD_MEMEN) != 0);
999 * Add a resource based on a pci map register. Return 1 if the map
1000 * register is a 32bit map register or 2 if it is a 64bit register.
1003 pci_add_map(device_t dev, pcicfgregs* cfg, int reg)
1005 struct pci_devinfo *dinfo = device_get_ivars(dev);
1006 struct resource_list *rl = &dinfo->resources;
1015 map = pci_cfgread(cfg, reg, 4);
1017 if (map == 0 || map == 0xffffffff)
1018 return 1; /* skip invalid entry */
1020 pci_cfgwrite(cfg, reg, 0xffffffff, 4);
1021 testval = pci_cfgread(cfg, reg, 4);
1022 pci_cfgwrite(cfg, reg, map, 4);
1024 base = pci_mapbase(map);
1025 if (pci_maptype(map) & PCI_MAPMEM)
1026 type = SYS_RES_MEMORY;
1028 type = SYS_RES_IOPORT;
1029 ln2size = pci_mapsize(testval);
1030 ln2range = pci_maprange(testval);
1031 if (ln2range == 64) {
1032 /* Read the other half of a 64bit map register */
1033 base |= (u_int64_t) pci_cfgread(cfg, reg + 4, 4) << 32;
1038 * XXX: encode hose number in the base addr,
1039 * This will go away once the bus_space functions
1040 * can deal with multiple hoses
1044 u_int32_t mask, shift, maxh;
1046 switch (hwrpb->rpb_type) {
1050 maxh = 4; /* not a hose. MCPCIA instance # */
1069 printf("base addr = 0x%llx\n", (long long) base);
1070 printf("mask addr = 0x%lx\n", (long) mask);
1071 printf("hacked addr = 0x%llx\n", (long long)
1072 (base | ((u_int64_t)cfg->hose << shift)));
1073 panic("hose encoding hack would clobber base addr");
1076 if (cfg->hose >= maxh) {
1077 panic("Hose %d - can only encode %d hose(s)",
1081 base |= ((u_int64_t)cfg->hose << shift);
1085 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d",
1086 reg, pci_maptype(map), ln2range,
1087 (unsigned int) base, ln2size);
1088 if (type == SYS_RES_IOPORT && !pci_porten(cfg))
1089 printf(", port disabled\n");
1090 else if (type == SYS_RES_MEMORY && !pci_memen(cfg))
1091 printf(", memory disabled\n");
1093 printf(", enabled\n");
1096 if (type == SYS_RES_IOPORT && !pci_porten(cfg))
1098 if (type == SYS_RES_MEMORY && !pci_memen(cfg))
1101 resource_list_add(rl, type, reg,
1102 base, base + (1 << ln2size) - 1,
1105 return (ln2range == 64) ? 2 : 1;
1109 pci_add_resources(device_t dev, pcicfgregs* cfg)
1111 struct pci_devinfo *dinfo = device_get_ivars(dev);
1112 struct resource_list *rl = &dinfo->resources;
1113 struct pci_quirk *q;
1116 for (i = 0; i < cfg->nummaps;) {
1117 i += pci_add_map(dev, cfg, PCIR_MAPS + i*4);
1120 for (q = &pci_quirks[0]; q->devid; q++) {
1121 if (q->devid == ((cfg->device << 16) | cfg->vendor)
1122 && q->type == PCI_QUIRK_MAP_REG)
1123 pci_add_map(dev, cfg, q->arg1);
1126 if (cfg->intpin > 0 && cfg->intline != 255)
1127 resource_list_add(rl, SYS_RES_IRQ, 0,
1128 cfg->intline, cfg->intline, 1);
1132 pci_add_children(device_t dev, int busno)
1138 #define PCI_SLOTMAX 0
1141 bzero(&probe, sizeof probe);
1143 probe.hose = pcib_get_hose(dev);
1150 for (probe.slot = 0; probe.slot <= PCI_SLOTMAX; probe.slot++) {
1151 int pcifunchigh = 0;
1152 for (probe.func = 0; probe.func <= pcifunchigh; probe.func++) {
1153 struct pci_devinfo *dinfo = pci_readcfg(&probe);
1154 if (dinfo != NULL) {
1155 if (dinfo->cfg.mfdev)
1158 pci_print_verbose(dinfo);
1159 dinfo->cfg.dev = device_add_child(dev, NULL, -1);
1160 device_set_ivars(dinfo->cfg.dev, dinfo);
1161 pci_add_resources(dinfo->cfg.dev, &dinfo->cfg);
1168 pci_new_probe(device_t dev)
1172 device_set_desc(dev, "PCI bus");
1173 pci_add_children(dev, device_get_unit(dev));
1175 make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, "pci");
1183 pci_print_resources(struct resource_list *rl, const char *name, int type,
1186 struct resource_list_entry *rle;
1187 int printed, retval;
1191 /* Yes, this is kinda cheating */
1192 SLIST_FOREACH(rle, rl, link) {
1193 if (rle->type == type) {
1195 retval += printf(" %s ", name);
1196 else if (printed > 0)
1197 retval += printf(",");
1199 retval += printf(format, rle->start);
1200 if (rle->count > 1) {
1201 retval += printf("-");
1202 retval += printf(format, rle->start +
1211 pci_print_child(device_t dev, device_t child)
1213 struct pci_devinfo *dinfo;
1214 struct resource_list *rl;
1218 dinfo = device_get_ivars(child);
1220 rl = &dinfo->resources;
1222 retval += bus_print_child_header(dev, child);
1224 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx");
1225 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx");
1226 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld");
1227 if (device_get_flags(dev))
1228 retval += printf(" flags %#x", device_get_flags(dev));
1230 retval += printf(" at device %d.%d", pci_get_slot(child),
1231 pci_get_function(child));
1233 retval += bus_print_child_footer(dev, child);
1239 pci_probe_nomatch(device_t dev, device_t child)
1241 struct pci_devinfo *dinfo;
1247 dinfo = device_get_ivars(child);
1249 desc = pci_ata_match(child);
1250 if (!desc) desc = pci_usb_match(child);
1251 if (!desc) desc = pci_vga_match(child);
1253 desc = "unknown card";
1256 device_printf(dev, "<%s>", desc);
1257 if (bootverbose || unknown) {
1258 printf(" (vendor=0x%04x, dev=0x%04x)",
1263 pci_get_slot(child),
1264 pci_get_function(child));
1265 if (cfg->intpin > 0 && cfg->intline != 255) {
1266 printf(" irq %d", cfg->intline);
1274 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1276 struct pci_devinfo *dinfo;
1279 dinfo = device_get_ivars(child);
1283 case PCI_IVAR_SUBVENDOR:
1284 *result = cfg->subvendor;
1286 case PCI_IVAR_SUBDEVICE:
1287 *result = cfg->subdevice;
1289 case PCI_IVAR_VENDOR:
1290 *result = cfg->vendor;
1292 case PCI_IVAR_DEVICE:
1293 *result = cfg->device;
1295 case PCI_IVAR_DEVID:
1296 *result = (cfg->device << 16) | cfg->vendor;
1298 case PCI_IVAR_CLASS:
1299 *result = cfg->baseclass;
1301 case PCI_IVAR_SUBCLASS:
1302 *result = cfg->subclass;
1304 case PCI_IVAR_PROGIF:
1305 *result = cfg->progif;
1307 case PCI_IVAR_REVID:
1308 *result = cfg->revid;
1310 case PCI_IVAR_INTPIN:
1311 *result = cfg->intpin;
1314 *result = cfg->intline;
1320 *result = cfg->slot;
1322 case PCI_IVAR_FUNCTION:
1323 *result = cfg->func;
1325 case PCI_IVAR_SECONDARYBUS:
1326 *result = cfg->secondarybus;
1328 case PCI_IVAR_SUBORDINATEBUS:
1329 *result = cfg->subordinatebus;
1333 * Pass up to parent bridge.
1335 *result = pcib_get_hose(dev);
1344 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1346 struct pci_devinfo *dinfo;
1349 dinfo = device_get_ivars(child);
1353 case PCI_IVAR_SUBVENDOR:
1354 case PCI_IVAR_SUBDEVICE:
1355 case PCI_IVAR_VENDOR:
1356 case PCI_IVAR_DEVICE:
1357 case PCI_IVAR_DEVID:
1358 case PCI_IVAR_CLASS:
1359 case PCI_IVAR_SUBCLASS:
1360 case PCI_IVAR_PROGIF:
1361 case PCI_IVAR_REVID:
1362 case PCI_IVAR_INTPIN:
1366 case PCI_IVAR_FUNCTION:
1367 return EINVAL; /* disallow for now */
1369 case PCI_IVAR_SECONDARYBUS:
1370 cfg->secondarybus = value;
1372 case PCI_IVAR_SUBORDINATEBUS:
1373 cfg->subordinatebus = value;
1381 static struct resource *
1382 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
1383 u_long start, u_long end, u_long count, u_int flags)
1385 struct pci_devinfo *dinfo = device_get_ivars(child);
1386 struct resource_list *rl = &dinfo->resources;
1388 return resource_list_alloc(rl, dev, child, type, rid,
1389 start, end, count, flags);
1393 pci_release_resource(device_t dev, device_t child, int type, int rid,
1396 struct pci_devinfo *dinfo = device_get_ivars(child);
1397 struct resource_list *rl = &dinfo->resources;
1399 return resource_list_release(rl, dev, child, type, rid, r);
1403 pci_set_resource(device_t dev, device_t child, int type, int rid,
1404 u_long start, u_long count)
1406 struct pci_devinfo *dinfo = device_get_ivars(child);
1407 struct resource_list *rl = &dinfo->resources;
1409 resource_list_add(rl, type, rid, start, start + count - 1, count);
1414 pci_get_resource(device_t dev, device_t child, int type, int rid,
1415 u_long *startp, u_long *countp)
1417 struct pci_devinfo *dinfo = device_get_ivars(child);
1418 struct resource_list *rl = &dinfo->resources;
1419 struct resource_list_entry *rle;
1421 rle = resource_list_find(rl, type, rid);
1426 *startp = rle->start;
1428 *countp = rle->count;
1434 pci_delete_resource(device_t dev, device_t child, int type, int rid)
1436 printf("pci_delete_resource: PCI resources can not be deleted\n");
1440 pci_read_config_method(device_t dev, device_t child, int reg, int width)
1442 struct pci_devinfo *dinfo = device_get_ivars(child);
1443 pcicfgregs *cfg = &dinfo->cfg;
1444 return pci_cfgread(cfg, reg, width);
1448 pci_write_config_method(device_t dev, device_t child, int reg,
1449 u_int32_t val, int width)
1451 struct pci_devinfo *dinfo = device_get_ivars(child);
1452 pcicfgregs *cfg = &dinfo->cfg;
1453 pci_cfgwrite(cfg, reg, val, width);
1457 pci_modevent(module_t mod, int what, void *arg)
1461 STAILQ_INIT(&pci_devq);
1471 static device_method_t pci_methods[] = {
1472 /* Device interface */
1473 DEVMETHOD(device_probe, pci_new_probe),
1474 DEVMETHOD(device_attach, bus_generic_attach),
1475 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1476 DEVMETHOD(device_suspend, bus_generic_suspend),
1477 DEVMETHOD(device_resume, bus_generic_resume),
1480 DEVMETHOD(bus_print_child, pci_print_child),
1481 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
1482 DEVMETHOD(bus_read_ivar, pci_read_ivar),
1483 DEVMETHOD(bus_write_ivar, pci_write_ivar),
1484 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
1485 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
1486 DEVMETHOD(bus_release_resource, pci_release_resource),
1487 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
1488 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
1489 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
1490 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
1491 DEVMETHOD(bus_set_resource, pci_set_resource),
1492 DEVMETHOD(bus_get_resource, pci_get_resource),
1493 DEVMETHOD(bus_delete_resource, pci_delete_resource),
1496 DEVMETHOD(pci_read_config, pci_read_config_method),
1497 DEVMETHOD(pci_write_config, pci_write_config_method),
1502 static driver_t pci_driver = {
1508 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);