2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000, BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/linker.h>
39 #include <sys/fcntl.h>
41 #include <sys/kernel.h>
42 #include <sys/queue.h>
43 #include <sys/sysctl.h>
44 #include <sys/types.h>
48 #include <vm/vm_extern.h>
51 #include <machine/bus.h>
53 #include <machine/resource.h>
55 #include <sys/pciio.h>
56 #include <dev/pci/pcireg.h>
57 #include <dev/pci/pcivar.h>
58 #include <dev/pci/pci_private.h>
63 #if (defined(__i386__) && !defined(PC98)) || defined(__amd64__) || \
65 #include <contrib/dev/acpica/acpi.h>
68 #define ACPI_PWR_FOR_SLEEP(x, y, z)
71 static uint32_t pci_mapbase(unsigned mapreg);
72 static int pci_maptype(unsigned mapreg);
73 static int pci_mapsize(unsigned testval);
74 static int pci_maprange(unsigned mapreg);
75 static void pci_fixancient(pcicfgregs *cfg);
77 static int pci_porten(device_t pcib, int b, int s, int f);
78 static int pci_memen(device_t pcib, int b, int s, int f);
79 static void pci_assign_interrupt(device_t bus, device_t dev,
81 static int pci_add_map(device_t pcib, device_t bus, device_t dev,
82 int b, int s, int f, int reg,
83 struct resource_list *rl, int force, int prefetch);
84 static int pci_probe(device_t dev);
85 static int pci_attach(device_t dev);
86 static void pci_load_vendor_data(void);
87 static int pci_describe_parse_line(char **ptr, int *vendor,
88 int *device, char **desc);
89 static char *pci_describe_device(device_t dev);
90 static int pci_modevent(module_t mod, int what, void *arg);
91 static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
93 static void pci_read_extcap(device_t pcib, pcicfgregs *cfg);
95 static device_method_t pci_methods[] = {
96 /* Device interface */
97 DEVMETHOD(device_probe, pci_probe),
98 DEVMETHOD(device_attach, pci_attach),
99 DEVMETHOD(device_detach, bus_generic_detach),
100 DEVMETHOD(device_shutdown, bus_generic_shutdown),
101 DEVMETHOD(device_suspend, pci_suspend),
102 DEVMETHOD(device_resume, pci_resume),
105 DEVMETHOD(bus_print_child, pci_print_child),
106 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
107 DEVMETHOD(bus_read_ivar, pci_read_ivar),
108 DEVMETHOD(bus_write_ivar, pci_write_ivar),
109 DEVMETHOD(bus_driver_added, pci_driver_added),
110 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
111 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
113 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
114 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
115 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
116 DEVMETHOD(bus_delete_resource, pci_delete_resource),
117 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
118 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
119 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
120 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
121 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
122 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
125 DEVMETHOD(pci_read_config, pci_read_config_method),
126 DEVMETHOD(pci_write_config, pci_write_config_method),
127 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
128 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
129 DEVMETHOD(pci_enable_io, pci_enable_io_method),
130 DEVMETHOD(pci_disable_io, pci_disable_io_method),
131 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
132 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
133 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
134 DEVMETHOD(pci_find_extcap, pci_find_extcap_method),
139 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0);
141 devclass_t pci_devclass;
142 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
143 MODULE_VERSION(pci, 1);
145 static char *pci_vendordata;
146 static size_t pci_vendordata_size;
150 uint32_t devid; /* Vendor/device of the card */
152 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
157 struct pci_quirk pci_quirks[] = {
158 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */
159 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
160 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
161 /* As does the Serverworks OSB4 (the SMBus mapping register) */
162 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
167 /* map register information */
168 #define PCI_MAPMEM 0x01 /* memory map */
169 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
170 #define PCI_MAPPORT 0x04 /* port map */
172 struct devlist pci_devq;
173 uint32_t pci_generation;
174 uint32_t pci_numdevs = 0;
177 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters");
179 static int pci_enable_io_modes = 1;
180 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes);
181 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW,
182 &pci_enable_io_modes, 1,
183 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\
184 enable these bits correctly. We'd like to do this all the time, but there\n\
185 are some peripherals that this causes problems with.");
187 static int pci_do_power_nodriver = 0;
188 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver);
189 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW,
190 &pci_do_power_nodriver, 0,
191 "Place a function into D3 state when no driver attaches to it. 0 means\n\
192 disable. 1 means conservatively place devices into D3 state. 2 means\n\
193 agressively place devices into D3 state. 3 means put absolutely everything\n\
196 static int pci_do_power_resume = 1;
197 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume);
198 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW,
199 &pci_do_power_resume, 1,
200 "Transition from D3 -> D0 on resume.");
202 /* Find a device_t by bus/slot/function */
205 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
207 struct pci_devinfo *dinfo;
209 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
210 if ((dinfo->cfg.bus == bus) &&
211 (dinfo->cfg.slot == slot) &&
212 (dinfo->cfg.func == func)) {
213 return (dinfo->cfg.dev);
220 /* Find a device_t by vendor/device ID */
223 pci_find_device(uint16_t vendor, uint16_t device)
225 struct pci_devinfo *dinfo;
227 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
228 if ((dinfo->cfg.vendor == vendor) &&
229 (dinfo->cfg.device == device)) {
230 return (dinfo->cfg.dev);
237 /* return base address of memory or port map */
240 pci_mapbase(unsigned mapreg)
243 if ((mapreg & 0x01) == 0)
245 return (mapreg & ~mask);
248 /* return map type of memory or port map */
251 pci_maptype(unsigned mapreg)
253 static uint8_t maptype[0x10] = {
254 PCI_MAPMEM, PCI_MAPPORT,
256 PCI_MAPMEM, PCI_MAPPORT,
258 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
259 PCI_MAPMEM|PCI_MAPMEMP, 0,
260 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
264 return maptype[mapreg & 0x0f];
267 /* return log2 of map size decoded for memory or port map */
270 pci_mapsize(unsigned testval)
274 testval = pci_mapbase(testval);
277 while ((testval & 1) == 0)
286 /* return log2 of address range supported by map register */
289 pci_maprange(unsigned mapreg)
292 switch (mapreg & 0x07) {
308 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
311 pci_fixancient(pcicfgregs *cfg)
313 if (cfg->hdrtype != 0)
316 /* PCI to PCI bridges use header type 1 */
317 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
321 /* extract header type specific config data */
324 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
326 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
327 switch (cfg->hdrtype) {
329 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
330 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
331 cfg->nummaps = PCI_MAXMAPS_0;
334 cfg->subvendor = REG(PCIR_SUBVEND_1, 2);
335 cfg->subdevice = REG(PCIR_SUBDEV_1, 2);
336 cfg->nummaps = PCI_MAXMAPS_1;
339 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
340 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
341 cfg->nummaps = PCI_MAXMAPS_2;
347 /* read configuration header into pcicfgregs structure */
350 pci_read_device(device_t pcib, int b, int s, int f, size_t size)
352 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
353 pcicfgregs *cfg = NULL;
354 struct pci_devinfo *devlist_entry;
355 struct devlist *devlist_head;
357 devlist_head = &pci_devq;
359 devlist_entry = NULL;
361 if (REG(PCIR_DEVVENDOR, 4) != -1) {
362 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
363 if (devlist_entry == NULL)
366 cfg = &devlist_entry->cfg;
371 cfg->vendor = REG(PCIR_VENDOR, 2);
372 cfg->device = REG(PCIR_DEVICE, 2);
373 cfg->cmdreg = REG(PCIR_COMMAND, 2);
374 cfg->statreg = REG(PCIR_STATUS, 2);
375 cfg->baseclass = REG(PCIR_CLASS, 1);
376 cfg->subclass = REG(PCIR_SUBCLASS, 1);
377 cfg->progif = REG(PCIR_PROGIF, 1);
378 cfg->revid = REG(PCIR_REVID, 1);
379 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
380 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
381 cfg->lattimer = REG(PCIR_LATTIMER, 1);
382 cfg->intpin = REG(PCIR_INTPIN, 1);
383 cfg->intline = REG(PCIR_INTLINE, 1);
385 cfg->mingnt = REG(PCIR_MINGNT, 1);
386 cfg->maxlat = REG(PCIR_MAXLAT, 1);
388 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
389 cfg->hdrtype &= ~PCIM_MFDEV;
392 pci_hdrtypedata(pcib, b, s, f, cfg);
394 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
395 pci_read_extcap(pcib, cfg);
397 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
399 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
400 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
401 devlist_entry->conf.pc_sel.pc_func = cfg->func;
402 devlist_entry->conf.pc_hdr = cfg->hdrtype;
404 devlist_entry->conf.pc_subvendor = cfg->subvendor;
405 devlist_entry->conf.pc_subdevice = cfg->subdevice;
406 devlist_entry->conf.pc_vendor = cfg->vendor;
407 devlist_entry->conf.pc_device = cfg->device;
409 devlist_entry->conf.pc_class = cfg->baseclass;
410 devlist_entry->conf.pc_subclass = cfg->subclass;
411 devlist_entry->conf.pc_progif = cfg->progif;
412 devlist_entry->conf.pc_revid = cfg->revid;
417 return (devlist_entry);
422 pci_read_extcap(device_t pcib, pcicfgregs *cfg)
424 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
425 int ptr, nextptr, ptrptr;
427 switch (cfg->hdrtype & PCIM_HDRTYPE) {
429 ptrptr = PCIR_CAP_PTR;
432 ptrptr = PCIR_CAP_PTR_2;
435 return; /* no extended capabilities support */
437 nextptr = REG(ptrptr, 1); /* sanity check? */
440 * Read capability entries.
442 while (nextptr != 0) {
445 printf("illegal PCI extended capability offset %d\n",
449 /* Find the next entry */
451 nextptr = REG(ptr + PCICAP_NEXTPTR, 1);
453 /* Process this entry */
454 switch (REG(ptr + PCICAP_ID, 1)) {
455 case PCIY_PMG: /* PCI power management */
456 if (cfg->pp.pp_cap == 0) {
457 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
458 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS;
459 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR;
460 if ((nextptr - ptr) > PCIR_POWER_DATA)
461 cfg->pp.pp_data = ptr + PCIR_POWER_DATA;
464 case PCIY_MSI: /* PCI MSI */
465 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
466 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT)
467 cfg->msi.msi_data = PCIR_MSI_DATA_64BIT;
469 cfg->msi.msi_data = PCIR_MSI_DATA;
470 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl &
471 PCIM_MSICTRL_MMC_MASK)>>1);
480 * Return the offset in configuration space of the requested extended
481 * capability entry or 0 if the specified capability was not found.
484 pci_find_extcap_method(device_t dev, device_t child, int capability,
487 struct pci_devinfo *dinfo = device_get_ivars(child);
488 pcicfgregs *cfg = &dinfo->cfg;
493 * Check the CAP_LIST bit of the PCI status register first.
495 status = pci_read_config(child, PCIR_STATUS, 2);
496 if (!(status & PCIM_STATUS_CAPPRESENT))
500 * Determine the start pointer of the capabilities list.
502 switch (cfg->hdrtype & PCIM_HDRTYPE) {
507 ptr = PCIR_CAP_PTR_2;
511 return (ENXIO); /* no extended capabilities support */
513 ptr = pci_read_config(child, ptr, 1);
516 * Traverse the capabilities list.
519 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
524 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
530 /* free pcicfgregs structure and all depending data structures */
533 pci_freecfg(struct pci_devinfo *dinfo)
535 struct devlist *devlist_head;
537 devlist_head = &pci_devq;
539 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
540 free(dinfo, M_DEVBUF);
542 /* increment the generation count */
545 /* we're losing one device */
551 * PCI power manangement
554 pci_set_powerstate_method(device_t dev, device_t child, int state)
556 struct pci_devinfo *dinfo = device_get_ivars(child);
557 pcicfgregs *cfg = &dinfo->cfg;
559 int result, oldstate, highest, delay;
561 if (cfg->pp.pp_cap == 0)
565 * Optimize a no state change request away. While it would be OK to
566 * write to the hardware in theory, some devices have shown odd
567 * behavior when going from D3 -> D3.
569 oldstate = pci_get_powerstate(child);
570 if (oldstate == state)
574 * The PCI power management specification states that after a state
575 * transition between PCI power states, system software must
576 * guarantee a minimal delay before the function accesses the device.
577 * Compute the worst case delay that we need to guarantee before we
578 * access the device. Many devices will be responsive much more
579 * quickly than this delay, but there are some that don't respond
580 * instantly to state changes. Transitions to/from D3 state require
581 * 10ms, while D2 requires 200us, and D0/1 require none. The delay
582 * is done below with DELAY rather than a sleeper function because
583 * this function can be called from contexts where we cannot sleep.
585 highest = (oldstate > state) ? oldstate : state;
586 if (highest == PCI_POWERSTATE_D3)
588 else if (highest == PCI_POWERSTATE_D2)
592 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
596 case PCI_POWERSTATE_D0:
597 status |= PCIM_PSTAT_D0;
599 case PCI_POWERSTATE_D1:
600 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
602 status |= PCIM_PSTAT_D1;
604 case PCI_POWERSTATE_D2:
605 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
607 status |= PCIM_PSTAT_D2;
609 case PCI_POWERSTATE_D3:
610 status |= PCIM_PSTAT_D3;
618 "pci%d:%d:%d: Transition from D%d to D%d\n",
619 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func,
622 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
629 pci_get_powerstate_method(device_t dev, device_t child)
631 struct pci_devinfo *dinfo = device_get_ivars(child);
632 pcicfgregs *cfg = &dinfo->cfg;
636 if (cfg->pp.pp_cap != 0) {
637 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
638 switch (status & PCIM_PSTAT_DMASK) {
640 result = PCI_POWERSTATE_D0;
643 result = PCI_POWERSTATE_D1;
646 result = PCI_POWERSTATE_D2;
649 result = PCI_POWERSTATE_D3;
652 result = PCI_POWERSTATE_UNKNOWN;
656 /* No support, device is always at D0 */
657 result = PCI_POWERSTATE_D0;
663 * Some convenience functions for PCI device drivers.
667 pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
671 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
673 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
677 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
681 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
683 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
687 pci_enable_busmaster_method(device_t dev, device_t child)
689 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
694 pci_disable_busmaster_method(device_t dev, device_t child)
696 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
701 pci_enable_io_method(device_t dev, device_t child, int space)
712 bit = PCIM_CMD_PORTEN;
716 bit = PCIM_CMD_MEMEN;
722 pci_set_command_bit(dev, child, bit);
723 /* Some devices seem to need a brief stall here, what do to? */
724 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
727 device_printf(child, "failed to enable %s mapping!\n", error);
732 pci_disable_io_method(device_t dev, device_t child, int space)
743 bit = PCIM_CMD_PORTEN;
747 bit = PCIM_CMD_MEMEN;
753 pci_clear_command_bit(dev, child, bit);
754 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
756 device_printf(child, "failed to disable %s mapping!\n", error);
763 * New style pci driver. Parent device is either a pci-host-bridge or a
764 * pci-pci-bridge. Both kinds are represented by instances of pcib.
768 pci_print_verbose(struct pci_devinfo *dinfo)
771 pcicfgregs *cfg = &dinfo->cfg;
773 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
774 cfg->vendor, cfg->device, cfg->revid);
775 printf("\tbus=%d, slot=%d, func=%d\n",
776 cfg->bus, cfg->slot, cfg->func);
777 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
778 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
780 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
781 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
782 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
783 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
784 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
786 printf("\tintpin=%c, irq=%d\n",
787 cfg->intpin +'a' -1, cfg->intline);
788 if (cfg->pp.pp_cap) {
791 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
792 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
793 cfg->pp.pp_cap & PCIM_PCAP_SPEC,
794 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
795 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
796 status & PCIM_PSTAT_DMASK);
798 if (cfg->msi.msi_data) {
801 ctrl = cfg->msi.msi_ctrl;
802 printf("\tMSI supports %d message%s%s%s\n",
804 (cfg->msi.msi_msgnum == 1) ? "" : "s",
805 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
806 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");
812 pci_porten(device_t pcib, int b, int s, int f)
814 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
815 & PCIM_CMD_PORTEN) != 0;
819 pci_memen(device_t pcib, int b, int s, int f)
821 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
822 & PCIM_CMD_MEMEN) != 0;
826 * Add a resource based on a pci map register. Return 1 if the map
827 * register is a 32bit map register or 2 if it is a 64bit register.
830 pci_add_map(device_t pcib, device_t bus, device_t dev,
831 int b, int s, int f, int reg, struct resource_list *rl, int force,
836 uint64_t start, end, count;
843 struct resource *res;
845 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
846 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
847 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
848 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
850 if (pci_maptype(map) & PCI_MAPMEM)
851 type = SYS_RES_MEMORY;
853 type = SYS_RES_IOPORT;
854 ln2size = pci_mapsize(testval);
855 ln2range = pci_maprange(testval);
856 base = pci_mapbase(map);
857 barlen = ln2range == 64 ? 2 : 1;
860 * For I/O registers, if bottom bit is set, and the next bit up
861 * isn't clear, we know we have a BAR that doesn't conform to the
862 * spec, so ignore it. Also, sanity check the size of the data
863 * areas to the type of memory involved. Memory must be at least
864 * 32 bytes in size, while I/O ranges must be at least 4.
866 if ((testval & 0x1) == 0x1 &&
867 (testval & 0x2) != 0)
869 if ((type == SYS_RES_MEMORY && ln2size < 5) ||
870 (type == SYS_RES_IOPORT && ln2size < 2))
874 /* Read the other half of a 64bit map register */
875 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32;
878 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d",
879 reg, pci_maptype(map), ln2range,
880 (unsigned int) base, ln2size);
881 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
882 printf(", port disabled\n");
883 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
884 printf(", memory disabled\n");
886 printf(", enabled\n");
890 * If base is 0, then we have problems. It is best to ignore
891 * such entries for the moment. These will be allocated later if
892 * the driver specifically requests them. However, some
893 * removable busses look better when all resources are allocated,
894 * so allow '0' to be overriden.
896 * Similarly treat maps whose values is the same as the test value
897 * read back. These maps have had all f's written to them by the
898 * BIOS in an attempt to disable the resources.
900 if (!force && (base == 0 || map == testval)) {
902 printf("ignored rid %#x: base %#llx map %#x testval %#x\n",
903 reg, base, map, testval);
908 * This code theoretically does the right thing, but has
909 * undesirable side effects in some cases where peripherals
910 * respond oddly to having these bits enabled. Let the user
911 * be able to turn them off (since pci_enable_io_modes is 1 by
914 if (pci_enable_io_modes) {
915 /* Turn on resources that have been left off by a lazy BIOS */
916 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
917 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
918 cmd |= PCIM_CMD_PORTEN;
919 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
921 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
922 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
923 cmd |= PCIM_CMD_MEMEN;
924 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
927 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
929 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
933 count = 1 << ln2size;
934 if (base == 0 || base == pci_mapbase(testval)) {
935 start = 0; /* Let the parent deside */
939 end = base + (1 << ln2size) - 1;
941 resource_list_add(rl, type, reg, start, end, count);
944 * Not quite sure what to do on failure of allocating the resource
945 * since I can postulate several right answers.
947 res = resource_list_alloc(rl, bus, dev, type, ®, start, end, count,
948 prefetch ? RF_PREFETCHABLE : 0);
950 printf("alloc failed\n");
952 printf("Allocated for %#x: start %#lx end %#lx\n", reg, rman_get_start(res), rman_get_end(res));
954 pci_write_config(dev, reg, rman_get_start(res), 4);
959 * For ATA devices we need to decide early what addressing mode to use.
960 * Legacy demands that the primary and secondary ATA ports sits on the
961 * same addresses that old ISA hardware did. This dictates that we use
962 * those addresses and ignore the BAR's if we cannot set PCI native
966 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b,
967 int s, int f, struct resource_list *rl, int force, uint32_t prefetchmask)
969 int rid, type, progif;
971 /* if this device supports PCI native addressing use it */
972 progif = pci_read_config(dev, PCIR_PROGIF, 1);
973 if ((progif & 0x8a) == 0x8a) {
974 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
975 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
976 printf("Trying ATA native PCI addressing mode\n");
977 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
981 progif = pci_read_config(dev, PCIR_PROGIF, 1);
982 type = SYS_RES_IOPORT;
983 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
984 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl, force,
985 prefetchmask & (1 << 0));
986 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl, force,
987 prefetchmask & (1 << 1));
990 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
991 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8,
994 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
995 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1,
998 if (progif & PCIP_STORAGE_IDE_MODESEC) {
999 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl, force,
1000 prefetchmask & (1 << 2));
1001 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl, force,
1002 prefetchmask & (1 << 3));
1005 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
1006 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8,
1009 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
1010 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1,
1013 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl, force,
1014 prefetchmask & (1 << 4));
1015 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl, force,
1016 prefetchmask & (1 << 5));
1020 pci_assign_interrupt(device_t bus, device_t dev, int force_route)
1022 struct pci_devinfo *dinfo = device_get_ivars(dev);
1023 pcicfgregs *cfg = &dinfo->cfg;
1024 char tunable_name[64];
1027 /* Has to have an intpin to have an interrupt. */
1028 if (cfg->intpin == 0)
1031 /* Let the user override the IRQ with a tunable. */
1032 irq = PCI_INVALID_IRQ;
1033 snprintf(tunable_name, sizeof(tunable_name), "hw.pci%d.%d.INT%c.irq",
1034 cfg->bus, cfg->slot, cfg->intpin + 'A' - 1);
1035 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0))
1036 irq = PCI_INVALID_IRQ;
1039 * If we didn't get an IRQ via the tunable, then we either use the
1040 * IRQ value in the intline register or we ask the bus to route an
1041 * interrupt for us. If force_route is true, then we only use the
1042 * value in the intline register if the bus was unable to assign an
1045 if (!PCI_INTERRUPT_VALID(irq)) {
1046 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
1047 irq = PCI_ASSIGN_INTERRUPT(bus, dev);
1048 if (!PCI_INTERRUPT_VALID(irq))
1052 /* If after all that we don't have an IRQ, just bail. */
1053 if (!PCI_INTERRUPT_VALID(irq))
1056 /* Update the config register if it changed. */
1057 if (irq != cfg->intline) {
1059 pci_write_config(dev, PCIR_INTLINE, irq, 1);
1062 /* Add this IRQ as rid 0 interrupt resource. */
1063 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1);
1067 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask)
1070 struct pci_devinfo *dinfo = device_get_ivars(dev);
1071 pcicfgregs *cfg = &dinfo->cfg;
1072 struct resource_list *rl = &dinfo->resources;
1073 struct pci_quirk *q;
1076 pcib = device_get_parent(bus);
1082 /* ATA devices needs special map treatment */
1083 if ((pci_get_class(dev) == PCIC_STORAGE) &&
1084 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
1085 (pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV))
1086 pci_ata_maps(pcib, bus, dev, b, s, f, rl, force, prefetchmask);
1088 for (i = 0; i < cfg->nummaps;)
1089 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i),
1090 rl, force, prefetchmask & (1 << i));
1093 * Add additional, quirked resources.
1095 for (q = &pci_quirks[0]; q->devid; q++) {
1096 if (q->devid == ((cfg->device << 16) | cfg->vendor)
1097 && q->type == PCI_QUIRK_MAP_REG)
1098 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl,
1102 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
1103 #if defined(__ia64__) || defined(__i386__) || defined(__amd64__) || \
1104 defined(__arm__) || defined(__alpha__)
1106 * Try to re-route interrupts. Sometimes the BIOS or
1107 * firmware may leave bogus values in these registers.
1108 * If the re-route fails, then just stick with what we
1111 pci_assign_interrupt(bus, dev, 1);
1113 pci_assign_interrupt(bus, dev, 0);
1119 pci_add_children(device_t dev, int busno, size_t dinfo_size)
1121 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
1122 device_t pcib = device_get_parent(dev);
1123 struct pci_devinfo *dinfo;
1125 int s, f, pcifunchigh;
1128 KASSERT(dinfo_size >= sizeof(struct pci_devinfo),
1129 ("dinfo_size too small"));
1130 maxslots = PCIB_MAXSLOTS(pcib);
1131 for (s = 0; s <= maxslots; s++) {
1135 hdrtype = REG(PCIR_HDRTYPE, 1);
1136 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
1138 if (hdrtype & PCIM_MFDEV)
1139 pcifunchigh = PCI_FUNCMAX;
1140 for (f = 0; f <= pcifunchigh; f++) {
1141 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size);
1142 if (dinfo != NULL) {
1143 pci_add_child(dev, dinfo);
1151 pci_add_child(device_t bus, struct pci_devinfo *dinfo)
1153 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
1154 device_set_ivars(dinfo->cfg.dev, dinfo);
1155 resource_list_init(&dinfo->resources);
1156 pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
1157 pci_cfg_restore(dinfo->cfg.dev, dinfo);
1158 pci_print_verbose(dinfo);
1159 pci_add_resources(bus, dinfo->cfg.dev, 0, 0);
1163 pci_probe(device_t dev)
1166 device_set_desc(dev, "PCI bus");
1168 /* Allow other subclasses to override this driver. */
1173 pci_attach(device_t dev)
1178 * Since there can be multiple independantly numbered PCI
1179 * busses on some large alpha systems, we can't use the unit
1180 * number to decide what bus we are probing. We ask the parent
1181 * pcib what our bus number is.
1183 busno = pcib_get_bus(dev);
1185 device_printf(dev, "physical bus=%d\n", busno);
1187 pci_add_children(dev, busno, sizeof(struct pci_devinfo));
1189 return (bus_generic_attach(dev));
1193 pci_suspend(device_t dev)
1195 int dstate, error, i, numdevs;
1196 device_t acpi_dev, child, *devlist;
1197 struct pci_devinfo *dinfo;
1200 * Save the PCI configuration space for each child and set the
1201 * device in the appropriate power state for this sleep state.
1204 if (pci_do_power_resume)
1205 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
1206 device_get_children(dev, &devlist, &numdevs);
1207 for (i = 0; i < numdevs; i++) {
1209 dinfo = (struct pci_devinfo *) device_get_ivars(child);
1210 pci_cfg_save(child, dinfo, 0);
1213 /* Suspend devices before potentially powering them down. */
1214 error = bus_generic_suspend(dev);
1216 free(devlist, M_TEMP);
1221 * Always set the device to D3. If ACPI suggests a different
1222 * power state, use it instead. If ACPI is not present, the
1223 * firmware is responsible for managing device power. Skip
1224 * children who aren't attached since they are powered down
1225 * separately. Only manage type 0 devices for now.
1227 for (i = 0; acpi_dev && i < numdevs; i++) {
1229 dinfo = (struct pci_devinfo *) device_get_ivars(child);
1230 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) {
1231 dstate = PCI_POWERSTATE_D3;
1232 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate);
1233 pci_set_powerstate(child, dstate);
1236 free(devlist, M_TEMP);
1241 pci_resume(device_t dev)
1244 device_t acpi_dev, child, *devlist;
1245 struct pci_devinfo *dinfo;
1248 * Set each child to D0 and restore its PCI configuration space.
1251 if (pci_do_power_resume)
1252 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
1253 device_get_children(dev, &devlist, &numdevs);
1254 for (i = 0; i < numdevs; i++) {
1256 * Notify ACPI we're going to D0 but ignore the result. If
1257 * ACPI is not present, the firmware is responsible for
1258 * managing device power. Only manage type 0 devices for now.
1261 dinfo = (struct pci_devinfo *) device_get_ivars(child);
1262 if (acpi_dev && device_is_attached(child) &&
1263 dinfo->cfg.hdrtype == 0) {
1264 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL);
1265 pci_set_powerstate(child, PCI_POWERSTATE_D0);
1268 /* Now the device is powered up, restore its config space. */
1269 pci_cfg_restore(child, dinfo);
1271 free(devlist, M_TEMP);
1272 return (bus_generic_resume(dev));
1276 pci_load_vendor_data(void)
1278 caddr_t vendordata, info;
1280 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) {
1281 info = preload_search_info(vendordata, MODINFO_ADDR);
1282 pci_vendordata = *(char **)info;
1283 info = preload_search_info(vendordata, MODINFO_SIZE);
1284 pci_vendordata_size = *(size_t *)info;
1285 /* terminate the database */
1286 pci_vendordata[pci_vendordata_size] = '\n';
1291 pci_driver_added(device_t dev, driver_t *driver)
1296 struct pci_devinfo *dinfo;
1300 device_printf(dev, "driver added\n");
1301 DEVICE_IDENTIFY(driver, dev);
1302 device_get_children(dev, &devlist, &numdevs);
1303 for (i = 0; i < numdevs; i++) {
1305 if (device_get_state(child) != DS_NOTPRESENT)
1307 dinfo = device_get_ivars(child);
1308 pci_print_verbose(dinfo);
1310 printf("pci%d:%d:%d: reprobing on driver added\n",
1311 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func);
1312 pci_cfg_restore(child, dinfo);
1313 if (device_probe_and_attach(child) != 0)
1314 pci_cfg_save(child, dinfo, 1);
1316 free(devlist, M_TEMP);
1320 pci_print_child(device_t dev, device_t child)
1322 struct pci_devinfo *dinfo;
1323 struct resource_list *rl;
1326 dinfo = device_get_ivars(child);
1327 rl = &dinfo->resources;
1329 retval += bus_print_child_header(dev, child);
1331 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx");
1332 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
1333 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
1334 if (device_get_flags(dev))
1335 retval += printf(" flags %#x", device_get_flags(dev));
1337 retval += printf(" at device %d.%d", pci_get_slot(child),
1338 pci_get_function(child));
1340 retval += bus_print_child_footer(dev, child);
1350 } pci_nomatch_tab[] = {
1351 {PCIC_OLD, -1, "old"},
1352 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"},
1353 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"},
1354 {PCIC_STORAGE, -1, "mass storage"},
1355 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"},
1356 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"},
1357 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"},
1358 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"},
1359 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"},
1360 {PCIC_NETWORK, -1, "network"},
1361 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"},
1362 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"},
1363 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"},
1364 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"},
1365 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"},
1366 {PCIC_DISPLAY, -1, "display"},
1367 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"},
1368 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"},
1369 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"},
1370 {PCIC_MULTIMEDIA, -1, "multimedia"},
1371 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"},
1372 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"},
1373 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"},
1374 {PCIC_MEMORY, -1, "memory"},
1375 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"},
1376 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"},
1377 {PCIC_BRIDGE, -1, "bridge"},
1378 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"},
1379 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"},
1380 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"},
1381 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"},
1382 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"},
1383 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"},
1384 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"},
1385 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"},
1386 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"},
1387 {PCIC_SIMPLECOMM, -1, "simple comms"},
1388 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */
1389 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"},
1390 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"},
1391 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"},
1392 {PCIC_BASEPERIPH, -1, "base peripheral"},
1393 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"},
1394 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"},
1395 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"},
1396 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"},
1397 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"},
1398 {PCIC_INPUTDEV, -1, "input device"},
1399 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"},
1400 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"},
1401 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"},
1402 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"},
1403 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"},
1404 {PCIC_DOCKING, -1, "docking station"},
1405 {PCIC_PROCESSOR, -1, "processor"},
1406 {PCIC_SERIALBUS, -1, "serial bus"},
1407 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"},
1408 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"},
1409 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"},
1410 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"},
1411 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"},
1412 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"},
1413 {PCIC_WIRELESS, -1, "wireless controller"},
1414 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"},
1415 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"},
1416 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"},
1417 {PCIC_INTELLIIO, -1, "intelligent I/O controller"},
1418 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"},
1419 {PCIC_SATCOM, -1, "satellite communication"},
1420 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"},
1421 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"},
1422 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"},
1423 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"},
1424 {PCIC_CRYPTO, -1, "encrypt/decrypt"},
1425 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"},
1426 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "entertainment crypto"},
1427 {PCIC_DASP, -1, "dasp"},
1428 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"},
1433 pci_probe_nomatch(device_t dev, device_t child)
1436 char *cp, *scp, *device;
1439 * Look for a listing for this device in a loaded device database.
1441 if ((device = pci_describe_device(child)) != NULL) {
1442 device_printf(dev, "<%s>", device);
1443 free(device, M_DEVBUF);
1446 * Scan the class/subclass descriptions for a general
1451 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) {
1452 if (pci_nomatch_tab[i].class == pci_get_class(child)) {
1453 if (pci_nomatch_tab[i].subclass == -1) {
1454 cp = pci_nomatch_tab[i].desc;
1455 } else if (pci_nomatch_tab[i].subclass ==
1456 pci_get_subclass(child)) {
1457 scp = pci_nomatch_tab[i].desc;
1461 device_printf(dev, "<%s%s%s>",
1463 ((cp != NULL) && (scp != NULL)) ? ", " : "",
1466 printf(" at device %d.%d (no driver attached)\n",
1467 pci_get_slot(child), pci_get_function(child));
1468 if (pci_do_power_nodriver)
1470 (struct pci_devinfo *) device_get_ivars(child), 1);
1475 * Parse the PCI device database, if loaded, and return a pointer to a
1476 * description of the device.
1478 * The database is flat text formatted as follows:
1480 * Any line not in a valid format is ignored.
1481 * Lines are terminated with newline '\n' characters.
1483 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then
1486 * A DEVICE line is entered immediately below the corresponding VENDOR ID.
1487 * - devices cannot be listed without a corresponding VENDOR line.
1488 * A DEVICE line consists of a TAB, the 4 digit (hex) device code,
1489 * another TAB, then the device name.
1493 * Assuming (ptr) points to the beginning of a line in the database,
1494 * return the vendor or device and description of the next entry.
1495 * The value of (vendor) or (device) inappropriate for the entry type
1496 * is set to -1. Returns nonzero at the end of the database.
1498 * Note that this is slightly unrobust in the face of corrupt data;
1499 * we attempt to safeguard against this by spamming the end of the
1500 * database with a newline when we initialise.
1503 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc)
1512 left = pci_vendordata_size - (cp - pci_vendordata);
1520 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2)
1524 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2)
1527 /* skip to next line */
1528 while (*cp != '\n' && left > 0) {
1537 /* skip to next line */
1538 while (*cp != '\n' && left > 0) {
1542 if (*cp == '\n' && left > 0)
1549 pci_describe_device(device_t dev)
1552 char *desc, *vp, *dp, *line;
1554 desc = vp = dp = NULL;
1557 * If we have no vendor data, we can't do anything.
1559 if (pci_vendordata == NULL)
1563 * Scan the vendor data looking for this device
1565 line = pci_vendordata;
1566 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
1569 if (pci_describe_parse_line(&line, &vendor, &device, &vp))
1571 if (vendor == pci_get_vendor(dev))
1574 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
1577 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) {
1585 if (device == pci_get_device(dev))
1589 snprintf(dp, 80, "0x%x", pci_get_device(dev));
1590 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) !=
1592 sprintf(desc, "%s, %s", vp, dp);
1602 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1604 struct pci_devinfo *dinfo;
1607 dinfo = device_get_ivars(child);
1611 case PCI_IVAR_ETHADDR:
1613 * The generic accessor doesn't deal with failure, so
1614 * we set the return value, then return an error.
1616 *((uint8_t **) result) = NULL;
1618 case PCI_IVAR_SUBVENDOR:
1619 *result = cfg->subvendor;
1621 case PCI_IVAR_SUBDEVICE:
1622 *result = cfg->subdevice;
1624 case PCI_IVAR_VENDOR:
1625 *result = cfg->vendor;
1627 case PCI_IVAR_DEVICE:
1628 *result = cfg->device;
1630 case PCI_IVAR_DEVID:
1631 *result = (cfg->device << 16) | cfg->vendor;
1633 case PCI_IVAR_CLASS:
1634 *result = cfg->baseclass;
1636 case PCI_IVAR_SUBCLASS:
1637 *result = cfg->subclass;
1639 case PCI_IVAR_PROGIF:
1640 *result = cfg->progif;
1642 case PCI_IVAR_REVID:
1643 *result = cfg->revid;
1645 case PCI_IVAR_INTPIN:
1646 *result = cfg->intpin;
1649 *result = cfg->intline;
1655 *result = cfg->slot;
1657 case PCI_IVAR_FUNCTION:
1658 *result = cfg->func;
1660 case PCI_IVAR_CMDREG:
1661 *result = cfg->cmdreg;
1663 case PCI_IVAR_CACHELNSZ:
1664 *result = cfg->cachelnsz;
1666 case PCI_IVAR_MINGNT:
1667 *result = cfg->mingnt;
1669 case PCI_IVAR_MAXLAT:
1670 *result = cfg->maxlat;
1672 case PCI_IVAR_LATTIMER:
1673 *result = cfg->lattimer;
1682 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1684 struct pci_devinfo *dinfo;
1686 dinfo = device_get_ivars(child);
1689 case PCI_IVAR_INTPIN:
1690 dinfo->cfg.intpin = value;
1692 case PCI_IVAR_ETHADDR:
1693 case PCI_IVAR_SUBVENDOR:
1694 case PCI_IVAR_SUBDEVICE:
1695 case PCI_IVAR_VENDOR:
1696 case PCI_IVAR_DEVICE:
1697 case PCI_IVAR_DEVID:
1698 case PCI_IVAR_CLASS:
1699 case PCI_IVAR_SUBCLASS:
1700 case PCI_IVAR_PROGIF:
1701 case PCI_IVAR_REVID:
1705 case PCI_IVAR_FUNCTION:
1706 return (EINVAL); /* disallow for now */
1714 #include "opt_ddb.h"
1716 #include <ddb/ddb.h>
1717 #include <sys/cons.h>
1720 * List resources based on pci map registers, used for within ddb
1723 DB_SHOW_COMMAND(pciregs, db_pci_dump)
1725 struct pci_devinfo *dinfo;
1726 struct devlist *devlist_head;
1729 int i, error, none_count, quit;
1732 /* get the head of the device queue */
1733 devlist_head = &pci_devq;
1736 * Go through the list of devices and print out devices
1738 db_setup_paging(db_simple_pager, &quit, db_lines_per_page);
1739 for (error = 0, i = 0, quit = 0,
1740 dinfo = STAILQ_FIRST(devlist_head);
1741 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !quit;
1742 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
1744 /* Populate pd_name and pd_unit */
1747 name = device_get_name(dinfo->cfg.dev);
1750 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x "
1751 "chip=0x%08x rev=0x%02x hdr=0x%02x\n",
1752 (name && *name) ? name : "none",
1753 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
1755 p->pc_sel.pc_bus, p->pc_sel.pc_dev,
1756 p->pc_sel.pc_func, (p->pc_class << 16) |
1757 (p->pc_subclass << 8) | p->pc_progif,
1758 (p->pc_subdevice << 16) | p->pc_subvendor,
1759 (p->pc_device << 16) | p->pc_vendor,
1760 p->pc_revid, p->pc_hdr);
1765 static struct resource *
1766 pci_alloc_map(device_t dev, device_t child, int type, int *rid,
1767 u_long start, u_long end, u_long count, u_int flags)
1769 struct pci_devinfo *dinfo = device_get_ivars(child);
1770 struct resource_list *rl = &dinfo->resources;
1771 struct resource_list_entry *rle;
1772 struct resource *res;
1773 uint32_t map, testval;
1777 * Weed out the bogons, and figure out how large the BAR/map
1778 * is. Bars that read back 0 here are bogus and unimplemented.
1779 * Note: atapci in legacy mode are special and handled elsewhere
1780 * in the code. If you have a atapci device in legacy mode and
1781 * it fails here, that other code is broken.
1784 map = pci_read_config(child, *rid, 4);
1785 pci_write_config(child, *rid, 0xffffffff, 4);
1786 testval = pci_read_config(child, *rid, 4);
1787 if (pci_mapbase(testval) == 0)
1789 if (pci_maptype(testval) & PCI_MAPMEM) {
1790 if (type != SYS_RES_MEMORY) {
1793 "child %s requested type %d for rid %#x,"
1794 " but the BAR says it is an memio\n",
1795 device_get_nameunit(child), type, *rid);
1799 if (type != SYS_RES_IOPORT) {
1802 "child %s requested type %d for rid %#x,"
1803 " but the BAR says it is an ioport\n",
1804 device_get_nameunit(child), type, *rid);
1809 * For real BARs, we need to override the size that
1810 * the driver requests, because that's what the BAR
1811 * actually uses and we would otherwise have a
1812 * situation where we might allocate the excess to
1813 * another driver, which won't work.
1815 mapsize = pci_mapsize(testval);
1816 count = 1 << mapsize;
1817 if (RF_ALIGNMENT(flags) < mapsize)
1818 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
1821 * Allocate enough resource, and then write back the
1822 * appropriate bar for that resource.
1824 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
1825 start, end, count, flags);
1827 device_printf(child,
1828 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n",
1829 count, *rid, type, start, end);
1832 resource_list_add(rl, type, *rid, start, end, count);
1833 rle = resource_list_find(rl, type, *rid);
1835 panic("pci_alloc_map: unexpectedly can't find resource.");
1837 rle->start = rman_get_start(res);
1838 rle->end = rman_get_end(res);
1841 device_printf(child,
1842 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n",
1843 count, *rid, type, rman_get_start(res));
1844 map = rman_get_start(res);
1846 pci_write_config(child, *rid, map, 4);
1852 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
1853 u_long start, u_long end, u_long count, u_int flags)
1855 struct pci_devinfo *dinfo = device_get_ivars(child);
1856 struct resource_list *rl = &dinfo->resources;
1857 struct resource_list_entry *rle;
1858 pcicfgregs *cfg = &dinfo->cfg;
1861 * Perform lazy resource allocation
1863 if (device_get_parent(child) == dev) {
1867 * If the child device doesn't have an
1868 * interrupt routed and is deserving of an
1869 * interrupt, try to assign it one.
1871 if (!PCI_INTERRUPT_VALID(cfg->intline) &&
1873 pci_assign_interrupt(dev, child, 0);
1875 case SYS_RES_IOPORT:
1876 case SYS_RES_MEMORY:
1877 if (*rid < PCIR_BAR(cfg->nummaps)) {
1879 * Enable the I/O mode. We should
1880 * also be assigning resources too
1881 * when none are present. The
1882 * resource_list_alloc kind of sorta does
1885 if (PCI_ENABLE_IO(dev, child, type))
1888 rle = resource_list_find(rl, type, *rid);
1890 return (pci_alloc_map(dev, child, type, rid,
1891 start, end, count, flags));
1895 * If we've already allocated the resource, then
1896 * return it now. But first we may need to activate
1897 * it, since we don't allocate the resource as active
1898 * above. Normally this would be done down in the
1899 * nexus, but since we short-circuit that path we have
1900 * to do its job here. Not sure if we should free the
1901 * resource if it fails to activate.
1903 rle = resource_list_find(rl, type, *rid);
1904 if (rle != NULL && rle->res != NULL) {
1906 device_printf(child,
1907 "Reserved %#lx bytes for rid %#x type %d at %#lx\n",
1908 rman_get_size(rle->res), *rid, type,
1909 rman_get_start(rle->res));
1910 if ((flags & RF_ACTIVE) &&
1911 bus_generic_activate_resource(dev, child, type,
1912 *rid, rle->res) != 0)
1917 return (resource_list_alloc(rl, dev, child, type, rid,
1918 start, end, count, flags));
1922 pci_delete_resource(device_t dev, device_t child, int type, int rid)
1924 struct pci_devinfo *dinfo;
1925 struct resource_list *rl;
1926 struct resource_list_entry *rle;
1928 if (device_get_parent(child) != dev)
1931 dinfo = device_get_ivars(child);
1932 rl = &dinfo->resources;
1933 rle = resource_list_find(rl, type, rid);
1936 if (rman_get_device(rle->res) != dev ||
1937 rman_get_flags(rle->res) & RF_ACTIVE) {
1938 device_printf(dev, "delete_resource: "
1939 "Resource still owned by child, oops. "
1940 "(type=%d, rid=%d, addr=%lx)\n",
1941 rle->type, rle->rid,
1942 rman_get_start(rle->res));
1945 bus_release_resource(dev, type, rid, rle->res);
1947 resource_list_delete(rl, type, rid);
1950 * Why do we turn off the PCI configuration BAR when we delete a
1953 pci_write_config(child, rid, 0, 4);
1954 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid);
1957 struct resource_list *
1958 pci_get_resource_list (device_t dev, device_t child)
1960 struct pci_devinfo *dinfo = device_get_ivars(child);
1962 return (&dinfo->resources);
1966 pci_read_config_method(device_t dev, device_t child, int reg, int width)
1968 struct pci_devinfo *dinfo = device_get_ivars(child);
1969 pcicfgregs *cfg = &dinfo->cfg;
1971 return (PCIB_READ_CONFIG(device_get_parent(dev),
1972 cfg->bus, cfg->slot, cfg->func, reg, width));
1976 pci_write_config_method(device_t dev, device_t child, int reg,
1977 uint32_t val, int width)
1979 struct pci_devinfo *dinfo = device_get_ivars(child);
1980 pcicfgregs *cfg = &dinfo->cfg;
1982 PCIB_WRITE_CONFIG(device_get_parent(dev),
1983 cfg->bus, cfg->slot, cfg->func, reg, val, width);
1987 pci_child_location_str_method(device_t dev, device_t child, char *buf,
1991 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
1992 pci_get_function(child));
1997 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
2000 struct pci_devinfo *dinfo;
2003 dinfo = device_get_ivars(child);
2005 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
2006 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
2007 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
2013 pci_assign_interrupt_method(device_t dev, device_t child)
2015 struct pci_devinfo *dinfo = device_get_ivars(child);
2016 pcicfgregs *cfg = &dinfo->cfg;
2018 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
2023 pci_modevent(module_t mod, int what, void *arg)
2025 static struct cdev *pci_cdev;
2029 STAILQ_INIT(&pci_devq);
2031 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644,
2033 pci_load_vendor_data();
2037 destroy_dev(pci_cdev);
2045 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
2050 * Only do header type 0 devices. Type 1 devices are bridges,
2051 * which we know need special treatment. Type 2 devices are
2052 * cardbus bridges which also require special treatment.
2053 * Other types are unknown, and we err on the side of safety
2056 if (dinfo->cfg.hdrtype != 0)
2060 * Restore the device to full power mode. We must do this
2061 * before we restore the registers because moving from D3 to
2062 * D0 will cause the chip's BARs and some other registers to
2063 * be reset to some unknown power on reset values. Cut down
2064 * the noise on boot by doing nothing if we are already in
2067 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
2068 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
2070 for (i = 0; i < dinfo->cfg.nummaps; i++)
2071 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4);
2072 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4);
2073 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
2074 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
2075 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
2076 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
2077 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
2078 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
2079 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
2080 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
2081 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
2085 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
2092 * Only do header type 0 devices. Type 1 devices are bridges, which
2093 * we know need special treatment. Type 2 devices are cardbus bridges
2094 * which also require special treatment. Other types are unknown, and
2095 * we err on the side of safety by ignoring them. Powering down
2096 * bridges should not be undertaken lightly.
2098 if (dinfo->cfg.hdrtype != 0)
2100 for (i = 0; i < dinfo->cfg.nummaps; i++)
2101 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4);
2102 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4);
2105 * Some drivers apparently write to these registers w/o updating our
2106 * cached copy. No harm happens if we update the copy, so do so here
2107 * so we can restore them. The COMMAND register is modified by the
2108 * bus w/o updating the cache. This should represent the normally
2109 * writable portion of the 'defined' part of type 0 headers. In
2110 * theory we also need to save/restore the PCI capability structures
2111 * we know about, but apart from power we don't know any that are
2114 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
2115 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
2116 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
2117 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
2118 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
2119 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
2120 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
2121 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
2122 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
2123 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
2124 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
2125 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
2126 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
2127 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
2128 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
2131 * don't set the state for display devices, base peripherals and
2132 * memory devices since bad things happen when they are powered down.
2133 * We should (a) have drivers that can easily detach and (b) use
2134 * generic drivers for these devices so that some device actually
2135 * attaches. We need to make sure that when we implement (a) we don't
2136 * power the device down on a reattach.
2138 cls = pci_get_class(dev);
2141 switch (pci_do_power_nodriver)
2143 case 0: /* NO powerdown at all */
2145 case 1: /* Conservative about what to power down */
2146 if (cls == PCIC_STORAGE)
2149 case 2: /* Agressive about what to power down */
2150 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY ||
2151 cls == PCIC_BASEPERIPH)
2154 case 3: /* Power down everything */
2158 * PCI spec says we can only go into D3 state from D0 state.
2159 * Transition from D[12] into D0 before going to D3 state.
2161 ps = pci_get_powerstate(dev);
2162 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
2163 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
2164 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
2165 pci_set_powerstate(dev, PCI_POWERSTATE_D3);