2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000, BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/linker.h>
39 #include <sys/fcntl.h>
41 #include <sys/kernel.h>
42 #include <sys/queue.h>
43 #include <sys/sysctl.h>
44 #include <sys/endian.h>
48 #include <vm/vm_extern.h>
51 #include <machine/bus.h>
53 #include <machine/resource.h>
55 #if defined(__i386__) || defined(__amd64__)
56 #include <machine/intr_machdep.h>
59 #include <sys/pciio.h>
60 #include <dev/pci/pcireg.h>
61 #include <dev/pci/pcivar.h>
62 #include <dev/pci/pci_private.h>
68 #include <contrib/dev/acpica/acpi.h>
71 #define ACPI_PWR_FOR_SLEEP(x, y, z)
74 static pci_addr_t pci_mapbase(uint64_t mapreg);
75 static const char *pci_maptype(uint64_t mapreg);
76 static int pci_mapsize(uint64_t testval);
77 static int pci_maprange(uint64_t mapreg);
78 static void pci_fixancient(pcicfgregs *cfg);
80 static int pci_porten(device_t dev);
81 static int pci_memen(device_t dev);
82 static void pci_assign_interrupt(device_t bus, device_t dev,
84 static int pci_add_map(device_t bus, device_t dev, int reg,
85 struct resource_list *rl, int force, int prefetch);
86 static int pci_probe(device_t dev);
87 static int pci_attach(device_t dev);
88 static void pci_load_vendor_data(void);
89 static int pci_describe_parse_line(char **ptr, int *vendor,
90 int *device, char **desc);
91 static char *pci_describe_device(device_t dev);
92 static int pci_modevent(module_t mod, int what, void *arg);
93 static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
95 static void pci_read_extcap(device_t pcib, pcicfgregs *cfg);
96 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg,
97 int reg, uint32_t *data);
99 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg,
100 int reg, uint32_t data);
102 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg);
103 static void pci_disable_msi(device_t dev);
104 static void pci_enable_msi(device_t dev, uint64_t address,
106 static void pci_enable_msix(device_t dev, u_int index,
107 uint64_t address, uint32_t data);
108 static void pci_mask_msix(device_t dev, u_int index);
109 static void pci_unmask_msix(device_t dev, u_int index);
110 static int pci_msi_blacklisted(void);
111 static void pci_resume_msi(device_t dev);
112 static void pci_resume_msix(device_t dev);
114 static device_method_t pci_methods[] = {
115 /* Device interface */
116 DEVMETHOD(device_probe, pci_probe),
117 DEVMETHOD(device_attach, pci_attach),
118 DEVMETHOD(device_detach, bus_generic_detach),
119 DEVMETHOD(device_shutdown, bus_generic_shutdown),
120 DEVMETHOD(device_suspend, pci_suspend),
121 DEVMETHOD(device_resume, pci_resume),
124 DEVMETHOD(bus_print_child, pci_print_child),
125 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
126 DEVMETHOD(bus_read_ivar, pci_read_ivar),
127 DEVMETHOD(bus_write_ivar, pci_write_ivar),
128 DEVMETHOD(bus_driver_added, pci_driver_added),
129 DEVMETHOD(bus_setup_intr, pci_setup_intr),
130 DEVMETHOD(bus_teardown_intr, pci_teardown_intr),
132 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
133 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
134 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
135 DEVMETHOD(bus_delete_resource, pci_delete_resource),
136 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
137 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
138 DEVMETHOD(bus_activate_resource, pci_activate_resource),
139 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
140 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
141 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
144 DEVMETHOD(pci_read_config, pci_read_config_method),
145 DEVMETHOD(pci_write_config, pci_write_config_method),
146 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
147 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
148 DEVMETHOD(pci_enable_io, pci_enable_io_method),
149 DEVMETHOD(pci_disable_io, pci_disable_io_method),
150 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method),
151 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method),
152 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
153 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
154 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
155 DEVMETHOD(pci_find_extcap, pci_find_extcap_method),
156 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method),
157 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method),
158 DEVMETHOD(pci_remap_msix, pci_remap_msix_method),
159 DEVMETHOD(pci_release_msi, pci_release_msi_method),
160 DEVMETHOD(pci_msi_count, pci_msi_count_method),
161 DEVMETHOD(pci_msix_count, pci_msix_count_method),
166 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0);
168 static devclass_t pci_devclass;
169 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
170 MODULE_VERSION(pci, 1);
172 static char *pci_vendordata;
173 static size_t pci_vendordata_size;
177 uint32_t devid; /* Vendor/device of the card */
179 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
180 #define PCI_QUIRK_DISABLE_MSI 2 /* MSI/MSI-X doesn't work */
185 struct pci_quirk pci_quirks[] = {
186 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */
187 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
188 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
189 /* As does the Serverworks OSB4 (the SMBus mapping register) */
190 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
193 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
194 * or the CMIC-SL (AKA ServerWorks GC_LE).
196 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
197 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
200 * MSI doesn't work on earlier Intel chipsets including
201 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
203 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
204 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
205 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
206 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
207 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
208 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
209 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
212 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
215 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 },
220 /* map register information */
221 #define PCI_MAPMEM 0x01 /* memory map */
222 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
223 #define PCI_MAPPORT 0x04 /* port map */
225 struct devlist pci_devq;
226 uint32_t pci_generation;
227 uint32_t pci_numdevs = 0;
228 static int pcie_chipset, pcix_chipset;
231 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters");
233 static int pci_enable_io_modes = 1;
234 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes);
235 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW,
236 &pci_enable_io_modes, 1,
237 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\
238 enable these bits correctly. We'd like to do this all the time, but there\n\
239 are some peripherals that this causes problems with.");
241 static int pci_do_power_nodriver = 0;
242 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver);
243 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW,
244 &pci_do_power_nodriver, 0,
245 "Place a function into D3 state when no driver attaches to it. 0 means\n\
246 disable. 1 means conservatively place devices into D3 state. 2 means\n\
247 agressively place devices into D3 state. 3 means put absolutely everything\n\
250 static int pci_do_power_resume = 1;
251 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume);
252 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW,
253 &pci_do_power_resume, 1,
254 "Transition from D3 -> D0 on resume.");
256 static int pci_do_msi = 1;
257 TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi);
258 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1,
259 "Enable support for MSI interrupts");
261 static int pci_do_msix = 1;
262 TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix);
263 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1,
264 "Enable support for MSI-X interrupts");
266 static int pci_honor_msi_blacklist = 1;
267 TUNABLE_INT("hw.pci.honor_msi_blacklist", &pci_honor_msi_blacklist);
268 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RD,
269 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI");
271 /* Find a device_t by bus/slot/function in domain 0 */
274 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
277 return (pci_find_dbsf(0, bus, slot, func));
280 /* Find a device_t by domain/bus/slot/function */
283 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func)
285 struct pci_devinfo *dinfo;
287 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
288 if ((dinfo->cfg.domain == domain) &&
289 (dinfo->cfg.bus == bus) &&
290 (dinfo->cfg.slot == slot) &&
291 (dinfo->cfg.func == func)) {
292 return (dinfo->cfg.dev);
299 /* Find a device_t by vendor/device ID */
302 pci_find_device(uint16_t vendor, uint16_t device)
304 struct pci_devinfo *dinfo;
306 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
307 if ((dinfo->cfg.vendor == vendor) &&
308 (dinfo->cfg.device == device)) {
309 return (dinfo->cfg.dev);
316 /* return base address of memory or port map */
319 pci_mapbase(uint64_t mapreg)
322 if (PCI_BAR_MEM(mapreg))
323 return (mapreg & PCIM_BAR_MEM_BASE);
325 return (mapreg & PCIM_BAR_IO_BASE);
328 /* return map type of memory or port map */
331 pci_maptype(uint64_t mapreg)
334 if (PCI_BAR_IO(mapreg))
336 if (mapreg & PCIM_BAR_MEM_PREFETCH)
337 return ("Prefetchable Memory");
341 /* return log2 of map size decoded for memory or port map */
344 pci_mapsize(uint64_t testval)
348 testval = pci_mapbase(testval);
351 while ((testval & 1) == 0)
360 /* return log2 of address range supported by map register */
363 pci_maprange(uint64_t mapreg)
367 if (PCI_BAR_IO(mapreg))
370 switch (mapreg & PCIM_BAR_MEM_TYPE) {
371 case PCIM_BAR_MEM_32:
374 case PCIM_BAR_MEM_1MB:
377 case PCIM_BAR_MEM_64:
384 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
387 pci_fixancient(pcicfgregs *cfg)
389 if (cfg->hdrtype != 0)
392 /* PCI to PCI bridges use header type 1 */
393 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
397 /* extract header type specific config data */
400 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
402 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
403 switch (cfg->hdrtype) {
405 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
406 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
407 cfg->nummaps = PCI_MAXMAPS_0;
410 cfg->nummaps = PCI_MAXMAPS_1;
413 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
414 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
415 cfg->nummaps = PCI_MAXMAPS_2;
421 /* read configuration header into pcicfgregs structure */
423 pci_read_device(device_t pcib, int d, int b, int s, int f, size_t size)
425 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
426 pcicfgregs *cfg = NULL;
427 struct pci_devinfo *devlist_entry;
428 struct devlist *devlist_head;
430 devlist_head = &pci_devq;
432 devlist_entry = NULL;
434 if (REG(PCIR_DEVVENDOR, 4) != 0xfffffffful) {
435 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
436 if (devlist_entry == NULL)
439 cfg = &devlist_entry->cfg;
445 cfg->vendor = REG(PCIR_VENDOR, 2);
446 cfg->device = REG(PCIR_DEVICE, 2);
447 cfg->cmdreg = REG(PCIR_COMMAND, 2);
448 cfg->statreg = REG(PCIR_STATUS, 2);
449 cfg->baseclass = REG(PCIR_CLASS, 1);
450 cfg->subclass = REG(PCIR_SUBCLASS, 1);
451 cfg->progif = REG(PCIR_PROGIF, 1);
452 cfg->revid = REG(PCIR_REVID, 1);
453 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
454 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
455 cfg->lattimer = REG(PCIR_LATTIMER, 1);
456 cfg->intpin = REG(PCIR_INTPIN, 1);
457 cfg->intline = REG(PCIR_INTLINE, 1);
459 cfg->mingnt = REG(PCIR_MINGNT, 1);
460 cfg->maxlat = REG(PCIR_MAXLAT, 1);
462 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
463 cfg->hdrtype &= ~PCIM_MFDEV;
466 pci_hdrtypedata(pcib, b, s, f, cfg);
468 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
469 pci_read_extcap(pcib, cfg);
471 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
473 devlist_entry->conf.pc_sel.pc_domain = cfg->domain;
474 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
475 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
476 devlist_entry->conf.pc_sel.pc_func = cfg->func;
477 devlist_entry->conf.pc_hdr = cfg->hdrtype;
479 devlist_entry->conf.pc_subvendor = cfg->subvendor;
480 devlist_entry->conf.pc_subdevice = cfg->subdevice;
481 devlist_entry->conf.pc_vendor = cfg->vendor;
482 devlist_entry->conf.pc_device = cfg->device;
484 devlist_entry->conf.pc_class = cfg->baseclass;
485 devlist_entry->conf.pc_subclass = cfg->subclass;
486 devlist_entry->conf.pc_progif = cfg->progif;
487 devlist_entry->conf.pc_revid = cfg->revid;
492 return (devlist_entry);
497 pci_read_extcap(device_t pcib, pcicfgregs *cfg)
499 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
500 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
501 #if defined(__i386__) || defined(__amd64__)
505 int ptr, nextptr, ptrptr;
507 switch (cfg->hdrtype & PCIM_HDRTYPE) {
510 ptrptr = PCIR_CAP_PTR;
513 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */
516 return; /* no extended capabilities support */
518 nextptr = REG(ptrptr, 1); /* sanity check? */
521 * Read capability entries.
523 while (nextptr != 0) {
526 printf("illegal PCI extended capability offset %d\n",
530 /* Find the next entry */
532 nextptr = REG(ptr + PCICAP_NEXTPTR, 1);
534 /* Process this entry */
535 switch (REG(ptr + PCICAP_ID, 1)) {
536 case PCIY_PMG: /* PCI power management */
537 if (cfg->pp.pp_cap == 0) {
538 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
539 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS;
540 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR;
541 if ((nextptr - ptr) > PCIR_POWER_DATA)
542 cfg->pp.pp_data = ptr + PCIR_POWER_DATA;
545 #if defined(__i386__) || defined(__amd64__)
546 case PCIY_HT: /* HyperTransport */
547 /* Determine HT-specific capability type. */
548 val = REG(ptr + PCIR_HT_COMMAND, 2);
549 switch (val & PCIM_HTCMD_CAP_MASK) {
550 case PCIM_HTCAP_MSI_MAPPING:
551 if (!(val & PCIM_HTCMD_MSI_FIXED)) {
552 /* Sanity check the mapping window. */
553 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI,
556 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO,
558 if (addr != MSI_INTEL_ADDR_BASE)
560 "HT Bridge at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n",
561 cfg->domain, cfg->bus,
562 cfg->slot, cfg->func,
565 addr = MSI_INTEL_ADDR_BASE;
567 cfg->ht.ht_msimap = ptr;
568 cfg->ht.ht_msictrl = val;
569 cfg->ht.ht_msiaddr = addr;
574 case PCIY_MSI: /* PCI MSI */
575 cfg->msi.msi_location = ptr;
576 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
577 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl &
578 PCIM_MSICTRL_MMC_MASK)>>1);
580 case PCIY_MSIX: /* PCI MSI-X */
581 cfg->msix.msix_location = ptr;
582 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);
583 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl &
584 PCIM_MSIXCTRL_TABLE_SIZE) + 1;
585 val = REG(ptr + PCIR_MSIX_TABLE, 4);
586 cfg->msix.msix_table_bar = PCIR_BAR(val &
588 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK;
589 val = REG(ptr + PCIR_MSIX_PBA, 4);
590 cfg->msix.msix_pba_bar = PCIR_BAR(val &
592 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK;
594 case PCIY_VPD: /* PCI Vital Product Data */
595 cfg->vpd.vpd_reg = ptr;
598 /* Should always be true. */
599 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1) {
600 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4);
601 cfg->subvendor = val & 0xffff;
602 cfg->subdevice = val >> 16;
605 case PCIY_PCIX: /* PCI-X */
607 * Assume we have a PCI-X chipset if we have
608 * at least one PCI-PCI bridge with a PCI-X
609 * capability. Note that some systems with
610 * PCI-express or HT chipsets might match on
611 * this check as well.
613 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1)
616 case PCIY_EXPRESS: /* PCI-express */
618 * Assume we have a PCI-express chipset if we have
619 * at least one PCI-express device.
627 /* REG and WREG use carry through to next functions */
631 * PCI Vital Product Data
634 #define PCI_VPD_TIMEOUT 1000000
637 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data)
639 int count = PCI_VPD_TIMEOUT;
641 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
643 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2);
645 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {
648 DELAY(1); /* limit looping */
650 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));
657 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data)
659 int count = PCI_VPD_TIMEOUT;
661 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
663 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
664 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
665 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
668 DELAY(1); /* limit looping */
675 #undef PCI_VPD_TIMEOUT
677 struct vpd_readstate {
687 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data)
692 if (vrs->bytesinval == 0) {
693 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®))
695 vrs->val = le32toh(reg);
697 byte = vrs->val & 0xff;
700 vrs->val = vrs->val >> 8;
701 byte = vrs->val & 0xff;
711 pci_read_vpd(device_t pcib, pcicfgregs *cfg)
713 struct vpd_readstate vrs;
718 int alloc, off; /* alloc/off for RO/W arrays */
724 /* init vpd reader */
732 name = remain = i = 0; /* shut up stupid gcc */
733 alloc = off = 0; /* shut up stupid gcc */
734 dflen = 0; /* shut up stupid gcc */
737 if (vpd_nextbyte(&vrs, &byte)) {
742 printf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \
743 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val,
744 vrs.off, vrs.bytesinval, byte, state, remain, name, i);
747 case 0: /* item name */
749 if (vpd_nextbyte(&vrs, &byte2)) {
754 if (vpd_nextbyte(&vrs, &byte2)) {
758 remain |= byte2 << 8;
759 if (remain > (0x7f*4 - vrs.off)) {
762 "pci%d:%d:%d:%d: invalid VPD data, remain %#x\n",
763 cfg->domain, cfg->bus, cfg->slot,
769 name = (byte >> 3) & 0xf;
772 case 0x2: /* String */
773 cfg->vpd.vpd_ident = malloc(remain + 1,
781 case 0x10: /* VPD-R */
784 cfg->vpd.vpd_ros = malloc(alloc *
785 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF,
789 case 0x11: /* VPD-W */
792 cfg->vpd.vpd_w = malloc(alloc *
793 sizeof(*cfg->vpd.vpd_w), M_DEVBUF,
797 default: /* Invalid data, abort */
803 case 1: /* Identifier String */
804 cfg->vpd.vpd_ident[i++] = byte;
807 cfg->vpd.vpd_ident[i] = '\0';
812 case 2: /* VPD-R Keyword Header */
814 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros,
815 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros),
816 M_DEVBUF, M_WAITOK | M_ZERO);
818 cfg->vpd.vpd_ros[off].keyword[0] = byte;
819 if (vpd_nextbyte(&vrs, &byte2)) {
823 cfg->vpd.vpd_ros[off].keyword[1] = byte2;
824 if (vpd_nextbyte(&vrs, &byte2)) {
830 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV",
833 * if this happens, we can't trust the rest
837 "pci%d:%d:%d:%d: bad keyword length: %d\n",
838 cfg->domain, cfg->bus, cfg->slot,
843 } else if (dflen == 0) {
844 cfg->vpd.vpd_ros[off].value = malloc(1 *
845 sizeof(*cfg->vpd.vpd_ros[off].value),
847 cfg->vpd.vpd_ros[off].value[0] = '\x00';
849 cfg->vpd.vpd_ros[off].value = malloc(
851 sizeof(*cfg->vpd.vpd_ros[off].value),
855 /* keep in sync w/ state 3's transistions */
856 if (dflen == 0 && remain == 0)
864 case 3: /* VPD-R Keyword Value */
865 cfg->vpd.vpd_ros[off].value[i++] = byte;
866 if (strncmp(cfg->vpd.vpd_ros[off].keyword,
867 "RV", 2) == 0 && cksumvalid == -1) {
873 "pci%d:%d:%d:%d: bad VPD cksum, remain %hhu\n",
874 cfg->domain, cfg->bus,
875 cfg->slot, cfg->func,
884 /* keep in sync w/ state 2's transistions */
886 cfg->vpd.vpd_ros[off++].value[i++] = '\0';
887 if (dflen == 0 && remain == 0) {
888 cfg->vpd.vpd_rocnt = off;
889 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros,
890 off * sizeof(*cfg->vpd.vpd_ros),
891 M_DEVBUF, M_WAITOK | M_ZERO);
893 } else if (dflen == 0)
903 case 5: /* VPD-W Keyword Header */
905 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w,
906 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w),
907 M_DEVBUF, M_WAITOK | M_ZERO);
909 cfg->vpd.vpd_w[off].keyword[0] = byte;
910 if (vpd_nextbyte(&vrs, &byte2)) {
914 cfg->vpd.vpd_w[off].keyword[1] = byte2;
915 if (vpd_nextbyte(&vrs, &byte2)) {
919 cfg->vpd.vpd_w[off].len = dflen = byte2;
920 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval;
921 cfg->vpd.vpd_w[off].value = malloc((dflen + 1) *
922 sizeof(*cfg->vpd.vpd_w[off].value),
926 /* keep in sync w/ state 6's transistions */
927 if (dflen == 0 && remain == 0)
935 case 6: /* VPD-W Keyword Value */
936 cfg->vpd.vpd_w[off].value[i++] = byte;
939 /* keep in sync w/ state 5's transistions */
941 cfg->vpd.vpd_w[off++].value[i++] = '\0';
942 if (dflen == 0 && remain == 0) {
943 cfg->vpd.vpd_wcnt = off;
944 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w,
945 off * sizeof(*cfg->vpd.vpd_w),
946 M_DEVBUF, M_WAITOK | M_ZERO);
948 } else if (dflen == 0)
953 printf("pci%d:%d:%d:%d: invalid state: %d\n",
954 cfg->domain, cfg->bus, cfg->slot, cfg->func,
961 if (cksumvalid == 0 || state < -1) {
962 /* read-only data bad, clean up */
963 if (cfg->vpd.vpd_ros != NULL) {
964 for (off = 0; cfg->vpd.vpd_ros[off].value; off++)
965 free(cfg->vpd.vpd_ros[off].value, M_DEVBUF);
966 free(cfg->vpd.vpd_ros, M_DEVBUF);
967 cfg->vpd.vpd_ros = NULL;
971 /* I/O error, clean up */
972 printf("pci%d:%d:%d:%d: failed to read VPD data.\n",
973 cfg->domain, cfg->bus, cfg->slot, cfg->func);
974 if (cfg->vpd.vpd_ident != NULL) {
975 free(cfg->vpd.vpd_ident, M_DEVBUF);
976 cfg->vpd.vpd_ident = NULL;
978 if (cfg->vpd.vpd_w != NULL) {
979 for (off = 0; cfg->vpd.vpd_w[off].value; off++)
980 free(cfg->vpd.vpd_w[off].value, M_DEVBUF);
981 free(cfg->vpd.vpd_w, M_DEVBUF);
982 cfg->vpd.vpd_w = NULL;
985 cfg->vpd.vpd_cached = 1;
991 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr)
993 struct pci_devinfo *dinfo = device_get_ivars(child);
994 pcicfgregs *cfg = &dinfo->cfg;
996 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
997 pci_read_vpd(device_get_parent(dev), cfg);
999 *identptr = cfg->vpd.vpd_ident;
1001 if (*identptr == NULL)
1008 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw,
1011 struct pci_devinfo *dinfo = device_get_ivars(child);
1012 pcicfgregs *cfg = &dinfo->cfg;
1015 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1016 pci_read_vpd(device_get_parent(dev), cfg);
1018 for (i = 0; i < cfg->vpd.vpd_rocnt; i++)
1019 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword,
1020 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) {
1021 *vptr = cfg->vpd.vpd_ros[i].value;
1024 if (i != cfg->vpd.vpd_rocnt)
1032 * Find the requested extended capability and return the offset in
1033 * configuration space via the pointer provided. The function returns
1034 * 0 on success and error code otherwise.
1037 pci_find_extcap_method(device_t dev, device_t child, int capability,
1040 struct pci_devinfo *dinfo = device_get_ivars(child);
1041 pcicfgregs *cfg = &dinfo->cfg;
1046 * Check the CAP_LIST bit of the PCI status register first.
1048 status = pci_read_config(child, PCIR_STATUS, 2);
1049 if (!(status & PCIM_STATUS_CAPPRESENT))
1053 * Determine the start pointer of the capabilities list.
1055 switch (cfg->hdrtype & PCIM_HDRTYPE) {
1061 ptr = PCIR_CAP_PTR_2;
1065 return (ENXIO); /* no extended capabilities support */
1067 ptr = pci_read_config(child, ptr, 1);
1070 * Traverse the capabilities list.
1073 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
1078 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1085 * Support for MSI-X message interrupts.
1088 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data)
1090 struct pci_devinfo *dinfo = device_get_ivars(dev);
1091 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1094 KASSERT(msix->msix_table_len > index, ("bogus index"));
1095 offset = msix->msix_table_offset + index * 16;
1096 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
1097 bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
1098 bus_write_4(msix->msix_table_res, offset + 8, data);
1100 /* Enable MSI -> HT mapping. */
1101 pci_ht_map_msi(dev, address);
1105 pci_mask_msix(device_t dev, u_int index)
1107 struct pci_devinfo *dinfo = device_get_ivars(dev);
1108 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1109 uint32_t offset, val;
1111 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1112 offset = msix->msix_table_offset + index * 16 + 12;
1113 val = bus_read_4(msix->msix_table_res, offset);
1114 if (!(val & PCIM_MSIX_VCTRL_MASK)) {
1115 val |= PCIM_MSIX_VCTRL_MASK;
1116 bus_write_4(msix->msix_table_res, offset, val);
1121 pci_unmask_msix(device_t dev, u_int index)
1123 struct pci_devinfo *dinfo = device_get_ivars(dev);
1124 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1125 uint32_t offset, val;
1127 KASSERT(msix->msix_table_len > index, ("bogus index"));
1128 offset = msix->msix_table_offset + index * 16 + 12;
1129 val = bus_read_4(msix->msix_table_res, offset);
1130 if (val & PCIM_MSIX_VCTRL_MASK) {
1131 val &= ~PCIM_MSIX_VCTRL_MASK;
1132 bus_write_4(msix->msix_table_res, offset, val);
1137 pci_pending_msix(device_t dev, u_int index)
1139 struct pci_devinfo *dinfo = device_get_ivars(dev);
1140 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1141 uint32_t offset, bit;
1143 KASSERT(msix->msix_table_len > index, ("bogus index"));
1144 offset = msix->msix_pba_offset + (index / 32) * 4;
1145 bit = 1 << index % 32;
1146 return (bus_read_4(msix->msix_pba_res, offset) & bit);
1150 * Restore MSI-X registers and table during resume. If MSI-X is
1151 * enabled then walk the virtual table to restore the actual MSI-X
1155 pci_resume_msix(device_t dev)
1157 struct pci_devinfo *dinfo = device_get_ivars(dev);
1158 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1159 struct msix_table_entry *mte;
1160 struct msix_vector *mv;
1163 if (msix->msix_alloc > 0) {
1164 /* First, mask all vectors. */
1165 for (i = 0; i < msix->msix_msgnum; i++)
1166 pci_mask_msix(dev, i);
1168 /* Second, program any messages with at least one handler. */
1169 for (i = 0; i < msix->msix_table_len; i++) {
1170 mte = &msix->msix_table[i];
1171 if (mte->mte_vector == 0 || mte->mte_handlers == 0)
1173 mv = &msix->msix_vectors[mte->mte_vector - 1];
1174 pci_enable_msix(dev, i, mv->mv_address, mv->mv_data);
1175 pci_unmask_msix(dev, i);
1178 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1179 msix->msix_ctrl, 2);
1183 * Attempt to allocate *count MSI-X messages. The actual number allocated is
1184 * returned in *count. After this function returns, each message will be
1185 * available to the driver as SYS_RES_IRQ resources starting at rid 1.
1188 pci_alloc_msix_method(device_t dev, device_t child, int *count)
1190 struct pci_devinfo *dinfo = device_get_ivars(child);
1191 pcicfgregs *cfg = &dinfo->cfg;
1192 struct resource_list_entry *rle;
1193 int actual, error, i, irq, max;
1195 /* Don't let count == 0 get us into trouble. */
1199 /* If rid 0 is allocated, then fail. */
1200 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1201 if (rle != NULL && rle->res != NULL)
1204 /* Already have allocated messages? */
1205 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1208 /* If MSI is blacklisted for this system, fail. */
1209 if (pci_msi_blacklisted())
1212 /* MSI-X capability present? */
1213 if (cfg->msix.msix_location == 0 || !pci_do_msix)
1216 /* Make sure the appropriate BARs are mapped. */
1217 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1218 cfg->msix.msix_table_bar);
1219 if (rle == NULL || rle->res == NULL ||
1220 !(rman_get_flags(rle->res) & RF_ACTIVE))
1222 cfg->msix.msix_table_res = rle->res;
1223 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) {
1224 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1225 cfg->msix.msix_pba_bar);
1226 if (rle == NULL || rle->res == NULL ||
1227 !(rman_get_flags(rle->res) & RF_ACTIVE))
1230 cfg->msix.msix_pba_res = rle->res;
1233 device_printf(child,
1234 "attempting to allocate %d MSI-X vectors (%d supported)\n",
1235 *count, cfg->msix.msix_msgnum);
1236 max = min(*count, cfg->msix.msix_msgnum);
1237 for (i = 0; i < max; i++) {
1238 /* Allocate a message. */
1239 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq);
1242 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1248 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1);
1250 device_printf(child, "using IRQ %lu for MSI-X\n",
1256 * Be fancy and try to print contiguous runs of
1257 * IRQ values as ranges. 'irq' is the previous IRQ.
1258 * 'run' is true if we are in a range.
1260 device_printf(child, "using IRQs %lu", rle->start);
1263 for (i = 1; i < actual; i++) {
1264 rle = resource_list_find(&dinfo->resources,
1265 SYS_RES_IRQ, i + 1);
1267 /* Still in a run? */
1268 if (rle->start == irq + 1) {
1274 /* Finish previous range. */
1280 /* Start new range. */
1281 printf(",%lu", rle->start);
1285 /* Unfinished range? */
1288 printf(" for MSI-X\n");
1292 /* Mask all vectors. */
1293 for (i = 0; i < cfg->msix.msix_msgnum; i++)
1294 pci_mask_msix(child, i);
1296 /* Allocate and initialize vector data and virtual table. */
1297 cfg->msix.msix_vectors = malloc(sizeof(struct msix_vector) * actual,
1298 M_DEVBUF, M_WAITOK | M_ZERO);
1299 cfg->msix.msix_table = malloc(sizeof(struct msix_table_entry) * actual,
1300 M_DEVBUF, M_WAITOK | M_ZERO);
1301 for (i = 0; i < actual; i++) {
1302 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1303 cfg->msix.msix_vectors[i].mv_irq = rle->start;
1304 cfg->msix.msix_table[i].mte_vector = i + 1;
1307 /* Update control register to enable MSI-X. */
1308 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
1309 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL,
1310 cfg->msix.msix_ctrl, 2);
1312 /* Update counts of alloc'd messages. */
1313 cfg->msix.msix_alloc = actual;
1314 cfg->msix.msix_table_len = actual;
1320 * By default, pci_alloc_msix() will assign the allocated IRQ
1321 * resources consecutively to the first N messages in the MSI-X table.
1322 * However, device drivers may want to use different layouts if they
1323 * either receive fewer messages than they asked for, or they wish to
1324 * populate the MSI-X table sparsely. This method allows the driver
1325 * to specify what layout it wants. It must be called after a
1326 * successful pci_alloc_msix() but before any of the associated
1327 * SYS_RES_IRQ resources are allocated via bus_alloc_resource().
1329 * The 'vectors' array contains 'count' message vectors. The array
1330 * maps directly to the MSI-X table in that index 0 in the array
1331 * specifies the vector for the first message in the MSI-X table, etc.
1332 * The vector value in each array index can either be 0 to indicate
1333 * that no vector should be assigned to a message slot, or it can be a
1334 * number from 1 to N (where N is the count returned from a
1335 * succcessful call to pci_alloc_msix()) to indicate which message
1336 * vector (IRQ) to be used for the corresponding message.
1338 * On successful return, each message with a non-zero vector will have
1339 * an associated SYS_RES_IRQ whose rid is equal to the array index +
1340 * 1. Additionally, if any of the IRQs allocated via the previous
1341 * call to pci_alloc_msix() are not used in the mapping, those IRQs
1342 * will be freed back to the system automatically.
1344 * For example, suppose a driver has a MSI-X table with 6 messages and
1345 * asks for 6 messages, but pci_alloc_msix() only returns a count of
1346 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and
1347 * C. After the call to pci_alloc_msix(), the device will be setup to
1348 * have an MSI-X table of ABC--- (where - means no vector assigned).
1349 * If the driver ten passes a vector array of { 1, 0, 1, 2, 0, 2 },
1350 * then the MSI-X table will look like A-AB-B, and the 'C' vector will
1351 * be freed back to the system. This device will also have valid
1352 * SYS_RES_IRQ rids of 1, 3, 4, and 6.
1354 * In any case, the SYS_RES_IRQ rid X will always map to the message
1355 * at MSI-X table index X - 1 and will only be valid if a vector is
1356 * assigned to that table entry.
1359 pci_remap_msix_method(device_t dev, device_t child, int count,
1360 const u_int *vectors)
1362 struct pci_devinfo *dinfo = device_get_ivars(child);
1363 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1364 struct resource_list_entry *rle;
1365 int i, irq, j, *used;
1368 * Have to have at least one message in the table but the
1369 * table can't be bigger than the actual MSI-X table in the
1372 if (count == 0 || count > msix->msix_msgnum)
1375 /* Sanity check the vectors. */
1376 for (i = 0; i < count; i++)
1377 if (vectors[i] > msix->msix_alloc)
1381 * Make sure there aren't any holes in the vectors to be used.
1382 * It's a big pain to support it, and it doesn't really make
1383 * sense anyway. Also, at least one vector must be used.
1385 used = malloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK |
1387 for (i = 0; i < count; i++)
1388 if (vectors[i] != 0)
1389 used[vectors[i] - 1] = 1;
1390 for (i = 0; i < msix->msix_alloc - 1; i++)
1391 if (used[i] == 0 && used[i + 1] == 1) {
1392 free(used, M_DEVBUF);
1396 free(used, M_DEVBUF);
1400 /* Make sure none of the resources are allocated. */
1401 for (i = 0; i < msix->msix_table_len; i++) {
1402 if (msix->msix_table[i].mte_vector == 0)
1404 if (msix->msix_table[i].mte_handlers > 0)
1406 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1407 KASSERT(rle != NULL, ("missing resource"));
1408 if (rle->res != NULL)
1412 /* Free the existing resource list entries. */
1413 for (i = 0; i < msix->msix_table_len; i++) {
1414 if (msix->msix_table[i].mte_vector == 0)
1416 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1420 * Build the new virtual table keeping track of which vectors are
1423 free(msix->msix_table, M_DEVBUF);
1424 msix->msix_table = malloc(sizeof(struct msix_table_entry) * count,
1425 M_DEVBUF, M_WAITOK | M_ZERO);
1426 for (i = 0; i < count; i++)
1427 msix->msix_table[i].mte_vector = vectors[i];
1428 msix->msix_table_len = count;
1430 /* Free any unused IRQs and resize the vectors array if necessary. */
1431 j = msix->msix_alloc - 1;
1433 struct msix_vector *vec;
1435 while (used[j] == 0) {
1436 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1437 msix->msix_vectors[j].mv_irq);
1440 vec = malloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF,
1442 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) *
1444 free(msix->msix_vectors, M_DEVBUF);
1445 msix->msix_vectors = vec;
1446 msix->msix_alloc = j + 1;
1448 free(used, M_DEVBUF);
1450 /* Map the IRQs onto the rids. */
1451 for (i = 0; i < count; i++) {
1452 if (vectors[i] == 0)
1454 irq = msix->msix_vectors[vectors[i]].mv_irq;
1455 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1460 device_printf(child, "Remapped MSI-X IRQs as: ");
1461 for (i = 0; i < count; i++) {
1464 if (vectors[i] == 0)
1468 msix->msix_vectors[vectors[i]].mv_irq);
1477 pci_release_msix(device_t dev, device_t child)
1479 struct pci_devinfo *dinfo = device_get_ivars(child);
1480 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1481 struct resource_list_entry *rle;
1484 /* Do we have any messages to release? */
1485 if (msix->msix_alloc == 0)
1488 /* Make sure none of the resources are allocated. */
1489 for (i = 0; i < msix->msix_table_len; i++) {
1490 if (msix->msix_table[i].mte_vector == 0)
1492 if (msix->msix_table[i].mte_handlers > 0)
1494 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1495 KASSERT(rle != NULL, ("missing resource"));
1496 if (rle->res != NULL)
1500 /* Update control register to disable MSI-X. */
1501 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
1502 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL,
1503 msix->msix_ctrl, 2);
1505 /* Free the resource list entries. */
1506 for (i = 0; i < msix->msix_table_len; i++) {
1507 if (msix->msix_table[i].mte_vector == 0)
1509 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1511 free(msix->msix_table, M_DEVBUF);
1512 msix->msix_table_len = 0;
1514 /* Release the IRQs. */
1515 for (i = 0; i < msix->msix_alloc; i++)
1516 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1517 msix->msix_vectors[i].mv_irq);
1518 free(msix->msix_vectors, M_DEVBUF);
1519 msix->msix_alloc = 0;
1524 * Return the max supported MSI-X messages this device supports.
1525 * Basically, assuming the MD code can alloc messages, this function
1526 * should return the maximum value that pci_alloc_msix() can return.
1527 * Thus, it is subject to the tunables, etc.
1530 pci_msix_count_method(device_t dev, device_t child)
1532 struct pci_devinfo *dinfo = device_get_ivars(child);
1533 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1535 if (pci_do_msix && msix->msix_location != 0)
1536 return (msix->msix_msgnum);
1541 * HyperTransport MSI mapping control
1544 pci_ht_map_msi(device_t dev, uint64_t addr)
1546 struct pci_devinfo *dinfo = device_get_ivars(dev);
1547 struct pcicfg_ht *ht = &dinfo->cfg.ht;
1552 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) &&
1553 ht->ht_msiaddr >> 20 == addr >> 20) {
1554 /* Enable MSI -> HT mapping. */
1555 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
1556 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1560 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) {
1561 /* Disable MSI -> HT mapping. */
1562 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE;
1563 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1569 * Support for MSI message signalled interrupts.
1572 pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
1574 struct pci_devinfo *dinfo = device_get_ivars(dev);
1575 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1577 /* Write data and address values. */
1578 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1579 address & 0xffffffff, 4);
1580 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1581 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR_HIGH,
1583 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA_64BIT,
1586 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, data,
1589 /* Enable MSI in the control register. */
1590 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE;
1591 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1594 /* Enable MSI -> HT mapping. */
1595 pci_ht_map_msi(dev, address);
1599 pci_disable_msi(device_t dev)
1601 struct pci_devinfo *dinfo = device_get_ivars(dev);
1602 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1604 /* Disable MSI -> HT mapping. */
1605 pci_ht_map_msi(dev, 0);
1607 /* Disable MSI in the control register. */
1608 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE;
1609 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1614 * Restore MSI registers during resume. If MSI is enabled then
1615 * restore the data and address registers in addition to the control
1619 pci_resume_msi(device_t dev)
1621 struct pci_devinfo *dinfo = device_get_ivars(dev);
1622 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1626 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) {
1627 address = msi->msi_addr;
1628 data = msi->msi_data;
1629 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1630 address & 0xffffffff, 4);
1631 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1632 pci_write_config(dev, msi->msi_location +
1633 PCIR_MSI_ADDR_HIGH, address >> 32, 4);
1634 pci_write_config(dev, msi->msi_location +
1635 PCIR_MSI_DATA_64BIT, data, 2);
1637 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA,
1640 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1645 pci_remap_msi_irq(device_t dev, u_int irq)
1647 struct pci_devinfo *dinfo = device_get_ivars(dev);
1648 pcicfgregs *cfg = &dinfo->cfg;
1649 struct resource_list_entry *rle;
1650 struct msix_table_entry *mte;
1651 struct msix_vector *mv;
1657 bus = device_get_parent(dev);
1660 * Handle MSI first. We try to find this IRQ among our list
1661 * of MSI IRQs. If we find it, we request updated address and
1662 * data registers and apply the results.
1664 if (cfg->msi.msi_alloc > 0) {
1666 /* If we don't have any active handlers, nothing to do. */
1667 if (cfg->msi.msi_handlers == 0)
1669 for (i = 0; i < cfg->msi.msi_alloc; i++) {
1670 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ,
1672 if (rle->start == irq) {
1673 error = PCIB_MAP_MSI(device_get_parent(bus),
1674 dev, irq, &addr, &data);
1677 pci_disable_msi(dev);
1678 dinfo->cfg.msi.msi_addr = addr;
1679 dinfo->cfg.msi.msi_data = data;
1680 pci_enable_msi(dev, addr, data);
1688 * For MSI-X, we check to see if we have this IRQ. If we do,
1689 * we request the updated mapping info. If that works, we go
1690 * through all the slots that use this IRQ and update them.
1692 if (cfg->msix.msix_alloc > 0) {
1693 for (i = 0; i < cfg->msix.msix_alloc; i++) {
1694 mv = &cfg->msix.msix_vectors[i];
1695 if (mv->mv_irq == irq) {
1696 error = PCIB_MAP_MSI(device_get_parent(bus),
1697 dev, irq, &addr, &data);
1700 mv->mv_address = addr;
1702 for (j = 0; j < cfg->msix.msix_table_len; j++) {
1703 mte = &cfg->msix.msix_table[j];
1704 if (mte->mte_vector != i + 1)
1706 if (mte->mte_handlers == 0)
1708 pci_mask_msix(dev, j);
1709 pci_enable_msix(dev, j, addr, data);
1710 pci_unmask_msix(dev, j);
1721 * Returns true if the specified device is blacklisted because MSI
1725 pci_msi_device_blacklisted(device_t dev)
1727 struct pci_quirk *q;
1729 if (!pci_honor_msi_blacklist)
1732 for (q = &pci_quirks[0]; q->devid; q++) {
1733 if (q->devid == pci_get_devid(dev) &&
1734 q->type == PCI_QUIRK_DISABLE_MSI)
1741 * Determine if MSI is blacklisted globally on this sytem. Currently,
1742 * we just check for blacklisted chipsets as represented by the
1743 * host-PCI bridge at device 0:0:0. In the future, it may become
1744 * necessary to check other system attributes, such as the kenv values
1745 * that give the motherboard manufacturer and model number.
1748 pci_msi_blacklisted(void)
1752 if (!pci_honor_msi_blacklist)
1755 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */
1756 if (!(pcie_chipset || pcix_chipset))
1759 dev = pci_find_bsf(0, 0, 0);
1761 return (pci_msi_device_blacklisted(dev));
1766 * Attempt to allocate *count MSI messages. The actual number allocated is
1767 * returned in *count. After this function returns, each message will be
1768 * available to the driver as SYS_RES_IRQ resources starting at a rid 1.
1771 pci_alloc_msi_method(device_t dev, device_t child, int *count)
1773 struct pci_devinfo *dinfo = device_get_ivars(child);
1774 pcicfgregs *cfg = &dinfo->cfg;
1775 struct resource_list_entry *rle;
1776 int actual, error, i, irqs[32];
1779 /* Don't let count == 0 get us into trouble. */
1783 /* If rid 0 is allocated, then fail. */
1784 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1785 if (rle != NULL && rle->res != NULL)
1788 /* Already have allocated messages? */
1789 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1792 /* If MSI is blacklisted for this system, fail. */
1793 if (pci_msi_blacklisted())
1796 /* MSI capability present? */
1797 if (cfg->msi.msi_location == 0 || !pci_do_msi)
1801 device_printf(child,
1802 "attempting to allocate %d MSI vectors (%d supported)\n",
1803 *count, cfg->msi.msi_msgnum);
1805 /* Don't ask for more than the device supports. */
1806 actual = min(*count, cfg->msi.msi_msgnum);
1808 /* Don't ask for more than 32 messages. */
1809 actual = min(actual, 32);
1811 /* MSI requires power of 2 number of messages. */
1812 if (!powerof2(actual))
1816 /* Try to allocate N messages. */
1817 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual,
1818 cfg->msi.msi_msgnum, irqs);
1829 * We now have N actual messages mapped onto SYS_RES_IRQ
1830 * resources in the irqs[] array, so add new resources
1831 * starting at rid 1.
1833 for (i = 0; i < actual; i++)
1834 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1,
1835 irqs[i], irqs[i], 1);
1839 device_printf(child, "using IRQ %d for MSI\n", irqs[0]);
1844 * Be fancy and try to print contiguous runs
1845 * of IRQ values as ranges. 'run' is true if
1846 * we are in a range.
1848 device_printf(child, "using IRQs %d", irqs[0]);
1850 for (i = 1; i < actual; i++) {
1852 /* Still in a run? */
1853 if (irqs[i] == irqs[i - 1] + 1) {
1858 /* Finish previous range. */
1860 printf("-%d", irqs[i - 1]);
1864 /* Start new range. */
1865 printf(",%d", irqs[i]);
1868 /* Unfinished range? */
1870 printf("-%d", irqs[actual - 1]);
1871 printf(" for MSI\n");
1875 /* Update control register with actual count. */
1876 ctrl = cfg->msi.msi_ctrl;
1877 ctrl &= ~PCIM_MSICTRL_MME_MASK;
1878 ctrl |= (ffs(actual) - 1) << 4;
1879 cfg->msi.msi_ctrl = ctrl;
1880 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2);
1882 /* Update counts of alloc'd messages. */
1883 cfg->msi.msi_alloc = actual;
1884 cfg->msi.msi_handlers = 0;
1889 /* Release the MSI messages associated with this device. */
1891 pci_release_msi_method(device_t dev, device_t child)
1893 struct pci_devinfo *dinfo = device_get_ivars(child);
1894 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1895 struct resource_list_entry *rle;
1896 int error, i, irqs[32];
1898 /* Try MSI-X first. */
1899 error = pci_release_msix(dev, child);
1900 if (error != ENODEV)
1903 /* Do we have any messages to release? */
1904 if (msi->msi_alloc == 0)
1906 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages"));
1908 /* Make sure none of the resources are allocated. */
1909 if (msi->msi_handlers > 0)
1911 for (i = 0; i < msi->msi_alloc; i++) {
1912 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1913 KASSERT(rle != NULL, ("missing MSI resource"));
1914 if (rle->res != NULL)
1916 irqs[i] = rle->start;
1919 /* Update control register with 0 count. */
1920 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE),
1921 ("%s: MSI still enabled", __func__));
1922 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK;
1923 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
1926 /* Release the messages. */
1927 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs);
1928 for (i = 0; i < msi->msi_alloc; i++)
1929 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1931 /* Update alloc count. */
1939 * Return the max supported MSI messages this device supports.
1940 * Basically, assuming the MD code can alloc messages, this function
1941 * should return the maximum value that pci_alloc_msi() can return.
1942 * Thus, it is subject to the tunables, etc.
1945 pci_msi_count_method(device_t dev, device_t child)
1947 struct pci_devinfo *dinfo = device_get_ivars(child);
1948 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1950 if (pci_do_msi && msi->msi_location != 0)
1951 return (msi->msi_msgnum);
1955 /* free pcicfgregs structure and all depending data structures */
1958 pci_freecfg(struct pci_devinfo *dinfo)
1960 struct devlist *devlist_head;
1963 devlist_head = &pci_devq;
1965 if (dinfo->cfg.vpd.vpd_reg) {
1966 free(dinfo->cfg.vpd.vpd_ident, M_DEVBUF);
1967 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++)
1968 free(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF);
1969 free(dinfo->cfg.vpd.vpd_ros, M_DEVBUF);
1970 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++)
1971 free(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF);
1972 free(dinfo->cfg.vpd.vpd_w, M_DEVBUF);
1974 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
1975 free(dinfo, M_DEVBUF);
1977 /* increment the generation count */
1980 /* we're losing one device */
1986 * PCI power manangement
1989 pci_set_powerstate_method(device_t dev, device_t child, int state)
1991 struct pci_devinfo *dinfo = device_get_ivars(child);
1992 pcicfgregs *cfg = &dinfo->cfg;
1994 int result, oldstate, highest, delay;
1996 if (cfg->pp.pp_cap == 0)
1997 return (EOPNOTSUPP);
2000 * Optimize a no state change request away. While it would be OK to
2001 * write to the hardware in theory, some devices have shown odd
2002 * behavior when going from D3 -> D3.
2004 oldstate = pci_get_powerstate(child);
2005 if (oldstate == state)
2009 * The PCI power management specification states that after a state
2010 * transition between PCI power states, system software must
2011 * guarantee a minimal delay before the function accesses the device.
2012 * Compute the worst case delay that we need to guarantee before we
2013 * access the device. Many devices will be responsive much more
2014 * quickly than this delay, but there are some that don't respond
2015 * instantly to state changes. Transitions to/from D3 state require
2016 * 10ms, while D2 requires 200us, and D0/1 require none. The delay
2017 * is done below with DELAY rather than a sleeper function because
2018 * this function can be called from contexts where we cannot sleep.
2020 highest = (oldstate > state) ? oldstate : state;
2021 if (highest == PCI_POWERSTATE_D3)
2023 else if (highest == PCI_POWERSTATE_D2)
2027 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
2028 & ~PCIM_PSTAT_DMASK;
2031 case PCI_POWERSTATE_D0:
2032 status |= PCIM_PSTAT_D0;
2034 case PCI_POWERSTATE_D1:
2035 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
2036 return (EOPNOTSUPP);
2037 status |= PCIM_PSTAT_D1;
2039 case PCI_POWERSTATE_D2:
2040 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
2041 return (EOPNOTSUPP);
2042 status |= PCIM_PSTAT_D2;
2044 case PCI_POWERSTATE_D3:
2045 status |= PCIM_PSTAT_D3;
2053 "pci%d:%d:%d:%d: Transition from D%d to D%d\n",
2054 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
2055 dinfo->cfg.func, oldstate, state);
2057 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
2064 pci_get_powerstate_method(device_t dev, device_t child)
2066 struct pci_devinfo *dinfo = device_get_ivars(child);
2067 pcicfgregs *cfg = &dinfo->cfg;
2071 if (cfg->pp.pp_cap != 0) {
2072 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
2073 switch (status & PCIM_PSTAT_DMASK) {
2075 result = PCI_POWERSTATE_D0;
2078 result = PCI_POWERSTATE_D1;
2081 result = PCI_POWERSTATE_D2;
2084 result = PCI_POWERSTATE_D3;
2087 result = PCI_POWERSTATE_UNKNOWN;
2091 /* No support, device is always at D0 */
2092 result = PCI_POWERSTATE_D0;
2098 * Some convenience functions for PCI device drivers.
2101 static __inline void
2102 pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
2106 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2108 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2111 static __inline void
2112 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
2116 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2118 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2122 pci_enable_busmaster_method(device_t dev, device_t child)
2124 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2129 pci_disable_busmaster_method(device_t dev, device_t child)
2131 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2136 pci_enable_io_method(device_t dev, device_t child, int space)
2146 case SYS_RES_IOPORT:
2147 bit = PCIM_CMD_PORTEN;
2150 case SYS_RES_MEMORY:
2151 bit = PCIM_CMD_MEMEN;
2157 pci_set_command_bit(dev, child, bit);
2158 /* Some devices seem to need a brief stall here, what do to? */
2159 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2162 device_printf(child, "failed to enable %s mapping!\n", error);
2167 pci_disable_io_method(device_t dev, device_t child, int space)
2177 case SYS_RES_IOPORT:
2178 bit = PCIM_CMD_PORTEN;
2181 case SYS_RES_MEMORY:
2182 bit = PCIM_CMD_MEMEN;
2188 pci_clear_command_bit(dev, child, bit);
2189 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2190 if (command & bit) {
2191 device_printf(child, "failed to disable %s mapping!\n", error);
2198 * New style pci driver. Parent device is either a pci-host-bridge or a
2199 * pci-pci-bridge. Both kinds are represented by instances of pcib.
2203 pci_print_verbose(struct pci_devinfo *dinfo)
2207 pcicfgregs *cfg = &dinfo->cfg;
2209 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
2210 cfg->vendor, cfg->device, cfg->revid);
2211 printf("\tdomain=%d, bus=%d, slot=%d, func=%d\n",
2212 cfg->domain, cfg->bus, cfg->slot, cfg->func);
2213 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
2214 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
2216 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
2217 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
2218 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
2219 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
2220 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
2221 if (cfg->intpin > 0)
2222 printf("\tintpin=%c, irq=%d\n",
2223 cfg->intpin +'a' -1, cfg->intline);
2224 if (cfg->pp.pp_cap) {
2227 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
2228 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
2229 cfg->pp.pp_cap & PCIM_PCAP_SPEC,
2230 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
2231 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
2232 status & PCIM_PSTAT_DMASK);
2234 if (cfg->msi.msi_location) {
2237 ctrl = cfg->msi.msi_ctrl;
2238 printf("\tMSI supports %d message%s%s%s\n",
2239 cfg->msi.msi_msgnum,
2240 (cfg->msi.msi_msgnum == 1) ? "" : "s",
2241 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
2242 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");
2244 if (cfg->msix.msix_location) {
2245 printf("\tMSI-X supports %d message%s ",
2246 cfg->msix.msix_msgnum,
2247 (cfg->msix.msix_msgnum == 1) ? "" : "s");
2248 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar)
2249 printf("in map 0x%x\n",
2250 cfg->msix.msix_table_bar);
2252 printf("in maps 0x%x and 0x%x\n",
2253 cfg->msix.msix_table_bar,
2254 cfg->msix.msix_pba_bar);
2260 pci_porten(device_t dev)
2262 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_PORTEN) != 0;
2266 pci_memen(device_t dev)
2268 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0;
2272 pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp)
2274 pci_addr_t map, testval;
2278 map = pci_read_config(dev, reg, 4);
2279 ln2range = pci_maprange(map);
2281 map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32;
2284 * Disable decoding via the command register before
2285 * determining the BAR's length since we will be placing it in
2288 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2289 pci_write_config(dev, PCIR_COMMAND,
2290 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2);
2293 * Determine the BAR's length by writing all 1's. The bottom
2294 * log_2(size) bits of the BAR will stick as 0 when we read
2297 pci_write_config(dev, reg, 0xffffffff, 4);
2298 testval = pci_read_config(dev, reg, 4);
2299 if (ln2range == 64) {
2300 pci_write_config(dev, reg + 4, 0xffffffff, 4);
2301 testval |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32;
2305 * Restore the original value of the BAR. We may have reprogrammed
2306 * the BAR of the low-level console device and when booting verbose,
2307 * we need the console device addressable.
2309 pci_write_config(dev, reg, map, 4);
2311 pci_write_config(dev, reg + 4, map >> 32, 4);
2312 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
2315 *testvalp = testval;
2319 pci_write_bar(device_t dev, int reg, pci_addr_t base)
2324 map = pci_read_config(dev, reg, 4);
2325 ln2range = pci_maprange(map);
2326 pci_write_config(dev, reg, base, 4);
2328 pci_write_config(dev, reg + 4, base >> 32, 4);
2332 * Add a resource based on a pci map register. Return 1 if the map
2333 * register is a 32bit map register or 2 if it is a 64bit register.
2336 pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl,
2337 int force, int prefetch)
2339 pci_addr_t base, map, testval;
2340 pci_addr_t start, end, count;
2341 int barlen, maprange, mapsize, type;
2343 struct resource *res;
2345 pci_read_bar(dev, reg, &map, &testval);
2346 if (PCI_BAR_MEM(map)) {
2347 type = SYS_RES_MEMORY;
2348 if (map & PCIM_BAR_MEM_PREFETCH)
2351 type = SYS_RES_IOPORT;
2352 mapsize = pci_mapsize(testval);
2353 base = pci_mapbase(map);
2354 maprange = pci_maprange(map);
2355 barlen = maprange == 64 ? 2 : 1;
2358 * For I/O registers, if bottom bit is set, and the next bit up
2359 * isn't clear, we know we have a BAR that doesn't conform to the
2360 * spec, so ignore it. Also, sanity check the size of the data
2361 * areas to the type of memory involved. Memory must be at least
2362 * 16 bytes in size, while I/O ranges must be at least 4.
2364 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0)
2366 if ((type == SYS_RES_MEMORY && mapsize < 4) ||
2367 (type == SYS_RES_IOPORT && mapsize < 2))
2371 printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d",
2372 reg, pci_maptype(map), maprange, (uintmax_t)base, mapsize);
2373 if (type == SYS_RES_IOPORT && !pci_porten(dev))
2374 printf(", port disabled\n");
2375 else if (type == SYS_RES_MEMORY && !pci_memen(dev))
2376 printf(", memory disabled\n");
2378 printf(", enabled\n");
2382 * If base is 0, then we have problems. It is best to ignore
2383 * such entries for the moment. These will be allocated later if
2384 * the driver specifically requests them. However, some
2385 * removable busses look better when all resources are allocated,
2386 * so allow '0' to be overriden.
2388 * Similarly treat maps whose values is the same as the test value
2389 * read back. These maps have had all f's written to them by the
2390 * BIOS in an attempt to disable the resources.
2392 if (!force && (base == 0 || map == testval))
2394 if ((u_long)base != base) {
2396 "pci%d:%d:%d:%d bar %#x too many address bits",
2397 pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev),
2398 pci_get_function(dev), reg);
2403 * This code theoretically does the right thing, but has
2404 * undesirable side effects in some cases where peripherals
2405 * respond oddly to having these bits enabled. Let the user
2406 * be able to turn them off (since pci_enable_io_modes is 1 by
2409 if (pci_enable_io_modes) {
2410 /* Turn on resources that have been left off by a lazy BIOS */
2411 if (type == SYS_RES_IOPORT && !pci_porten(dev)) {
2412 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2413 cmd |= PCIM_CMD_PORTEN;
2414 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
2416 if (type == SYS_RES_MEMORY && !pci_memen(dev)) {
2417 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2418 cmd |= PCIM_CMD_MEMEN;
2419 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
2422 if (type == SYS_RES_IOPORT && !pci_porten(dev))
2424 if (type == SYS_RES_MEMORY && !pci_memen(dev))
2428 count = 1 << mapsize;
2429 if (base == 0 || base == pci_mapbase(testval)) {
2430 start = 0; /* Let the parent decide. */
2434 end = base + (1 << mapsize) - 1;
2436 resource_list_add(rl, type, reg, start, end, count);
2439 * Try to allocate the resource for this BAR from our parent
2440 * so that this resource range is already reserved. The
2441 * driver for this device will later inherit this resource in
2442 * pci_alloc_resource().
2444 res = resource_list_alloc(rl, bus, dev, type, ®, start, end, count,
2445 prefetch ? RF_PREFETCHABLE : 0);
2448 * If the allocation fails, clear the BAR and delete
2449 * the resource list entry to force
2450 * pci_alloc_resource() to allocate resources from the
2453 resource_list_delete(rl, type, reg);
2456 start = rman_get_start(res);
2457 rman_set_device(res, bus);
2459 pci_write_bar(dev, reg, start);
2464 * For ATA devices we need to decide early what addressing mode to use.
2465 * Legacy demands that the primary and secondary ATA ports sits on the
2466 * same addresses that old ISA hardware did. This dictates that we use
2467 * those addresses and ignore the BAR's if we cannot set PCI native
2471 pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force,
2472 uint32_t prefetchmask)
2475 int rid, type, progif;
2477 /* if this device supports PCI native addressing use it */
2478 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2479 if ((progif & 0x8a) == 0x8a) {
2480 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
2481 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
2482 printf("Trying ATA native PCI addressing mode\n");
2483 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
2487 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2488 type = SYS_RES_IOPORT;
2489 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
2490 pci_add_map(bus, dev, PCIR_BAR(0), rl, force,
2491 prefetchmask & (1 << 0));
2492 pci_add_map(bus, dev, PCIR_BAR(1), rl, force,
2493 prefetchmask & (1 << 1));
2496 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
2497 r = resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7,
2499 rman_set_device(r, bus);
2501 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
2502 r = resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6,
2504 rman_set_device(r, bus);
2506 if (progif & PCIP_STORAGE_IDE_MODESEC) {
2507 pci_add_map(bus, dev, PCIR_BAR(2), rl, force,
2508 prefetchmask & (1 << 2));
2509 pci_add_map(bus, dev, PCIR_BAR(3), rl, force,
2510 prefetchmask & (1 << 3));
2513 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
2514 r = resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177,
2516 rman_set_device(r, bus);
2518 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
2519 r = resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376,
2521 rman_set_device(r, bus);
2523 pci_add_map(bus, dev, PCIR_BAR(4), rl, force,
2524 prefetchmask & (1 << 4));
2525 pci_add_map(bus, dev, PCIR_BAR(5), rl, force,
2526 prefetchmask & (1 << 5));
2530 pci_assign_interrupt(device_t bus, device_t dev, int force_route)
2532 struct pci_devinfo *dinfo = device_get_ivars(dev);
2533 pcicfgregs *cfg = &dinfo->cfg;
2534 char tunable_name[64];
2537 /* Has to have an intpin to have an interrupt. */
2538 if (cfg->intpin == 0)
2541 /* Let the user override the IRQ with a tunable. */
2542 irq = PCI_INVALID_IRQ;
2543 snprintf(tunable_name, sizeof(tunable_name),
2544 "hw.pci%d.%d.%d.INT%c.irq",
2545 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1);
2546 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0))
2547 irq = PCI_INVALID_IRQ;
2550 * If we didn't get an IRQ via the tunable, then we either use the
2551 * IRQ value in the intline register or we ask the bus to route an
2552 * interrupt for us. If force_route is true, then we only use the
2553 * value in the intline register if the bus was unable to assign an
2556 if (!PCI_INTERRUPT_VALID(irq)) {
2557 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
2558 irq = PCI_ASSIGN_INTERRUPT(bus, dev);
2559 if (!PCI_INTERRUPT_VALID(irq))
2563 /* If after all that we don't have an IRQ, just bail. */
2564 if (!PCI_INTERRUPT_VALID(irq))
2567 /* Update the config register if it changed. */
2568 if (irq != cfg->intline) {
2570 pci_write_config(dev, PCIR_INTLINE, irq, 1);
2573 /* Add this IRQ as rid 0 interrupt resource. */
2574 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1);
2578 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask)
2580 struct pci_devinfo *dinfo = device_get_ivars(dev);
2581 pcicfgregs *cfg = &dinfo->cfg;
2582 struct resource_list *rl = &dinfo->resources;
2583 struct pci_quirk *q;
2586 /* ATA devices needs special map treatment */
2587 if ((pci_get_class(dev) == PCIC_STORAGE) &&
2588 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
2589 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
2590 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
2591 !pci_read_config(dev, PCIR_BAR(2), 4))) )
2592 pci_ata_maps(bus, dev, rl, force, prefetchmask);
2594 for (i = 0; i < cfg->nummaps;)
2595 i += pci_add_map(bus, dev, PCIR_BAR(i), rl, force,
2596 prefetchmask & (1 << i));
2599 * Add additional, quirked resources.
2601 for (q = &pci_quirks[0]; q->devid; q++) {
2602 if (q->devid == ((cfg->device << 16) | cfg->vendor)
2603 && q->type == PCI_QUIRK_MAP_REG)
2604 pci_add_map(bus, dev, q->arg1, rl, force, 0);
2607 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
2608 #ifdef __PCI_REROUTE_INTERRUPT
2610 * Try to re-route interrupts. Sometimes the BIOS or
2611 * firmware may leave bogus values in these registers.
2612 * If the re-route fails, then just stick with what we
2615 pci_assign_interrupt(bus, dev, 1);
2617 pci_assign_interrupt(bus, dev, 0);
2623 pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size)
2625 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
2626 device_t pcib = device_get_parent(dev);
2627 struct pci_devinfo *dinfo;
2629 int s, f, pcifunchigh;
2632 KASSERT(dinfo_size >= sizeof(struct pci_devinfo),
2633 ("dinfo_size too small"));
2634 maxslots = PCIB_MAXSLOTS(pcib);
2635 for (s = 0; s <= maxslots; s++) {
2639 hdrtype = REG(PCIR_HDRTYPE, 1);
2640 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
2642 if (hdrtype & PCIM_MFDEV)
2643 pcifunchigh = PCI_FUNCMAX;
2644 for (f = 0; f <= pcifunchigh; f++) {
2645 dinfo = pci_read_device(pcib, domain, busno, s, f,
2647 if (dinfo != NULL) {
2648 pci_add_child(dev, dinfo);
2656 pci_add_child(device_t bus, struct pci_devinfo *dinfo)
2658 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
2659 device_set_ivars(dinfo->cfg.dev, dinfo);
2660 resource_list_init(&dinfo->resources);
2661 pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
2662 pci_cfg_restore(dinfo->cfg.dev, dinfo);
2663 pci_print_verbose(dinfo);
2664 pci_add_resources(bus, dinfo->cfg.dev, 0, 0);
2668 pci_probe(device_t dev)
2671 device_set_desc(dev, "PCI bus");
2673 /* Allow other subclasses to override this driver. */
2674 return (BUS_PROBE_GENERIC);
2678 pci_attach(device_t dev)
2683 * Since there can be multiple independantly numbered PCI
2684 * busses on systems with multiple PCI domains, we can't use
2685 * the unit number to decide which bus we are probing. We ask
2686 * the parent pcib what our domain and bus numbers are.
2688 domain = pcib_get_domain(dev);
2689 busno = pcib_get_bus(dev);
2691 device_printf(dev, "domain=%d, physical bus=%d\n",
2693 pci_add_children(dev, domain, busno, sizeof(struct pci_devinfo));
2694 return (bus_generic_attach(dev));
2698 pci_suspend(device_t dev)
2700 int dstate, error, i, numdevs;
2701 device_t acpi_dev, child, *devlist;
2702 struct pci_devinfo *dinfo;
2705 * Save the PCI configuration space for each child and set the
2706 * device in the appropriate power state for this sleep state.
2709 if (pci_do_power_resume)
2710 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
2711 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0)
2713 for (i = 0; i < numdevs; i++) {
2715 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2716 pci_cfg_save(child, dinfo, 0);
2719 /* Suspend devices before potentially powering them down. */
2720 error = bus_generic_suspend(dev);
2722 free(devlist, M_TEMP);
2727 * Always set the device to D3. If ACPI suggests a different
2728 * power state, use it instead. If ACPI is not present, the
2729 * firmware is responsible for managing device power. Skip
2730 * children who aren't attached since they are powered down
2731 * separately. Only manage type 0 devices for now.
2733 for (i = 0; acpi_dev && i < numdevs; i++) {
2735 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2736 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) {
2737 dstate = PCI_POWERSTATE_D3;
2738 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate);
2739 pci_set_powerstate(child, dstate);
2742 free(devlist, M_TEMP);
2747 pci_resume(device_t dev)
2749 int i, numdevs, error;
2750 device_t acpi_dev, child, *devlist;
2751 struct pci_devinfo *dinfo;
2754 * Set each child to D0 and restore its PCI configuration space.
2757 if (pci_do_power_resume)
2758 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
2759 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0)
2761 for (i = 0; i < numdevs; i++) {
2763 * Notify ACPI we're going to D0 but ignore the result. If
2764 * ACPI is not present, the firmware is responsible for
2765 * managing device power. Only manage type 0 devices for now.
2768 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2769 if (acpi_dev && device_is_attached(child) &&
2770 dinfo->cfg.hdrtype == 0) {
2771 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL);
2772 pci_set_powerstate(child, PCI_POWERSTATE_D0);
2775 /* Now the device is powered up, restore its config space. */
2776 pci_cfg_restore(child, dinfo);
2778 free(devlist, M_TEMP);
2779 return (bus_generic_resume(dev));
2783 pci_load_vendor_data(void)
2785 caddr_t vendordata, info;
2787 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) {
2788 info = preload_search_info(vendordata, MODINFO_ADDR);
2789 pci_vendordata = *(char **)info;
2790 info = preload_search_info(vendordata, MODINFO_SIZE);
2791 pci_vendordata_size = *(size_t *)info;
2792 /* terminate the database */
2793 pci_vendordata[pci_vendordata_size] = '\n';
2798 pci_driver_added(device_t dev, driver_t *driver)
2803 struct pci_devinfo *dinfo;
2807 device_printf(dev, "driver added\n");
2808 DEVICE_IDENTIFY(driver, dev);
2809 if (device_get_children(dev, &devlist, &numdevs) != 0)
2811 for (i = 0; i < numdevs; i++) {
2813 if (device_get_state(child) != DS_NOTPRESENT)
2815 dinfo = device_get_ivars(child);
2816 pci_print_verbose(dinfo);
2818 printf("pci%d:%d:%d:%d: reprobing on driver added\n",
2819 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
2821 pci_cfg_restore(child, dinfo);
2822 if (device_probe_and_attach(child) != 0)
2823 pci_cfg_save(child, dinfo, 1);
2825 free(devlist, M_TEMP);
2829 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
2830 driver_filter_t *filter, driver_intr_t *intr, void *arg, void **cookiep)
2832 struct pci_devinfo *dinfo;
2833 struct msix_table_entry *mte;
2834 struct msix_vector *mv;
2840 error = bus_generic_setup_intr(dev, child, irq, flags, filter, intr,
2845 /* If this is not a direct child, just bail out. */
2846 if (device_get_parent(child) != dev) {
2851 rid = rman_get_rid(irq);
2853 /* Make sure that INTx is enabled */
2854 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
2857 * Check to see if the interrupt is MSI or MSI-X.
2858 * Ask our parent to map the MSI and give
2859 * us the address and data register values.
2860 * If we fail for some reason, teardown the
2861 * interrupt handler.
2863 dinfo = device_get_ivars(child);
2864 if (dinfo->cfg.msi.msi_alloc > 0) {
2865 if (dinfo->cfg.msi.msi_addr == 0) {
2866 KASSERT(dinfo->cfg.msi.msi_handlers == 0,
2867 ("MSI has handlers, but vectors not mapped"));
2868 error = PCIB_MAP_MSI(device_get_parent(dev),
2869 child, rman_get_start(irq), &addr, &data);
2872 dinfo->cfg.msi.msi_addr = addr;
2873 dinfo->cfg.msi.msi_data = data;
2874 pci_enable_msi(child, addr, data);
2876 dinfo->cfg.msi.msi_handlers++;
2878 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
2879 ("No MSI or MSI-X interrupts allocated"));
2880 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
2881 ("MSI-X index too high"));
2882 mte = &dinfo->cfg.msix.msix_table[rid - 1];
2883 KASSERT(mte->mte_vector != 0, ("no message vector"));
2884 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1];
2885 KASSERT(mv->mv_irq == rman_get_start(irq),
2887 if (mv->mv_address == 0) {
2888 KASSERT(mte->mte_handlers == 0,
2889 ("MSI-X table entry has handlers, but vector not mapped"));
2890 error = PCIB_MAP_MSI(device_get_parent(dev),
2891 child, rman_get_start(irq), &addr, &data);
2894 mv->mv_address = addr;
2897 if (mte->mte_handlers == 0) {
2898 pci_enable_msix(child, rid - 1, mv->mv_address,
2900 pci_unmask_msix(child, rid - 1);
2902 mte->mte_handlers++;
2905 /* Make sure that INTx is disabled if we are using MSI/MSIX */
2906 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
2909 (void)bus_generic_teardown_intr(dev, child, irq,
2919 pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
2922 struct msix_table_entry *mte;
2923 struct resource_list_entry *rle;
2924 struct pci_devinfo *dinfo;
2927 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE))
2930 /* If this isn't a direct child, just bail out */
2931 if (device_get_parent(child) != dev)
2932 return(bus_generic_teardown_intr(dev, child, irq, cookie));
2934 rid = rman_get_rid(irq);
2937 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
2940 * Check to see if the interrupt is MSI or MSI-X. If so,
2941 * decrement the appropriate handlers count and mask the
2942 * MSI-X message, or disable MSI messages if the count
2945 dinfo = device_get_ivars(child);
2946 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
2947 if (rle->res != irq)
2949 if (dinfo->cfg.msi.msi_alloc > 0) {
2950 KASSERT(rid <= dinfo->cfg.msi.msi_alloc,
2951 ("MSI-X index too high"));
2952 if (dinfo->cfg.msi.msi_handlers == 0)
2954 dinfo->cfg.msi.msi_handlers--;
2955 if (dinfo->cfg.msi.msi_handlers == 0)
2956 pci_disable_msi(child);
2958 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
2959 ("No MSI or MSI-X interrupts allocated"));
2960 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
2961 ("MSI-X index too high"));
2962 mte = &dinfo->cfg.msix.msix_table[rid - 1];
2963 if (mte->mte_handlers == 0)
2965 mte->mte_handlers--;
2966 if (mte->mte_handlers == 0)
2967 pci_mask_msix(child, rid - 1);
2970 error = bus_generic_teardown_intr(dev, child, irq, cookie);
2973 ("%s: generic teardown failed for MSI/MSI-X", __func__));
2978 pci_print_child(device_t dev, device_t child)
2980 struct pci_devinfo *dinfo;
2981 struct resource_list *rl;
2984 dinfo = device_get_ivars(child);
2985 rl = &dinfo->resources;
2987 retval += bus_print_child_header(dev, child);
2989 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx");
2990 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
2991 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
2992 if (device_get_flags(dev))
2993 retval += printf(" flags %#x", device_get_flags(dev));
2995 retval += printf(" at device %d.%d", pci_get_slot(child),
2996 pci_get_function(child));
2998 retval += bus_print_child_footer(dev, child);
3008 } pci_nomatch_tab[] = {
3009 {PCIC_OLD, -1, "old"},
3010 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"},
3011 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"},
3012 {PCIC_STORAGE, -1, "mass storage"},
3013 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"},
3014 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"},
3015 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"},
3016 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"},
3017 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"},
3018 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, "ATA (ADMA)"},
3019 {PCIC_STORAGE, PCIS_STORAGE_SATA, "SATA"},
3020 {PCIC_STORAGE, PCIS_STORAGE_SAS, "SAS"},
3021 {PCIC_NETWORK, -1, "network"},
3022 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"},
3023 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"},
3024 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"},
3025 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"},
3026 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"},
3027 {PCIC_DISPLAY, -1, "display"},
3028 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"},
3029 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"},
3030 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"},
3031 {PCIC_MULTIMEDIA, -1, "multimedia"},
3032 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"},
3033 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"},
3034 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"},
3035 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, "HDA"},
3036 {PCIC_MEMORY, -1, "memory"},
3037 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"},
3038 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"},
3039 {PCIC_BRIDGE, -1, "bridge"},
3040 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"},
3041 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"},
3042 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"},
3043 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"},
3044 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"},
3045 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"},
3046 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"},
3047 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"},
3048 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"},
3049 {PCIC_SIMPLECOMM, -1, "simple comms"},
3050 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */
3051 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"},
3052 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"},
3053 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"},
3054 {PCIC_BASEPERIPH, -1, "base peripheral"},
3055 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"},
3056 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"},
3057 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"},
3058 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"},
3059 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"},
3060 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, "SD host controller"},
3061 {PCIC_INPUTDEV, -1, "input device"},
3062 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"},
3063 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"},
3064 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"},
3065 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"},
3066 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"},
3067 {PCIC_DOCKING, -1, "docking station"},
3068 {PCIC_PROCESSOR, -1, "processor"},
3069 {PCIC_SERIALBUS, -1, "serial bus"},
3070 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"},
3071 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"},
3072 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"},
3073 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"},
3074 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"},
3075 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"},
3076 {PCIC_WIRELESS, -1, "wireless controller"},
3077 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"},
3078 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"},
3079 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"},
3080 {PCIC_INTELLIIO, -1, "intelligent I/O controller"},
3081 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"},
3082 {PCIC_SATCOM, -1, "satellite communication"},
3083 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"},
3084 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"},
3085 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"},
3086 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"},
3087 {PCIC_CRYPTO, -1, "encrypt/decrypt"},
3088 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"},
3089 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"},
3090 {PCIC_DASP, -1, "dasp"},
3091 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"},
3096 pci_probe_nomatch(device_t dev, device_t child)
3099 char *cp, *scp, *device;
3102 * Look for a listing for this device in a loaded device database.
3104 if ((device = pci_describe_device(child)) != NULL) {
3105 device_printf(dev, "<%s>", device);
3106 free(device, M_DEVBUF);
3109 * Scan the class/subclass descriptions for a general
3114 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) {
3115 if (pci_nomatch_tab[i].class == pci_get_class(child)) {
3116 if (pci_nomatch_tab[i].subclass == -1) {
3117 cp = pci_nomatch_tab[i].desc;
3118 } else if (pci_nomatch_tab[i].subclass ==
3119 pci_get_subclass(child)) {
3120 scp = pci_nomatch_tab[i].desc;
3124 device_printf(dev, "<%s%s%s>",
3126 ((cp != NULL) && (scp != NULL)) ? ", " : "",
3129 printf(" at device %d.%d (no driver attached)\n",
3130 pci_get_slot(child), pci_get_function(child));
3131 pci_cfg_save(child, (struct pci_devinfo *)device_get_ivars(child), 1);
3136 * Parse the PCI device database, if loaded, and return a pointer to a
3137 * description of the device.
3139 * The database is flat text formatted as follows:
3141 * Any line not in a valid format is ignored.
3142 * Lines are terminated with newline '\n' characters.
3144 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then
3147 * A DEVICE line is entered immediately below the corresponding VENDOR ID.
3148 * - devices cannot be listed without a corresponding VENDOR line.
3149 * A DEVICE line consists of a TAB, the 4 digit (hex) device code,
3150 * another TAB, then the device name.
3154 * Assuming (ptr) points to the beginning of a line in the database,
3155 * return the vendor or device and description of the next entry.
3156 * The value of (vendor) or (device) inappropriate for the entry type
3157 * is set to -1. Returns nonzero at the end of the database.
3159 * Note that this is slightly unrobust in the face of corrupt data;
3160 * we attempt to safeguard against this by spamming the end of the
3161 * database with a newline when we initialise.
3164 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc)
3173 left = pci_vendordata_size - (cp - pci_vendordata);
3181 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2)
3185 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2)
3188 /* skip to next line */
3189 while (*cp != '\n' && left > 0) {
3198 /* skip to next line */
3199 while (*cp != '\n' && left > 0) {
3203 if (*cp == '\n' && left > 0)
3210 pci_describe_device(device_t dev)
3213 char *desc, *vp, *dp, *line;
3215 desc = vp = dp = NULL;
3218 * If we have no vendor data, we can't do anything.
3220 if (pci_vendordata == NULL)
3224 * Scan the vendor data looking for this device
3226 line = pci_vendordata;
3227 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3230 if (pci_describe_parse_line(&line, &vendor, &device, &vp))
3232 if (vendor == pci_get_vendor(dev))
3235 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3238 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) {
3246 if (device == pci_get_device(dev))
3250 snprintf(dp, 80, "0x%x", pci_get_device(dev));
3251 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) !=
3253 sprintf(desc, "%s, %s", vp, dp);
3263 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
3265 struct pci_devinfo *dinfo;
3268 dinfo = device_get_ivars(child);
3272 case PCI_IVAR_ETHADDR:
3274 * The generic accessor doesn't deal with failure, so
3275 * we set the return value, then return an error.
3277 *((uint8_t **) result) = NULL;
3279 case PCI_IVAR_SUBVENDOR:
3280 *result = cfg->subvendor;
3282 case PCI_IVAR_SUBDEVICE:
3283 *result = cfg->subdevice;
3285 case PCI_IVAR_VENDOR:
3286 *result = cfg->vendor;
3288 case PCI_IVAR_DEVICE:
3289 *result = cfg->device;
3291 case PCI_IVAR_DEVID:
3292 *result = (cfg->device << 16) | cfg->vendor;
3294 case PCI_IVAR_CLASS:
3295 *result = cfg->baseclass;
3297 case PCI_IVAR_SUBCLASS:
3298 *result = cfg->subclass;
3300 case PCI_IVAR_PROGIF:
3301 *result = cfg->progif;
3303 case PCI_IVAR_REVID:
3304 *result = cfg->revid;
3306 case PCI_IVAR_INTPIN:
3307 *result = cfg->intpin;
3310 *result = cfg->intline;
3312 case PCI_IVAR_DOMAIN:
3313 *result = cfg->domain;
3319 *result = cfg->slot;
3321 case PCI_IVAR_FUNCTION:
3322 *result = cfg->func;
3324 case PCI_IVAR_CMDREG:
3325 *result = cfg->cmdreg;
3327 case PCI_IVAR_CACHELNSZ:
3328 *result = cfg->cachelnsz;
3330 case PCI_IVAR_MINGNT:
3331 *result = cfg->mingnt;
3333 case PCI_IVAR_MAXLAT:
3334 *result = cfg->maxlat;
3336 case PCI_IVAR_LATTIMER:
3337 *result = cfg->lattimer;
3346 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
3348 struct pci_devinfo *dinfo;
3350 dinfo = device_get_ivars(child);
3353 case PCI_IVAR_INTPIN:
3354 dinfo->cfg.intpin = value;
3356 case PCI_IVAR_ETHADDR:
3357 case PCI_IVAR_SUBVENDOR:
3358 case PCI_IVAR_SUBDEVICE:
3359 case PCI_IVAR_VENDOR:
3360 case PCI_IVAR_DEVICE:
3361 case PCI_IVAR_DEVID:
3362 case PCI_IVAR_CLASS:
3363 case PCI_IVAR_SUBCLASS:
3364 case PCI_IVAR_PROGIF:
3365 case PCI_IVAR_REVID:
3367 case PCI_IVAR_DOMAIN:
3370 case PCI_IVAR_FUNCTION:
3371 return (EINVAL); /* disallow for now */
3379 #include "opt_ddb.h"
3381 #include <ddb/ddb.h>
3382 #include <sys/cons.h>
3385 * List resources based on pci map registers, used for within ddb
3388 DB_SHOW_COMMAND(pciregs, db_pci_dump)
3390 struct pci_devinfo *dinfo;
3391 struct devlist *devlist_head;
3394 int i, error, none_count;
3397 /* get the head of the device queue */
3398 devlist_head = &pci_devq;
3401 * Go through the list of devices and print out devices
3403 for (error = 0, i = 0,
3404 dinfo = STAILQ_FIRST(devlist_head);
3405 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit;
3406 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
3408 /* Populate pd_name and pd_unit */
3411 name = device_get_name(dinfo->cfg.dev);
3414 db_printf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x "
3415 "chip=0x%08x rev=0x%02x hdr=0x%02x\n",
3416 (name && *name) ? name : "none",
3417 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
3419 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev,
3420 p->pc_sel.pc_func, (p->pc_class << 16) |
3421 (p->pc_subclass << 8) | p->pc_progif,
3422 (p->pc_subdevice << 16) | p->pc_subvendor,
3423 (p->pc_device << 16) | p->pc_vendor,
3424 p->pc_revid, p->pc_hdr);
3429 static struct resource *
3430 pci_alloc_map(device_t dev, device_t child, int type, int *rid,
3431 u_long start, u_long end, u_long count, u_int flags)
3433 struct pci_devinfo *dinfo = device_get_ivars(child);
3434 struct resource_list *rl = &dinfo->resources;
3435 struct resource_list_entry *rle;
3436 struct resource *res;
3437 pci_addr_t map, testval;
3441 * Weed out the bogons, and figure out how large the BAR/map
3442 * is. Bars that read back 0 here are bogus and unimplemented.
3443 * Note: atapci in legacy mode are special and handled elsewhere
3444 * in the code. If you have a atapci device in legacy mode and
3445 * it fails here, that other code is broken.
3448 pci_read_bar(child, *rid, &map, &testval);
3450 /* Ignore a BAR with a base of 0. */
3451 if (pci_mapbase(testval) == 0)
3454 if (PCI_BAR_MEM(testval)) {
3455 if (type != SYS_RES_MEMORY) {
3458 "child %s requested type %d for rid %#x,"
3459 " but the BAR says it is an memio\n",
3460 device_get_nameunit(child), type, *rid);
3464 if (type != SYS_RES_IOPORT) {
3467 "child %s requested type %d for rid %#x,"
3468 " but the BAR says it is an ioport\n",
3469 device_get_nameunit(child), type, *rid);
3475 * For real BARs, we need to override the size that
3476 * the driver requests, because that's what the BAR
3477 * actually uses and we would otherwise have a
3478 * situation where we might allocate the excess to
3479 * another driver, which won't work.
3481 mapsize = pci_mapsize(testval);
3482 count = 1UL << mapsize;
3483 if (RF_ALIGNMENT(flags) < mapsize)
3484 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
3485 if (PCI_BAR_MEM(testval) && (testval & PCIM_BAR_MEM_PREFETCH))
3486 flags |= RF_PREFETCHABLE;
3489 * Allocate enough resource, and then write back the
3490 * appropriate bar for that resource.
3492 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
3493 start, end, count, flags & ~RF_ACTIVE);
3495 device_printf(child,
3496 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n",
3497 count, *rid, type, start, end);
3500 rman_set_device(res, dev);
3501 resource_list_add(rl, type, *rid, start, end, count);
3502 rle = resource_list_find(rl, type, *rid);
3504 panic("pci_alloc_map: unexpectedly can't find resource.");
3506 rle->start = rman_get_start(res);
3507 rle->end = rman_get_end(res);
3510 device_printf(child,
3511 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n",
3512 count, *rid, type, rman_get_start(res));
3513 map = rman_get_start(res);
3514 pci_write_bar(child, *rid, map);
3521 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
3522 u_long start, u_long end, u_long count, u_int flags)
3524 struct pci_devinfo *dinfo = device_get_ivars(child);
3525 struct resource_list *rl = &dinfo->resources;
3526 struct resource_list_entry *rle;
3527 struct resource *res;
3528 pcicfgregs *cfg = &dinfo->cfg;
3530 if (device_get_parent(child) != dev)
3531 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
3532 type, rid, start, end, count, flags));
3535 * Perform lazy resource allocation
3540 * Can't alloc legacy interrupt once MSI messages have
3543 if (*rid == 0 && (cfg->msi.msi_alloc > 0 ||
3544 cfg->msix.msix_alloc > 0))
3548 * If the child device doesn't have an interrupt
3549 * routed and is deserving of an interrupt, try to
3552 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) &&
3554 pci_assign_interrupt(dev, child, 0);
3556 case SYS_RES_IOPORT:
3557 case SYS_RES_MEMORY:
3558 /* Allocate resources for this BAR if needed. */
3559 rle = resource_list_find(rl, type, *rid);
3561 res = pci_alloc_map(dev, child, type, rid, start, end,
3565 rle = resource_list_find(rl, type, *rid);
3569 * If the resource belongs to the bus, then give it to
3570 * the child. We need to activate it if requested
3571 * since the bus always allocates inactive resources.
3573 if (rle != NULL && rle->res != NULL &&
3574 rman_get_device(rle->res) == dev) {
3576 device_printf(child,
3577 "Reserved %#lx bytes for rid %#x type %d at %#lx\n",
3578 rman_get_size(rle->res), *rid, type,
3579 rman_get_start(rle->res));
3580 rman_set_device(rle->res, child);
3581 if ((flags & RF_ACTIVE) &&
3582 bus_activate_resource(child, type, *rid,
3588 return (resource_list_alloc(rl, dev, child, type, rid,
3589 start, end, count, flags));
3593 pci_release_resource(device_t dev, device_t child, int type, int rid,
3598 if (device_get_parent(child) != dev)
3599 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
3603 * For BARs we don't actually want to release the resource.
3604 * Instead, we deactivate the resource if needed and then give
3605 * ownership of the BAR back to the bus.
3608 case SYS_RES_IOPORT:
3609 case SYS_RES_MEMORY:
3610 if (rman_get_device(r) != child)
3612 if (rman_get_flags(r) & RF_ACTIVE) {
3613 error = bus_deactivate_resource(child, type, rid, r);
3617 rman_set_device(r, dev);
3620 return (bus_generic_rl_release_resource(dev, child, type, rid, r));
3624 pci_activate_resource(device_t dev, device_t child, int type, int rid,
3629 error = bus_generic_activate_resource(dev, child, type, rid, r);
3633 /* Enable decoding in the command register when activating BARs. */
3634 if (device_get_parent(child) == dev) {
3636 case SYS_RES_IOPORT:
3637 case SYS_RES_MEMORY:
3638 error = PCI_ENABLE_IO(dev, child, type);
3646 pci_delete_resource(device_t dev, device_t child, int type, int rid)
3648 struct pci_devinfo *dinfo;
3649 struct resource_list *rl;
3650 struct resource_list_entry *rle;
3652 if (device_get_parent(child) != dev)
3655 dinfo = device_get_ivars(child);
3656 rl = &dinfo->resources;
3657 rle = resource_list_find(rl, type, rid);
3662 if (rman_get_device(rle->res) != dev ||
3663 rman_get_flags(rle->res) & RF_ACTIVE) {
3664 device_printf(dev, "delete_resource: "
3665 "Resource still owned by child, oops. "
3666 "(type=%d, rid=%d, addr=%lx)\n",
3667 rle->type, rle->rid,
3668 rman_get_start(rle->res));
3673 * If this is a BAR, clear the BAR so it stops
3674 * decoding before releasing the resource.
3677 case SYS_RES_IOPORT:
3678 case SYS_RES_MEMORY:
3679 pci_write_bar(child, rid, 0);
3682 bus_release_resource(dev, type, rid, rle->res);
3684 resource_list_delete(rl, type, rid);
3687 struct resource_list *
3688 pci_get_resource_list (device_t dev, device_t child)
3690 struct pci_devinfo *dinfo = device_get_ivars(child);
3692 return (&dinfo->resources);
3696 pci_read_config_method(device_t dev, device_t child, int reg, int width)
3698 struct pci_devinfo *dinfo = device_get_ivars(child);
3699 pcicfgregs *cfg = &dinfo->cfg;
3701 return (PCIB_READ_CONFIG(device_get_parent(dev),
3702 cfg->bus, cfg->slot, cfg->func, reg, width));
3706 pci_write_config_method(device_t dev, device_t child, int reg,
3707 uint32_t val, int width)
3709 struct pci_devinfo *dinfo = device_get_ivars(child);
3710 pcicfgregs *cfg = &dinfo->cfg;
3712 PCIB_WRITE_CONFIG(device_get_parent(dev),
3713 cfg->bus, cfg->slot, cfg->func, reg, val, width);
3717 pci_child_location_str_method(device_t dev, device_t child, char *buf,
3721 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
3722 pci_get_function(child));
3727 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
3730 struct pci_devinfo *dinfo;
3733 dinfo = device_get_ivars(child);
3735 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
3736 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
3737 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
3743 pci_assign_interrupt_method(device_t dev, device_t child)
3745 struct pci_devinfo *dinfo = device_get_ivars(child);
3746 pcicfgregs *cfg = &dinfo->cfg;
3748 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
3753 pci_modevent(module_t mod, int what, void *arg)
3755 static struct cdev *pci_cdev;
3759 STAILQ_INIT(&pci_devq);
3761 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644,
3763 pci_load_vendor_data();
3767 destroy_dev(pci_cdev);
3775 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
3780 * Only do header type 0 devices. Type 1 devices are bridges,
3781 * which we know need special treatment. Type 2 devices are
3782 * cardbus bridges which also require special treatment.
3783 * Other types are unknown, and we err on the side of safety
3786 if (dinfo->cfg.hdrtype != 0)
3790 * Restore the device to full power mode. We must do this
3791 * before we restore the registers because moving from D3 to
3792 * D0 will cause the chip's BARs and some other registers to
3793 * be reset to some unknown power on reset values. Cut down
3794 * the noise on boot by doing nothing if we are already in
3797 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
3798 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
3800 for (i = 0; i < dinfo->cfg.nummaps; i++)
3801 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4);
3802 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4);
3803 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
3804 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
3805 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
3806 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
3807 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
3808 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
3809 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
3810 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
3811 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
3813 /* Restore MSI and MSI-X configurations if they are present. */
3814 if (dinfo->cfg.msi.msi_location != 0)
3815 pci_resume_msi(dev);
3816 if (dinfo->cfg.msix.msix_location != 0)
3817 pci_resume_msix(dev);
3821 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
3828 * Only do header type 0 devices. Type 1 devices are bridges, which
3829 * we know need special treatment. Type 2 devices are cardbus bridges
3830 * which also require special treatment. Other types are unknown, and
3831 * we err on the side of safety by ignoring them. Powering down
3832 * bridges should not be undertaken lightly.
3834 if (dinfo->cfg.hdrtype != 0)
3836 for (i = 0; i < dinfo->cfg.nummaps; i++)
3837 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4);
3838 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4);
3841 * Some drivers apparently write to these registers w/o updating our
3842 * cached copy. No harm happens if we update the copy, so do so here
3843 * so we can restore them. The COMMAND register is modified by the
3844 * bus w/o updating the cache. This should represent the normally
3845 * writable portion of the 'defined' part of type 0 headers. In
3846 * theory we also need to save/restore the PCI capability structures
3847 * we know about, but apart from power we don't know any that are
3850 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
3851 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
3852 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
3853 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
3854 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
3855 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
3856 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
3857 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
3858 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
3859 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
3860 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
3861 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
3862 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
3863 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
3864 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
3867 * don't set the state for display devices, base peripherals and
3868 * memory devices since bad things happen when they are powered down.
3869 * We should (a) have drivers that can easily detach and (b) use
3870 * generic drivers for these devices so that some device actually
3871 * attaches. We need to make sure that when we implement (a) we don't
3872 * power the device down on a reattach.
3874 cls = pci_get_class(dev);
3877 switch (pci_do_power_nodriver)
3879 case 0: /* NO powerdown at all */
3881 case 1: /* Conservative about what to power down */
3882 if (cls == PCIC_STORAGE)
3885 case 2: /* Agressive about what to power down */
3886 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY ||
3887 cls == PCIC_BASEPERIPH)
3890 case 3: /* Power down everything */
3894 * PCI spec says we can only go into D3 state from D0 state.
3895 * Transition from D[12] into D0 before going to D3 state.
3897 ps = pci_get_powerstate(dev);
3898 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
3899 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
3900 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
3901 pci_set_powerstate(dev, PCI_POWERSTATE_D3);