2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
5 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
6 * Copyright (c) 2000, BSDi
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice unmodified, this list of conditions, and the following
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
35 #include "opt_iommu.h"
38 #include <sys/param.h>
40 #include <sys/endian.h>
41 #include <sys/eventhandler.h>
42 #include <sys/fcntl.h>
43 #include <sys/kernel.h>
44 #include <sys/limits.h>
45 #include <sys/linker.h>
46 #include <sys/malloc.h>
47 #include <sys/module.h>
48 #include <sys/queue.h>
49 #include <sys/sysctl.h>
50 #include <sys/systm.h>
51 #include <sys/taskqueue.h>
56 #include <vm/vm_extern.h>
59 #include <machine/bus.h>
61 #include <machine/resource.h>
62 #include <machine/stdarg.h>
64 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
65 #include <machine/intr_machdep.h>
68 #include <sys/pciio.h>
69 #include <dev/pci/pcireg.h>
70 #include <dev/pci/pcivar.h>
71 #include <dev/pci/pci_private.h>
75 #include <dev/pci/pci_iov_private.h>
78 #include <dev/usb/controller/xhcireg.h>
79 #include <dev/usb/controller/ehcireg.h>
80 #include <dev/usb/controller/ohcireg.h>
81 #include <dev/usb/controller/uhcireg.h>
83 #include <dev/iommu/iommu.h>
88 #define PCIR_IS_BIOS(cfg, reg) \
89 (((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \
90 ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1))
92 static int pci_has_quirk(uint32_t devid, int quirk);
93 static pci_addr_t pci_mapbase(uint64_t mapreg);
94 static const char *pci_maptype(uint64_t mapreg);
95 static int pci_maprange(uint64_t mapreg);
96 static pci_addr_t pci_rombase(uint64_t mapreg);
97 static int pci_romsize(uint64_t testval);
98 static void pci_fixancient(pcicfgregs *cfg);
99 static int pci_printf(pcicfgregs *cfg, const char *fmt, ...);
101 static int pci_porten(device_t dev);
102 static int pci_memen(device_t dev);
103 static void pci_assign_interrupt(device_t bus, device_t dev,
105 static int pci_add_map(device_t bus, device_t dev, int reg,
106 struct resource_list *rl, int force, int prefetch);
107 static int pci_probe(device_t dev);
108 static void pci_load_vendor_data(void);
109 static int pci_describe_parse_line(char **ptr, int *vendor,
110 int *device, char **desc);
111 static char *pci_describe_device(device_t dev);
112 static int pci_modevent(module_t mod, int what, void *arg);
113 static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
115 static void pci_read_cap(device_t pcib, pcicfgregs *cfg);
116 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg,
117 int reg, uint32_t *data);
119 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg,
120 int reg, uint32_t data);
122 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg);
123 static void pci_mask_msix(device_t dev, u_int index);
124 static void pci_unmask_msix(device_t dev, u_int index);
125 static int pci_msi_blacklisted(void);
126 static int pci_msix_blacklisted(void);
127 static void pci_resume_msi(device_t dev);
128 static void pci_resume_msix(device_t dev);
129 static int pci_remap_intr_method(device_t bus, device_t dev,
131 static void pci_hint_device_unit(device_t acdev, device_t child,
132 const char *name, int *unitp);
133 static int pci_reset_post(device_t dev, device_t child);
134 static int pci_reset_prepare(device_t dev, device_t child);
135 static int pci_reset_child(device_t dev, device_t child,
138 static int pci_get_id_method(device_t dev, device_t child,
139 enum pci_id_type type, uintptr_t *rid);
141 static struct pci_devinfo * pci_fill_devinfo(device_t pcib, device_t bus, int d,
142 int b, int s, int f, uint16_t vid, uint16_t did);
144 static device_method_t pci_methods[] = {
145 /* Device interface */
146 DEVMETHOD(device_probe, pci_probe),
147 DEVMETHOD(device_attach, pci_attach),
148 DEVMETHOD(device_detach, pci_detach),
149 DEVMETHOD(device_shutdown, bus_generic_shutdown),
150 DEVMETHOD(device_suspend, bus_generic_suspend),
151 DEVMETHOD(device_resume, pci_resume),
154 DEVMETHOD(bus_print_child, pci_print_child),
155 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
156 DEVMETHOD(bus_read_ivar, pci_read_ivar),
157 DEVMETHOD(bus_write_ivar, pci_write_ivar),
158 DEVMETHOD(bus_driver_added, pci_driver_added),
159 DEVMETHOD(bus_setup_intr, pci_setup_intr),
160 DEVMETHOD(bus_teardown_intr, pci_teardown_intr),
161 DEVMETHOD(bus_reset_prepare, pci_reset_prepare),
162 DEVMETHOD(bus_reset_post, pci_reset_post),
163 DEVMETHOD(bus_reset_child, pci_reset_child),
165 DEVMETHOD(bus_get_dma_tag, pci_get_dma_tag),
166 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
167 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
168 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
169 DEVMETHOD(bus_delete_resource, pci_delete_resource),
170 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
171 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
172 DEVMETHOD(bus_release_resource, pci_release_resource),
173 DEVMETHOD(bus_activate_resource, pci_activate_resource),
174 DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource),
175 DEVMETHOD(bus_child_deleted, pci_child_deleted),
176 DEVMETHOD(bus_child_detached, pci_child_detached),
177 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
178 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
179 DEVMETHOD(bus_hint_device_unit, pci_hint_device_unit),
180 DEVMETHOD(bus_remap_intr, pci_remap_intr_method),
181 DEVMETHOD(bus_suspend_child, pci_suspend_child),
182 DEVMETHOD(bus_resume_child, pci_resume_child),
183 DEVMETHOD(bus_rescan, pci_rescan_method),
186 DEVMETHOD(pci_read_config, pci_read_config_method),
187 DEVMETHOD(pci_write_config, pci_write_config_method),
188 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
189 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
190 DEVMETHOD(pci_enable_io, pci_enable_io_method),
191 DEVMETHOD(pci_disable_io, pci_disable_io_method),
192 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method),
193 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method),
194 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
195 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
196 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
197 DEVMETHOD(pci_find_cap, pci_find_cap_method),
198 DEVMETHOD(pci_find_next_cap, pci_find_next_cap_method),
199 DEVMETHOD(pci_find_extcap, pci_find_extcap_method),
200 DEVMETHOD(pci_find_next_extcap, pci_find_next_extcap_method),
201 DEVMETHOD(pci_find_htcap, pci_find_htcap_method),
202 DEVMETHOD(pci_find_next_htcap, pci_find_next_htcap_method),
203 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method),
204 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method),
205 DEVMETHOD(pci_enable_msi, pci_enable_msi_method),
206 DEVMETHOD(pci_enable_msix, pci_enable_msix_method),
207 DEVMETHOD(pci_disable_msi, pci_disable_msi_method),
208 DEVMETHOD(pci_remap_msix, pci_remap_msix_method),
209 DEVMETHOD(pci_release_msi, pci_release_msi_method),
210 DEVMETHOD(pci_msi_count, pci_msi_count_method),
211 DEVMETHOD(pci_msix_count, pci_msix_count_method),
212 DEVMETHOD(pci_msix_pba_bar, pci_msix_pba_bar_method),
213 DEVMETHOD(pci_msix_table_bar, pci_msix_table_bar_method),
214 DEVMETHOD(pci_get_id, pci_get_id_method),
215 DEVMETHOD(pci_alloc_devinfo, pci_alloc_devinfo_method),
216 DEVMETHOD(pci_child_added, pci_child_added_method),
218 DEVMETHOD(pci_iov_attach, pci_iov_attach_method),
219 DEVMETHOD(pci_iov_detach, pci_iov_detach_method),
220 DEVMETHOD(pci_create_iov_child, pci_create_iov_child_method),
226 DEFINE_CLASS_0(pci, pci_driver, pci_methods, sizeof(struct pci_softc));
228 static devclass_t pci_devclass;
229 EARLY_DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, NULL,
231 MODULE_VERSION(pci, 1);
233 static char *pci_vendordata;
234 static size_t pci_vendordata_size;
237 uint32_t devid; /* Vendor/device of the card */
239 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
240 #define PCI_QUIRK_DISABLE_MSI 2 /* Neither MSI nor MSI-X work */
241 #define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI works */
242 #define PCI_QUIRK_UNMAP_REG 4 /* Ignore PCI map register */
243 #define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */
244 #define PCI_QUIRK_MSI_INTX_BUG 6 /* PCIM_CMD_INTxDIS disables MSI */
245 #define PCI_QUIRK_REALLOC_BAR 7 /* Can't allocate memory at the default address */
250 static const struct pci_quirk pci_quirks[] = {
251 /* The Intel 82371AB and 82443MX have a map register at offset 0x90. */
252 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
253 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
254 /* As does the Serverworks OSB4 (the SMBus mapping register) */
255 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
258 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
259 * or the CMIC-SL (AKA ServerWorks GC_LE).
261 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
262 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
265 * MSI doesn't work on earlier Intel chipsets including
266 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
268 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
269 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
270 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
271 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
272 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
273 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
274 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
277 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
280 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 },
283 * Some virtualization environments emulate an older chipset
284 * but support MSI just fine. QEMU uses the Intel 82440.
286 { 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0 },
289 * HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus
290 * controller depending on SoftPciRst register (PM_IO 0x55 [7]).
291 * It prevents us from attaching hpet(4) when the bit is unset.
292 * Note this quirk only affects SB600 revision A13 and earlier.
293 * For SB600 A21 and later, firmware must set the bit to hide it.
294 * For SB700 and later, it is unused and hardcoded to zero.
296 { 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0 },
299 * Atheros AR8161/AR8162/E2200/E2400/E2500 Ethernet controllers have
300 * a bug that MSI interrupt does not assert if PCIM_CMD_INTxDIS bit
301 * of the command register is set.
303 { 0x10911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },
304 { 0xE0911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },
305 { 0xE0A11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },
306 { 0xE0B11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },
307 { 0x10901969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },
310 * Broadcom BCM5714(S)/BCM5715(S)/BCM5780(S) Ethernet MACs don't
311 * issue MSI interrupts with PCIM_CMD_INTxDIS set either.
313 { 0x166814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714 */
314 { 0x166914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714S */
315 { 0x166a14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780 */
316 { 0x166b14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780S */
317 { 0x167814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715 */
318 { 0x167914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715S */
321 * HPE Gen 10 VGA has a memory range that can't be allocated in the
324 { 0x98741002, PCI_QUIRK_REALLOC_BAR, 0, 0 },
328 /* map register information */
329 #define PCI_MAPMEM 0x01 /* memory map */
330 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
331 #define PCI_MAPPORT 0x04 /* port map */
333 struct devlist pci_devq;
334 uint32_t pci_generation;
335 uint32_t pci_numdevs = 0;
336 static int pcie_chipset, pcix_chipset;
339 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
340 "PCI bus tuning parameters");
342 static int pci_enable_io_modes = 1;
343 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RWTUN,
344 &pci_enable_io_modes, 1,
345 "Enable I/O and memory bits in the config register. Some BIOSes do not"
346 " enable these bits correctly. We'd like to do this all the time, but"
347 " there are some peripherals that this causes problems with.");
349 static int pci_do_realloc_bars = 1;
350 SYSCTL_INT(_hw_pci, OID_AUTO, realloc_bars, CTLFLAG_RWTUN,
351 &pci_do_realloc_bars, 0,
352 "Attempt to allocate a new range for any BARs whose original "
353 "firmware-assigned ranges fail to allocate during the initial device scan.");
355 static int pci_do_power_nodriver = 0;
356 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RWTUN,
357 &pci_do_power_nodriver, 0,
358 "Place a function into D3 state when no driver attaches to it. 0 means"
359 " disable. 1 means conservatively place devices into D3 state. 2 means"
360 " aggressively place devices into D3 state. 3 means put absolutely"
361 " everything in D3 state.");
363 int pci_do_power_resume = 1;
364 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RWTUN,
365 &pci_do_power_resume, 1,
366 "Transition from D3 -> D0 on resume.");
368 int pci_do_power_suspend = 1;
369 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_suspend, CTLFLAG_RWTUN,
370 &pci_do_power_suspend, 1,
371 "Transition from D0 -> D3 on suspend.");
373 static int pci_do_msi = 1;
374 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RWTUN, &pci_do_msi, 1,
375 "Enable support for MSI interrupts");
377 static int pci_do_msix = 1;
378 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RWTUN, &pci_do_msix, 1,
379 "Enable support for MSI-X interrupts");
381 static int pci_msix_rewrite_table = 0;
382 SYSCTL_INT(_hw_pci, OID_AUTO, msix_rewrite_table, CTLFLAG_RWTUN,
383 &pci_msix_rewrite_table, 0,
384 "Rewrite entire MSI-X table when updating MSI-X entries");
386 static int pci_honor_msi_blacklist = 1;
387 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RDTUN,
388 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI/MSI-X");
390 #if defined(__i386__) || defined(__amd64__)
391 static int pci_usb_takeover = 1;
393 static int pci_usb_takeover = 0;
395 SYSCTL_INT(_hw_pci, OID_AUTO, usb_early_takeover, CTLFLAG_RDTUN,
396 &pci_usb_takeover, 1,
397 "Enable early takeover of USB controllers. Disable this if you depend on"
398 " BIOS emulation of USB devices, that is you use USB devices (like"
399 " keyboard or mouse) but do not load USB drivers");
401 static int pci_clear_bars;
402 SYSCTL_INT(_hw_pci, OID_AUTO, clear_bars, CTLFLAG_RDTUN, &pci_clear_bars, 0,
403 "Ignore firmware-assigned resources for BARs.");
405 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
406 static int pci_clear_buses;
407 SYSCTL_INT(_hw_pci, OID_AUTO, clear_buses, CTLFLAG_RDTUN, &pci_clear_buses, 0,
408 "Ignore firmware-assigned bus numbers.");
411 static int pci_enable_ari = 1;
412 SYSCTL_INT(_hw_pci, OID_AUTO, enable_ari, CTLFLAG_RDTUN, &pci_enable_ari,
413 0, "Enable support for PCIe Alternative RID Interpretation");
415 int pci_enable_aspm = 1;
416 SYSCTL_INT(_hw_pci, OID_AUTO, enable_aspm, CTLFLAG_RDTUN, &pci_enable_aspm,
417 0, "Enable support for PCIe Active State Power Management");
419 static int pci_clear_aer_on_attach = 0;
420 SYSCTL_INT(_hw_pci, OID_AUTO, clear_aer_on_attach, CTLFLAG_RWTUN,
421 &pci_clear_aer_on_attach, 0,
422 "Clear port and device AER state on driver attach");
425 pci_has_quirk(uint32_t devid, int quirk)
427 const struct pci_quirk *q;
429 for (q = &pci_quirks[0]; q->devid; q++) {
430 if (q->devid == devid && q->type == quirk)
436 /* Find a device_t by bus/slot/function in domain 0 */
439 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
442 return (pci_find_dbsf(0, bus, slot, func));
445 /* Find a device_t by domain/bus/slot/function */
448 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func)
450 struct pci_devinfo *dinfo = NULL;
452 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
453 if ((dinfo->cfg.domain == domain) &&
454 (dinfo->cfg.bus == bus) &&
455 (dinfo->cfg.slot == slot) &&
456 (dinfo->cfg.func == func)) {
461 return (dinfo != NULL ? dinfo->cfg.dev : NULL);
464 /* Find a device_t by vendor/device ID */
467 pci_find_device(uint16_t vendor, uint16_t device)
469 struct pci_devinfo *dinfo;
471 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
472 if ((dinfo->cfg.vendor == vendor) &&
473 (dinfo->cfg.device == device)) {
474 return (dinfo->cfg.dev);
482 pci_find_class(uint8_t class, uint8_t subclass)
484 struct pci_devinfo *dinfo;
486 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
487 if (dinfo->cfg.baseclass == class &&
488 dinfo->cfg.subclass == subclass) {
489 return (dinfo->cfg.dev);
497 pci_find_class_from(uint8_t class, uint8_t subclass, device_t from)
499 struct pci_devinfo *dinfo;
502 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
503 if (from != NULL && found == false) {
504 if (from != dinfo->cfg.dev)
509 if (dinfo->cfg.baseclass == class &&
510 dinfo->cfg.subclass == subclass) {
511 return (dinfo->cfg.dev);
519 pci_printf(pcicfgregs *cfg, const char *fmt, ...)
524 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot,
527 retval += vprintf(fmt, ap);
532 /* return base address of memory or port map */
535 pci_mapbase(uint64_t mapreg)
538 if (PCI_BAR_MEM(mapreg))
539 return (mapreg & PCIM_BAR_MEM_BASE);
541 return (mapreg & PCIM_BAR_IO_BASE);
544 /* return map type of memory or port map */
547 pci_maptype(uint64_t mapreg)
550 if (PCI_BAR_IO(mapreg))
552 if (mapreg & PCIM_BAR_MEM_PREFETCH)
553 return ("Prefetchable Memory");
557 /* return log2 of map size decoded for memory or port map */
560 pci_mapsize(uint64_t testval)
564 testval = pci_mapbase(testval);
567 while ((testval & 1) == 0)
576 /* return base address of device ROM */
579 pci_rombase(uint64_t mapreg)
582 return (mapreg & PCIM_BIOS_ADDR_MASK);
585 /* return log2 of map size decided for device ROM */
588 pci_romsize(uint64_t testval)
592 testval = pci_rombase(testval);
595 while ((testval & 1) == 0)
604 /* return log2 of address range supported by map register */
607 pci_maprange(uint64_t mapreg)
611 if (PCI_BAR_IO(mapreg))
614 switch (mapreg & PCIM_BAR_MEM_TYPE) {
615 case PCIM_BAR_MEM_32:
618 case PCIM_BAR_MEM_1MB:
621 case PCIM_BAR_MEM_64:
628 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
631 pci_fixancient(pcicfgregs *cfg)
633 if ((cfg->hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL)
636 /* PCI to PCI bridges use header type 1 */
637 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
638 cfg->hdrtype = PCIM_HDRTYPE_BRIDGE;
641 /* extract header type specific config data */
644 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
646 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
647 switch (cfg->hdrtype & PCIM_HDRTYPE) {
648 case PCIM_HDRTYPE_NORMAL:
649 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
650 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
651 cfg->mingnt = REG(PCIR_MINGNT, 1);
652 cfg->maxlat = REG(PCIR_MAXLAT, 1);
653 cfg->nummaps = PCI_MAXMAPS_0;
655 case PCIM_HDRTYPE_BRIDGE:
656 cfg->bridge.br_seclat = REG(PCIR_SECLAT_1, 1);
657 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_1, 1);
658 cfg->bridge.br_secbus = REG(PCIR_SECBUS_1, 1);
659 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_1, 1);
660 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_1, 2);
661 cfg->nummaps = PCI_MAXMAPS_1;
663 case PCIM_HDRTYPE_CARDBUS:
664 cfg->bridge.br_seclat = REG(PCIR_SECLAT_2, 1);
665 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_2, 1);
666 cfg->bridge.br_secbus = REG(PCIR_SECBUS_2, 1);
667 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_2, 1);
668 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_2, 2);
669 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
670 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
671 cfg->nummaps = PCI_MAXMAPS_2;
677 /* read configuration header into pcicfgregs structure */
679 pci_read_device(device_t pcib, device_t bus, int d, int b, int s, int f)
681 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
684 vid = REG(PCIR_VENDOR, 2);
685 did = REG(PCIR_DEVICE, 2);
687 return (pci_fill_devinfo(pcib, bus, d, b, s, f, vid, did));
693 pci_alloc_devinfo_method(device_t dev)
696 return (malloc(sizeof(struct pci_devinfo), M_DEVBUF,
700 static struct pci_devinfo *
701 pci_fill_devinfo(device_t pcib, device_t bus, int d, int b, int s, int f,
702 uint16_t vid, uint16_t did)
704 struct pci_devinfo *devlist_entry;
707 devlist_entry = PCI_ALLOC_DEVINFO(bus);
709 cfg = &devlist_entry->cfg;
717 cfg->cmdreg = REG(PCIR_COMMAND, 2);
718 cfg->statreg = REG(PCIR_STATUS, 2);
719 cfg->baseclass = REG(PCIR_CLASS, 1);
720 cfg->subclass = REG(PCIR_SUBCLASS, 1);
721 cfg->progif = REG(PCIR_PROGIF, 1);
722 cfg->revid = REG(PCIR_REVID, 1);
723 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
724 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
725 cfg->lattimer = REG(PCIR_LATTIMER, 1);
726 cfg->intpin = REG(PCIR_INTPIN, 1);
727 cfg->intline = REG(PCIR_INTLINE, 1);
729 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
730 cfg->hdrtype &= ~PCIM_MFDEV;
731 STAILQ_INIT(&cfg->maps);
736 pci_hdrtypedata(pcib, b, s, f, cfg);
738 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
739 pci_read_cap(pcib, cfg);
741 STAILQ_INSERT_TAIL(&pci_devq, devlist_entry, pci_links);
743 devlist_entry->conf.pc_sel.pc_domain = cfg->domain;
744 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
745 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
746 devlist_entry->conf.pc_sel.pc_func = cfg->func;
747 devlist_entry->conf.pc_hdr = cfg->hdrtype;
749 devlist_entry->conf.pc_subvendor = cfg->subvendor;
750 devlist_entry->conf.pc_subdevice = cfg->subdevice;
751 devlist_entry->conf.pc_vendor = cfg->vendor;
752 devlist_entry->conf.pc_device = cfg->device;
754 devlist_entry->conf.pc_class = cfg->baseclass;
755 devlist_entry->conf.pc_subclass = cfg->subclass;
756 devlist_entry->conf.pc_progif = cfg->progif;
757 devlist_entry->conf.pc_revid = cfg->revid;
762 return (devlist_entry);
767 pci_ea_fill_info(device_t pcib, pcicfgregs *cfg)
769 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, \
770 cfg->ea.ea_location + (n), w)
777 uint64_t base, max_offset;
778 struct pci_ea_entry *eae;
780 if (cfg->ea.ea_location == 0)
783 STAILQ_INIT(&cfg->ea.ea_entries);
785 /* Determine the number of entries */
786 num_ent = REG(PCIR_EA_NUM_ENT, 2);
787 num_ent &= PCIM_EA_NUM_ENT_MASK;
789 /* Find the first entry to care of */
790 ptr = PCIR_EA_FIRST_ENT;
792 /* Skip DWORD 2 for type 1 functions */
793 if ((cfg->hdrtype & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE)
796 for (a = 0; a < num_ent; a++) {
797 eae = malloc(sizeof(*eae), M_DEVBUF, M_WAITOK | M_ZERO);
798 eae->eae_cfg_offset = cfg->ea.ea_location + ptr;
800 /* Read a number of dwords in the entry */
803 ent_size = (val & PCIM_EA_ES);
805 for (b = 0; b < ent_size; b++) {
810 eae->eae_flags = val;
811 eae->eae_bei = (PCIM_EA_BEI & val) >> PCIM_EA_BEI_OFFSET;
813 base = dw[0] & PCIM_EA_FIELD_MASK;
814 max_offset = dw[1] | ~PCIM_EA_FIELD_MASK;
816 if (((dw[0] & PCIM_EA_IS_64) != 0) && (b < ent_size)) {
817 base |= (uint64_t)dw[b] << 32UL;
820 if (((dw[1] & PCIM_EA_IS_64) != 0)
822 max_offset |= (uint64_t)dw[b] << 32UL;
826 eae->eae_base = base;
827 eae->eae_max_offset = max_offset;
829 STAILQ_INSERT_TAIL(&cfg->ea.ea_entries, eae, eae_link);
832 printf("PCI(EA) dev %04x:%04x, bei %d, flags #%x, base #%jx, max_offset #%jx\n",
833 cfg->vendor, cfg->device, eae->eae_bei, eae->eae_flags,
834 (uintmax_t)eae->eae_base, (uintmax_t)eae->eae_max_offset);
841 pci_read_cap(device_t pcib, pcicfgregs *cfg)
843 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
844 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
845 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
849 int ptr, nextptr, ptrptr;
851 switch (cfg->hdrtype & PCIM_HDRTYPE) {
852 case PCIM_HDRTYPE_NORMAL:
853 case PCIM_HDRTYPE_BRIDGE:
854 ptrptr = PCIR_CAP_PTR;
856 case PCIM_HDRTYPE_CARDBUS:
857 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */
860 return; /* no extended capabilities support */
862 nextptr = REG(ptrptr, 1); /* sanity check? */
865 * Read capability entries.
867 while (nextptr != 0) {
870 printf("illegal PCI extended capability offset %d\n",
874 /* Find the next entry */
876 nextptr = REG(ptr + PCICAP_NEXTPTR, 1);
878 /* Process this entry */
879 switch (REG(ptr + PCICAP_ID, 1)) {
880 case PCIY_PMG: /* PCI power management */
881 if (cfg->pp.pp_cap == 0) {
882 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
883 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS;
884 cfg->pp.pp_bse = ptr + PCIR_POWER_BSE;
885 if ((nextptr - ptr) > PCIR_POWER_DATA)
886 cfg->pp.pp_data = ptr + PCIR_POWER_DATA;
889 case PCIY_HT: /* HyperTransport */
890 /* Determine HT-specific capability type. */
891 val = REG(ptr + PCIR_HT_COMMAND, 2);
893 if ((val & 0xe000) == PCIM_HTCAP_SLAVE)
894 cfg->ht.ht_slave = ptr;
896 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
897 switch (val & PCIM_HTCMD_CAP_MASK) {
898 case PCIM_HTCAP_MSI_MAPPING:
899 if (!(val & PCIM_HTCMD_MSI_FIXED)) {
900 /* Sanity check the mapping window. */
901 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI,
904 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO,
906 if (addr != MSI_INTEL_ADDR_BASE)
908 "HT device at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n",
909 cfg->domain, cfg->bus,
910 cfg->slot, cfg->func,
913 addr = MSI_INTEL_ADDR_BASE;
915 cfg->ht.ht_msimap = ptr;
916 cfg->ht.ht_msictrl = val;
917 cfg->ht.ht_msiaddr = addr;
922 case PCIY_MSI: /* PCI MSI */
923 cfg->msi.msi_location = ptr;
924 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
925 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl &
926 PCIM_MSICTRL_MMC_MASK)>>1);
928 case PCIY_MSIX: /* PCI MSI-X */
929 cfg->msix.msix_location = ptr;
930 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);
931 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl &
932 PCIM_MSIXCTRL_TABLE_SIZE) + 1;
933 val = REG(ptr + PCIR_MSIX_TABLE, 4);
934 cfg->msix.msix_table_bar = PCIR_BAR(val &
936 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK;
937 val = REG(ptr + PCIR_MSIX_PBA, 4);
938 cfg->msix.msix_pba_bar = PCIR_BAR(val &
940 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK;
942 case PCIY_VPD: /* PCI Vital Product Data */
943 cfg->vpd.vpd_reg = ptr;
946 /* Should always be true. */
947 if ((cfg->hdrtype & PCIM_HDRTYPE) ==
948 PCIM_HDRTYPE_BRIDGE) {
949 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4);
950 cfg->subvendor = val & 0xffff;
951 cfg->subdevice = val >> 16;
954 case PCIY_PCIX: /* PCI-X */
956 * Assume we have a PCI-X chipset if we have
957 * at least one PCI-PCI bridge with a PCI-X
958 * capability. Note that some systems with
959 * PCI-express or HT chipsets might match on
960 * this check as well.
962 if ((cfg->hdrtype & PCIM_HDRTYPE) ==
965 cfg->pcix.pcix_location = ptr;
967 case PCIY_EXPRESS: /* PCI-express */
969 * Assume we have a PCI-express chipset if we have
970 * at least one PCI-express device.
973 cfg->pcie.pcie_location = ptr;
974 val = REG(ptr + PCIER_FLAGS, 2);
975 cfg->pcie.pcie_type = val & PCIEM_FLAGS_TYPE;
977 case PCIY_EA: /* Enhanced Allocation */
978 cfg->ea.ea_location = ptr;
979 pci_ea_fill_info(pcib, cfg);
986 #if defined(__powerpc__)
988 * Enable the MSI mapping window for all HyperTransport
989 * slaves. PCI-PCI bridges have their windows enabled via
992 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 &&
993 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) {
995 "Enabling MSI window for HyperTransport slave at pci%d:%d:%d:%d\n",
996 cfg->domain, cfg->bus, cfg->slot, cfg->func);
997 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
998 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl,
1002 /* REG and WREG use carry through to next functions */
1006 * PCI Vital Product Data
1009 #define PCI_VPD_TIMEOUT 1000000
1012 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data)
1014 int count = PCI_VPD_TIMEOUT;
1016 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
1018 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2);
1020 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {
1023 DELAY(1); /* limit looping */
1025 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));
1032 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data)
1034 int count = PCI_VPD_TIMEOUT;
1036 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
1038 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
1039 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
1040 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
1043 DELAY(1); /* limit looping */
1050 #undef PCI_VPD_TIMEOUT
1052 struct vpd_readstate {
1062 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data)
1067 if (vrs->bytesinval == 0) {
1068 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®))
1070 vrs->val = le32toh(reg);
1072 byte = vrs->val & 0xff;
1073 vrs->bytesinval = 3;
1075 vrs->val = vrs->val >> 8;
1076 byte = vrs->val & 0xff;
1086 pci_read_vpd(device_t pcib, pcicfgregs *cfg)
1088 struct vpd_readstate vrs;
1093 int alloc, off; /* alloc/off for RO/W arrays */
1099 /* init vpd reader */
1107 name = remain = i = 0; /* shut up stupid gcc */
1108 alloc = off = 0; /* shut up stupid gcc */
1109 dflen = 0; /* shut up stupid gcc */
1111 while (state >= 0) {
1112 if (vpd_nextbyte(&vrs, &byte)) {
1117 printf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \
1118 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val,
1119 vrs.off, vrs.bytesinval, byte, state, remain, name, i);
1122 case 0: /* item name */
1124 if (vpd_nextbyte(&vrs, &byte2)) {
1129 if (vpd_nextbyte(&vrs, &byte2)) {
1133 remain |= byte2 << 8;
1136 remain = byte & 0x7;
1137 name = (byte >> 3) & 0xf;
1139 if (vrs.off + remain - vrs.bytesinval > 0x8000) {
1141 "VPD data overflow, remain %#x\n", remain);
1146 case 0x2: /* String */
1147 cfg->vpd.vpd_ident = malloc(remain + 1,
1148 M_DEVBUF, M_WAITOK);
1155 case 0x10: /* VPD-R */
1158 cfg->vpd.vpd_ros = malloc(alloc *
1159 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF,
1163 case 0x11: /* VPD-W */
1166 cfg->vpd.vpd_w = malloc(alloc *
1167 sizeof(*cfg->vpd.vpd_w), M_DEVBUF,
1171 default: /* Invalid data, abort */
1177 case 1: /* Identifier String */
1178 cfg->vpd.vpd_ident[i++] = byte;
1181 cfg->vpd.vpd_ident[i] = '\0';
1186 case 2: /* VPD-R Keyword Header */
1188 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros,
1189 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros),
1190 M_DEVBUF, M_WAITOK | M_ZERO);
1192 cfg->vpd.vpd_ros[off].keyword[0] = byte;
1193 if (vpd_nextbyte(&vrs, &byte2)) {
1197 cfg->vpd.vpd_ros[off].keyword[1] = byte2;
1198 if (vpd_nextbyte(&vrs, &byte2)) {
1202 cfg->vpd.vpd_ros[off].len = dflen = byte2;
1204 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV",
1207 * if this happens, we can't trust the rest
1210 pci_printf(cfg, "bad keyword length: %d\n",
1215 } else if (dflen == 0) {
1216 cfg->vpd.vpd_ros[off].value = malloc(1 *
1217 sizeof(*cfg->vpd.vpd_ros[off].value),
1218 M_DEVBUF, M_WAITOK);
1219 cfg->vpd.vpd_ros[off].value[0] = '\x00';
1221 cfg->vpd.vpd_ros[off].value = malloc(
1223 sizeof(*cfg->vpd.vpd_ros[off].value),
1224 M_DEVBUF, M_WAITOK);
1227 /* keep in sync w/ state 3's transistions */
1228 if (dflen == 0 && remain == 0)
1230 else if (dflen == 0)
1236 case 3: /* VPD-R Keyword Value */
1237 cfg->vpd.vpd_ros[off].value[i++] = byte;
1238 if (strncmp(cfg->vpd.vpd_ros[off].keyword,
1239 "RV", 2) == 0 && cksumvalid == -1) {
1245 "bad VPD cksum, remain %hhu\n",
1254 /* keep in sync w/ state 2's transistions */
1256 cfg->vpd.vpd_ros[off++].value[i++] = '\0';
1257 if (dflen == 0 && remain == 0) {
1258 cfg->vpd.vpd_rocnt = off;
1259 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros,
1260 off * sizeof(*cfg->vpd.vpd_ros),
1261 M_DEVBUF, M_WAITOK | M_ZERO);
1263 } else if (dflen == 0)
1273 case 5: /* VPD-W Keyword Header */
1275 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w,
1276 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w),
1277 M_DEVBUF, M_WAITOK | M_ZERO);
1279 cfg->vpd.vpd_w[off].keyword[0] = byte;
1280 if (vpd_nextbyte(&vrs, &byte2)) {
1284 cfg->vpd.vpd_w[off].keyword[1] = byte2;
1285 if (vpd_nextbyte(&vrs, &byte2)) {
1289 cfg->vpd.vpd_w[off].len = dflen = byte2;
1290 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval;
1291 cfg->vpd.vpd_w[off].value = malloc((dflen + 1) *
1292 sizeof(*cfg->vpd.vpd_w[off].value),
1293 M_DEVBUF, M_WAITOK);
1296 /* keep in sync w/ state 6's transistions */
1297 if (dflen == 0 && remain == 0)
1299 else if (dflen == 0)
1305 case 6: /* VPD-W Keyword Value */
1306 cfg->vpd.vpd_w[off].value[i++] = byte;
1309 /* keep in sync w/ state 5's transistions */
1311 cfg->vpd.vpd_w[off++].value[i++] = '\0';
1312 if (dflen == 0 && remain == 0) {
1313 cfg->vpd.vpd_wcnt = off;
1314 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w,
1315 off * sizeof(*cfg->vpd.vpd_w),
1316 M_DEVBUF, M_WAITOK | M_ZERO);
1318 } else if (dflen == 0)
1323 pci_printf(cfg, "invalid state: %d\n", state);
1329 if (cksumvalid == 0 || state < -1) {
1330 /* read-only data bad, clean up */
1331 if (cfg->vpd.vpd_ros != NULL) {
1332 for (off = 0; cfg->vpd.vpd_ros[off].value; off++)
1333 free(cfg->vpd.vpd_ros[off].value, M_DEVBUF);
1334 free(cfg->vpd.vpd_ros, M_DEVBUF);
1335 cfg->vpd.vpd_ros = NULL;
1339 /* I/O error, clean up */
1340 pci_printf(cfg, "failed to read VPD data.\n");
1341 if (cfg->vpd.vpd_ident != NULL) {
1342 free(cfg->vpd.vpd_ident, M_DEVBUF);
1343 cfg->vpd.vpd_ident = NULL;
1345 if (cfg->vpd.vpd_w != NULL) {
1346 for (off = 0; cfg->vpd.vpd_w[off].value; off++)
1347 free(cfg->vpd.vpd_w[off].value, M_DEVBUF);
1348 free(cfg->vpd.vpd_w, M_DEVBUF);
1349 cfg->vpd.vpd_w = NULL;
1352 cfg->vpd.vpd_cached = 1;
1358 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr)
1360 struct pci_devinfo *dinfo = device_get_ivars(child);
1361 pcicfgregs *cfg = &dinfo->cfg;
1363 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1364 pci_read_vpd(device_get_parent(dev), cfg);
1366 *identptr = cfg->vpd.vpd_ident;
1368 if (*identptr == NULL)
1375 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw,
1378 struct pci_devinfo *dinfo = device_get_ivars(child);
1379 pcicfgregs *cfg = &dinfo->cfg;
1382 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1383 pci_read_vpd(device_get_parent(dev), cfg);
1385 for (i = 0; i < cfg->vpd.vpd_rocnt; i++)
1386 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword,
1387 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) {
1388 *vptr = cfg->vpd.vpd_ros[i].value;
1397 pci_fetch_vpd_list(device_t dev)
1399 struct pci_devinfo *dinfo = device_get_ivars(dev);
1400 pcicfgregs *cfg = &dinfo->cfg;
1402 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1403 pci_read_vpd(device_get_parent(device_get_parent(dev)), cfg);
1408 * Find the requested HyperTransport capability and return the offset
1409 * in configuration space via the pointer provided. The function
1410 * returns 0 on success and an error code otherwise.
1413 pci_find_htcap_method(device_t dev, device_t child, int capability, int *capreg)
1418 error = pci_find_cap(child, PCIY_HT, &ptr);
1423 * Traverse the capabilities list checking each HT capability
1424 * to see if it matches the requested HT capability.
1427 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2);
1428 if (capability == PCIM_HTCAP_SLAVE ||
1429 capability == PCIM_HTCAP_HOST)
1432 val &= PCIM_HTCMD_CAP_MASK;
1433 if (val == capability) {
1439 /* Skip to the next HT capability. */
1440 if (pci_find_next_cap(child, PCIY_HT, ptr, &ptr) != 0)
1448 * Find the next requested HyperTransport capability after start and return
1449 * the offset in configuration space via the pointer provided. The function
1450 * returns 0 on success and an error code otherwise.
1453 pci_find_next_htcap_method(device_t dev, device_t child, int capability,
1454 int start, int *capreg)
1459 KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == PCIY_HT,
1460 ("start capability is not HyperTransport capability"));
1464 * Traverse the capabilities list checking each HT capability
1465 * to see if it matches the requested HT capability.
1468 /* Skip to the next HT capability. */
1469 if (pci_find_next_cap(child, PCIY_HT, ptr, &ptr) != 0)
1472 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2);
1473 if (capability == PCIM_HTCAP_SLAVE ||
1474 capability == PCIM_HTCAP_HOST)
1477 val &= PCIM_HTCMD_CAP_MASK;
1478 if (val == capability) {
1489 * Find the requested capability and return the offset in
1490 * configuration space via the pointer provided. The function returns
1491 * 0 on success and an error code otherwise.
1494 pci_find_cap_method(device_t dev, device_t child, int capability,
1497 struct pci_devinfo *dinfo = device_get_ivars(child);
1498 pcicfgregs *cfg = &dinfo->cfg;
1503 * Check the CAP_LIST bit of the PCI status register first.
1505 status = pci_read_config(child, PCIR_STATUS, 2);
1506 if (!(status & PCIM_STATUS_CAPPRESENT))
1510 * Determine the start pointer of the capabilities list.
1512 switch (cfg->hdrtype & PCIM_HDRTYPE) {
1513 case PCIM_HDRTYPE_NORMAL:
1514 case PCIM_HDRTYPE_BRIDGE:
1517 case PCIM_HDRTYPE_CARDBUS:
1518 ptr = PCIR_CAP_PTR_2;
1522 return (ENXIO); /* no extended capabilities support */
1524 ptr = pci_read_config(child, ptr, 1);
1527 * Traverse the capabilities list.
1530 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
1535 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1542 * Find the next requested capability after start and return the offset in
1543 * configuration space via the pointer provided. The function returns
1544 * 0 on success and an error code otherwise.
1547 pci_find_next_cap_method(device_t dev, device_t child, int capability,
1548 int start, int *capreg)
1552 KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == capability,
1553 ("start capability is not expected capability"));
1555 ptr = pci_read_config(child, start + PCICAP_NEXTPTR, 1);
1557 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
1562 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1569 * Find the requested extended capability and return the offset in
1570 * configuration space via the pointer provided. The function returns
1571 * 0 on success and an error code otherwise.
1574 pci_find_extcap_method(device_t dev, device_t child, int capability,
1577 struct pci_devinfo *dinfo = device_get_ivars(child);
1578 pcicfgregs *cfg = &dinfo->cfg;
1582 /* Only supported for PCI-express devices. */
1583 if (cfg->pcie.pcie_location == 0)
1587 ecap = pci_read_config(child, ptr, 4);
1588 if (ecap == 0xffffffff || ecap == 0)
1591 if (PCI_EXTCAP_ID(ecap) == capability) {
1596 ptr = PCI_EXTCAP_NEXTPTR(ecap);
1599 ecap = pci_read_config(child, ptr, 4);
1606 * Find the next requested extended capability after start and return the
1607 * offset in configuration space via the pointer provided. The function
1608 * returns 0 on success and an error code otherwise.
1611 pci_find_next_extcap_method(device_t dev, device_t child, int capability,
1612 int start, int *capreg)
1614 struct pci_devinfo *dinfo = device_get_ivars(child);
1615 pcicfgregs *cfg = &dinfo->cfg;
1619 /* Only supported for PCI-express devices. */
1620 if (cfg->pcie.pcie_location == 0)
1623 ecap = pci_read_config(child, start, 4);
1624 KASSERT(PCI_EXTCAP_ID(ecap) == capability,
1625 ("start extended capability is not expected capability"));
1626 ptr = PCI_EXTCAP_NEXTPTR(ecap);
1628 ecap = pci_read_config(child, ptr, 4);
1629 if (PCI_EXTCAP_ID(ecap) == capability) {
1634 ptr = PCI_EXTCAP_NEXTPTR(ecap);
1641 * Support for MSI-X message interrupts.
1644 pci_write_msix_entry(device_t dev, u_int index, uint64_t address, uint32_t data)
1646 struct pci_devinfo *dinfo = device_get_ivars(dev);
1647 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1650 KASSERT(msix->msix_table_len > index, ("bogus index"));
1651 offset = msix->msix_table_offset + index * 16;
1652 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
1653 bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
1654 bus_write_4(msix->msix_table_res, offset + 8, data);
1658 pci_enable_msix_method(device_t dev, device_t child, u_int index,
1659 uint64_t address, uint32_t data)
1662 if (pci_msix_rewrite_table) {
1663 struct pci_devinfo *dinfo = device_get_ivars(child);
1664 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1667 * Some VM hosts require MSIX to be disabled in the
1668 * control register before updating the MSIX table
1669 * entries are allowed. It is not enough to only
1670 * disable MSIX while updating a single entry. MSIX
1671 * must be disabled while updating all entries in the
1674 pci_write_config(child,
1675 msix->msix_location + PCIR_MSIX_CTRL,
1676 msix->msix_ctrl & ~PCIM_MSIXCTRL_MSIX_ENABLE, 2);
1677 pci_resume_msix(child);
1679 pci_write_msix_entry(child, index, address, data);
1681 /* Enable MSI -> HT mapping. */
1682 pci_ht_map_msi(child, address);
1686 pci_mask_msix(device_t dev, u_int index)
1688 struct pci_devinfo *dinfo = device_get_ivars(dev);
1689 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1690 uint32_t offset, val;
1692 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1693 offset = msix->msix_table_offset + index * 16 + 12;
1694 val = bus_read_4(msix->msix_table_res, offset);
1695 val |= PCIM_MSIX_VCTRL_MASK;
1698 * Some devices (e.g. Samsung PM961) do not support reads of this
1699 * register, so always write the new value.
1701 bus_write_4(msix->msix_table_res, offset, val);
1705 pci_unmask_msix(device_t dev, u_int index)
1707 struct pci_devinfo *dinfo = device_get_ivars(dev);
1708 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1709 uint32_t offset, val;
1711 KASSERT(msix->msix_table_len > index, ("bogus index"));
1712 offset = msix->msix_table_offset + index * 16 + 12;
1713 val = bus_read_4(msix->msix_table_res, offset);
1714 val &= ~PCIM_MSIX_VCTRL_MASK;
1717 * Some devices (e.g. Samsung PM961) do not support reads of this
1718 * register, so always write the new value.
1720 bus_write_4(msix->msix_table_res, offset, val);
1724 pci_pending_msix(device_t dev, u_int index)
1726 struct pci_devinfo *dinfo = device_get_ivars(dev);
1727 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1728 uint32_t offset, bit;
1730 KASSERT(msix->msix_table_len > index, ("bogus index"));
1731 offset = msix->msix_pba_offset + (index / 32) * 4;
1732 bit = 1 << index % 32;
1733 return (bus_read_4(msix->msix_pba_res, offset) & bit);
1737 * Restore MSI-X registers and table during resume. If MSI-X is
1738 * enabled then walk the virtual table to restore the actual MSI-X
1742 pci_resume_msix(device_t dev)
1744 struct pci_devinfo *dinfo = device_get_ivars(dev);
1745 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1746 struct msix_table_entry *mte;
1747 struct msix_vector *mv;
1750 if (msix->msix_alloc > 0) {
1751 /* First, mask all vectors. */
1752 for (i = 0; i < msix->msix_msgnum; i++)
1753 pci_mask_msix(dev, i);
1755 /* Second, program any messages with at least one handler. */
1756 for (i = 0; i < msix->msix_table_len; i++) {
1757 mte = &msix->msix_table[i];
1758 if (mte->mte_vector == 0 || mte->mte_handlers == 0)
1760 mv = &msix->msix_vectors[mte->mte_vector - 1];
1761 pci_write_msix_entry(dev, i, mv->mv_address,
1763 pci_unmask_msix(dev, i);
1766 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1767 msix->msix_ctrl, 2);
1771 * Attempt to allocate *count MSI-X messages. The actual number allocated is
1772 * returned in *count. After this function returns, each message will be
1773 * available to the driver as SYS_RES_IRQ resources starting at rid 1.
1776 pci_alloc_msix_method(device_t dev, device_t child, int *count)
1778 struct pci_devinfo *dinfo = device_get_ivars(child);
1779 pcicfgregs *cfg = &dinfo->cfg;
1780 struct resource_list_entry *rle;
1781 int actual, error, i, irq, max;
1783 /* Don't let count == 0 get us into trouble. */
1787 /* If rid 0 is allocated, then fail. */
1788 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1789 if (rle != NULL && rle->res != NULL)
1792 /* Already have allocated messages? */
1793 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1796 /* If MSI-X is blacklisted for this system, fail. */
1797 if (pci_msix_blacklisted())
1800 /* MSI-X capability present? */
1801 if (cfg->msix.msix_location == 0 || !pci_do_msix)
1804 /* Make sure the appropriate BARs are mapped. */
1805 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1806 cfg->msix.msix_table_bar);
1807 if (rle == NULL || rle->res == NULL ||
1808 !(rman_get_flags(rle->res) & RF_ACTIVE))
1810 cfg->msix.msix_table_res = rle->res;
1811 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) {
1812 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1813 cfg->msix.msix_pba_bar);
1814 if (rle == NULL || rle->res == NULL ||
1815 !(rman_get_flags(rle->res) & RF_ACTIVE))
1818 cfg->msix.msix_pba_res = rle->res;
1821 device_printf(child,
1822 "attempting to allocate %d MSI-X vectors (%d supported)\n",
1823 *count, cfg->msix.msix_msgnum);
1824 max = min(*count, cfg->msix.msix_msgnum);
1825 for (i = 0; i < max; i++) {
1826 /* Allocate a message. */
1827 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq);
1833 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1839 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1);
1841 device_printf(child, "using IRQ %ju for MSI-X\n",
1847 * Be fancy and try to print contiguous runs of
1848 * IRQ values as ranges. 'irq' is the previous IRQ.
1849 * 'run' is true if we are in a range.
1851 device_printf(child, "using IRQs %ju", rle->start);
1854 for (i = 1; i < actual; i++) {
1855 rle = resource_list_find(&dinfo->resources,
1856 SYS_RES_IRQ, i + 1);
1858 /* Still in a run? */
1859 if (rle->start == irq + 1) {
1865 /* Finish previous range. */
1871 /* Start new range. */
1872 printf(",%ju", rle->start);
1876 /* Unfinished range? */
1879 printf(" for MSI-X\n");
1883 /* Mask all vectors. */
1884 for (i = 0; i < cfg->msix.msix_msgnum; i++)
1885 pci_mask_msix(child, i);
1887 /* Allocate and initialize vector data and virtual table. */
1888 cfg->msix.msix_vectors = malloc(sizeof(struct msix_vector) * actual,
1889 M_DEVBUF, M_WAITOK | M_ZERO);
1890 cfg->msix.msix_table = malloc(sizeof(struct msix_table_entry) * actual,
1891 M_DEVBUF, M_WAITOK | M_ZERO);
1892 for (i = 0; i < actual; i++) {
1893 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1894 cfg->msix.msix_vectors[i].mv_irq = rle->start;
1895 cfg->msix.msix_table[i].mte_vector = i + 1;
1898 /* Update control register to enable MSI-X. */
1899 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
1900 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL,
1901 cfg->msix.msix_ctrl, 2);
1903 /* Update counts of alloc'd messages. */
1904 cfg->msix.msix_alloc = actual;
1905 cfg->msix.msix_table_len = actual;
1911 * By default, pci_alloc_msix() will assign the allocated IRQ
1912 * resources consecutively to the first N messages in the MSI-X table.
1913 * However, device drivers may want to use different layouts if they
1914 * either receive fewer messages than they asked for, or they wish to
1915 * populate the MSI-X table sparsely. This method allows the driver
1916 * to specify what layout it wants. It must be called after a
1917 * successful pci_alloc_msix() but before any of the associated
1918 * SYS_RES_IRQ resources are allocated via bus_alloc_resource().
1920 * The 'vectors' array contains 'count' message vectors. The array
1921 * maps directly to the MSI-X table in that index 0 in the array
1922 * specifies the vector for the first message in the MSI-X table, etc.
1923 * The vector value in each array index can either be 0 to indicate
1924 * that no vector should be assigned to a message slot, or it can be a
1925 * number from 1 to N (where N is the count returned from a
1926 * succcessful call to pci_alloc_msix()) to indicate which message
1927 * vector (IRQ) to be used for the corresponding message.
1929 * On successful return, each message with a non-zero vector will have
1930 * an associated SYS_RES_IRQ whose rid is equal to the array index +
1931 * 1. Additionally, if any of the IRQs allocated via the previous
1932 * call to pci_alloc_msix() are not used in the mapping, those IRQs
1933 * will be freed back to the system automatically.
1935 * For example, suppose a driver has a MSI-X table with 6 messages and
1936 * asks for 6 messages, but pci_alloc_msix() only returns a count of
1937 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and
1938 * C. After the call to pci_alloc_msix(), the device will be setup to
1939 * have an MSI-X table of ABC--- (where - means no vector assigned).
1940 * If the driver then passes a vector array of { 1, 0, 1, 2, 0, 2 },
1941 * then the MSI-X table will look like A-AB-B, and the 'C' vector will
1942 * be freed back to the system. This device will also have valid
1943 * SYS_RES_IRQ rids of 1, 3, 4, and 6.
1945 * In any case, the SYS_RES_IRQ rid X will always map to the message
1946 * at MSI-X table index X - 1 and will only be valid if a vector is
1947 * assigned to that table entry.
1950 pci_remap_msix_method(device_t dev, device_t child, int count,
1951 const u_int *vectors)
1953 struct pci_devinfo *dinfo = device_get_ivars(child);
1954 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1955 struct resource_list_entry *rle;
1956 int i, irq, j, *used;
1959 * Have to have at least one message in the table but the
1960 * table can't be bigger than the actual MSI-X table in the
1963 if (count == 0 || count > msix->msix_msgnum)
1966 /* Sanity check the vectors. */
1967 for (i = 0; i < count; i++)
1968 if (vectors[i] > msix->msix_alloc)
1972 * Make sure there aren't any holes in the vectors to be used.
1973 * It's a big pain to support it, and it doesn't really make
1974 * sense anyway. Also, at least one vector must be used.
1976 used = malloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK |
1978 for (i = 0; i < count; i++)
1979 if (vectors[i] != 0)
1980 used[vectors[i] - 1] = 1;
1981 for (i = 0; i < msix->msix_alloc - 1; i++)
1982 if (used[i] == 0 && used[i + 1] == 1) {
1983 free(used, M_DEVBUF);
1987 free(used, M_DEVBUF);
1991 /* Make sure none of the resources are allocated. */
1992 for (i = 0; i < msix->msix_table_len; i++) {
1993 if (msix->msix_table[i].mte_vector == 0)
1995 if (msix->msix_table[i].mte_handlers > 0) {
1996 free(used, M_DEVBUF);
1999 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
2000 KASSERT(rle != NULL, ("missing resource"));
2001 if (rle->res != NULL) {
2002 free(used, M_DEVBUF);
2007 /* Free the existing resource list entries. */
2008 for (i = 0; i < msix->msix_table_len; i++) {
2009 if (msix->msix_table[i].mte_vector == 0)
2011 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
2015 * Build the new virtual table keeping track of which vectors are
2018 free(msix->msix_table, M_DEVBUF);
2019 msix->msix_table = malloc(sizeof(struct msix_table_entry) * count,
2020 M_DEVBUF, M_WAITOK | M_ZERO);
2021 for (i = 0; i < count; i++)
2022 msix->msix_table[i].mte_vector = vectors[i];
2023 msix->msix_table_len = count;
2025 /* Free any unused IRQs and resize the vectors array if necessary. */
2026 j = msix->msix_alloc - 1;
2028 struct msix_vector *vec;
2030 while (used[j] == 0) {
2031 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
2032 msix->msix_vectors[j].mv_irq);
2035 vec = malloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF,
2037 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) *
2039 free(msix->msix_vectors, M_DEVBUF);
2040 msix->msix_vectors = vec;
2041 msix->msix_alloc = j + 1;
2043 free(used, M_DEVBUF);
2045 /* Map the IRQs onto the rids. */
2046 for (i = 0; i < count; i++) {
2047 if (vectors[i] == 0)
2049 irq = msix->msix_vectors[vectors[i] - 1].mv_irq;
2050 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
2055 device_printf(child, "Remapped MSI-X IRQs as: ");
2056 for (i = 0; i < count; i++) {
2059 if (vectors[i] == 0)
2063 msix->msix_vectors[vectors[i] - 1].mv_irq);
2072 pci_release_msix(device_t dev, device_t child)
2074 struct pci_devinfo *dinfo = device_get_ivars(child);
2075 struct pcicfg_msix *msix = &dinfo->cfg.msix;
2076 struct resource_list_entry *rle;
2079 /* Do we have any messages to release? */
2080 if (msix->msix_alloc == 0)
2083 /* Make sure none of the resources are allocated. */
2084 for (i = 0; i < msix->msix_table_len; i++) {
2085 if (msix->msix_table[i].mte_vector == 0)
2087 if (msix->msix_table[i].mte_handlers > 0)
2089 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
2090 KASSERT(rle != NULL, ("missing resource"));
2091 if (rle->res != NULL)
2095 /* Update control register to disable MSI-X. */
2096 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
2097 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL,
2098 msix->msix_ctrl, 2);
2100 /* Free the resource list entries. */
2101 for (i = 0; i < msix->msix_table_len; i++) {
2102 if (msix->msix_table[i].mte_vector == 0)
2104 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
2106 free(msix->msix_table, M_DEVBUF);
2107 msix->msix_table_len = 0;
2109 /* Release the IRQs. */
2110 for (i = 0; i < msix->msix_alloc; i++)
2111 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
2112 msix->msix_vectors[i].mv_irq);
2113 free(msix->msix_vectors, M_DEVBUF);
2114 msix->msix_alloc = 0;
2119 * Return the max supported MSI-X messages this device supports.
2120 * Basically, assuming the MD code can alloc messages, this function
2121 * should return the maximum value that pci_alloc_msix() can return.
2122 * Thus, it is subject to the tunables, etc.
2125 pci_msix_count_method(device_t dev, device_t child)
2127 struct pci_devinfo *dinfo = device_get_ivars(child);
2128 struct pcicfg_msix *msix = &dinfo->cfg.msix;
2130 if (pci_do_msix && msix->msix_location != 0)
2131 return (msix->msix_msgnum);
2136 pci_msix_pba_bar_method(device_t dev, device_t child)
2138 struct pci_devinfo *dinfo = device_get_ivars(child);
2139 struct pcicfg_msix *msix = &dinfo->cfg.msix;
2141 if (pci_do_msix && msix->msix_location != 0)
2142 return (msix->msix_pba_bar);
2147 pci_msix_table_bar_method(device_t dev, device_t child)
2149 struct pci_devinfo *dinfo = device_get_ivars(child);
2150 struct pcicfg_msix *msix = &dinfo->cfg.msix;
2152 if (pci_do_msix && msix->msix_location != 0)
2153 return (msix->msix_table_bar);
2158 * HyperTransport MSI mapping control
2161 pci_ht_map_msi(device_t dev, uint64_t addr)
2163 struct pci_devinfo *dinfo = device_get_ivars(dev);
2164 struct pcicfg_ht *ht = &dinfo->cfg.ht;
2169 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) &&
2170 ht->ht_msiaddr >> 20 == addr >> 20) {
2171 /* Enable MSI -> HT mapping. */
2172 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
2173 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
2177 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) {
2178 /* Disable MSI -> HT mapping. */
2179 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE;
2180 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
2186 pci_get_max_payload(device_t dev)
2188 struct pci_devinfo *dinfo = device_get_ivars(dev);
2192 cap = dinfo->cfg.pcie.pcie_location;
2195 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2);
2196 val &= PCIEM_CTL_MAX_PAYLOAD;
2198 return (1 << (val + 7));
2202 pci_get_max_read_req(device_t dev)
2204 struct pci_devinfo *dinfo = device_get_ivars(dev);
2208 cap = dinfo->cfg.pcie.pcie_location;
2211 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2);
2212 val &= PCIEM_CTL_MAX_READ_REQUEST;
2214 return (1 << (val + 7));
2218 pci_set_max_read_req(device_t dev, int size)
2220 struct pci_devinfo *dinfo = device_get_ivars(dev);
2224 cap = dinfo->cfg.pcie.pcie_location;
2231 size = (1 << (fls(size) - 1));
2232 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2);
2233 val &= ~PCIEM_CTL_MAX_READ_REQUEST;
2234 val |= (fls(size) - 8) << 12;
2235 pci_write_config(dev, cap + PCIER_DEVICE_CTL, val, 2);
2240 pcie_read_config(device_t dev, int reg, int width)
2242 struct pci_devinfo *dinfo = device_get_ivars(dev);
2245 cap = dinfo->cfg.pcie.pcie_location;
2249 return (0xffffffff);
2252 return (pci_read_config(dev, cap + reg, width));
2256 pcie_write_config(device_t dev, int reg, uint32_t value, int width)
2258 struct pci_devinfo *dinfo = device_get_ivars(dev);
2261 cap = dinfo->cfg.pcie.pcie_location;
2264 pci_write_config(dev, cap + reg, value, width);
2268 * Adjusts a PCI-e capability register by clearing the bits in mask
2269 * and setting the bits in (value & mask). Bits not set in mask are
2272 * Returns the old value on success or all ones on failure.
2275 pcie_adjust_config(device_t dev, int reg, uint32_t mask, uint32_t value,
2278 struct pci_devinfo *dinfo = device_get_ivars(dev);
2282 cap = dinfo->cfg.pcie.pcie_location;
2286 return (0xffffffff);
2289 old = pci_read_config(dev, cap + reg, width);
2291 new |= (value & mask);
2292 pci_write_config(dev, cap + reg, new, width);
2297 * Support for MSI message signalled interrupts.
2300 pci_enable_msi_method(device_t dev, device_t child, uint64_t address,
2303 struct pci_devinfo *dinfo = device_get_ivars(child);
2304 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2306 /* Write data and address values. */
2307 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR,
2308 address & 0xffffffff, 4);
2309 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
2310 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR_HIGH,
2312 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA_64BIT,
2315 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA, data,
2318 /* Enable MSI in the control register. */
2319 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE;
2320 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
2323 /* Enable MSI -> HT mapping. */
2324 pci_ht_map_msi(child, address);
2328 pci_disable_msi_method(device_t dev, device_t child)
2330 struct pci_devinfo *dinfo = device_get_ivars(child);
2331 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2333 /* Disable MSI -> HT mapping. */
2334 pci_ht_map_msi(child, 0);
2336 /* Disable MSI in the control register. */
2337 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE;
2338 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
2343 * Restore MSI registers during resume. If MSI is enabled then
2344 * restore the data and address registers in addition to the control
2348 pci_resume_msi(device_t dev)
2350 struct pci_devinfo *dinfo = device_get_ivars(dev);
2351 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2355 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) {
2356 address = msi->msi_addr;
2357 data = msi->msi_data;
2358 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
2359 address & 0xffffffff, 4);
2360 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
2361 pci_write_config(dev, msi->msi_location +
2362 PCIR_MSI_ADDR_HIGH, address >> 32, 4);
2363 pci_write_config(dev, msi->msi_location +
2364 PCIR_MSI_DATA_64BIT, data, 2);
2366 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA,
2369 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
2374 pci_remap_intr_method(device_t bus, device_t dev, u_int irq)
2376 struct pci_devinfo *dinfo = device_get_ivars(dev);
2377 pcicfgregs *cfg = &dinfo->cfg;
2378 struct resource_list_entry *rle;
2379 struct msix_table_entry *mte;
2380 struct msix_vector *mv;
2386 * Handle MSI first. We try to find this IRQ among our list
2387 * of MSI IRQs. If we find it, we request updated address and
2388 * data registers and apply the results.
2390 if (cfg->msi.msi_alloc > 0) {
2391 /* If we don't have any active handlers, nothing to do. */
2392 if (cfg->msi.msi_handlers == 0)
2394 for (i = 0; i < cfg->msi.msi_alloc; i++) {
2395 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ,
2397 if (rle->start == irq) {
2398 error = PCIB_MAP_MSI(device_get_parent(bus),
2399 dev, irq, &addr, &data);
2402 pci_disable_msi(dev);
2403 dinfo->cfg.msi.msi_addr = addr;
2404 dinfo->cfg.msi.msi_data = data;
2405 pci_enable_msi(dev, addr, data);
2413 * For MSI-X, we check to see if we have this IRQ. If we do,
2414 * we request the updated mapping info. If that works, we go
2415 * through all the slots that use this IRQ and update them.
2417 if (cfg->msix.msix_alloc > 0) {
2418 for (i = 0; i < cfg->msix.msix_alloc; i++) {
2419 mv = &cfg->msix.msix_vectors[i];
2420 if (mv->mv_irq == irq) {
2421 error = PCIB_MAP_MSI(device_get_parent(bus),
2422 dev, irq, &addr, &data);
2425 mv->mv_address = addr;
2427 for (j = 0; j < cfg->msix.msix_table_len; j++) {
2428 mte = &cfg->msix.msix_table[j];
2429 if (mte->mte_vector != i + 1)
2431 if (mte->mte_handlers == 0)
2433 pci_mask_msix(dev, j);
2434 pci_enable_msix(dev, j, addr, data);
2435 pci_unmask_msix(dev, j);
2446 * Returns true if the specified device is blacklisted because MSI
2450 pci_msi_device_blacklisted(device_t dev)
2453 if (!pci_honor_msi_blacklist)
2456 return (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSI));
2460 * Determine if MSI is blacklisted globally on this system. Currently,
2461 * we just check for blacklisted chipsets as represented by the
2462 * host-PCI bridge at device 0:0:0. In the future, it may become
2463 * necessary to check other system attributes, such as the kenv values
2464 * that give the motherboard manufacturer and model number.
2467 pci_msi_blacklisted(void)
2471 if (!pci_honor_msi_blacklist)
2474 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */
2475 if (!(pcie_chipset || pcix_chipset)) {
2476 if (vm_guest != VM_GUEST_NO) {
2478 * Whitelist older chipsets in virtual
2479 * machines known to support MSI.
2481 dev = pci_find_bsf(0, 0, 0);
2483 return (!pci_has_quirk(pci_get_devid(dev),
2484 PCI_QUIRK_ENABLE_MSI_VM));
2489 dev = pci_find_bsf(0, 0, 0);
2491 return (pci_msi_device_blacklisted(dev));
2496 * Returns true if the specified device is blacklisted because MSI-X
2497 * doesn't work. Note that this assumes that if MSI doesn't work,
2498 * MSI-X doesn't either.
2501 pci_msix_device_blacklisted(device_t dev)
2504 if (!pci_honor_msi_blacklist)
2507 if (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSIX))
2510 return (pci_msi_device_blacklisted(dev));
2514 * Determine if MSI-X is blacklisted globally on this system. If MSI
2515 * is blacklisted, assume that MSI-X is as well. Check for additional
2516 * chipsets where MSI works but MSI-X does not.
2519 pci_msix_blacklisted(void)
2523 if (!pci_honor_msi_blacklist)
2526 dev = pci_find_bsf(0, 0, 0);
2527 if (dev != NULL && pci_has_quirk(pci_get_devid(dev),
2528 PCI_QUIRK_DISABLE_MSIX))
2531 return (pci_msi_blacklisted());
2535 * Attempt to allocate *count MSI messages. The actual number allocated is
2536 * returned in *count. After this function returns, each message will be
2537 * available to the driver as SYS_RES_IRQ resources starting at a rid 1.
2540 pci_alloc_msi_method(device_t dev, device_t child, int *count)
2542 struct pci_devinfo *dinfo = device_get_ivars(child);
2543 pcicfgregs *cfg = &dinfo->cfg;
2544 struct resource_list_entry *rle;
2545 int actual, error, i, irqs[32];
2548 /* Don't let count == 0 get us into trouble. */
2552 /* If rid 0 is allocated, then fail. */
2553 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
2554 if (rle != NULL && rle->res != NULL)
2557 /* Already have allocated messages? */
2558 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
2561 /* If MSI is blacklisted for this system, fail. */
2562 if (pci_msi_blacklisted())
2565 /* MSI capability present? */
2566 if (cfg->msi.msi_location == 0 || !pci_do_msi)
2570 device_printf(child,
2571 "attempting to allocate %d MSI vectors (%d supported)\n",
2572 *count, cfg->msi.msi_msgnum);
2574 /* Don't ask for more than the device supports. */
2575 actual = min(*count, cfg->msi.msi_msgnum);
2577 /* Don't ask for more than 32 messages. */
2578 actual = min(actual, 32);
2580 /* MSI requires power of 2 number of messages. */
2581 if (!powerof2(actual))
2585 /* Try to allocate N messages. */
2586 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual,
2598 * We now have N actual messages mapped onto SYS_RES_IRQ
2599 * resources in the irqs[] array, so add new resources
2600 * starting at rid 1.
2602 for (i = 0; i < actual; i++)
2603 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1,
2604 irqs[i], irqs[i], 1);
2608 device_printf(child, "using IRQ %d for MSI\n", irqs[0]);
2613 * Be fancy and try to print contiguous runs
2614 * of IRQ values as ranges. 'run' is true if
2615 * we are in a range.
2617 device_printf(child, "using IRQs %d", irqs[0]);
2619 for (i = 1; i < actual; i++) {
2620 /* Still in a run? */
2621 if (irqs[i] == irqs[i - 1] + 1) {
2626 /* Finish previous range. */
2628 printf("-%d", irqs[i - 1]);
2632 /* Start new range. */
2633 printf(",%d", irqs[i]);
2636 /* Unfinished range? */
2638 printf("-%d", irqs[actual - 1]);
2639 printf(" for MSI\n");
2643 /* Update control register with actual count. */
2644 ctrl = cfg->msi.msi_ctrl;
2645 ctrl &= ~PCIM_MSICTRL_MME_MASK;
2646 ctrl |= (ffs(actual) - 1) << 4;
2647 cfg->msi.msi_ctrl = ctrl;
2648 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2);
2650 /* Update counts of alloc'd messages. */
2651 cfg->msi.msi_alloc = actual;
2652 cfg->msi.msi_handlers = 0;
2657 /* Release the MSI messages associated with this device. */
2659 pci_release_msi_method(device_t dev, device_t child)
2661 struct pci_devinfo *dinfo = device_get_ivars(child);
2662 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2663 struct resource_list_entry *rle;
2664 int error, i, irqs[32];
2666 /* Try MSI-X first. */
2667 error = pci_release_msix(dev, child);
2668 if (error != ENODEV)
2671 /* Do we have any messages to release? */
2672 if (msi->msi_alloc == 0)
2674 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages"));
2676 /* Make sure none of the resources are allocated. */
2677 if (msi->msi_handlers > 0)
2679 for (i = 0; i < msi->msi_alloc; i++) {
2680 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
2681 KASSERT(rle != NULL, ("missing MSI resource"));
2682 if (rle->res != NULL)
2684 irqs[i] = rle->start;
2687 /* Update control register with 0 count. */
2688 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE),
2689 ("%s: MSI still enabled", __func__));
2690 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK;
2691 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
2694 /* Release the messages. */
2695 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs);
2696 for (i = 0; i < msi->msi_alloc; i++)
2697 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
2699 /* Update alloc count. */
2707 * Return the max supported MSI messages this device supports.
2708 * Basically, assuming the MD code can alloc messages, this function
2709 * should return the maximum value that pci_alloc_msi() can return.
2710 * Thus, it is subject to the tunables, etc.
2713 pci_msi_count_method(device_t dev, device_t child)
2715 struct pci_devinfo *dinfo = device_get_ivars(child);
2716 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2718 if (pci_do_msi && msi->msi_location != 0)
2719 return (msi->msi_msgnum);
2723 /* free pcicfgregs structure and all depending data structures */
2726 pci_freecfg(struct pci_devinfo *dinfo)
2728 struct devlist *devlist_head;
2729 struct pci_map *pm, *next;
2732 devlist_head = &pci_devq;
2734 if (dinfo->cfg.vpd.vpd_reg) {
2735 free(dinfo->cfg.vpd.vpd_ident, M_DEVBUF);
2736 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++)
2737 free(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF);
2738 free(dinfo->cfg.vpd.vpd_ros, M_DEVBUF);
2739 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++)
2740 free(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF);
2741 free(dinfo->cfg.vpd.vpd_w, M_DEVBUF);
2743 STAILQ_FOREACH_SAFE(pm, &dinfo->cfg.maps, pm_link, next) {
2746 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
2747 free(dinfo, M_DEVBUF);
2749 /* increment the generation count */
2752 /* we're losing one device */
2758 * PCI power manangement
2761 pci_set_powerstate_method(device_t dev, device_t child, int state)
2763 struct pci_devinfo *dinfo = device_get_ivars(child);
2764 pcicfgregs *cfg = &dinfo->cfg;
2766 int oldstate, highest, delay;
2768 if (cfg->pp.pp_cap == 0)
2769 return (EOPNOTSUPP);
2772 * Optimize a no state change request away. While it would be OK to
2773 * write to the hardware in theory, some devices have shown odd
2774 * behavior when going from D3 -> D3.
2776 oldstate = pci_get_powerstate(child);
2777 if (oldstate == state)
2781 * The PCI power management specification states that after a state
2782 * transition between PCI power states, system software must
2783 * guarantee a minimal delay before the function accesses the device.
2784 * Compute the worst case delay that we need to guarantee before we
2785 * access the device. Many devices will be responsive much more
2786 * quickly than this delay, but there are some that don't respond
2787 * instantly to state changes. Transitions to/from D3 state require
2788 * 10ms, while D2 requires 200us, and D0/1 require none. The delay
2789 * is done below with DELAY rather than a sleeper function because
2790 * this function can be called from contexts where we cannot sleep.
2792 highest = (oldstate > state) ? oldstate : state;
2793 if (highest == PCI_POWERSTATE_D3)
2795 else if (highest == PCI_POWERSTATE_D2)
2799 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
2800 & ~PCIM_PSTAT_DMASK;
2802 case PCI_POWERSTATE_D0:
2803 status |= PCIM_PSTAT_D0;
2805 case PCI_POWERSTATE_D1:
2806 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
2807 return (EOPNOTSUPP);
2808 status |= PCIM_PSTAT_D1;
2810 case PCI_POWERSTATE_D2:
2811 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
2812 return (EOPNOTSUPP);
2813 status |= PCIM_PSTAT_D2;
2815 case PCI_POWERSTATE_D3:
2816 status |= PCIM_PSTAT_D3;
2823 pci_printf(cfg, "Transition from D%d to D%d\n", oldstate,
2826 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
2833 pci_get_powerstate_method(device_t dev, device_t child)
2835 struct pci_devinfo *dinfo = device_get_ivars(child);
2836 pcicfgregs *cfg = &dinfo->cfg;
2840 if (cfg->pp.pp_cap != 0) {
2841 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
2842 switch (status & PCIM_PSTAT_DMASK) {
2844 result = PCI_POWERSTATE_D0;
2847 result = PCI_POWERSTATE_D1;
2850 result = PCI_POWERSTATE_D2;
2853 result = PCI_POWERSTATE_D3;
2856 result = PCI_POWERSTATE_UNKNOWN;
2860 /* No support, device is always at D0 */
2861 result = PCI_POWERSTATE_D0;
2867 * Some convenience functions for PCI device drivers.
2870 static __inline void
2871 pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
2875 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2877 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2880 static __inline void
2881 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
2885 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2887 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2891 pci_enable_busmaster_method(device_t dev, device_t child)
2893 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2898 pci_disable_busmaster_method(device_t dev, device_t child)
2900 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2905 pci_enable_io_method(device_t dev, device_t child, int space)
2910 case SYS_RES_IOPORT:
2911 bit = PCIM_CMD_PORTEN;
2913 case SYS_RES_MEMORY:
2914 bit = PCIM_CMD_MEMEN;
2919 pci_set_command_bit(dev, child, bit);
2924 pci_disable_io_method(device_t dev, device_t child, int space)
2929 case SYS_RES_IOPORT:
2930 bit = PCIM_CMD_PORTEN;
2932 case SYS_RES_MEMORY:
2933 bit = PCIM_CMD_MEMEN;
2938 pci_clear_command_bit(dev, child, bit);
2943 * New style pci driver. Parent device is either a pci-host-bridge or a
2944 * pci-pci-bridge. Both kinds are represented by instances of pcib.
2948 pci_print_verbose(struct pci_devinfo *dinfo)
2952 pcicfgregs *cfg = &dinfo->cfg;
2954 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
2955 cfg->vendor, cfg->device, cfg->revid);
2956 printf("\tdomain=%d, bus=%d, slot=%d, func=%d\n",
2957 cfg->domain, cfg->bus, cfg->slot, cfg->func);
2958 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
2959 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
2961 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
2962 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
2963 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
2964 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
2965 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
2966 if (cfg->intpin > 0)
2967 printf("\tintpin=%c, irq=%d\n",
2968 cfg->intpin +'a' -1, cfg->intline);
2969 if (cfg->pp.pp_cap) {
2972 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
2973 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
2974 cfg->pp.pp_cap & PCIM_PCAP_SPEC,
2975 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
2976 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
2977 status & PCIM_PSTAT_DMASK);
2979 if (cfg->msi.msi_location) {
2982 ctrl = cfg->msi.msi_ctrl;
2983 printf("\tMSI supports %d message%s%s%s\n",
2984 cfg->msi.msi_msgnum,
2985 (cfg->msi.msi_msgnum == 1) ? "" : "s",
2986 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
2987 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");
2989 if (cfg->msix.msix_location) {
2990 printf("\tMSI-X supports %d message%s ",
2991 cfg->msix.msix_msgnum,
2992 (cfg->msix.msix_msgnum == 1) ? "" : "s");
2993 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar)
2994 printf("in map 0x%x\n",
2995 cfg->msix.msix_table_bar);
2997 printf("in maps 0x%x and 0x%x\n",
2998 cfg->msix.msix_table_bar,
2999 cfg->msix.msix_pba_bar);
3005 pci_porten(device_t dev)
3007 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_PORTEN) != 0;
3011 pci_memen(device_t dev)
3013 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0;
3017 pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp,
3020 struct pci_devinfo *dinfo;
3021 pci_addr_t map, testval;
3026 * The device ROM BAR is special. It is always a 32-bit
3027 * memory BAR. Bit 0 is special and should not be set when
3030 dinfo = device_get_ivars(dev);
3031 if (PCIR_IS_BIOS(&dinfo->cfg, reg)) {
3032 map = pci_read_config(dev, reg, 4);
3033 pci_write_config(dev, reg, 0xfffffffe, 4);
3034 testval = pci_read_config(dev, reg, 4);
3035 pci_write_config(dev, reg, map, 4);
3037 *testvalp = testval;
3043 map = pci_read_config(dev, reg, 4);
3044 ln2range = pci_maprange(map);
3046 map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32;
3049 * Disable decoding via the command register before
3050 * determining the BAR's length since we will be placing it in
3053 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
3054 pci_write_config(dev, PCIR_COMMAND,
3055 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2);
3058 * Determine the BAR's length by writing all 1's. The bottom
3059 * log_2(size) bits of the BAR will stick as 0 when we read
3062 * NB: according to the PCI Local Bus Specification, rev. 3.0:
3063 * "Software writes 0FFFFFFFFh to both registers, reads them back,
3064 * and combines the result into a 64-bit value." (section 6.2.5.1)
3066 * Writes to both registers must be performed before attempting to
3067 * read back the size value.
3070 pci_write_config(dev, reg, 0xffffffff, 4);
3071 if (ln2range == 64) {
3072 pci_write_config(dev, reg + 4, 0xffffffff, 4);
3073 testval |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32;
3075 testval |= pci_read_config(dev, reg, 4);
3078 * Restore the original value of the BAR. We may have reprogrammed
3079 * the BAR of the low-level console device and when booting verbose,
3080 * we need the console device addressable.
3082 pci_write_config(dev, reg, map, 4);
3084 pci_write_config(dev, reg + 4, map >> 32, 4);
3085 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
3088 *testvalp = testval;
3090 *bar64 = (ln2range == 64);
3094 pci_write_bar(device_t dev, struct pci_map *pm, pci_addr_t base)
3096 struct pci_devinfo *dinfo;
3099 /* The device ROM BAR is always a 32-bit memory BAR. */
3100 dinfo = device_get_ivars(dev);
3101 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg))
3104 ln2range = pci_maprange(pm->pm_value);
3105 pci_write_config(dev, pm->pm_reg, base, 4);
3107 pci_write_config(dev, pm->pm_reg + 4, base >> 32, 4);
3108 pm->pm_value = pci_read_config(dev, pm->pm_reg, 4);
3110 pm->pm_value |= (pci_addr_t)pci_read_config(dev,
3111 pm->pm_reg + 4, 4) << 32;
3115 pci_find_bar(device_t dev, int reg)
3117 struct pci_devinfo *dinfo;
3120 dinfo = device_get_ivars(dev);
3121 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) {
3122 if (pm->pm_reg == reg)
3129 pci_bar_enabled(device_t dev, struct pci_map *pm)
3131 struct pci_devinfo *dinfo;
3134 dinfo = device_get_ivars(dev);
3135 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) &&
3136 !(pm->pm_value & PCIM_BIOS_ENABLE))
3138 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
3139 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) || PCI_BAR_MEM(pm->pm_value))
3140 return ((cmd & PCIM_CMD_MEMEN) != 0);
3142 return ((cmd & PCIM_CMD_PORTEN) != 0);
3146 pci_add_bar(device_t dev, int reg, pci_addr_t value, pci_addr_t size)
3148 struct pci_devinfo *dinfo;
3149 struct pci_map *pm, *prev;
3151 dinfo = device_get_ivars(dev);
3152 pm = malloc(sizeof(*pm), M_DEVBUF, M_WAITOK | M_ZERO);
3154 pm->pm_value = value;
3156 STAILQ_FOREACH(prev, &dinfo->cfg.maps, pm_link) {
3157 KASSERT(prev->pm_reg != pm->pm_reg, ("duplicate map %02x",
3159 if (STAILQ_NEXT(prev, pm_link) == NULL ||
3160 STAILQ_NEXT(prev, pm_link)->pm_reg > pm->pm_reg)
3164 STAILQ_INSERT_AFTER(&dinfo->cfg.maps, prev, pm, pm_link);
3166 STAILQ_INSERT_TAIL(&dinfo->cfg.maps, pm, pm_link);
3171 pci_restore_bars(device_t dev)
3173 struct pci_devinfo *dinfo;
3177 dinfo = device_get_ivars(dev);
3178 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) {
3179 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg))
3182 ln2range = pci_maprange(pm->pm_value);
3183 pci_write_config(dev, pm->pm_reg, pm->pm_value, 4);
3185 pci_write_config(dev, pm->pm_reg + 4,
3186 pm->pm_value >> 32, 4);
3191 * Add a resource based on a pci map register. Return 1 if the map
3192 * register is a 32bit map register or 2 if it is a 64bit register.
3195 pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl,
3196 int force, int prefetch)
3199 pci_addr_t base, map, testval;
3200 pci_addr_t start, end, count;
3201 int barlen, basezero, flags, maprange, mapsize, type;
3203 struct resource *res;
3206 * The BAR may already exist if the device is a CardBus card
3207 * whose CIS is stored in this BAR.
3209 pm = pci_find_bar(dev, reg);
3211 maprange = pci_maprange(pm->pm_value);
3212 barlen = maprange == 64 ? 2 : 1;
3216 pci_read_bar(dev, reg, &map, &testval, NULL);
3217 if (PCI_BAR_MEM(map)) {
3218 type = SYS_RES_MEMORY;
3219 if (map & PCIM_BAR_MEM_PREFETCH)
3222 type = SYS_RES_IOPORT;
3223 mapsize = pci_mapsize(testval);
3224 base = pci_mapbase(map);
3225 #ifdef __PCI_BAR_ZERO_VALID
3228 basezero = base == 0;
3230 maprange = pci_maprange(map);
3231 barlen = maprange == 64 ? 2 : 1;
3234 * For I/O registers, if bottom bit is set, and the next bit up
3235 * isn't clear, we know we have a BAR that doesn't conform to the
3236 * spec, so ignore it. Also, sanity check the size of the data
3237 * areas to the type of memory involved. Memory must be at least
3238 * 16 bytes in size, while I/O ranges must be at least 4.
3240 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0)
3242 if ((type == SYS_RES_MEMORY && mapsize < 4) ||
3243 (type == SYS_RES_IOPORT && mapsize < 2))
3246 /* Save a record of this BAR. */
3247 pm = pci_add_bar(dev, reg, map, mapsize);
3249 printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d",
3250 reg, pci_maptype(map), maprange, (uintmax_t)base, mapsize);
3251 if (type == SYS_RES_IOPORT && !pci_porten(dev))
3252 printf(", port disabled\n");
3253 else if (type == SYS_RES_MEMORY && !pci_memen(dev))
3254 printf(", memory disabled\n");
3256 printf(", enabled\n");
3260 * If base is 0, then we have problems if this architecture does
3261 * not allow that. It is best to ignore such entries for the
3262 * moment. These will be allocated later if the driver specifically
3263 * requests them. However, some removable buses look better when
3264 * all resources are allocated, so allow '0' to be overriden.
3266 * Similarly treat maps whose values is the same as the test value
3267 * read back. These maps have had all f's written to them by the
3268 * BIOS in an attempt to disable the resources.
3270 if (!force && (basezero || map == testval))
3272 if ((u_long)base != base) {
3274 "pci%d:%d:%d:%d bar %#x too many address bits",
3275 pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev),
3276 pci_get_function(dev), reg);
3281 * This code theoretically does the right thing, but has
3282 * undesirable side effects in some cases where peripherals
3283 * respond oddly to having these bits enabled. Let the user
3284 * be able to turn them off (since pci_enable_io_modes is 1 by
3287 if (pci_enable_io_modes) {
3288 /* Turn on resources that have been left off by a lazy BIOS */
3289 if (type == SYS_RES_IOPORT && !pci_porten(dev)) {
3290 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
3291 cmd |= PCIM_CMD_PORTEN;
3292 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
3294 if (type == SYS_RES_MEMORY && !pci_memen(dev)) {
3295 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
3296 cmd |= PCIM_CMD_MEMEN;
3297 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
3300 if (type == SYS_RES_IOPORT && !pci_porten(dev))
3302 if (type == SYS_RES_MEMORY && !pci_memen(dev))
3306 count = (pci_addr_t)1 << mapsize;
3307 flags = RF_ALIGNMENT_LOG2(mapsize);
3309 flags |= RF_PREFETCHABLE;
3310 if (basezero || base == pci_mapbase(testval) || pci_clear_bars) {
3311 start = 0; /* Let the parent decide. */
3315 end = base + count - 1;
3317 resource_list_add(rl, type, reg, start, end, count);
3320 * Try to allocate the resource for this BAR from our parent
3321 * so that this resource range is already reserved. The
3322 * driver for this device will later inherit this resource in
3323 * pci_alloc_resource().
3325 res = resource_list_reserve(rl, bus, dev, type, ®, start, end, count,
3327 if ((pci_do_realloc_bars
3328 || pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_REALLOC_BAR))
3329 && res == NULL && (start != 0 || end != ~0)) {
3331 * If the allocation fails, try to allocate a resource for
3332 * this BAR using any available range. The firmware felt
3333 * it was important enough to assign a resource, so don't
3334 * disable decoding if we can help it.
3336 resource_list_delete(rl, type, reg);
3337 resource_list_add(rl, type, reg, 0, ~0, count);
3338 res = resource_list_reserve(rl, bus, dev, type, ®, 0, ~0,
3343 * If the allocation fails, delete the resource list entry
3344 * and disable decoding for this device.
3346 * If the driver requests this resource in the future,
3347 * pci_reserve_map() will try to allocate a fresh
3350 resource_list_delete(rl, type, reg);
3351 pci_disable_io(dev, type);
3354 "pci%d:%d:%d:%d bar %#x failed to allocate\n",
3355 pci_get_domain(dev), pci_get_bus(dev),
3356 pci_get_slot(dev), pci_get_function(dev), reg);
3358 start = rman_get_start(res);
3359 pci_write_bar(dev, pm, start);
3365 * For ATA devices we need to decide early what addressing mode to use.
3366 * Legacy demands that the primary and secondary ATA ports sits on the
3367 * same addresses that old ISA hardware did. This dictates that we use
3368 * those addresses and ignore the BAR's if we cannot set PCI native
3372 pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force,
3373 uint32_t prefetchmask)
3375 int rid, type, progif;
3377 /* if this device supports PCI native addressing use it */
3378 progif = pci_read_config(dev, PCIR_PROGIF, 1);
3379 if ((progif & 0x8a) == 0x8a) {
3380 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
3381 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
3382 printf("Trying ATA native PCI addressing mode\n");
3383 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
3387 progif = pci_read_config(dev, PCIR_PROGIF, 1);
3388 type = SYS_RES_IOPORT;
3389 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
3390 pci_add_map(bus, dev, PCIR_BAR(0), rl, force,
3391 prefetchmask & (1 << 0));
3392 pci_add_map(bus, dev, PCIR_BAR(1), rl, force,
3393 prefetchmask & (1 << 1));
3396 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
3397 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x1f0,
3400 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
3401 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x3f6,
3404 if (progif & PCIP_STORAGE_IDE_MODESEC) {
3405 pci_add_map(bus, dev, PCIR_BAR(2), rl, force,
3406 prefetchmask & (1 << 2));
3407 pci_add_map(bus, dev, PCIR_BAR(3), rl, force,
3408 prefetchmask & (1 << 3));
3411 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
3412 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x170,
3415 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
3416 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x376,
3419 pci_add_map(bus, dev, PCIR_BAR(4), rl, force,
3420 prefetchmask & (1 << 4));
3421 pci_add_map(bus, dev, PCIR_BAR(5), rl, force,
3422 prefetchmask & (1 << 5));
3426 pci_assign_interrupt(device_t bus, device_t dev, int force_route)
3428 struct pci_devinfo *dinfo = device_get_ivars(dev);
3429 pcicfgregs *cfg = &dinfo->cfg;
3430 char tunable_name[64];
3433 /* Has to have an intpin to have an interrupt. */
3434 if (cfg->intpin == 0)
3437 /* Let the user override the IRQ with a tunable. */
3438 irq = PCI_INVALID_IRQ;
3439 snprintf(tunable_name, sizeof(tunable_name),
3440 "hw.pci%d.%d.%d.INT%c.irq",
3441 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1);
3442 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0))
3443 irq = PCI_INVALID_IRQ;
3446 * If we didn't get an IRQ via the tunable, then we either use the
3447 * IRQ value in the intline register or we ask the bus to route an
3448 * interrupt for us. If force_route is true, then we only use the
3449 * value in the intline register if the bus was unable to assign an
3452 if (!PCI_INTERRUPT_VALID(irq)) {
3453 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
3454 irq = PCI_ASSIGN_INTERRUPT(bus, dev);
3455 if (!PCI_INTERRUPT_VALID(irq))
3459 /* If after all that we don't have an IRQ, just bail. */
3460 if (!PCI_INTERRUPT_VALID(irq))
3463 /* Update the config register if it changed. */
3464 if (irq != cfg->intline) {
3466 pci_write_config(dev, PCIR_INTLINE, irq, 1);
3469 /* Add this IRQ as rid 0 interrupt resource. */
3470 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1);
3473 /* Perform early OHCI takeover from SMM. */
3475 ohci_early_takeover(device_t self)
3477 struct resource *res;
3483 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
3487 ctl = bus_read_4(res, OHCI_CONTROL);
3488 if (ctl & OHCI_IR) {
3490 printf("ohci early: "
3491 "SMM active, request owner change\n");
3492 bus_write_4(res, OHCI_COMMAND_STATUS, OHCI_OCR);
3493 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) {
3495 ctl = bus_read_4(res, OHCI_CONTROL);
3497 if (ctl & OHCI_IR) {
3499 printf("ohci early: "
3500 "SMM does not respond, resetting\n");
3501 bus_write_4(res, OHCI_CONTROL, OHCI_HCFS_RESET);
3503 /* Disable interrupts */
3504 bus_write_4(res, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS);
3507 bus_release_resource(self, SYS_RES_MEMORY, rid, res);
3510 /* Perform early UHCI takeover from SMM. */
3512 uhci_early_takeover(device_t self)
3514 struct resource *res;
3518 * Set the PIRQD enable bit and switch off all the others. We don't
3519 * want legacy support to interfere with us XXX Does this also mean
3520 * that the BIOS won't touch the keyboard anymore if it is connected
3521 * to the ports of the root hub?
3523 pci_write_config(self, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN, 2);
3525 /* Disable interrupts */
3526 rid = PCI_UHCI_BASE_REG;
3527 res = bus_alloc_resource_any(self, SYS_RES_IOPORT, &rid, RF_ACTIVE);
3529 bus_write_2(res, UHCI_INTR, 0);
3530 bus_release_resource(self, SYS_RES_IOPORT, rid, res);
3534 /* Perform early EHCI takeover from SMM. */
3536 ehci_early_takeover(device_t self)
3538 struct resource *res;
3548 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
3552 cparams = bus_read_4(res, EHCI_HCCPARAMS);
3554 /* Synchronise with the BIOS if it owns the controller. */
3555 for (eecp = EHCI_HCC_EECP(cparams); eecp != 0;
3556 eecp = EHCI_EECP_NEXT(eec)) {
3557 eec = pci_read_config(self, eecp, 4);
3558 if (EHCI_EECP_ID(eec) != EHCI_EC_LEGSUP) {
3561 bios_sem = pci_read_config(self, eecp +
3562 EHCI_LEGSUP_BIOS_SEM, 1);
3563 if (bios_sem == 0) {
3567 printf("ehci early: "
3568 "SMM active, request owner change\n");
3570 pci_write_config(self, eecp + EHCI_LEGSUP_OS_SEM, 1, 1);
3572 for (i = 0; (i < 100) && (bios_sem != 0); i++) {
3574 bios_sem = pci_read_config(self, eecp +
3575 EHCI_LEGSUP_BIOS_SEM, 1);
3578 if (bios_sem != 0) {
3580 printf("ehci early: "
3581 "SMM does not respond\n");
3583 /* Disable interrupts */
3584 offs = EHCI_CAPLENGTH(bus_read_4(res, EHCI_CAPLEN_HCIVERSION));
3585 bus_write_4(res, offs + EHCI_USBINTR, 0);
3587 bus_release_resource(self, SYS_RES_MEMORY, rid, res);
3590 /* Perform early XHCI takeover from SMM. */
3592 xhci_early_takeover(device_t self)
3594 struct resource *res;
3604 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
3608 cparams = bus_read_4(res, XHCI_HCSPARAMS0);
3612 /* Synchronise with the BIOS if it owns the controller. */
3613 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec);
3614 eecp += XHCI_XECP_NEXT(eec) << 2) {
3615 eec = bus_read_4(res, eecp);
3617 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY)
3620 bios_sem = bus_read_1(res, eecp + XHCI_XECP_BIOS_SEM);
3625 printf("xhci early: "
3626 "SMM active, request owner change\n");
3628 bus_write_1(res, eecp + XHCI_XECP_OS_SEM, 1);
3630 /* wait a maximum of 5 second */
3632 for (i = 0; (i < 5000) && (bios_sem != 0); i++) {
3634 bios_sem = bus_read_1(res, eecp +
3635 XHCI_XECP_BIOS_SEM);
3638 if (bios_sem != 0) {
3640 printf("xhci early: "
3641 "SMM does not respond\n");
3644 /* Disable interrupts */
3645 offs = bus_read_1(res, XHCI_CAPLENGTH);
3646 bus_write_4(res, offs + XHCI_USBCMD, 0);
3647 bus_read_4(res, offs + XHCI_USBSTS);
3649 bus_release_resource(self, SYS_RES_MEMORY, rid, res);
3652 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
3654 pci_reserve_secbus(device_t bus, device_t dev, pcicfgregs *cfg,
3655 struct resource_list *rl)
3657 struct resource *res;
3659 rman_res_t start, end, count;
3660 int rid, sec_bus, sec_reg, sub_bus, sub_reg, sup_bus;
3662 switch (cfg->hdrtype & PCIM_HDRTYPE) {
3663 case PCIM_HDRTYPE_BRIDGE:
3664 sec_reg = PCIR_SECBUS_1;
3665 sub_reg = PCIR_SUBBUS_1;
3667 case PCIM_HDRTYPE_CARDBUS:
3668 sec_reg = PCIR_SECBUS_2;
3669 sub_reg = PCIR_SUBBUS_2;
3676 * If the existing bus range is valid, attempt to reserve it
3677 * from our parent. If this fails for any reason, clear the
3678 * secbus and subbus registers.
3680 * XXX: Should we reset sub_bus to sec_bus if it is < sec_bus?
3681 * This would at least preserve the existing sec_bus if it is
3684 sec_bus = PCI_READ_CONFIG(bus, dev, sec_reg, 1);
3685 sub_bus = PCI_READ_CONFIG(bus, dev, sub_reg, 1);
3687 /* Quirk handling. */
3688 switch (pci_get_devid(dev)) {
3689 case 0x12258086: /* Intel 82454KX/GX (Orion) */
3690 sup_bus = pci_read_config(dev, 0x41, 1);
3691 if (sup_bus != 0xff) {
3692 sec_bus = sup_bus + 1;
3693 sub_bus = sup_bus + 1;
3694 PCI_WRITE_CONFIG(bus, dev, sec_reg, sec_bus, 1);
3695 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1);
3700 /* Compaq R3000 BIOS sets wrong subordinate bus number. */
3701 if ((cp = kern_getenv("smbios.planar.maker")) == NULL)
3703 if (strncmp(cp, "Compal", 6) != 0) {
3708 if ((cp = kern_getenv("smbios.planar.product")) == NULL)
3710 if (strncmp(cp, "08A0", 4) != 0) {
3715 if (sub_bus < 0xa) {
3717 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1);
3723 printf("\tsecbus=%d, subbus=%d\n", sec_bus, sub_bus);
3724 if (sec_bus > 0 && sub_bus >= sec_bus) {
3727 count = end - start + 1;
3729 resource_list_add(rl, PCI_RES_BUS, 0, 0, ~0, count);
3732 * If requested, clear secondary bus registers in
3733 * bridge devices to force a complete renumbering
3734 * rather than reserving the existing range. However,
3735 * preserve the existing size.
3737 if (pci_clear_buses)
3741 res = resource_list_reserve(rl, bus, dev, PCI_RES_BUS, &rid,
3742 start, end, count, 0);
3748 "pci%d:%d:%d:%d secbus failed to allocate\n",
3749 pci_get_domain(dev), pci_get_bus(dev),
3750 pci_get_slot(dev), pci_get_function(dev));
3754 PCI_WRITE_CONFIG(bus, dev, sec_reg, 0, 1);
3755 PCI_WRITE_CONFIG(bus, dev, sub_reg, 0, 1);
3758 static struct resource *
3759 pci_alloc_secbus(device_t dev, device_t child, int *rid, rman_res_t start,
3760 rman_res_t end, rman_res_t count, u_int flags)
3762 struct pci_devinfo *dinfo;
3764 struct resource_list *rl;
3765 struct resource *res;
3766 int sec_reg, sub_reg;
3768 dinfo = device_get_ivars(child);
3770 rl = &dinfo->resources;
3771 switch (cfg->hdrtype & PCIM_HDRTYPE) {
3772 case PCIM_HDRTYPE_BRIDGE:
3773 sec_reg = PCIR_SECBUS_1;
3774 sub_reg = PCIR_SUBBUS_1;
3776 case PCIM_HDRTYPE_CARDBUS:
3777 sec_reg = PCIR_SECBUS_2;
3778 sub_reg = PCIR_SUBBUS_2;
3787 if (resource_list_find(rl, PCI_RES_BUS, *rid) == NULL)
3788 resource_list_add(rl, PCI_RES_BUS, *rid, start, end, count);
3789 if (!resource_list_reserved(rl, PCI_RES_BUS, *rid)) {
3790 res = resource_list_reserve(rl, dev, child, PCI_RES_BUS, rid,
3791 start, end, count, flags & ~RF_ACTIVE);
3793 resource_list_delete(rl, PCI_RES_BUS, *rid);
3794 device_printf(child, "allocating %ju bus%s failed\n",
3795 count, count == 1 ? "" : "es");
3799 device_printf(child,
3800 "Lazy allocation of %ju bus%s at %ju\n", count,
3801 count == 1 ? "" : "es", rman_get_start(res));
3802 PCI_WRITE_CONFIG(dev, child, sec_reg, rman_get_start(res), 1);
3803 PCI_WRITE_CONFIG(dev, child, sub_reg, rman_get_end(res), 1);
3805 return (resource_list_alloc(rl, dev, child, PCI_RES_BUS, rid, start,
3806 end, count, flags));
3811 pci_ea_bei_to_rid(device_t dev, int bei)
3814 struct pci_devinfo *dinfo;
3816 struct pcicfg_iov *iov;
3818 dinfo = device_get_ivars(dev);
3819 iov = dinfo->cfg.iov;
3821 iov_pos = iov->iov_pos;
3826 /* Check if matches BAR */
3827 if ((bei >= PCIM_EA_BEI_BAR_0) &&
3828 (bei <= PCIM_EA_BEI_BAR_5))
3829 return (PCIR_BAR(bei));
3832 if (bei == PCIM_EA_BEI_ROM)
3836 /* Check if matches VF_BAR */
3837 if ((iov != NULL) && (bei >= PCIM_EA_BEI_VF_BAR_0) &&
3838 (bei <= PCIM_EA_BEI_VF_BAR_5))
3839 return (PCIR_SRIOV_BAR(bei - PCIM_EA_BEI_VF_BAR_0) +
3847 pci_ea_is_enabled(device_t dev, int rid)
3849 struct pci_ea_entry *ea;
3850 struct pci_devinfo *dinfo;
3852 dinfo = device_get_ivars(dev);
3854 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) {
3855 if (pci_ea_bei_to_rid(dev, ea->eae_bei) == rid)
3856 return ((ea->eae_flags & PCIM_EA_ENABLE) > 0);
3863 pci_add_resources_ea(device_t bus, device_t dev, int alloc_iov)
3865 struct pci_ea_entry *ea;
3866 struct pci_devinfo *dinfo;
3867 pci_addr_t start, end, count;
3868 struct resource_list *rl;
3869 int type, flags, rid;
3870 struct resource *res;
3873 struct pcicfg_iov *iov;
3876 dinfo = device_get_ivars(dev);
3877 rl = &dinfo->resources;
3881 iov = dinfo->cfg.iov;
3884 if (dinfo->cfg.ea.ea_location == 0)
3887 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) {
3889 * TODO: Ignore EA-BAR if is not enabled.
3890 * Currently the EA implementation supports
3891 * only situation, where EA structure contains
3892 * predefined entries. In case they are not enabled
3893 * leave them unallocated and proceed with
3894 * a legacy-BAR mechanism.
3896 if ((ea->eae_flags & PCIM_EA_ENABLE) == 0)
3899 switch ((ea->eae_flags & PCIM_EA_PP) >> PCIM_EA_PP_OFFSET) {
3900 case PCIM_EA_P_MEM_PREFETCH:
3901 case PCIM_EA_P_VF_MEM_PREFETCH:
3902 flags = RF_PREFETCHABLE;
3904 case PCIM_EA_P_VF_MEM:
3906 type = SYS_RES_MEMORY;
3909 type = SYS_RES_IOPORT;
3915 if (alloc_iov != 0) {
3917 /* Allocating IOV, confirm BEI matches */
3918 if ((ea->eae_bei < PCIM_EA_BEI_VF_BAR_0) ||
3919 (ea->eae_bei > PCIM_EA_BEI_VF_BAR_5))
3925 /* Allocating BAR, confirm BEI matches */
3926 if (((ea->eae_bei < PCIM_EA_BEI_BAR_0) ||
3927 (ea->eae_bei > PCIM_EA_BEI_BAR_5)) &&
3928 (ea->eae_bei != PCIM_EA_BEI_ROM))
3932 rid = pci_ea_bei_to_rid(dev, ea->eae_bei);
3936 /* Skip resources already allocated by EA */
3937 if ((resource_list_find(rl, SYS_RES_MEMORY, rid) != NULL) ||
3938 (resource_list_find(rl, SYS_RES_IOPORT, rid) != NULL))
3941 start = ea->eae_base;
3942 count = ea->eae_max_offset + 1;
3945 count = count * iov->iov_num_vfs;
3947 end = start + count - 1;
3951 resource_list_add(rl, type, rid, start, end, count);
3952 res = resource_list_reserve(rl, bus, dev, type, &rid, start, end, count,
3955 resource_list_delete(rl, type, rid);
3958 * Failed to allocate using EA, disable entry.
3959 * Another attempt to allocation will be performed
3960 * further, but this time using legacy BAR registers
3962 tmp = pci_read_config(dev, ea->eae_cfg_offset, 4);
3963 tmp &= ~PCIM_EA_ENABLE;
3964 pci_write_config(dev, ea->eae_cfg_offset, tmp, 4);
3967 * Disabling entry might fail in case it is hardwired.
3968 * Read flags again to match current status.
3970 ea->eae_flags = pci_read_config(dev, ea->eae_cfg_offset, 4);
3975 /* As per specification, fill BAR with zeros */
3976 pci_write_config(dev, rid, 0, 4);
3981 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask)
3983 struct pci_devinfo *dinfo;
3985 struct resource_list *rl;
3986 const struct pci_quirk *q;
3990 dinfo = device_get_ivars(dev);
3992 rl = &dinfo->resources;
3993 devid = (cfg->device << 16) | cfg->vendor;
3995 /* Allocate resources using Enhanced Allocation */
3996 pci_add_resources_ea(bus, dev, 0);
3998 /* ATA devices needs special map treatment */
3999 if ((pci_get_class(dev) == PCIC_STORAGE) &&
4000 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
4001 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
4002 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
4003 !pci_read_config(dev, PCIR_BAR(2), 4))) )
4004 pci_ata_maps(bus, dev, rl, force, prefetchmask);
4006 for (i = 0; i < cfg->nummaps;) {
4007 /* Skip resources already managed by EA */
4008 if ((resource_list_find(rl, SYS_RES_MEMORY, PCIR_BAR(i)) != NULL) ||
4009 (resource_list_find(rl, SYS_RES_IOPORT, PCIR_BAR(i)) != NULL) ||
4010 pci_ea_is_enabled(dev, PCIR_BAR(i))) {
4016 * Skip quirked resources.
4018 for (q = &pci_quirks[0]; q->devid != 0; q++)
4019 if (q->devid == devid &&
4020 q->type == PCI_QUIRK_UNMAP_REG &&
4021 q->arg1 == PCIR_BAR(i))
4023 if (q->devid != 0) {
4027 i += pci_add_map(bus, dev, PCIR_BAR(i), rl, force,
4028 prefetchmask & (1 << i));
4032 * Add additional, quirked resources.
4034 for (q = &pci_quirks[0]; q->devid != 0; q++)
4035 if (q->devid == devid && q->type == PCI_QUIRK_MAP_REG)
4036 pci_add_map(bus, dev, q->arg1, rl, force, 0);
4038 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
4039 #ifdef __PCI_REROUTE_INTERRUPT
4041 * Try to re-route interrupts. Sometimes the BIOS or
4042 * firmware may leave bogus values in these registers.
4043 * If the re-route fails, then just stick with what we
4046 pci_assign_interrupt(bus, dev, 1);
4048 pci_assign_interrupt(bus, dev, 0);
4052 if (pci_usb_takeover && pci_get_class(dev) == PCIC_SERIALBUS &&
4053 pci_get_subclass(dev) == PCIS_SERIALBUS_USB) {
4054 if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_XHCI)
4055 xhci_early_takeover(dev);
4056 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI)
4057 ehci_early_takeover(dev);
4058 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_OHCI)
4059 ohci_early_takeover(dev);
4060 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_UHCI)
4061 uhci_early_takeover(dev);
4064 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
4066 * Reserve resources for secondary bus ranges behind bridge
4069 pci_reserve_secbus(bus, dev, cfg, rl);
4073 static struct pci_devinfo *
4074 pci_identify_function(device_t pcib, device_t dev, int domain, int busno,
4077 struct pci_devinfo *dinfo;
4079 dinfo = pci_read_device(pcib, dev, domain, busno, slot, func);
4081 pci_add_child(dev, dinfo);
4087 pci_add_children(device_t dev, int domain, int busno)
4089 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
4090 device_t pcib = device_get_parent(dev);
4091 struct pci_devinfo *dinfo;
4093 int s, f, pcifunchigh;
4098 * Try to detect a device at slot 0, function 0. If it exists, try to
4099 * enable ARI. We must enable ARI before detecting the rest of the
4100 * functions on this bus as ARI changes the set of slots and functions
4101 * that are legal on this bus.
4103 dinfo = pci_identify_function(pcib, dev, domain, busno, 0, 0);
4104 if (dinfo != NULL && pci_enable_ari)
4105 PCIB_TRY_ENABLE_ARI(pcib, dinfo->cfg.dev);
4108 * Start looking for new devices on slot 0 at function 1 because we
4109 * just identified the device at slot 0, function 0.
4113 maxslots = PCIB_MAXSLOTS(pcib);
4114 for (s = 0; s <= maxslots; s++, first_func = 0) {
4118 hdrtype = REG(PCIR_HDRTYPE, 1);
4119 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
4121 if (hdrtype & PCIM_MFDEV)
4122 pcifunchigh = PCIB_MAXFUNCS(pcib);
4123 for (f = first_func; f <= pcifunchigh; f++)
4124 pci_identify_function(pcib, dev, domain, busno, s, f);
4130 pci_rescan_method(device_t dev)
4132 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
4133 device_t pcib = device_get_parent(dev);
4134 device_t child, *devlist, *unchanged;
4135 int devcount, error, i, j, maxslots, oldcount;
4136 int busno, domain, s, f, pcifunchigh;
4139 /* No need to check for ARI on a rescan. */
4140 error = device_get_children(dev, &devlist, &devcount);
4143 if (devcount != 0) {
4144 unchanged = malloc(devcount * sizeof(device_t), M_TEMP,
4146 if (unchanged == NULL) {
4147 free(devlist, M_TEMP);
4153 domain = pcib_get_domain(dev);
4154 busno = pcib_get_bus(dev);
4155 maxslots = PCIB_MAXSLOTS(pcib);
4156 for (s = 0; s <= maxslots; s++) {
4157 /* If function 0 is not present, skip to the next slot. */
4159 if (REG(PCIR_VENDOR, 2) == 0xffff)
4162 hdrtype = REG(PCIR_HDRTYPE, 1);
4163 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
4165 if (hdrtype & PCIM_MFDEV)
4166 pcifunchigh = PCIB_MAXFUNCS(pcib);
4167 for (f = 0; f <= pcifunchigh; f++) {
4168 if (REG(PCIR_VENDOR, 2) == 0xffff)
4172 * Found a valid function. Check if a
4173 * device_t for this device already exists.
4175 for (i = 0; i < devcount; i++) {
4179 if (pci_get_slot(child) == s &&
4180 pci_get_function(child) == f) {
4181 unchanged[i] = child;
4186 pci_identify_function(pcib, dev, domain, busno, s, f);
4191 /* Remove devices that are no longer present. */
4192 for (i = 0; i < devcount; i++) {
4193 if (unchanged[i] != NULL)
4195 device_delete_child(dev, devlist[i]);
4198 free(devlist, M_TEMP);
4199 oldcount = devcount;
4201 /* Try to attach the devices just added. */
4202 error = device_get_children(dev, &devlist, &devcount);
4204 free(unchanged, M_TEMP);
4208 for (i = 0; i < devcount; i++) {
4209 for (j = 0; j < oldcount; j++) {
4210 if (devlist[i] == unchanged[j])
4214 device_probe_and_attach(devlist[i]);
4218 free(unchanged, M_TEMP);
4219 free(devlist, M_TEMP);
4226 pci_add_iov_child(device_t bus, device_t pf, uint16_t rid, uint16_t vid,
4229 struct pci_devinfo *vf_dinfo;
4231 int busno, slot, func;
4233 pcib = device_get_parent(bus);
4235 PCIB_DECODE_RID(pcib, rid, &busno, &slot, &func);
4237 vf_dinfo = pci_fill_devinfo(pcib, bus, pci_get_domain(pcib), busno,
4238 slot, func, vid, did);
4240 vf_dinfo->cfg.flags |= PCICFG_VF;
4241 pci_add_child(bus, vf_dinfo);
4243 return (vf_dinfo->cfg.dev);
4247 pci_create_iov_child_method(device_t bus, device_t pf, uint16_t rid,
4248 uint16_t vid, uint16_t did)
4251 return (pci_add_iov_child(bus, pf, rid, vid, did));
4256 pci_add_child_clear_aer(device_t dev, struct pci_devinfo *dinfo)
4262 if (dinfo->cfg.pcie.pcie_location != 0 &&
4263 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) {
4264 r2 = pci_read_config(dev, dinfo->cfg.pcie.pcie_location +
4266 r2 &= ~(PCIEM_ROOT_CTL_SERR_CORR |
4267 PCIEM_ROOT_CTL_SERR_NONFATAL | PCIEM_ROOT_CTL_SERR_FATAL);
4268 pci_write_config(dev, dinfo->cfg.pcie.pcie_location +
4269 PCIER_ROOT_CTL, r2, 2);
4271 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) {
4272 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4);
4273 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4);
4274 if (r != 0 && bootverbose) {
4275 pci_printf(&dinfo->cfg,
4276 "clearing AER UC 0x%08x -> 0x%08x\n",
4277 r, pci_read_config(dev, aer + PCIR_AER_UC_STATUS,
4281 r = pci_read_config(dev, aer + PCIR_AER_UC_MASK, 4);
4282 r &= ~(PCIM_AER_UC_TRAINING_ERROR |
4283 PCIM_AER_UC_DL_PROTOCOL_ERROR |
4284 PCIM_AER_UC_SURPRISE_LINK_DOWN |
4285 PCIM_AER_UC_POISONED_TLP |
4286 PCIM_AER_UC_FC_PROTOCOL_ERROR |
4287 PCIM_AER_UC_COMPLETION_TIMEOUT |
4288 PCIM_AER_UC_COMPLETER_ABORT |
4289 PCIM_AER_UC_UNEXPECTED_COMPLETION |
4290 PCIM_AER_UC_RECEIVER_OVERFLOW |
4291 PCIM_AER_UC_MALFORMED_TLP |
4292 PCIM_AER_UC_ECRC_ERROR |
4293 PCIM_AER_UC_UNSUPPORTED_REQUEST |
4294 PCIM_AER_UC_ACS_VIOLATION |
4295 PCIM_AER_UC_INTERNAL_ERROR |
4296 PCIM_AER_UC_MC_BLOCKED_TLP |
4297 PCIM_AER_UC_ATOMIC_EGRESS_BLK |
4298 PCIM_AER_UC_TLP_PREFIX_BLOCKED);
4299 pci_write_config(dev, aer + PCIR_AER_UC_MASK, r, 4);
4301 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4);
4302 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4);
4303 if (r != 0 && bootverbose) {
4304 pci_printf(&dinfo->cfg,
4305 "clearing AER COR 0x%08x -> 0x%08x\n",
4306 r, pci_read_config(dev, aer + PCIR_AER_COR_STATUS,
4310 r = pci_read_config(dev, aer + PCIR_AER_COR_MASK, 4);
4311 r &= ~(PCIM_AER_COR_RECEIVER_ERROR |
4312 PCIM_AER_COR_BAD_TLP |
4313 PCIM_AER_COR_BAD_DLLP |
4314 PCIM_AER_COR_REPLAY_ROLLOVER |
4315 PCIM_AER_COR_REPLAY_TIMEOUT |
4316 PCIM_AER_COR_ADVISORY_NF_ERROR |
4317 PCIM_AER_COR_INTERNAL_ERROR |
4318 PCIM_AER_COR_HEADER_LOG_OVFLOW);
4319 pci_write_config(dev, aer + PCIR_AER_COR_MASK, r, 4);
4321 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location +
4322 PCIER_DEVICE_CTL, 2);
4323 r |= PCIEM_CTL_COR_ENABLE | PCIEM_CTL_NFER_ENABLE |
4324 PCIEM_CTL_FER_ENABLE | PCIEM_CTL_URR_ENABLE;
4325 pci_write_config(dev, dinfo->cfg.pcie.pcie_location +
4326 PCIER_DEVICE_CTL, r, 2);
4331 pci_add_child(device_t bus, struct pci_devinfo *dinfo)
4335 dinfo->cfg.dev = dev = device_add_child(bus, NULL, -1);
4336 device_set_ivars(dev, dinfo);
4337 resource_list_init(&dinfo->resources);
4338 pci_cfg_save(dev, dinfo, 0);
4339 pci_cfg_restore(dev, dinfo);
4340 pci_print_verbose(dinfo);
4341 pci_add_resources(bus, dev, 0, 0);
4342 pci_child_added(dinfo->cfg.dev);
4344 if (pci_clear_aer_on_attach)
4345 pci_add_child_clear_aer(dev, dinfo);
4347 EVENTHANDLER_INVOKE(pci_add_device, dinfo->cfg.dev);
4351 pci_child_added_method(device_t dev, device_t child)
4357 pci_probe(device_t dev)
4360 device_set_desc(dev, "PCI bus");
4362 /* Allow other subclasses to override this driver. */
4363 return (BUS_PROBE_GENERIC);
4367 pci_attach_common(device_t dev)
4369 struct pci_softc *sc;
4375 sc = device_get_softc(dev);
4376 domain = pcib_get_domain(dev);
4377 busno = pcib_get_bus(dev);
4380 sc->sc_bus = bus_alloc_resource(dev, PCI_RES_BUS, &rid, busno, busno,
4382 if (sc->sc_bus == NULL) {
4383 device_printf(dev, "failed to allocate bus number\n");
4388 device_printf(dev, "domain=%d, physical bus=%d\n",
4390 sc->sc_dma_tag = bus_get_dma_tag(dev);
4395 pci_attach(device_t dev)
4397 int busno, domain, error;
4399 error = pci_attach_common(dev);
4404 * Since there can be multiple independently numbered PCI
4405 * buses on systems with multiple PCI domains, we can't use
4406 * the unit number to decide which bus we are probing. We ask
4407 * the parent pcib what our domain and bus numbers are.
4409 domain = pcib_get_domain(dev);
4410 busno = pcib_get_bus(dev);
4411 pci_add_children(dev, domain, busno);
4412 return (bus_generic_attach(dev));
4416 pci_detach(device_t dev)
4419 struct pci_softc *sc;
4423 error = bus_generic_detach(dev);
4427 sc = device_get_softc(dev);
4428 error = bus_release_resource(dev, PCI_RES_BUS, 0, sc->sc_bus);
4432 return (device_delete_children(dev));
4436 pci_hint_device_unit(device_t dev, device_t child, const char *name, int *unitp)
4440 char me1[24], me2[32];
4444 d = pci_get_domain(child);
4445 b = pci_get_bus(child);
4446 s = pci_get_slot(child);
4447 f = pci_get_function(child);
4448 snprintf(me1, sizeof(me1), "pci%u:%u:%u", b, s, f);
4449 snprintf(me2, sizeof(me2), "pci%u:%u:%u:%u", d, b, s, f);
4451 while (resource_find_dev(&line, name, &unit, "at", NULL) == 0) {
4452 resource_string_value(name, unit, "at", &at);
4453 if (strcmp(at, me1) != 0 && strcmp(at, me2) != 0)
4454 continue; /* No match, try next candidate */
4461 pci_set_power_child(device_t dev, device_t child, int state)
4467 * Set the device to the given state. If the firmware suggests
4468 * a different power state, use it instead. If power management
4469 * is not present, the firmware is responsible for managing
4470 * device power. Skip children who aren't attached since they
4471 * are handled separately.
4473 pcib = device_get_parent(dev);
4475 if (device_is_attached(child) &&
4476 PCIB_POWER_FOR_SLEEP(pcib, child, &dstate) == 0)
4477 pci_set_powerstate(child, dstate);
4481 pci_suspend_child(device_t dev, device_t child)
4483 struct pci_devinfo *dinfo;
4484 struct resource_list_entry *rle;
4487 dinfo = device_get_ivars(child);
4490 * Save the PCI configuration space for the child and set the
4491 * device in the appropriate power state for this sleep state.
4493 pci_cfg_save(child, dinfo, 0);
4495 /* Suspend devices before potentially powering them down. */
4496 error = bus_generic_suspend_child(dev, child);
4501 if (pci_do_power_suspend) {
4503 * Make sure this device's interrupt handler is not invoked
4504 * in the case the device uses a shared interrupt that can
4505 * be raised by some other device.
4506 * This is applicable only to regular (legacy) PCI interrupts
4507 * as MSI/MSI-X interrupts are never shared.
4509 rle = resource_list_find(&dinfo->resources,
4511 if (rle != NULL && rle->res != NULL)
4512 (void)bus_suspend_intr(child, rle->res);
4513 pci_set_power_child(dev, child, PCI_POWERSTATE_D3);
4520 pci_resume_child(device_t dev, device_t child)
4522 struct pci_devinfo *dinfo;
4523 struct resource_list_entry *rle;
4525 if (pci_do_power_resume)
4526 pci_set_power_child(dev, child, PCI_POWERSTATE_D0);
4528 dinfo = device_get_ivars(child);
4529 pci_cfg_restore(child, dinfo);
4530 if (!device_is_attached(child))
4531 pci_cfg_save(child, dinfo, 1);
4533 bus_generic_resume_child(dev, child);
4536 * Allow interrupts only after fully resuming the driver and hardware.
4538 if (pci_do_power_suspend) {
4539 /* See pci_suspend_child for details. */
4540 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
4541 if (rle != NULL && rle->res != NULL)
4542 (void)bus_resume_intr(child, rle->res);
4549 pci_resume(device_t dev)
4551 device_t child, *devlist;
4552 int error, i, numdevs;
4554 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0)
4558 * Resume critical devices first, then everything else later.
4560 for (i = 0; i < numdevs; i++) {
4562 switch (pci_get_class(child)) {
4566 case PCIC_BASEPERIPH:
4567 BUS_RESUME_CHILD(dev, child);
4571 for (i = 0; i < numdevs; i++) {
4573 switch (pci_get_class(child)) {
4577 case PCIC_BASEPERIPH:
4580 BUS_RESUME_CHILD(dev, child);
4583 free(devlist, M_TEMP);
4588 pci_load_vendor_data(void)
4594 data = preload_search_by_type("pci_vendor_data");
4596 ptr = preload_fetch_addr(data);
4597 sz = preload_fetch_size(data);
4598 if (ptr != NULL && sz != 0) {
4599 pci_vendordata = ptr;
4600 pci_vendordata_size = sz;
4601 /* terminate the database */
4602 pci_vendordata[pci_vendordata_size] = '\n';
4608 pci_driver_added(device_t dev, driver_t *driver)
4613 struct pci_devinfo *dinfo;
4617 device_printf(dev, "driver added\n");
4618 DEVICE_IDENTIFY(driver, dev);
4619 if (device_get_children(dev, &devlist, &numdevs) != 0)
4621 for (i = 0; i < numdevs; i++) {
4623 if (device_get_state(child) != DS_NOTPRESENT)
4625 dinfo = device_get_ivars(child);
4626 pci_print_verbose(dinfo);
4628 pci_printf(&dinfo->cfg, "reprobing on driver added\n");
4629 pci_cfg_restore(child, dinfo);
4630 if (device_probe_and_attach(child) != 0)
4631 pci_child_detached(dev, child);
4633 free(devlist, M_TEMP);
4637 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
4638 driver_filter_t *filter, driver_intr_t *intr, void *arg, void **cookiep)
4640 struct pci_devinfo *dinfo;
4641 struct msix_table_entry *mte;
4642 struct msix_vector *mv;
4648 error = bus_generic_setup_intr(dev, child, irq, flags, filter, intr,
4653 /* If this is not a direct child, just bail out. */
4654 if (device_get_parent(child) != dev) {
4659 rid = rman_get_rid(irq);
4661 /* Make sure that INTx is enabled */
4662 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
4665 * Check to see if the interrupt is MSI or MSI-X.
4666 * Ask our parent to map the MSI and give
4667 * us the address and data register values.
4668 * If we fail for some reason, teardown the
4669 * interrupt handler.
4671 dinfo = device_get_ivars(child);
4672 if (dinfo->cfg.msi.msi_alloc > 0) {
4673 if (dinfo->cfg.msi.msi_addr == 0) {
4674 KASSERT(dinfo->cfg.msi.msi_handlers == 0,
4675 ("MSI has handlers, but vectors not mapped"));
4676 error = PCIB_MAP_MSI(device_get_parent(dev),
4677 child, rman_get_start(irq), &addr, &data);
4680 dinfo->cfg.msi.msi_addr = addr;
4681 dinfo->cfg.msi.msi_data = data;
4683 if (dinfo->cfg.msi.msi_handlers == 0)
4684 pci_enable_msi(child, dinfo->cfg.msi.msi_addr,
4685 dinfo->cfg.msi.msi_data);
4686 dinfo->cfg.msi.msi_handlers++;
4688 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
4689 ("No MSI or MSI-X interrupts allocated"));
4690 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
4691 ("MSI-X index too high"));
4692 mte = &dinfo->cfg.msix.msix_table[rid - 1];
4693 KASSERT(mte->mte_vector != 0, ("no message vector"));
4694 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1];
4695 KASSERT(mv->mv_irq == rman_get_start(irq),
4697 if (mv->mv_address == 0) {
4698 KASSERT(mte->mte_handlers == 0,
4699 ("MSI-X table entry has handlers, but vector not mapped"));
4700 error = PCIB_MAP_MSI(device_get_parent(dev),
4701 child, rman_get_start(irq), &addr, &data);
4704 mv->mv_address = addr;
4709 * The MSIX table entry must be made valid by
4710 * incrementing the mte_handlers before
4711 * calling pci_enable_msix() and
4712 * pci_resume_msix(). Else the MSIX rewrite
4713 * table quirk will not work as expected.
4715 mte->mte_handlers++;
4716 if (mte->mte_handlers == 1) {
4717 pci_enable_msix(child, rid - 1, mv->mv_address,
4719 pci_unmask_msix(child, rid - 1);
4724 * Make sure that INTx is disabled if we are using MSI/MSI-X,
4725 * unless the device is affected by PCI_QUIRK_MSI_INTX_BUG,
4726 * in which case we "enable" INTx so MSI/MSI-X actually works.
4728 if (!pci_has_quirk(pci_get_devid(child),
4729 PCI_QUIRK_MSI_INTX_BUG))
4730 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
4732 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
4735 (void)bus_generic_teardown_intr(dev, child, irq,
4745 pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
4748 struct msix_table_entry *mte;
4749 struct resource_list_entry *rle;
4750 struct pci_devinfo *dinfo;
4753 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE))
4756 /* If this isn't a direct child, just bail out */
4757 if (device_get_parent(child) != dev)
4758 return(bus_generic_teardown_intr(dev, child, irq, cookie));
4760 rid = rman_get_rid(irq);
4763 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
4766 * Check to see if the interrupt is MSI or MSI-X. If so,
4767 * decrement the appropriate handlers count and mask the
4768 * MSI-X message, or disable MSI messages if the count
4771 dinfo = device_get_ivars(child);
4772 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
4773 if (rle->res != irq)
4775 if (dinfo->cfg.msi.msi_alloc > 0) {
4776 KASSERT(rid <= dinfo->cfg.msi.msi_alloc,
4777 ("MSI-X index too high"));
4778 if (dinfo->cfg.msi.msi_handlers == 0)
4780 dinfo->cfg.msi.msi_handlers--;
4781 if (dinfo->cfg.msi.msi_handlers == 0)
4782 pci_disable_msi(child);
4784 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
4785 ("No MSI or MSI-X interrupts allocated"));
4786 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
4787 ("MSI-X index too high"));
4788 mte = &dinfo->cfg.msix.msix_table[rid - 1];
4789 if (mte->mte_handlers == 0)
4791 mte->mte_handlers--;
4792 if (mte->mte_handlers == 0)
4793 pci_mask_msix(child, rid - 1);
4796 error = bus_generic_teardown_intr(dev, child, irq, cookie);
4799 ("%s: generic teardown failed for MSI/MSI-X", __func__));
4804 pci_print_child(device_t dev, device_t child)
4806 struct pci_devinfo *dinfo;
4807 struct resource_list *rl;
4810 dinfo = device_get_ivars(child);
4811 rl = &dinfo->resources;
4813 retval += bus_print_child_header(dev, child);
4815 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#jx");
4816 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx");
4817 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd");
4818 if (device_get_flags(dev))
4819 retval += printf(" flags %#x", device_get_flags(dev));
4821 retval += printf(" at device %d.%d", pci_get_slot(child),
4822 pci_get_function(child));
4824 retval += bus_print_child_domain(dev, child);
4825 retval += bus_print_child_footer(dev, child);
4834 int report; /* 0 = bootverbose, 1 = always */
4836 } pci_nomatch_tab[] = {
4837 {PCIC_OLD, -1, 1, "old"},
4838 {PCIC_OLD, PCIS_OLD_NONVGA, 1, "non-VGA display device"},
4839 {PCIC_OLD, PCIS_OLD_VGA, 1, "VGA-compatible display device"},
4840 {PCIC_STORAGE, -1, 1, "mass storage"},
4841 {PCIC_STORAGE, PCIS_STORAGE_SCSI, 1, "SCSI"},
4842 {PCIC_STORAGE, PCIS_STORAGE_IDE, 1, "ATA"},
4843 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, 1, "floppy disk"},
4844 {PCIC_STORAGE, PCIS_STORAGE_IPI, 1, "IPI"},
4845 {PCIC_STORAGE, PCIS_STORAGE_RAID, 1, "RAID"},
4846 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, 1, "ATA (ADMA)"},
4847 {PCIC_STORAGE, PCIS_STORAGE_SATA, 1, "SATA"},
4848 {PCIC_STORAGE, PCIS_STORAGE_SAS, 1, "SAS"},
4849 {PCIC_STORAGE, PCIS_STORAGE_NVM, 1, "NVM"},
4850 {PCIC_NETWORK, -1, 1, "network"},
4851 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, 1, "ethernet"},
4852 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, 1, "token ring"},
4853 {PCIC_NETWORK, PCIS_NETWORK_FDDI, 1, "fddi"},
4854 {PCIC_NETWORK, PCIS_NETWORK_ATM, 1, "ATM"},
4855 {PCIC_NETWORK, PCIS_NETWORK_ISDN, 1, "ISDN"},
4856 {PCIC_DISPLAY, -1, 1, "display"},
4857 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, 1, "VGA"},
4858 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, 1, "XGA"},
4859 {PCIC_DISPLAY, PCIS_DISPLAY_3D, 1, "3D"},
4860 {PCIC_MULTIMEDIA, -1, 1, "multimedia"},
4861 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, 1, "video"},
4862 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, 1, "audio"},
4863 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, 1, "telephony"},
4864 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, 1, "HDA"},
4865 {PCIC_MEMORY, -1, 1, "memory"},
4866 {PCIC_MEMORY, PCIS_MEMORY_RAM, 1, "RAM"},
4867 {PCIC_MEMORY, PCIS_MEMORY_FLASH, 1, "flash"},
4868 {PCIC_BRIDGE, -1, 1, "bridge"},
4869 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, 1, "HOST-PCI"},
4870 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, 1, "PCI-ISA"},
4871 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, 1, "PCI-EISA"},
4872 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, 1, "PCI-MCA"},
4873 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, 1, "PCI-PCI"},
4874 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, 1, "PCI-PCMCIA"},
4875 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, 1, "PCI-NuBus"},
4876 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, 1, "PCI-CardBus"},
4877 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, 1, "PCI-RACEway"},
4878 {PCIC_SIMPLECOMM, -1, 1, "simple comms"},
4879 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, 1, "UART"}, /* could detect 16550 */
4880 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, 1, "parallel port"},
4881 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, 1, "multiport serial"},
4882 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, 1, "generic modem"},
4883 {PCIC_BASEPERIPH, -1, 0, "base peripheral"},
4884 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, 1, "interrupt controller"},
4885 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, 1, "DMA controller"},
4886 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, 1, "timer"},
4887 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, 1, "realtime clock"},
4888 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, 1, "PCI hot-plug controller"},
4889 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, 1, "SD host controller"},
4890 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_IOMMU, 1, "IOMMU"},
4891 {PCIC_INPUTDEV, -1, 1, "input device"},
4892 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, 1, "keyboard"},
4893 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,1, "digitizer"},
4894 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, 1, "mouse"},
4895 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, 1, "scanner"},
4896 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, 1, "gameport"},
4897 {PCIC_DOCKING, -1, 1, "docking station"},
4898 {PCIC_PROCESSOR, -1, 1, "processor"},
4899 {PCIC_SERIALBUS, -1, 1, "serial bus"},
4900 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, 1, "FireWire"},
4901 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, 1, "AccessBus"},
4902 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, 1, "SSA"},
4903 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, 1, "USB"},
4904 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, 1, "Fibre Channel"},
4905 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, 0, "SMBus"},
4906 {PCIC_WIRELESS, -1, 1, "wireless controller"},
4907 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, 1, "iRDA"},
4908 {PCIC_WIRELESS, PCIS_WIRELESS_IR, 1, "IR"},
4909 {PCIC_WIRELESS, PCIS_WIRELESS_RF, 1, "RF"},
4910 {PCIC_INTELLIIO, -1, 1, "intelligent I/O controller"},
4911 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, 1, "I2O"},
4912 {PCIC_SATCOM, -1, 1, "satellite communication"},
4913 {PCIC_SATCOM, PCIS_SATCOM_TV, 1, "sat TV"},
4914 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, 1, "sat audio"},
4915 {PCIC_SATCOM, PCIS_SATCOM_VOICE, 1, "sat voice"},
4916 {PCIC_SATCOM, PCIS_SATCOM_DATA, 1, "sat data"},
4917 {PCIC_CRYPTO, -1, 1, "encrypt/decrypt"},
4918 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, 1, "network/computer crypto"},
4919 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, 1, "entertainment crypto"},
4920 {PCIC_DASP, -1, 0, "dasp"},
4921 {PCIC_DASP, PCIS_DASP_DPIO, 1, "DPIO module"},
4922 {PCIC_DASP, PCIS_DASP_PERFCNTRS, 1, "performance counters"},
4923 {PCIC_DASP, PCIS_DASP_COMM_SYNC, 1, "communication synchronizer"},
4924 {PCIC_DASP, PCIS_DASP_MGMT_CARD, 1, "signal processing management"},
4929 pci_probe_nomatch(device_t dev, device_t child)
4932 const char *cp, *scp;
4936 * Look for a listing for this device in a loaded device database.
4939 if ((device = pci_describe_device(child)) != NULL) {
4940 device_printf(dev, "<%s>", device);
4941 free(device, M_DEVBUF);
4944 * Scan the class/subclass descriptions for a general
4949 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) {
4950 if (pci_nomatch_tab[i].class == pci_get_class(child)) {
4951 if (pci_nomatch_tab[i].subclass == -1) {
4952 cp = pci_nomatch_tab[i].desc;
4953 report = pci_nomatch_tab[i].report;
4954 } else if (pci_nomatch_tab[i].subclass ==
4955 pci_get_subclass(child)) {
4956 scp = pci_nomatch_tab[i].desc;
4957 report = pci_nomatch_tab[i].report;
4961 if (report || bootverbose) {
4962 device_printf(dev, "<%s%s%s>",
4964 ((cp != NULL) && (scp != NULL)) ? ", " : "",
4968 if (report || bootverbose) {
4969 printf(" at device %d.%d (no driver attached)\n",
4970 pci_get_slot(child), pci_get_function(child));
4972 pci_cfg_save(child, device_get_ivars(child), 1);
4976 pci_child_detached(device_t dev, device_t child)
4978 struct pci_devinfo *dinfo;
4979 struct resource_list *rl;
4981 dinfo = device_get_ivars(child);
4982 rl = &dinfo->resources;
4985 * Have to deallocate IRQs before releasing any MSI messages and
4986 * have to release MSI messages before deallocating any memory
4989 if (resource_list_release_active(rl, dev, child, SYS_RES_IRQ) != 0)
4990 pci_printf(&dinfo->cfg, "Device leaked IRQ resources\n");
4991 if (dinfo->cfg.msi.msi_alloc != 0 || dinfo->cfg.msix.msix_alloc != 0) {
4992 pci_printf(&dinfo->cfg, "Device leaked MSI vectors\n");
4993 (void)pci_release_msi(child);
4995 if (resource_list_release_active(rl, dev, child, SYS_RES_MEMORY) != 0)
4996 pci_printf(&dinfo->cfg, "Device leaked memory resources\n");
4997 if (resource_list_release_active(rl, dev, child, SYS_RES_IOPORT) != 0)
4998 pci_printf(&dinfo->cfg, "Device leaked I/O resources\n");
5000 if (resource_list_release_active(rl, dev, child, PCI_RES_BUS) != 0)
5001 pci_printf(&dinfo->cfg, "Device leaked PCI bus numbers\n");
5004 pci_cfg_save(child, dinfo, 1);
5008 * Parse the PCI device database, if loaded, and return a pointer to a
5009 * description of the device.
5011 * The database is flat text formatted as follows:
5013 * Any line not in a valid format is ignored.
5014 * Lines are terminated with newline '\n' characters.
5016 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then
5019 * A DEVICE line is entered immediately below the corresponding VENDOR ID.
5020 * - devices cannot be listed without a corresponding VENDOR line.
5021 * A DEVICE line consists of a TAB, the 4 digit (hex) device code,
5022 * another TAB, then the device name.
5026 * Assuming (ptr) points to the beginning of a line in the database,
5027 * return the vendor or device and description of the next entry.
5028 * The value of (vendor) or (device) inappropriate for the entry type
5029 * is set to -1. Returns nonzero at the end of the database.
5031 * Note that this is slightly unrobust in the face of corrupt data;
5032 * we attempt to safeguard against this by spamming the end of the
5033 * database with a newline when we initialise.
5036 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc)
5045 left = pci_vendordata_size - (cp - pci_vendordata);
5053 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2)
5057 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2)
5060 /* skip to next line */
5061 while (*cp != '\n' && left > 0) {
5070 /* skip to next line */
5071 while (*cp != '\n' && left > 0) {
5075 if (*cp == '\n' && left > 0)
5082 pci_describe_device(device_t dev)
5085 char *desc, *vp, *dp, *line;
5087 desc = vp = dp = NULL;
5090 * If we have no vendor data, we can't do anything.
5092 if (pci_vendordata == NULL)
5096 * Scan the vendor data looking for this device
5098 line = pci_vendordata;
5099 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
5102 if (pci_describe_parse_line(&line, &vendor, &device, &vp))
5104 if (vendor == pci_get_vendor(dev))
5107 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
5110 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) {
5118 if (device == pci_get_device(dev))
5122 snprintf(dp, 80, "0x%x", pci_get_device(dev));
5123 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) !=
5125 sprintf(desc, "%s, %s", vp, dp);
5135 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
5137 struct pci_devinfo *dinfo;
5140 dinfo = device_get_ivars(child);
5144 case PCI_IVAR_ETHADDR:
5146 * The generic accessor doesn't deal with failure, so
5147 * we set the return value, then return an error.
5149 *((uint8_t **) result) = NULL;
5151 case PCI_IVAR_SUBVENDOR:
5152 *result = cfg->subvendor;
5154 case PCI_IVAR_SUBDEVICE:
5155 *result = cfg->subdevice;
5157 case PCI_IVAR_VENDOR:
5158 *result = cfg->vendor;
5160 case PCI_IVAR_DEVICE:
5161 *result = cfg->device;
5163 case PCI_IVAR_DEVID:
5164 *result = (cfg->device << 16) | cfg->vendor;
5166 case PCI_IVAR_CLASS:
5167 *result = cfg->baseclass;
5169 case PCI_IVAR_SUBCLASS:
5170 *result = cfg->subclass;
5172 case PCI_IVAR_PROGIF:
5173 *result = cfg->progif;
5175 case PCI_IVAR_REVID:
5176 *result = cfg->revid;
5178 case PCI_IVAR_INTPIN:
5179 *result = cfg->intpin;
5182 *result = cfg->intline;
5184 case PCI_IVAR_DOMAIN:
5185 *result = cfg->domain;
5191 *result = cfg->slot;
5193 case PCI_IVAR_FUNCTION:
5194 *result = cfg->func;
5196 case PCI_IVAR_CMDREG:
5197 *result = cfg->cmdreg;
5199 case PCI_IVAR_CACHELNSZ:
5200 *result = cfg->cachelnsz;
5202 case PCI_IVAR_MINGNT:
5203 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) {
5207 *result = cfg->mingnt;
5209 case PCI_IVAR_MAXLAT:
5210 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) {
5214 *result = cfg->maxlat;
5216 case PCI_IVAR_LATTIMER:
5217 *result = cfg->lattimer;
5226 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
5228 struct pci_devinfo *dinfo;
5230 dinfo = device_get_ivars(child);
5233 case PCI_IVAR_INTPIN:
5234 dinfo->cfg.intpin = value;
5236 case PCI_IVAR_ETHADDR:
5237 case PCI_IVAR_SUBVENDOR:
5238 case PCI_IVAR_SUBDEVICE:
5239 case PCI_IVAR_VENDOR:
5240 case PCI_IVAR_DEVICE:
5241 case PCI_IVAR_DEVID:
5242 case PCI_IVAR_CLASS:
5243 case PCI_IVAR_SUBCLASS:
5244 case PCI_IVAR_PROGIF:
5245 case PCI_IVAR_REVID:
5247 case PCI_IVAR_DOMAIN:
5250 case PCI_IVAR_FUNCTION:
5251 return (EINVAL); /* disallow for now */
5258 #include "opt_ddb.h"
5260 #include <ddb/ddb.h>
5261 #include <sys/cons.h>
5264 * List resources based on pci map registers, used for within ddb
5267 DB_SHOW_COMMAND(pciregs, db_pci_dump)
5269 struct pci_devinfo *dinfo;
5270 struct devlist *devlist_head;
5273 int i, error, none_count;
5276 /* get the head of the device queue */
5277 devlist_head = &pci_devq;
5280 * Go through the list of devices and print out devices
5282 for (error = 0, i = 0,
5283 dinfo = STAILQ_FIRST(devlist_head);
5284 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit;
5285 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
5286 /* Populate pd_name and pd_unit */
5289 name = device_get_name(dinfo->cfg.dev);
5292 db_printf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x "
5293 "chip=0x%08x rev=0x%02x hdr=0x%02x\n",
5294 (name && *name) ? name : "none",
5295 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
5297 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev,
5298 p->pc_sel.pc_func, (p->pc_class << 16) |
5299 (p->pc_subclass << 8) | p->pc_progif,
5300 (p->pc_subdevice << 16) | p->pc_subvendor,
5301 (p->pc_device << 16) | p->pc_vendor,
5302 p->pc_revid, p->pc_hdr);
5307 static struct resource *
5308 pci_reserve_map(device_t dev, device_t child, int type, int *rid,
5309 rman_res_t start, rman_res_t end, rman_res_t count, u_int num,
5312 struct pci_devinfo *dinfo = device_get_ivars(child);
5313 struct resource_list *rl = &dinfo->resources;
5314 struct resource *res;
5317 pci_addr_t map, testval;
5322 /* If rid is managed by EA, ignore it */
5323 if (pci_ea_is_enabled(child, *rid))
5326 pm = pci_find_bar(child, *rid);
5328 /* This is a BAR that we failed to allocate earlier. */
5329 mapsize = pm->pm_size;
5333 * Weed out the bogons, and figure out how large the
5334 * BAR/map is. BARs that read back 0 here are bogus
5335 * and unimplemented. Note: atapci in legacy mode are
5336 * special and handled elsewhere in the code. If you
5337 * have a atapci device in legacy mode and it fails
5338 * here, that other code is broken.
5340 pci_read_bar(child, *rid, &map, &testval, NULL);
5343 * Determine the size of the BAR and ignore BARs with a size
5344 * of 0. Device ROM BARs use a different mask value.
5346 if (PCIR_IS_BIOS(&dinfo->cfg, *rid))
5347 mapsize = pci_romsize(testval);
5349 mapsize = pci_mapsize(testval);
5352 pm = pci_add_bar(child, *rid, map, mapsize);
5355 if (PCI_BAR_MEM(map) || PCIR_IS_BIOS(&dinfo->cfg, *rid)) {
5356 if (type != SYS_RES_MEMORY) {
5359 "child %s requested type %d for rid %#x,"
5360 " but the BAR says it is an memio\n",
5361 device_get_nameunit(child), type, *rid);
5365 if (type != SYS_RES_IOPORT) {
5368 "child %s requested type %d for rid %#x,"
5369 " but the BAR says it is an ioport\n",
5370 device_get_nameunit(child), type, *rid);
5376 * For real BARs, we need to override the size that
5377 * the driver requests, because that's what the BAR
5378 * actually uses and we would otherwise have a
5379 * situation where we might allocate the excess to
5380 * another driver, which won't work.
5382 count = ((pci_addr_t)1 << mapsize) * num;
5383 if (RF_ALIGNMENT(flags) < mapsize)
5384 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
5385 if (PCI_BAR_MEM(map) && (map & PCIM_BAR_MEM_PREFETCH))
5386 flags |= RF_PREFETCHABLE;
5389 * Allocate enough resource, and then write back the
5390 * appropriate BAR for that resource.
5392 resource_list_add(rl, type, *rid, start, end, count);
5393 res = resource_list_reserve(rl, dev, child, type, rid, start, end,
5394 count, flags & ~RF_ACTIVE);
5396 resource_list_delete(rl, type, *rid);
5397 device_printf(child,
5398 "%#jx bytes of rid %#x res %d failed (%#jx, %#jx).\n",
5399 count, *rid, type, start, end);
5403 device_printf(child,
5404 "Lazy allocation of %#jx bytes rid %#x type %d at %#jx\n",
5405 count, *rid, type, rman_get_start(res));
5407 /* Disable decoding via the CMD register before updating the BAR */
5408 cmd = pci_read_config(child, PCIR_COMMAND, 2);
5409 pci_write_config(child, PCIR_COMMAND,
5410 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2);
5412 map = rman_get_start(res);
5413 pci_write_bar(child, pm, map);
5415 /* Restore the original value of the CMD register */
5416 pci_write_config(child, PCIR_COMMAND, cmd, 2);
5422 pci_alloc_multi_resource(device_t dev, device_t child, int type, int *rid,
5423 rman_res_t start, rman_res_t end, rman_res_t count, u_long num,
5426 struct pci_devinfo *dinfo;
5427 struct resource_list *rl;
5428 struct resource_list_entry *rle;
5429 struct resource *res;
5433 * Perform lazy resource allocation
5435 dinfo = device_get_ivars(child);
5436 rl = &dinfo->resources;
5439 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
5441 return (pci_alloc_secbus(dev, child, rid, start, end, count,
5446 * Can't alloc legacy interrupt once MSI messages have
5449 if (*rid == 0 && (cfg->msi.msi_alloc > 0 ||
5450 cfg->msix.msix_alloc > 0))
5454 * If the child device doesn't have an interrupt
5455 * routed and is deserving of an interrupt, try to
5458 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) &&
5460 pci_assign_interrupt(dev, child, 0);
5462 case SYS_RES_IOPORT:
5463 case SYS_RES_MEMORY:
5466 * PCI-PCI bridge I/O window resources are not BARs.
5467 * For those allocations just pass the request up the
5470 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE) {
5472 case PCIR_IOBASEL_1:
5473 case PCIR_MEMBASE_1:
5474 case PCIR_PMBASEL_1:
5476 * XXX: Should we bother creating a resource
5479 return (bus_generic_alloc_resource(dev, child,
5480 type, rid, start, end, count, flags));
5484 /* Reserve resources for this BAR if needed. */
5485 rle = resource_list_find(rl, type, *rid);
5487 res = pci_reserve_map(dev, child, type, rid, start, end,
5493 return (resource_list_alloc(rl, dev, child, type, rid,
5494 start, end, count, flags));
5498 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
5499 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
5502 struct pci_devinfo *dinfo;
5505 if (device_get_parent(child) != dev)
5506 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
5507 type, rid, start, end, count, flags));
5510 dinfo = device_get_ivars(child);
5511 if (dinfo->cfg.flags & PCICFG_VF) {
5513 /* VFs can't have I/O BARs. */
5514 case SYS_RES_IOPORT:
5516 case SYS_RES_MEMORY:
5517 return (pci_vf_alloc_mem_resource(dev, child, rid,
5518 start, end, count, flags));
5521 /* Fall through for other types of resource allocations. */
5525 return (pci_alloc_multi_resource(dev, child, type, rid, start, end,
5530 pci_release_resource(device_t dev, device_t child, int type, int rid,
5533 struct pci_devinfo *dinfo;
5534 struct resource_list *rl;
5537 if (device_get_parent(child) != dev)
5538 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
5541 dinfo = device_get_ivars(child);
5545 if (dinfo->cfg.flags & PCICFG_VF) {
5547 /* VFs can't have I/O BARs. */
5548 case SYS_RES_IOPORT:
5550 case SYS_RES_MEMORY:
5551 return (pci_vf_release_mem_resource(dev, child, rid,
5555 /* Fall through for other types of resource allocations. */
5561 * PCI-PCI bridge I/O window resources are not BARs. For
5562 * those allocations just pass the request up the tree.
5564 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE &&
5565 (type == SYS_RES_IOPORT || type == SYS_RES_MEMORY)) {
5567 case PCIR_IOBASEL_1:
5568 case PCIR_MEMBASE_1:
5569 case PCIR_PMBASEL_1:
5570 return (bus_generic_release_resource(dev, child, type,
5576 rl = &dinfo->resources;
5577 return (resource_list_release(rl, dev, child, type, rid, r));
5581 pci_activate_resource(device_t dev, device_t child, int type, int rid,
5584 struct pci_devinfo *dinfo;
5587 error = bus_generic_activate_resource(dev, child, type, rid, r);
5591 /* Enable decoding in the command register when activating BARs. */
5592 if (device_get_parent(child) == dev) {
5593 /* Device ROMs need their decoding explicitly enabled. */
5594 dinfo = device_get_ivars(child);
5595 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid))
5596 pci_write_bar(child, pci_find_bar(child, rid),
5597 rman_get_start(r) | PCIM_BIOS_ENABLE);
5599 case SYS_RES_IOPORT:
5600 case SYS_RES_MEMORY:
5601 error = PCI_ENABLE_IO(dev, child, type);
5609 pci_deactivate_resource(device_t dev, device_t child, int type,
5610 int rid, struct resource *r)
5612 struct pci_devinfo *dinfo;
5615 error = bus_generic_deactivate_resource(dev, child, type, rid, r);
5619 /* Disable decoding for device ROMs. */
5620 if (device_get_parent(child) == dev) {
5621 dinfo = device_get_ivars(child);
5622 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid))
5623 pci_write_bar(child, pci_find_bar(child, rid),
5630 pci_child_deleted(device_t dev, device_t child)
5632 struct resource_list_entry *rle;
5633 struct resource_list *rl;
5634 struct pci_devinfo *dinfo;
5636 dinfo = device_get_ivars(child);
5637 rl = &dinfo->resources;
5639 EVENTHANDLER_INVOKE(pci_delete_device, child);
5641 /* Turn off access to resources we're about to free */
5642 if (bus_child_present(child) != 0) {
5643 pci_write_config(child, PCIR_COMMAND, pci_read_config(child,
5644 PCIR_COMMAND, 2) & ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN), 2);
5646 pci_disable_busmaster(child);
5649 /* Free all allocated resources */
5650 STAILQ_FOREACH(rle, rl, link) {
5652 if (rman_get_flags(rle->res) & RF_ACTIVE ||
5653 resource_list_busy(rl, rle->type, rle->rid)) {
5654 pci_printf(&dinfo->cfg,
5655 "Resource still owned, oops. "
5656 "(type=%d, rid=%d, addr=%lx)\n",
5657 rle->type, rle->rid,
5658 rman_get_start(rle->res));
5659 bus_release_resource(child, rle->type, rle->rid,
5662 resource_list_unreserve(rl, dev, child, rle->type,
5666 resource_list_free(rl);
5672 pci_delete_resource(device_t dev, device_t child, int type, int rid)
5674 struct pci_devinfo *dinfo;
5675 struct resource_list *rl;
5676 struct resource_list_entry *rle;
5678 if (device_get_parent(child) != dev)
5681 dinfo = device_get_ivars(child);
5682 rl = &dinfo->resources;
5683 rle = resource_list_find(rl, type, rid);
5688 if (rman_get_flags(rle->res) & RF_ACTIVE ||
5689 resource_list_busy(rl, type, rid)) {
5690 device_printf(dev, "delete_resource: "
5691 "Resource still owned by child, oops. "
5692 "(type=%d, rid=%d, addr=%jx)\n",
5693 type, rid, rman_get_start(rle->res));
5696 resource_list_unreserve(rl, dev, child, type, rid);
5698 resource_list_delete(rl, type, rid);
5701 struct resource_list *
5702 pci_get_resource_list (device_t dev, device_t child)
5704 struct pci_devinfo *dinfo = device_get_ivars(child);
5706 return (&dinfo->resources);
5711 pci_get_dma_tag(device_t bus, device_t dev)
5714 struct pci_softc *sc;
5716 if (device_get_parent(dev) == bus) {
5717 /* try iommu and return if it works */
5718 tag = iommu_get_dma_tag(bus, dev);
5722 sc = device_get_softc(bus);
5723 tag = sc->sc_dma_tag;
5729 pci_get_dma_tag(device_t bus, device_t dev)
5731 struct pci_softc *sc = device_get_softc(bus);
5733 return (sc->sc_dma_tag);
5738 pci_read_config_method(device_t dev, device_t child, int reg, int width)
5740 struct pci_devinfo *dinfo = device_get_ivars(child);
5741 pcicfgregs *cfg = &dinfo->cfg;
5745 * SR-IOV VFs don't implement the VID or DID registers, so we have to
5746 * emulate them here.
5748 if (cfg->flags & PCICFG_VF) {
5749 if (reg == PCIR_VENDOR) {
5752 return (cfg->device << 16 | cfg->vendor);
5754 return (cfg->vendor);
5756 return (cfg->vendor & 0xff);
5758 return (0xffffffff);
5760 } else if (reg == PCIR_DEVICE) {
5762 /* Note that an unaligned 4-byte read is an error. */
5764 return (cfg->device);
5766 return (cfg->device & 0xff);
5768 return (0xffffffff);
5774 return (PCIB_READ_CONFIG(device_get_parent(dev),
5775 cfg->bus, cfg->slot, cfg->func, reg, width));
5779 pci_write_config_method(device_t dev, device_t child, int reg,
5780 uint32_t val, int width)
5782 struct pci_devinfo *dinfo = device_get_ivars(child);
5783 pcicfgregs *cfg = &dinfo->cfg;
5785 PCIB_WRITE_CONFIG(device_get_parent(dev),
5786 cfg->bus, cfg->slot, cfg->func, reg, val, width);
5790 pci_child_location_str_method(device_t dev, device_t child, char *buf,
5794 snprintf(buf, buflen, "slot=%d function=%d dbsf=pci%d:%d:%d:%d",
5795 pci_get_slot(child), pci_get_function(child), pci_get_domain(child),
5796 pci_get_bus(child), pci_get_slot(child), pci_get_function(child));
5801 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
5804 struct pci_devinfo *dinfo;
5807 dinfo = device_get_ivars(child);
5809 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
5810 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
5811 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
5817 pci_assign_interrupt_method(device_t dev, device_t child)
5819 struct pci_devinfo *dinfo = device_get_ivars(child);
5820 pcicfgregs *cfg = &dinfo->cfg;
5822 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
5827 pci_lookup(void *arg, const char *name, device_t *dev)
5831 int domain, bus, slot, func;
5837 * Accept pciconf-style selectors of either pciD:B:S:F or
5838 * pciB:S:F. In the latter case, the domain is assumed to
5841 if (strncmp(name, "pci", 3) != 0)
5843 val = strtol(name + 3, &end, 10);
5844 if (val < 0 || val > INT_MAX || *end != ':')
5847 val = strtol(end + 1, &end, 10);
5848 if (val < 0 || val > INT_MAX || *end != ':')
5851 val = strtol(end + 1, &end, 10);
5852 if (val < 0 || val > INT_MAX)
5856 val = strtol(end + 1, &end, 10);
5857 if (val < 0 || val > INT_MAX || *end != '\0')
5860 } else if (*end == '\0') {
5868 if (domain > PCI_DOMAINMAX || bus > PCI_BUSMAX || slot > PCI_SLOTMAX ||
5869 func > PCIE_ARI_FUNCMAX || (slot != 0 && func > PCI_FUNCMAX))
5872 *dev = pci_find_dbsf(domain, bus, slot, func);
5876 pci_modevent(module_t mod, int what, void *arg)
5878 static struct cdev *pci_cdev;
5879 static eventhandler_tag tag;
5883 STAILQ_INIT(&pci_devq);
5885 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644,
5887 pci_load_vendor_data();
5888 tag = EVENTHANDLER_REGISTER(dev_lookup, pci_lookup, NULL,
5894 EVENTHANDLER_DEREGISTER(dev_lookup, tag);
5895 destroy_dev(pci_cdev);
5903 pci_cfg_restore_pcie(device_t dev, struct pci_devinfo *dinfo)
5905 #define WREG(n, v) pci_write_config(dev, pos + (n), (v), 2)
5906 struct pcicfg_pcie *cfg;
5909 cfg = &dinfo->cfg.pcie;
5910 pos = cfg->pcie_location;
5912 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION;
5914 WREG(PCIER_DEVICE_CTL, cfg->pcie_device_ctl);
5916 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
5917 cfg->pcie_type == PCIEM_TYPE_ENDPOINT ||
5918 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT)
5919 WREG(PCIER_LINK_CTL, cfg->pcie_link_ctl);
5921 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
5922 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT &&
5923 (cfg->pcie_flags & PCIEM_FLAGS_SLOT))))
5924 WREG(PCIER_SLOT_CTL, cfg->pcie_slot_ctl);
5926 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
5927 cfg->pcie_type == PCIEM_TYPE_ROOT_EC)
5928 WREG(PCIER_ROOT_CTL, cfg->pcie_root_ctl);
5931 WREG(PCIER_DEVICE_CTL2, cfg->pcie_device_ctl2);
5932 WREG(PCIER_LINK_CTL2, cfg->pcie_link_ctl2);
5933 WREG(PCIER_SLOT_CTL2, cfg->pcie_slot_ctl2);
5939 pci_cfg_restore_pcix(device_t dev, struct pci_devinfo *dinfo)
5941 pci_write_config(dev, dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND,
5942 dinfo->cfg.pcix.pcix_command, 2);
5946 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
5950 * Restore the device to full power mode. We must do this
5951 * before we restore the registers because moving from D3 to
5952 * D0 will cause the chip's BARs and some other registers to
5953 * be reset to some unknown power on reset values. Cut down
5954 * the noise on boot by doing nothing if we are already in
5957 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0)
5958 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
5959 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
5960 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
5961 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
5962 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
5963 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
5964 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
5965 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) {
5966 case PCIM_HDRTYPE_NORMAL:
5967 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
5968 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
5970 case PCIM_HDRTYPE_BRIDGE:
5971 pci_write_config(dev, PCIR_SECLAT_1,
5972 dinfo->cfg.bridge.br_seclat, 1);
5973 pci_write_config(dev, PCIR_SUBBUS_1,
5974 dinfo->cfg.bridge.br_subbus, 1);
5975 pci_write_config(dev, PCIR_SECBUS_1,
5976 dinfo->cfg.bridge.br_secbus, 1);
5977 pci_write_config(dev, PCIR_PRIBUS_1,
5978 dinfo->cfg.bridge.br_pribus, 1);
5979 pci_write_config(dev, PCIR_BRIDGECTL_1,
5980 dinfo->cfg.bridge.br_control, 2);
5982 case PCIM_HDRTYPE_CARDBUS:
5983 pci_write_config(dev, PCIR_SECLAT_2,
5984 dinfo->cfg.bridge.br_seclat, 1);
5985 pci_write_config(dev, PCIR_SUBBUS_2,
5986 dinfo->cfg.bridge.br_subbus, 1);
5987 pci_write_config(dev, PCIR_SECBUS_2,
5988 dinfo->cfg.bridge.br_secbus, 1);
5989 pci_write_config(dev, PCIR_PRIBUS_2,
5990 dinfo->cfg.bridge.br_pribus, 1);
5991 pci_write_config(dev, PCIR_BRIDGECTL_2,
5992 dinfo->cfg.bridge.br_control, 2);
5995 pci_restore_bars(dev);
5997 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_BRIDGE)
5998 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
6001 * Restore extended capabilities for PCI-Express and PCI-X
6003 if (dinfo->cfg.pcie.pcie_location != 0)
6004 pci_cfg_restore_pcie(dev, dinfo);
6005 if (dinfo->cfg.pcix.pcix_location != 0)
6006 pci_cfg_restore_pcix(dev, dinfo);
6008 /* Restore MSI and MSI-X configurations if they are present. */
6009 if (dinfo->cfg.msi.msi_location != 0)
6010 pci_resume_msi(dev);
6011 if (dinfo->cfg.msix.msix_location != 0)
6012 pci_resume_msix(dev);
6015 if (dinfo->cfg.iov != NULL)
6016 pci_iov_cfg_restore(dev, dinfo);
6021 pci_cfg_save_pcie(device_t dev, struct pci_devinfo *dinfo)
6023 #define RREG(n) pci_read_config(dev, pos + (n), 2)
6024 struct pcicfg_pcie *cfg;
6027 cfg = &dinfo->cfg.pcie;
6028 pos = cfg->pcie_location;
6030 cfg->pcie_flags = RREG(PCIER_FLAGS);
6032 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION;
6034 cfg->pcie_device_ctl = RREG(PCIER_DEVICE_CTL);
6036 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
6037 cfg->pcie_type == PCIEM_TYPE_ENDPOINT ||
6038 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT)
6039 cfg->pcie_link_ctl = RREG(PCIER_LINK_CTL);
6041 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
6042 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT &&
6043 (cfg->pcie_flags & PCIEM_FLAGS_SLOT))))
6044 cfg->pcie_slot_ctl = RREG(PCIER_SLOT_CTL);
6046 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
6047 cfg->pcie_type == PCIEM_TYPE_ROOT_EC)
6048 cfg->pcie_root_ctl = RREG(PCIER_ROOT_CTL);
6051 cfg->pcie_device_ctl2 = RREG(PCIER_DEVICE_CTL2);
6052 cfg->pcie_link_ctl2 = RREG(PCIER_LINK_CTL2);
6053 cfg->pcie_slot_ctl2 = RREG(PCIER_SLOT_CTL2);
6059 pci_cfg_save_pcix(device_t dev, struct pci_devinfo *dinfo)
6061 dinfo->cfg.pcix.pcix_command = pci_read_config(dev,
6062 dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 2);
6066 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
6072 * Some drivers apparently write to these registers w/o updating our
6073 * cached copy. No harm happens if we update the copy, so do so here
6074 * so we can restore them. The COMMAND register is modified by the
6075 * bus w/o updating the cache. This should represent the normally
6076 * writable portion of the 'defined' part of type 0/1/2 headers.
6078 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
6079 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
6080 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
6081 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
6082 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
6083 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
6084 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
6085 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
6086 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
6087 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
6088 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
6089 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) {
6090 case PCIM_HDRTYPE_NORMAL:
6091 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
6092 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
6093 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
6094 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
6096 case PCIM_HDRTYPE_BRIDGE:
6097 dinfo->cfg.bridge.br_seclat = pci_read_config(dev,
6099 dinfo->cfg.bridge.br_subbus = pci_read_config(dev,
6101 dinfo->cfg.bridge.br_secbus = pci_read_config(dev,
6103 dinfo->cfg.bridge.br_pribus = pci_read_config(dev,
6105 dinfo->cfg.bridge.br_control = pci_read_config(dev,
6106 PCIR_BRIDGECTL_1, 2);
6108 case PCIM_HDRTYPE_CARDBUS:
6109 dinfo->cfg.bridge.br_seclat = pci_read_config(dev,
6111 dinfo->cfg.bridge.br_subbus = pci_read_config(dev,
6113 dinfo->cfg.bridge.br_secbus = pci_read_config(dev,
6115 dinfo->cfg.bridge.br_pribus = pci_read_config(dev,
6117 dinfo->cfg.bridge.br_control = pci_read_config(dev,
6118 PCIR_BRIDGECTL_2, 2);
6119 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_2, 2);
6120 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_2, 2);
6124 if (dinfo->cfg.pcie.pcie_location != 0)
6125 pci_cfg_save_pcie(dev, dinfo);
6127 if (dinfo->cfg.pcix.pcix_location != 0)
6128 pci_cfg_save_pcix(dev, dinfo);
6131 if (dinfo->cfg.iov != NULL)
6132 pci_iov_cfg_save(dev, dinfo);
6136 * don't set the state for display devices, base peripherals and
6137 * memory devices since bad things happen when they are powered down.
6138 * We should (a) have drivers that can easily detach and (b) use
6139 * generic drivers for these devices so that some device actually
6140 * attaches. We need to make sure that when we implement (a) we don't
6141 * power the device down on a reattach.
6143 cls = pci_get_class(dev);
6146 switch (pci_do_power_nodriver)
6148 case 0: /* NO powerdown at all */
6150 case 1: /* Conservative about what to power down */
6151 if (cls == PCIC_STORAGE)
6154 case 2: /* Aggressive about what to power down */
6155 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY ||
6156 cls == PCIC_BASEPERIPH)
6159 case 3: /* Power down everything */
6163 * PCI spec says we can only go into D3 state from D0 state.
6164 * Transition from D[12] into D0 before going to D3 state.
6166 ps = pci_get_powerstate(dev);
6167 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
6168 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
6169 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
6170 pci_set_powerstate(dev, PCI_POWERSTATE_D3);
6173 /* Wrapper APIs suitable for device driver use. */
6175 pci_save_state(device_t dev)
6177 struct pci_devinfo *dinfo;
6179 dinfo = device_get_ivars(dev);
6180 pci_cfg_save(dev, dinfo, 0);
6184 pci_restore_state(device_t dev)
6186 struct pci_devinfo *dinfo;
6188 dinfo = device_get_ivars(dev);
6189 pci_cfg_restore(dev, dinfo);
6193 pci_get_id_method(device_t dev, device_t child, enum pci_id_type type,
6197 return (PCIB_GET_ID(device_get_parent(dev), child, type, id));
6200 /* Find the upstream port of a given PCI device in a root complex. */
6202 pci_find_pcie_root_port(device_t dev)
6204 struct pci_devinfo *dinfo;
6205 devclass_t pci_class;
6208 pci_class = devclass_find("pci");
6209 KASSERT(device_get_devclass(device_get_parent(dev)) == pci_class,
6210 ("%s: non-pci device %s", __func__, device_get_nameunit(dev)));
6213 * Walk the bridge hierarchy until we find a PCI-e root
6214 * port or a non-PCI device.
6217 bus = device_get_parent(dev);
6218 KASSERT(bus != NULL, ("%s: null parent of %s", __func__,
6219 device_get_nameunit(dev)));
6221 pcib = device_get_parent(bus);
6222 KASSERT(pcib != NULL, ("%s: null bridge of %s", __func__,
6223 device_get_nameunit(bus)));
6226 * pcib's parent must be a PCI bus for this to be a
6229 if (device_get_devclass(device_get_parent(pcib)) != pci_class)
6232 dinfo = device_get_ivars(pcib);
6233 if (dinfo->cfg.pcie.pcie_location != 0 &&
6234 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT)
6242 * Wait for pending transactions to complete on a PCI-express function.
6244 * The maximum delay is specified in milliseconds in max_delay. Note
6245 * that this function may sleep.
6247 * Returns true if the function is idle and false if the timeout is
6248 * exceeded. If dev is not a PCI-express function, this returns true.
6251 pcie_wait_for_pending_transactions(device_t dev, u_int max_delay)
6253 struct pci_devinfo *dinfo = device_get_ivars(dev);
6257 cap = dinfo->cfg.pcie.pcie_location;
6261 sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2);
6262 while (sta & PCIEM_STA_TRANSACTION_PND) {
6266 /* Poll once every 100 milliseconds up to the timeout. */
6267 if (max_delay > 100) {
6268 pause_sbt("pcietp", 100 * SBT_1MS, 0, C_HARDCLOCK);
6271 pause_sbt("pcietp", max_delay * SBT_1MS, 0,
6275 sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2);
6282 * Determine the maximum Completion Timeout in microseconds.
6284 * For non-PCI-express functions this returns 0.
6287 pcie_get_max_completion_timeout(device_t dev)
6289 struct pci_devinfo *dinfo = device_get_ivars(dev);
6292 cap = dinfo->cfg.pcie.pcie_location;
6297 * Functions using the 1.x spec use the default timeout range of
6298 * 50 microseconds to 50 milliseconds. Functions that do not
6299 * support programmable timeouts also use this range.
6301 if ((dinfo->cfg.pcie.pcie_flags & PCIEM_FLAGS_VERSION) < 2 ||
6302 (pci_read_config(dev, cap + PCIER_DEVICE_CAP2, 4) &
6303 PCIEM_CAP2_COMP_TIMO_RANGES) == 0)
6306 switch (pci_read_config(dev, cap + PCIER_DEVICE_CTL2, 2) &
6307 PCIEM_CTL2_COMP_TIMO_VAL) {
6308 case PCIEM_CTL2_COMP_TIMO_100US:
6310 case PCIEM_CTL2_COMP_TIMO_10MS:
6312 case PCIEM_CTL2_COMP_TIMO_55MS:
6314 case PCIEM_CTL2_COMP_TIMO_210MS:
6315 return (210 * 1000);
6316 case PCIEM_CTL2_COMP_TIMO_900MS:
6317 return (900 * 1000);
6318 case PCIEM_CTL2_COMP_TIMO_3500MS:
6319 return (3500 * 1000);
6320 case PCIEM_CTL2_COMP_TIMO_13S:
6321 return (13 * 1000 * 1000);
6322 case PCIEM_CTL2_COMP_TIMO_64S:
6323 return (64 * 1000 * 1000);
6330 pcie_apei_error(device_t dev, int sev, uint8_t *aerp)
6332 struct pci_devinfo *dinfo = device_get_ivars(dev);
6338 if (sev == PCIEM_STA_CORRECTABLE_ERROR)
6340 else if (sev == PCIEM_STA_NON_FATAL_ERROR)
6341 s = "Uncorrectable (Non-Fatal)";
6343 s = "Uncorrectable (Fatal)";
6344 device_printf(dev, "%s PCIe error reported by APEI\n", s);
6346 if (sev == PCIEM_STA_CORRECTABLE_ERROR) {
6347 r = le32dec(aerp + PCIR_AER_COR_STATUS);
6348 r1 = le32dec(aerp + PCIR_AER_COR_MASK);
6350 r = le32dec(aerp + PCIR_AER_UC_STATUS);
6351 r1 = le32dec(aerp + PCIR_AER_UC_MASK);
6353 device_printf(dev, "status 0x%08x mask 0x%08x", r, r1);
6354 if (sev != PCIEM_STA_CORRECTABLE_ERROR) {
6355 r = le32dec(aerp + PCIR_AER_UC_SEVERITY);
6356 rs = le16dec(aerp + PCIR_AER_CAP_CONTROL);
6357 printf(" severity 0x%08x first %d\n",
6363 /* As kind of recovery just report and clear the error statuses. */
6364 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) {
6365 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4);
6367 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4);
6368 device_printf(dev, "Clearing UC AER errors 0x%08x\n", r);
6371 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4);
6373 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4);
6374 device_printf(dev, "Clearing COR AER errors 0x%08x\n", r);
6377 if (dinfo->cfg.pcie.pcie_location != 0) {
6378 rs = pci_read_config(dev, dinfo->cfg.pcie.pcie_location +
6379 PCIER_DEVICE_STA, 2);
6380 if ((rs & (PCIEM_STA_CORRECTABLE_ERROR |
6381 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR |
6382 PCIEM_STA_UNSUPPORTED_REQ)) != 0) {
6383 pci_write_config(dev, dinfo->cfg.pcie.pcie_location +
6384 PCIER_DEVICE_STA, rs, 2);
6385 device_printf(dev, "Clearing PCIe errors 0x%04x\n", rs);
6391 * Perform a Function Level Reset (FLR) on a device.
6393 * This function first waits for any pending transactions to complete
6394 * within the timeout specified by max_delay. If transactions are
6395 * still pending, the function will return false without attempting a
6398 * If dev is not a PCI-express function or does not support FLR, this
6399 * function returns false.
6401 * Note that no registers are saved or restored. The caller is
6402 * responsible for saving and restoring any registers including
6403 * PCI-standard registers via pci_save_state() and
6404 * pci_restore_state().
6407 pcie_flr(device_t dev, u_int max_delay, bool force)
6409 struct pci_devinfo *dinfo = device_get_ivars(dev);
6414 cap = dinfo->cfg.pcie.pcie_location;
6418 if (!(pci_read_config(dev, cap + PCIER_DEVICE_CAP, 4) & PCIEM_CAP_FLR))
6422 * Disable busmastering to prevent generation of new
6423 * transactions while waiting for the device to go idle. If
6424 * the idle timeout fails, the command register is restored
6425 * which will re-enable busmastering.
6427 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
6428 pci_write_config(dev, PCIR_COMMAND, cmd & ~(PCIM_CMD_BUSMASTEREN), 2);
6429 if (!pcie_wait_for_pending_transactions(dev, max_delay)) {
6431 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
6434 pci_printf(&dinfo->cfg,
6435 "Resetting with transactions pending after %d ms\n",
6439 * Extend the post-FLR delay to cover the maximum
6440 * Completion Timeout delay of anything in flight
6441 * during the FLR delay. Enforce a minimum delay of
6444 compl_delay = pcie_get_max_completion_timeout(dev) / 1000;
6445 if (compl_delay < 10)
6450 /* Initiate the reset. */
6451 ctl = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2);
6452 pci_write_config(dev, cap + PCIER_DEVICE_CTL, ctl |
6453 PCIEM_CTL_INITIATE_FLR, 2);
6455 /* Wait for 100ms. */
6456 pause_sbt("pcieflr", (100 + compl_delay) * SBT_1MS, 0, C_HARDCLOCK);
6458 if (pci_read_config(dev, cap + PCIER_DEVICE_STA, 2) &
6459 PCIEM_STA_TRANSACTION_PND)
6460 pci_printf(&dinfo->cfg, "Transactions pending after FLR!\n");
6465 * Attempt a power-management reset by cycling the device in/out of D3
6466 * state. PCI spec says we can only go into D3 state from D0 state.
6467 * Transition from D[12] into D0 before going to D3 state.
6470 pci_power_reset(device_t dev)
6474 ps = pci_get_powerstate(dev);
6475 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
6476 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
6477 pci_set_powerstate(dev, PCI_POWERSTATE_D3);
6478 pci_set_powerstate(dev, ps);
6483 * Try link drop and retrain of the downstream port of upstream
6484 * switch, for PCIe. According to the PCIe 3.0 spec 6.6.1, this must
6485 * cause Conventional Hot reset of the device in the slot.
6486 * Alternative, for PCIe, could be the secondary bus reset initiatied
6487 * on the upstream switch PCIR_BRIDGECTL_1, bit 6.
6490 pcie_link_reset(device_t port, int pcie_location)
6494 v = pci_read_config(port, pcie_location + PCIER_LINK_CTL, 2);
6495 v |= PCIEM_LINK_CTL_LINK_DIS;
6496 pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2);
6497 pause_sbt("pcier1", mstosbt(20), 0, 0);
6498 v &= ~PCIEM_LINK_CTL_LINK_DIS;
6499 v |= PCIEM_LINK_CTL_RETRAIN_LINK;
6500 pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2);
6501 pause_sbt("pcier2", mstosbt(100), 0, 0); /* 100 ms */
6502 v = pci_read_config(port, pcie_location + PCIER_LINK_STA, 2);
6503 return ((v & PCIEM_LINK_STA_TRAINING) != 0 ? ETIMEDOUT : 0);
6507 pci_reset_post(device_t dev, device_t child)
6510 if (dev == device_get_parent(child))
6511 pci_restore_state(child);
6516 pci_reset_prepare(device_t dev, device_t child)
6519 if (dev == device_get_parent(child))
6520 pci_save_state(child);
6525 pci_reset_child(device_t dev, device_t child, int flags)
6529 if (dev == NULL || device_get_parent(child) != dev)
6531 if ((flags & DEVF_RESET_DETACH) != 0) {
6532 error = device_get_state(child) == DS_ATTACHED ?
6533 device_detach(child) : 0;
6535 error = BUS_SUSPEND_CHILD(dev, child);
6538 if (!pcie_flr(child, 1000, false)) {
6539 error = BUS_RESET_PREPARE(dev, child);
6541 pci_power_reset(child);
6542 BUS_RESET_POST(dev, child);
6544 if ((flags & DEVF_RESET_DETACH) != 0)
6545 device_probe_and_attach(child);
6547 BUS_RESUME_CHILD(dev, child);
6552 const struct pci_device_table *
6553 pci_match_device(device_t child, const struct pci_device_table *id, size_t nelt)
6556 uint16_t vendor, device, subvendor, subdevice, class, subclass, revid;
6558 vendor = pci_get_vendor(child);
6559 device = pci_get_device(child);
6560 subvendor = pci_get_subvendor(child);
6561 subdevice = pci_get_subdevice(child);
6562 class = pci_get_class(child);
6563 subclass = pci_get_subclass(child);
6564 revid = pci_get_revid(child);
6565 while (nelt-- > 0) {
6567 if (id->match_flag_vendor)
6568 match &= vendor == id->vendor;
6569 if (id->match_flag_device)
6570 match &= device == id->device;
6571 if (id->match_flag_subvendor)
6572 match &= subvendor == id->subvendor;
6573 if (id->match_flag_subdevice)
6574 match &= subdevice == id->subdevice;
6575 if (id->match_flag_class)
6576 match &= class == id->class_id;
6577 if (id->match_flag_subclass)
6578 match &= subclass == id->subclass;
6579 if (id->match_flag_revid)
6580 match &= revid == id->revid;
6589 pci_print_faulted_dev_name(const struct pci_devinfo *dinfo)
6591 const char *dev_name;
6594 dev = dinfo->cfg.dev;
6595 printf("pci%d:%d:%d:%d", dinfo->cfg.domain, dinfo->cfg.bus,
6596 dinfo->cfg.slot, dinfo->cfg.func);
6597 dev_name = device_get_name(dev);
6598 if (dev_name != NULL)
6599 printf(" (%s%d)", dev_name, device_get_unit(dev));
6603 pci_print_faulted_dev(void)
6605 struct pci_devinfo *dinfo;
6611 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
6612 dev = dinfo->cfg.dev;
6613 status = pci_read_config(dev, PCIR_STATUS, 2);
6614 status &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT |
6615 PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT |
6616 PCIM_STATUS_SERR | PCIM_STATUS_PERR;
6618 pci_print_faulted_dev_name(dinfo);
6619 printf(" error 0x%04x\n", status);
6621 if (dinfo->cfg.pcie.pcie_location != 0) {
6622 status = pci_read_config(dev,
6623 dinfo->cfg.pcie.pcie_location +
6624 PCIER_DEVICE_STA, 2);
6625 if ((status & (PCIEM_STA_CORRECTABLE_ERROR |
6626 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR |
6627 PCIEM_STA_UNSUPPORTED_REQ)) != 0) {
6628 pci_print_faulted_dev_name(dinfo);
6629 printf(" PCIe DEVCTL 0x%04x DEVSTA 0x%04x\n",
6630 pci_read_config(dev,
6631 dinfo->cfg.pcie.pcie_location +
6632 PCIER_DEVICE_CTL, 2),
6636 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) {
6637 r1 = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4);
6638 r2 = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4);
6639 if (r1 != 0 || r2 != 0) {
6640 pci_print_faulted_dev_name(dinfo);
6641 printf(" AER UC 0x%08x Mask 0x%08x Svr 0x%08x\n"
6642 " COR 0x%08x Mask 0x%08x Ctl 0x%08x\n",
6643 r1, pci_read_config(dev, aer +
6644 PCIR_AER_UC_MASK, 4),
6645 pci_read_config(dev, aer +
6646 PCIR_AER_UC_SEVERITY, 4),
6647 r2, pci_read_config(dev, aer +
6648 PCIR_AER_COR_MASK, 4),
6649 pci_read_config(dev, aer +
6650 PCIR_AER_CAP_CONTROL, 4));
6651 for (i = 0; i < 4; i++) {
6652 r1 = pci_read_config(dev, aer +
6653 PCIR_AER_HEADER_LOG + i * 4, 4);
6654 printf(" HL%d: 0x%08x\n", i, r1);
6662 DB_SHOW_COMMAND(pcierr, pci_print_faulted_dev_db)
6665 pci_print_faulted_dev();
6669 db_clear_pcie_errors(const struct pci_devinfo *dinfo)
6675 dev = dinfo->cfg.dev;
6676 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location +
6677 PCIER_DEVICE_STA, 2);
6678 pci_write_config(dev, dinfo->cfg.pcie.pcie_location +
6679 PCIER_DEVICE_STA, r, 2);
6681 if (pci_find_extcap(dev, PCIZ_AER, &aer) != 0)
6683 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4);
6685 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4);
6686 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4);
6688 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4);
6691 DB_COMMAND(pci_clearerr, db_pci_clearerr)
6693 struct pci_devinfo *dinfo;
6695 uint16_t status, status1;
6697 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
6698 dev = dinfo->cfg.dev;
6699 status1 = status = pci_read_config(dev, PCIR_STATUS, 2);
6700 status1 &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT |
6701 PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT |
6702 PCIM_STATUS_SERR | PCIM_STATUS_PERR;
6705 pci_write_config(dev, PCIR_STATUS, status, 2);
6707 if (dinfo->cfg.pcie.pcie_location != 0)
6708 db_clear_pcie_errors(dinfo);