2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000, BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/linker.h>
39 #include <sys/fcntl.h>
41 #include <sys/kernel.h>
42 #include <sys/queue.h>
43 #include <sys/sysctl.h>
44 #include <sys/endian.h>
48 #include <vm/vm_extern.h>
51 #include <machine/bus.h>
53 #include <machine/resource.h>
55 #include <sys/pciio.h>
56 #include <dev/pci/pcireg.h>
57 #include <dev/pci/pcivar.h>
58 #include <dev/pci/pci_private.h>
64 #include <contrib/dev/acpica/acpi.h>
67 #define ACPI_PWR_FOR_SLEEP(x, y, z)
70 static uint32_t pci_mapbase(unsigned mapreg);
71 static int pci_maptype(unsigned mapreg);
72 static int pci_mapsize(unsigned testval);
73 static int pci_maprange(unsigned mapreg);
74 static void pci_fixancient(pcicfgregs *cfg);
76 static int pci_porten(device_t pcib, int b, int s, int f);
77 static int pci_memen(device_t pcib, int b, int s, int f);
78 static void pci_assign_interrupt(device_t bus, device_t dev,
80 static int pci_add_map(device_t pcib, device_t bus, device_t dev,
81 int b, int s, int f, int reg,
82 struct resource_list *rl, int force, int prefetch);
83 static int pci_probe(device_t dev);
84 static int pci_attach(device_t dev);
85 static void pci_load_vendor_data(void);
86 static int pci_describe_parse_line(char **ptr, int *vendor,
87 int *device, char **desc);
88 static char *pci_describe_device(device_t dev);
89 static int pci_modevent(module_t mod, int what, void *arg);
90 static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
92 static void pci_read_extcap(device_t pcib, pcicfgregs *cfg);
93 static uint32_t pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg,
96 static void pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg,
97 int reg, uint32_t data);
99 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg);
101 static device_method_t pci_methods[] = {
102 /* Device interface */
103 DEVMETHOD(device_probe, pci_probe),
104 DEVMETHOD(device_attach, pci_attach),
105 DEVMETHOD(device_detach, bus_generic_detach),
106 DEVMETHOD(device_shutdown, bus_generic_shutdown),
107 DEVMETHOD(device_suspend, pci_suspend),
108 DEVMETHOD(device_resume, pci_resume),
111 DEVMETHOD(bus_print_child, pci_print_child),
112 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
113 DEVMETHOD(bus_read_ivar, pci_read_ivar),
114 DEVMETHOD(bus_write_ivar, pci_write_ivar),
115 DEVMETHOD(bus_driver_added, pci_driver_added),
116 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
117 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
119 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
120 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
121 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
122 DEVMETHOD(bus_delete_resource, pci_delete_resource),
123 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
124 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
125 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
126 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
127 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
128 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
131 DEVMETHOD(pci_read_config, pci_read_config_method),
132 DEVMETHOD(pci_write_config, pci_write_config_method),
133 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
134 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
135 DEVMETHOD(pci_enable_io, pci_enable_io_method),
136 DEVMETHOD(pci_disable_io, pci_disable_io_method),
137 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method),
138 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method),
139 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
140 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
141 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
142 DEVMETHOD(pci_find_extcap, pci_find_extcap_method),
147 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0);
149 static devclass_t pci_devclass;
150 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
151 MODULE_VERSION(pci, 1);
153 static char *pci_vendordata;
154 static size_t pci_vendordata_size;
158 uint32_t devid; /* Vendor/device of the card */
160 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
165 struct pci_quirk pci_quirks[] = {
166 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */
167 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
168 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
169 /* As does the Serverworks OSB4 (the SMBus mapping register) */
170 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
175 /* map register information */
176 #define PCI_MAPMEM 0x01 /* memory map */
177 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
178 #define PCI_MAPPORT 0x04 /* port map */
180 struct devlist pci_devq;
181 uint32_t pci_generation;
182 uint32_t pci_numdevs = 0;
185 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters");
187 static int pci_enable_io_modes = 1;
188 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes);
189 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW,
190 &pci_enable_io_modes, 1,
191 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\
192 enable these bits correctly. We'd like to do this all the time, but there\n\
193 are some peripherals that this causes problems with.");
195 static int pci_do_power_nodriver = 0;
196 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver);
197 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW,
198 &pci_do_power_nodriver, 0,
199 "Place a function into D3 state when no driver attaches to it. 0 means\n\
200 disable. 1 means conservatively place devices into D3 state. 2 means\n\
201 agressively place devices into D3 state. 3 means put absolutely everything\n\
204 static int pci_do_power_resume = 1;
205 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume);
206 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW,
207 &pci_do_power_resume, 1,
208 "Transition from D3 -> D0 on resume.");
210 /* Find a device_t by bus/slot/function */
213 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
215 struct pci_devinfo *dinfo;
217 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
218 if ((dinfo->cfg.bus == bus) &&
219 (dinfo->cfg.slot == slot) &&
220 (dinfo->cfg.func == func)) {
221 return (dinfo->cfg.dev);
228 /* Find a device_t by vendor/device ID */
231 pci_find_device(uint16_t vendor, uint16_t device)
233 struct pci_devinfo *dinfo;
235 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
236 if ((dinfo->cfg.vendor == vendor) &&
237 (dinfo->cfg.device == device)) {
238 return (dinfo->cfg.dev);
245 /* return base address of memory or port map */
248 pci_mapbase(uint32_t mapreg)
251 if ((mapreg & 0x01) == 0)
253 return (mapreg & ~mask);
256 /* return map type of memory or port map */
259 pci_maptype(unsigned mapreg)
261 static uint8_t maptype[0x10] = {
262 PCI_MAPMEM, PCI_MAPPORT,
264 PCI_MAPMEM, PCI_MAPPORT,
266 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
267 PCI_MAPMEM|PCI_MAPMEMP, 0,
268 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
272 return maptype[mapreg & 0x0f];
275 /* return log2 of map size decoded for memory or port map */
278 pci_mapsize(uint32_t testval)
282 testval = pci_mapbase(testval);
285 while ((testval & 1) == 0)
294 /* return log2 of address range supported by map register */
297 pci_maprange(unsigned mapreg)
300 switch (mapreg & 0x07) {
316 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
319 pci_fixancient(pcicfgregs *cfg)
321 if (cfg->hdrtype != 0)
324 /* PCI to PCI bridges use header type 1 */
325 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
329 /* extract header type specific config data */
332 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
334 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
335 switch (cfg->hdrtype) {
337 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
338 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
339 cfg->nummaps = PCI_MAXMAPS_0;
342 cfg->subvendor = REG(PCIR_SUBVEND_1, 2);
343 cfg->subdevice = REG(PCIR_SUBDEV_1, 2);
344 cfg->nummaps = PCI_MAXMAPS_1;
347 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
348 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
349 cfg->nummaps = PCI_MAXMAPS_2;
355 /* read configuration header into pcicfgregs structure */
357 pci_read_device(device_t pcib, int b, int s, int f, size_t size)
359 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
360 pcicfgregs *cfg = NULL;
361 struct pci_devinfo *devlist_entry;
362 struct devlist *devlist_head;
364 devlist_head = &pci_devq;
366 devlist_entry = NULL;
368 if (REG(PCIR_DEVVENDOR, 4) != -1) {
369 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
370 if (devlist_entry == NULL)
373 cfg = &devlist_entry->cfg;
378 cfg->vendor = REG(PCIR_VENDOR, 2);
379 cfg->device = REG(PCIR_DEVICE, 2);
380 cfg->cmdreg = REG(PCIR_COMMAND, 2);
381 cfg->statreg = REG(PCIR_STATUS, 2);
382 cfg->baseclass = REG(PCIR_CLASS, 1);
383 cfg->subclass = REG(PCIR_SUBCLASS, 1);
384 cfg->progif = REG(PCIR_PROGIF, 1);
385 cfg->revid = REG(PCIR_REVID, 1);
386 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
387 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
388 cfg->lattimer = REG(PCIR_LATTIMER, 1);
389 cfg->intpin = REG(PCIR_INTPIN, 1);
390 cfg->intline = REG(PCIR_INTLINE, 1);
392 cfg->mingnt = REG(PCIR_MINGNT, 1);
393 cfg->maxlat = REG(PCIR_MAXLAT, 1);
395 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
396 cfg->hdrtype &= ~PCIM_MFDEV;
399 pci_hdrtypedata(pcib, b, s, f, cfg);
401 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
402 pci_read_extcap(pcib, cfg);
404 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
406 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
407 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
408 devlist_entry->conf.pc_sel.pc_func = cfg->func;
409 devlist_entry->conf.pc_hdr = cfg->hdrtype;
411 devlist_entry->conf.pc_subvendor = cfg->subvendor;
412 devlist_entry->conf.pc_subdevice = cfg->subdevice;
413 devlist_entry->conf.pc_vendor = cfg->vendor;
414 devlist_entry->conf.pc_device = cfg->device;
416 devlist_entry->conf.pc_class = cfg->baseclass;
417 devlist_entry->conf.pc_subclass = cfg->subclass;
418 devlist_entry->conf.pc_progif = cfg->progif;
419 devlist_entry->conf.pc_revid = cfg->revid;
424 return (devlist_entry);
429 pci_read_extcap(device_t pcib, pcicfgregs *cfg)
431 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
432 int ptr, nextptr, ptrptr;
434 switch (cfg->hdrtype & PCIM_HDRTYPE) {
436 ptrptr = PCIR_CAP_PTR;
439 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */
442 return; /* no extended capabilities support */
444 nextptr = REG(ptrptr, 1); /* sanity check? */
447 * Read capability entries.
449 while (nextptr != 0) {
452 printf("illegal PCI extended capability offset %d\n",
456 /* Find the next entry */
458 nextptr = REG(ptr + PCICAP_NEXTPTR, 1);
460 /* Process this entry */
461 switch (REG(ptr + PCICAP_ID, 1)) {
462 case PCIY_PMG: /* PCI power management */
463 if (cfg->pp.pp_cap == 0) {
464 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
465 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS;
466 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR;
467 if ((nextptr - ptr) > PCIR_POWER_DATA)
468 cfg->pp.pp_data = ptr + PCIR_POWER_DATA;
471 case PCIY_MSI: /* PCI MSI */
472 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
473 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT)
474 cfg->msi.msi_data = PCIR_MSI_DATA_64BIT;
476 cfg->msi.msi_data = PCIR_MSI_DATA;
477 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl &
478 PCIM_MSICTRL_MMC_MASK)>>1);
480 case PCIY_VPD: /* PCI Vital Product Data */
481 cfg->vpd.vpd_reg = ptr;
482 pci_read_vpd(pcib, cfg);
488 /* REG use carry through to next functions */
492 * PCI Vital Product Data
495 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg)
497 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
499 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
501 WREG(cfg->vpd.vpd_reg + 2, reg, 2);
502 while ((REG(cfg->vpd.vpd_reg + 2, 2) & 0x8000) != 0x8000)
503 DELAY(1); /* limit looping */
505 return REG(cfg->vpd.vpd_reg + 4, 4);
510 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data)
512 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
514 WREG(cfg->vpd.vpd_reg + 4, data, 4);
515 WREG(cfg->vpd.vpd_reg + 2, reg | 0x8000, 2);
516 while ((REG(cfg->vpd.vpd_reg + 2, 2) & 0x8000) == 0x8000)
517 DELAY(1); /* limit looping */
524 struct vpd_readstate {
534 vpd_nextbyte(struct vpd_readstate *vrs)
538 if (vrs->bytesinval == 0) {
539 vrs->val = le32toh(pci_read_vpd_reg(vrs->pcib, vrs->cfg,
542 byte = vrs->val & 0xff;
545 vrs->val = vrs->val >> 8;
546 byte = vrs->val & 0xff;
555 pci_read_vpd(device_t pcib, pcicfgregs *cfg)
557 struct vpd_readstate vrs;
564 int alloc, off; /* alloc/off for RO/W arrays */
568 /* init vpd reader */
576 name = remain = i = 0; /* shut up stupid gcc */
577 alloc = off = 0; /* shut up stupid gcc */
578 dflen = 0; /* shut up stupid gcc */
582 byte = vpd_nextbyte(&vrs);
584 printf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \
585 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val,
586 vrs.off, vrs.bytesinval, byte, state, remain, name, i);
589 case 0: /* item name */
591 remain = vpd_nextbyte(&vrs);
592 remain |= vpd_nextbyte(&vrs) << 8;
593 if (remain > (0x7f*4 - vrs.off)) {
596 "pci%d:%d:%d: invalid vpd data, remain %#x\n",
597 cfg->bus, cfg->slot, cfg->func,
603 name = (byte >> 3) & 0xf;
606 case 0x2: /* String */
607 cfg->vpd.vpd_ident = malloc(remain + 1,
616 case 0x10: /* VPD-R */
619 cfg->vpd.vpd_ros = malloc(alloc *
620 sizeof *cfg->vpd.vpd_ros, M_DEVBUF,
624 case 0x11: /* VPD-W */
627 cfg->vpd.vpd_w = malloc(alloc *
628 sizeof *cfg->vpd.vpd_w, M_DEVBUF,
632 default: /* XXX - unimplemented */
638 case 1: /* Identifier String */
639 cfg->vpd.vpd_ident[i++] = byte;
642 cfg->vpd.vpd_ident[i] = '\0';
647 case 2: /* VPD-R Keyword Header */
649 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros,
650 (alloc *= 2) * sizeof *cfg->vpd.vpd_ros,
653 cfg->vpd.vpd_ros[off].keyword[0] = byte;
654 cfg->vpd.vpd_ros[off].keyword[1] = vpd_nextbyte(&vrs);
655 dflen = vpd_nextbyte(&vrs);
657 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV",
660 * if this happens, we can't trust the rest
663 printf("pci%d:%d:%d: bad keyword length: %d\n",
664 cfg->bus, cfg->slot, cfg->func, dflen);
668 } else if (dflen == 0) {
669 cfg->vpd.vpd_ros[off].value = malloc(1 *
670 sizeof *cfg->vpd.vpd_ros[off].value,
672 cfg->vpd.vpd_ros[off].value[0] = '\x00';
674 cfg->vpd.vpd_ros[off].value = malloc(
676 sizeof *cfg->vpd.vpd_ros[off].value,
680 /* keep in sync w/ state 3's transistions */
681 if (dflen == 0 && remain == 0)
689 case 3: /* VPD-R Keyword Value */
690 cfg->vpd.vpd_ros[off].value[i++] = byte;
691 if (strncmp(cfg->vpd.vpd_ros[off].keyword,
692 "RV", 2) == 0 && cksumvalid == -1) {
697 "pci%d:%d:%d: bad VPD cksum, remain %hhu\n",
698 cfg->bus, cfg->slot, cfg->func,
707 /* keep in sync w/ state 2's transistions */
709 cfg->vpd.vpd_ros[off++].value[i++] = '\0';
710 if (dflen == 0 && remain == 0) {
711 cfg->vpd.vpd_rocnt = off;
712 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros,
713 off * sizeof *cfg->vpd.vpd_ros,
716 } else if (dflen == 0)
726 case 5: /* VPD-W Keyword Header */
728 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w,
729 (alloc *= 2) * sizeof *cfg->vpd.vpd_w,
732 cfg->vpd.vpd_w[off].keyword[0] = byte;
733 cfg->vpd.vpd_w[off].keyword[1] = vpd_nextbyte(&vrs);
734 cfg->vpd.vpd_w[off].len = dflen = vpd_nextbyte(&vrs);
735 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval;
736 cfg->vpd.vpd_w[off].value = malloc((dflen + 1) *
737 sizeof *cfg->vpd.vpd_w[off].value,
741 /* keep in sync w/ state 6's transistions */
742 if (dflen == 0 && remain == 0)
750 case 6: /* VPD-W Keyword Value */
751 cfg->vpd.vpd_w[off].value[i++] = byte;
754 /* keep in sync w/ state 5's transistions */
756 cfg->vpd.vpd_w[off++].value[i++] = '\0';
757 if (dflen == 0 && remain == 0) {
758 cfg->vpd.vpd_wcnt = off;
759 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w,
760 off * sizeof *cfg->vpd.vpd_w,
763 } else if (dflen == 0)
768 printf("pci%d:%d:%d: invalid state: %d\n",
769 cfg->bus, cfg->slot, cfg->func, state);
775 if (cksumvalid == 0) {
776 /* read-only data bad, clean up */
778 free(cfg->vpd.vpd_ros[off].value, M_DEVBUF);
780 free(cfg->vpd.vpd_ros, M_DEVBUF);
781 cfg->vpd.vpd_ros = NULL;
787 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr)
789 struct pci_devinfo *dinfo = device_get_ivars(child);
790 pcicfgregs *cfg = &dinfo->cfg;
792 *identptr = cfg->vpd.vpd_ident;
794 if (*identptr == NULL)
801 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw,
804 struct pci_devinfo *dinfo = device_get_ivars(child);
805 pcicfgregs *cfg = &dinfo->cfg;
808 for (i = 0; i < cfg->vpd.vpd_rocnt; i++)
809 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword,
810 sizeof cfg->vpd.vpd_ros[i].keyword) == 0) {
811 *vptr = cfg->vpd.vpd_ros[i].value;
814 if (i != cfg->vpd.vpd_rocnt)
822 * Return the offset in configuration space of the requested extended
823 * capability entry or 0 if the specified capability was not found.
826 pci_find_extcap_method(device_t dev, device_t child, int capability,
829 struct pci_devinfo *dinfo = device_get_ivars(child);
830 pcicfgregs *cfg = &dinfo->cfg;
835 * Check the CAP_LIST bit of the PCI status register first.
837 status = pci_read_config(child, PCIR_STATUS, 2);
838 if (!(status & PCIM_STATUS_CAPPRESENT))
842 * Determine the start pointer of the capabilities list.
844 switch (cfg->hdrtype & PCIM_HDRTYPE) {
849 ptr = PCIR_CAP_PTR_2;
853 return (ENXIO); /* no extended capabilities support */
855 ptr = pci_read_config(child, ptr, 1);
858 * Traverse the capabilities list.
861 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
866 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
872 /* free pcicfgregs structure and all depending data structures */
875 pci_freecfg(struct pci_devinfo *dinfo)
877 struct devlist *devlist_head;
880 devlist_head = &pci_devq;
882 if (dinfo->cfg.vpd.vpd_reg) {
883 free(dinfo->cfg.vpd.vpd_ident, M_DEVBUF);
884 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++)
885 free(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF);
886 free(dinfo->cfg.vpd.vpd_ros, M_DEVBUF);
887 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++)
888 free(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF);
889 free(dinfo->cfg.vpd.vpd_w, M_DEVBUF);
891 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
892 free(dinfo, M_DEVBUF);
894 /* increment the generation count */
897 /* we're losing one device */
903 * PCI power manangement
906 pci_set_powerstate_method(device_t dev, device_t child, int state)
908 struct pci_devinfo *dinfo = device_get_ivars(child);
909 pcicfgregs *cfg = &dinfo->cfg;
911 int result, oldstate, highest, delay;
913 if (cfg->pp.pp_cap == 0)
917 * Optimize a no state change request away. While it would be OK to
918 * write to the hardware in theory, some devices have shown odd
919 * behavior when going from D3 -> D3.
921 oldstate = pci_get_powerstate(child);
922 if (oldstate == state)
926 * The PCI power management specification states that after a state
927 * transition between PCI power states, system software must
928 * guarantee a minimal delay before the function accesses the device.
929 * Compute the worst case delay that we need to guarantee before we
930 * access the device. Many devices will be responsive much more
931 * quickly than this delay, but there are some that don't respond
932 * instantly to state changes. Transitions to/from D3 state require
933 * 10ms, while D2 requires 200us, and D0/1 require none. The delay
934 * is done below with DELAY rather than a sleeper function because
935 * this function can be called from contexts where we cannot sleep.
937 highest = (oldstate > state) ? oldstate : state;
938 if (highest == PCI_POWERSTATE_D3)
940 else if (highest == PCI_POWERSTATE_D2)
944 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
948 case PCI_POWERSTATE_D0:
949 status |= PCIM_PSTAT_D0;
951 case PCI_POWERSTATE_D1:
952 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
954 status |= PCIM_PSTAT_D1;
956 case PCI_POWERSTATE_D2:
957 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
959 status |= PCIM_PSTAT_D2;
961 case PCI_POWERSTATE_D3:
962 status |= PCIM_PSTAT_D3;
970 "pci%d:%d:%d: Transition from D%d to D%d\n",
971 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func,
974 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
981 pci_get_powerstate_method(device_t dev, device_t child)
983 struct pci_devinfo *dinfo = device_get_ivars(child);
984 pcicfgregs *cfg = &dinfo->cfg;
988 if (cfg->pp.pp_cap != 0) {
989 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
990 switch (status & PCIM_PSTAT_DMASK) {
992 result = PCI_POWERSTATE_D0;
995 result = PCI_POWERSTATE_D1;
998 result = PCI_POWERSTATE_D2;
1001 result = PCI_POWERSTATE_D3;
1004 result = PCI_POWERSTATE_UNKNOWN;
1008 /* No support, device is always at D0 */
1009 result = PCI_POWERSTATE_D0;
1015 * Some convenience functions for PCI device drivers.
1018 static __inline void
1019 pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
1023 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
1025 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
1028 static __inline void
1029 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
1033 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
1035 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
1039 pci_enable_busmaster_method(device_t dev, device_t child)
1041 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
1046 pci_disable_busmaster_method(device_t dev, device_t child)
1048 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
1053 pci_enable_io_method(device_t dev, device_t child, int space)
1063 case SYS_RES_IOPORT:
1064 bit = PCIM_CMD_PORTEN;
1067 case SYS_RES_MEMORY:
1068 bit = PCIM_CMD_MEMEN;
1074 pci_set_command_bit(dev, child, bit);
1075 /* Some devices seem to need a brief stall here, what do to? */
1076 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
1079 device_printf(child, "failed to enable %s mapping!\n", error);
1084 pci_disable_io_method(device_t dev, device_t child, int space)
1094 case SYS_RES_IOPORT:
1095 bit = PCIM_CMD_PORTEN;
1098 case SYS_RES_MEMORY:
1099 bit = PCIM_CMD_MEMEN;
1105 pci_clear_command_bit(dev, child, bit);
1106 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
1107 if (command & bit) {
1108 device_printf(child, "failed to disable %s mapping!\n", error);
1115 * New style pci driver. Parent device is either a pci-host-bridge or a
1116 * pci-pci-bridge. Both kinds are represented by instances of pcib.
1120 pci_print_verbose(struct pci_devinfo *dinfo)
1125 pcicfgregs *cfg = &dinfo->cfg;
1127 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
1128 cfg->vendor, cfg->device, cfg->revid);
1129 printf("\tbus=%d, slot=%d, func=%d\n",
1130 cfg->bus, cfg->slot, cfg->func);
1131 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
1132 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
1134 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
1135 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
1136 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
1137 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
1138 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
1139 if (cfg->intpin > 0)
1140 printf("\tintpin=%c, irq=%d\n",
1141 cfg->intpin +'a' -1, cfg->intline);
1142 if (cfg->pp.pp_cap) {
1145 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
1146 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
1147 cfg->pp.pp_cap & PCIM_PCAP_SPEC,
1148 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
1149 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
1150 status & PCIM_PSTAT_DMASK);
1152 if (cfg->vpd.vpd_reg) {
1153 printf("\tVPD Ident: %s\n", cfg->vpd.vpd_ident);
1154 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) {
1155 struct vpd_readonly *vrop;
1156 vrop = &cfg->vpd.vpd_ros[i];
1157 if (strncmp("CP", vrop->keyword, 2) == 0)
1158 printf("\tCP: id %d, BAR%d, off %#x\n",
1159 vrop->value[0], vrop->value[1],
1161 *(uint16_t *)&vrop->value[2]));
1162 else if (strncmp("RV", vrop->keyword, 2) == 0)
1163 printf("\tRV: %#hhx\n", vrop->value[0]);
1165 printf("\t%.2s: %s\n", vrop->keyword,
1168 for (i = 0; i < cfg->vpd.vpd_wcnt; i++) {
1169 struct vpd_write *vwp;
1170 vwp = &cfg->vpd.vpd_w[i];
1171 if (strncmp("RW", vwp->keyword, 2) != 0)
1172 printf("\t%.2s(%#x-%#x): %s\n",
1173 vwp->keyword, vwp->start,
1174 vwp->start + vwp->len, vwp->value);
1177 if (cfg->msi.msi_data) {
1180 ctrl = cfg->msi.msi_ctrl;
1181 printf("\tMSI supports %d message%s%s%s\n",
1182 cfg->msi.msi_msgnum,
1183 (cfg->msi.msi_msgnum == 1) ? "" : "s",
1184 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
1185 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");
1191 pci_porten(device_t pcib, int b, int s, int f)
1193 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1194 & PCIM_CMD_PORTEN) != 0;
1198 pci_memen(device_t pcib, int b, int s, int f)
1200 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1201 & PCIM_CMD_MEMEN) != 0;
1205 * Add a resource based on a pci map register. Return 1 if the map
1206 * register is a 32bit map register or 2 if it is a 64bit register.
1209 pci_add_map(device_t pcib, device_t bus, device_t dev,
1210 int b, int s, int f, int reg, struct resource_list *rl, int force,
1215 pci_addr_t start, end, count;
1222 struct resource *res;
1224 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
1225 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
1226 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
1227 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
1229 if (pci_maptype(map) & PCI_MAPMEM)
1230 type = SYS_RES_MEMORY;
1232 type = SYS_RES_IOPORT;
1233 ln2size = pci_mapsize(testval);
1234 ln2range = pci_maprange(testval);
1235 base = pci_mapbase(map);
1236 barlen = ln2range == 64 ? 2 : 1;
1239 * For I/O registers, if bottom bit is set, and the next bit up
1240 * isn't clear, we know we have a BAR that doesn't conform to the
1241 * spec, so ignore it. Also, sanity check the size of the data
1242 * areas to the type of memory involved. Memory must be at least
1243 * 16 bytes in size, while I/O ranges must be at least 4.
1245 if ((testval & 0x1) == 0x1 &&
1246 (testval & 0x2) != 0)
1248 if ((type == SYS_RES_MEMORY && ln2size < 4) ||
1249 (type == SYS_RES_IOPORT && ln2size < 2))
1253 /* Read the other half of a 64bit map register */
1254 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32;
1256 printf("\tmap[%02x]: type %x, range %2d, base %#jx, size %2d",
1257 reg, pci_maptype(map), ln2range, (uintmax_t)base, ln2size);
1258 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
1259 printf(", port disabled\n");
1260 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
1261 printf(", memory disabled\n");
1263 printf(", enabled\n");
1267 * If base is 0, then we have problems. It is best to ignore
1268 * such entries for the moment. These will be allocated later if
1269 * the driver specifically requests them. However, some
1270 * removable busses look better when all resources are allocated,
1271 * so allow '0' to be overriden.
1273 * Similarly treat maps whose values is the same as the test value
1274 * read back. These maps have had all f's written to them by the
1275 * BIOS in an attempt to disable the resources.
1277 if (!force && (base == 0 || map == testval))
1279 if ((u_long)base != base) {
1281 "pci%d:%d:%d bar %#x too many address bits", b, s, f, reg);
1286 * This code theoretically does the right thing, but has
1287 * undesirable side effects in some cases where peripherals
1288 * respond oddly to having these bits enabled. Let the user
1289 * be able to turn them off (since pci_enable_io_modes is 1 by
1292 if (pci_enable_io_modes) {
1293 /* Turn on resources that have been left off by a lazy BIOS */
1294 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
1295 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1296 cmd |= PCIM_CMD_PORTEN;
1297 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
1299 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
1300 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1301 cmd |= PCIM_CMD_MEMEN;
1302 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
1305 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
1307 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
1311 count = 1 << ln2size;
1312 if (base == 0 || base == pci_mapbase(testval)) {
1313 start = 0; /* Let the parent deside */
1317 end = base + (1 << ln2size) - 1;
1319 resource_list_add(rl, type, reg, start, end, count);
1322 * Not quite sure what to do on failure of allocating the resource
1323 * since I can postulate several right answers.
1325 res = resource_list_alloc(rl, bus, dev, type, ®, start, end, count,
1326 prefetch ? RF_PREFETCHABLE : 0);
1329 start = rman_get_start(res);
1330 if ((u_long)start != start) {
1331 /* Wait a minute! this platform can't do this address. */
1333 "pci%d.%d.%x bar %#x start %#jx, too many bits.",
1334 b, s, f, reg, (uintmax_t)start);
1335 resource_list_release(rl, bus, dev, type, reg, res);
1338 pci_write_config(dev, reg, start, 4);
1340 pci_write_config(dev, reg + 4, start >> 32, 4);
1345 * For ATA devices we need to decide early what addressing mode to use.
1346 * Legacy demands that the primary and secondary ATA ports sits on the
1347 * same addresses that old ISA hardware did. This dictates that we use
1348 * those addresses and ignore the BAR's if we cannot set PCI native
1352 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b,
1353 int s, int f, struct resource_list *rl, int force, uint32_t prefetchmask)
1355 int rid, type, progif;
1357 /* if this device supports PCI native addressing use it */
1358 progif = pci_read_config(dev, PCIR_PROGIF, 1);
1359 if ((progif & 0x8a) == 0x8a) {
1360 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
1361 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
1362 printf("Trying ATA native PCI addressing mode\n");
1363 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
1367 progif = pci_read_config(dev, PCIR_PROGIF, 1);
1368 type = SYS_RES_IOPORT;
1369 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
1370 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl, force,
1371 prefetchmask & (1 << 0));
1372 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl, force,
1373 prefetchmask & (1 << 1));
1376 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
1377 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8,
1380 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
1381 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1,
1384 if (progif & PCIP_STORAGE_IDE_MODESEC) {
1385 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl, force,
1386 prefetchmask & (1 << 2));
1387 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl, force,
1388 prefetchmask & (1 << 3));
1391 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
1392 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8,
1395 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
1396 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1,
1399 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl, force,
1400 prefetchmask & (1 << 4));
1401 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl, force,
1402 prefetchmask & (1 << 5));
1406 pci_assign_interrupt(device_t bus, device_t dev, int force_route)
1408 struct pci_devinfo *dinfo = device_get_ivars(dev);
1409 pcicfgregs *cfg = &dinfo->cfg;
1410 char tunable_name[64];
1413 /* Has to have an intpin to have an interrupt. */
1414 if (cfg->intpin == 0)
1417 /* Let the user override the IRQ with a tunable. */
1418 irq = PCI_INVALID_IRQ;
1419 snprintf(tunable_name, sizeof(tunable_name), "hw.pci%d.%d.INT%c.irq",
1420 cfg->bus, cfg->slot, cfg->intpin + 'A' - 1);
1421 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0))
1422 irq = PCI_INVALID_IRQ;
1425 * If we didn't get an IRQ via the tunable, then we either use the
1426 * IRQ value in the intline register or we ask the bus to route an
1427 * interrupt for us. If force_route is true, then we only use the
1428 * value in the intline register if the bus was unable to assign an
1431 if (!PCI_INTERRUPT_VALID(irq)) {
1432 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
1433 irq = PCI_ASSIGN_INTERRUPT(bus, dev);
1434 if (!PCI_INTERRUPT_VALID(irq))
1438 /* If after all that we don't have an IRQ, just bail. */
1439 if (!PCI_INTERRUPT_VALID(irq))
1442 /* Update the config register if it changed. */
1443 if (irq != cfg->intline) {
1445 pci_write_config(dev, PCIR_INTLINE, irq, 1);
1448 /* Add this IRQ as rid 0 interrupt resource. */
1449 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1);
1453 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask)
1456 struct pci_devinfo *dinfo = device_get_ivars(dev);
1457 pcicfgregs *cfg = &dinfo->cfg;
1458 struct resource_list *rl = &dinfo->resources;
1459 struct pci_quirk *q;
1462 pcib = device_get_parent(bus);
1468 /* ATA devices needs special map treatment */
1469 if ((pci_get_class(dev) == PCIC_STORAGE) &&
1470 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
1471 (pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV))
1472 pci_ata_maps(pcib, bus, dev, b, s, f, rl, force, prefetchmask);
1474 for (i = 0; i < cfg->nummaps;)
1475 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i),
1476 rl, force, prefetchmask & (1 << i));
1479 * Add additional, quirked resources.
1481 for (q = &pci_quirks[0]; q->devid; q++) {
1482 if (q->devid == ((cfg->device << 16) | cfg->vendor)
1483 && q->type == PCI_QUIRK_MAP_REG)
1484 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl,
1488 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
1489 #ifdef __PCI_REROUTE_INTERRUPT
1491 * Try to re-route interrupts. Sometimes the BIOS or
1492 * firmware may leave bogus values in these registers.
1493 * If the re-route fails, then just stick with what we
1496 pci_assign_interrupt(bus, dev, 1);
1498 pci_assign_interrupt(bus, dev, 0);
1504 pci_add_children(device_t dev, int busno, size_t dinfo_size)
1506 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
1507 device_t pcib = device_get_parent(dev);
1508 struct pci_devinfo *dinfo;
1510 int s, f, pcifunchigh;
1513 KASSERT(dinfo_size >= sizeof(struct pci_devinfo),
1514 ("dinfo_size too small"));
1515 maxslots = PCIB_MAXSLOTS(pcib);
1516 for (s = 0; s <= maxslots; s++) {
1520 hdrtype = REG(PCIR_HDRTYPE, 1);
1521 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
1523 if (hdrtype & PCIM_MFDEV)
1524 pcifunchigh = PCI_FUNCMAX;
1525 for (f = 0; f <= pcifunchigh; f++) {
1526 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size);
1527 if (dinfo != NULL) {
1528 pci_add_child(dev, dinfo);
1536 pci_add_child(device_t bus, struct pci_devinfo *dinfo)
1538 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
1539 device_set_ivars(dinfo->cfg.dev, dinfo);
1540 resource_list_init(&dinfo->resources);
1541 pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
1542 pci_cfg_restore(dinfo->cfg.dev, dinfo);
1543 pci_print_verbose(dinfo);
1544 pci_add_resources(bus, dinfo->cfg.dev, 0, 0);
1548 pci_probe(device_t dev)
1551 device_set_desc(dev, "PCI bus");
1553 /* Allow other subclasses to override this driver. */
1558 pci_attach(device_t dev)
1563 * Since there can be multiple independantly numbered PCI
1564 * busses on systems with multiple PCI domains, we can't use
1565 * the unit number to decide which bus we are probing. We ask
1566 * the parent pcib what our bus number is.
1568 busno = pcib_get_bus(dev);
1570 device_printf(dev, "physical bus=%d\n", busno);
1572 pci_add_children(dev, busno, sizeof(struct pci_devinfo));
1574 return (bus_generic_attach(dev));
1578 pci_suspend(device_t dev)
1580 int dstate, error, i, numdevs;
1581 device_t acpi_dev, child, *devlist;
1582 struct pci_devinfo *dinfo;
1585 * Save the PCI configuration space for each child and set the
1586 * device in the appropriate power state for this sleep state.
1589 if (pci_do_power_resume)
1590 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
1591 device_get_children(dev, &devlist, &numdevs);
1592 for (i = 0; i < numdevs; i++) {
1594 dinfo = (struct pci_devinfo *) device_get_ivars(child);
1595 pci_cfg_save(child, dinfo, 0);
1598 /* Suspend devices before potentially powering them down. */
1599 error = bus_generic_suspend(dev);
1601 free(devlist, M_TEMP);
1606 * Always set the device to D3. If ACPI suggests a different
1607 * power state, use it instead. If ACPI is not present, the
1608 * firmware is responsible for managing device power. Skip
1609 * children who aren't attached since they are powered down
1610 * separately. Only manage type 0 devices for now.
1612 for (i = 0; acpi_dev && i < numdevs; i++) {
1614 dinfo = (struct pci_devinfo *) device_get_ivars(child);
1615 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) {
1616 dstate = PCI_POWERSTATE_D3;
1617 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate);
1618 pci_set_powerstate(child, dstate);
1621 free(devlist, M_TEMP);
1626 pci_resume(device_t dev)
1629 device_t acpi_dev, child, *devlist;
1630 struct pci_devinfo *dinfo;
1633 * Set each child to D0 and restore its PCI configuration space.
1636 if (pci_do_power_resume)
1637 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
1638 device_get_children(dev, &devlist, &numdevs);
1639 for (i = 0; i < numdevs; i++) {
1641 * Notify ACPI we're going to D0 but ignore the result. If
1642 * ACPI is not present, the firmware is responsible for
1643 * managing device power. Only manage type 0 devices for now.
1646 dinfo = (struct pci_devinfo *) device_get_ivars(child);
1647 if (acpi_dev && device_is_attached(child) &&
1648 dinfo->cfg.hdrtype == 0) {
1649 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL);
1650 pci_set_powerstate(child, PCI_POWERSTATE_D0);
1653 /* Now the device is powered up, restore its config space. */
1654 pci_cfg_restore(child, dinfo);
1656 free(devlist, M_TEMP);
1657 return (bus_generic_resume(dev));
1661 pci_load_vendor_data(void)
1663 caddr_t vendordata, info;
1665 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) {
1666 info = preload_search_info(vendordata, MODINFO_ADDR);
1667 pci_vendordata = *(char **)info;
1668 info = preload_search_info(vendordata, MODINFO_SIZE);
1669 pci_vendordata_size = *(size_t *)info;
1670 /* terminate the database */
1671 pci_vendordata[pci_vendordata_size] = '\n';
1676 pci_driver_added(device_t dev, driver_t *driver)
1681 struct pci_devinfo *dinfo;
1685 device_printf(dev, "driver added\n");
1686 DEVICE_IDENTIFY(driver, dev);
1687 device_get_children(dev, &devlist, &numdevs);
1688 for (i = 0; i < numdevs; i++) {
1690 if (device_get_state(child) != DS_NOTPRESENT)
1692 dinfo = device_get_ivars(child);
1693 pci_print_verbose(dinfo);
1695 printf("pci%d:%d:%d: reprobing on driver added\n",
1696 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func);
1697 pci_cfg_restore(child, dinfo);
1698 if (device_probe_and_attach(child) != 0)
1699 pci_cfg_save(child, dinfo, 1);
1701 free(devlist, M_TEMP);
1705 pci_print_child(device_t dev, device_t child)
1707 struct pci_devinfo *dinfo;
1708 struct resource_list *rl;
1711 dinfo = device_get_ivars(child);
1712 rl = &dinfo->resources;
1714 retval += bus_print_child_header(dev, child);
1716 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx");
1717 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
1718 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
1719 if (device_get_flags(dev))
1720 retval += printf(" flags %#x", device_get_flags(dev));
1722 retval += printf(" at device %d.%d", pci_get_slot(child),
1723 pci_get_function(child));
1725 retval += bus_print_child_footer(dev, child);
1735 } pci_nomatch_tab[] = {
1736 {PCIC_OLD, -1, "old"},
1737 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"},
1738 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"},
1739 {PCIC_STORAGE, -1, "mass storage"},
1740 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"},
1741 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"},
1742 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"},
1743 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"},
1744 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"},
1745 {PCIC_NETWORK, -1, "network"},
1746 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"},
1747 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"},
1748 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"},
1749 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"},
1750 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"},
1751 {PCIC_DISPLAY, -1, "display"},
1752 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"},
1753 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"},
1754 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"},
1755 {PCIC_MULTIMEDIA, -1, "multimedia"},
1756 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"},
1757 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"},
1758 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"},
1759 {PCIC_MEMORY, -1, "memory"},
1760 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"},
1761 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"},
1762 {PCIC_BRIDGE, -1, "bridge"},
1763 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"},
1764 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"},
1765 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"},
1766 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"},
1767 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"},
1768 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"},
1769 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"},
1770 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"},
1771 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"},
1772 {PCIC_SIMPLECOMM, -1, "simple comms"},
1773 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */
1774 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"},
1775 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"},
1776 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"},
1777 {PCIC_BASEPERIPH, -1, "base peripheral"},
1778 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"},
1779 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"},
1780 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"},
1781 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"},
1782 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"},
1783 {PCIC_INPUTDEV, -1, "input device"},
1784 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"},
1785 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"},
1786 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"},
1787 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"},
1788 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"},
1789 {PCIC_DOCKING, -1, "docking station"},
1790 {PCIC_PROCESSOR, -1, "processor"},
1791 {PCIC_SERIALBUS, -1, "serial bus"},
1792 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"},
1793 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"},
1794 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"},
1795 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"},
1796 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"},
1797 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"},
1798 {PCIC_WIRELESS, -1, "wireless controller"},
1799 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"},
1800 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"},
1801 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"},
1802 {PCIC_INTELLIIO, -1, "intelligent I/O controller"},
1803 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"},
1804 {PCIC_SATCOM, -1, "satellite communication"},
1805 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"},
1806 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"},
1807 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"},
1808 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"},
1809 {PCIC_CRYPTO, -1, "encrypt/decrypt"},
1810 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"},
1811 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"},
1812 {PCIC_DASP, -1, "dasp"},
1813 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"},
1818 pci_probe_nomatch(device_t dev, device_t child)
1821 char *cp, *scp, *device;
1824 * Look for a listing for this device in a loaded device database.
1826 if ((device = pci_describe_device(child)) != NULL) {
1827 device_printf(dev, "<%s>", device);
1828 free(device, M_DEVBUF);
1831 * Scan the class/subclass descriptions for a general
1836 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) {
1837 if (pci_nomatch_tab[i].class == pci_get_class(child)) {
1838 if (pci_nomatch_tab[i].subclass == -1) {
1839 cp = pci_nomatch_tab[i].desc;
1840 } else if (pci_nomatch_tab[i].subclass ==
1841 pci_get_subclass(child)) {
1842 scp = pci_nomatch_tab[i].desc;
1846 device_printf(dev, "<%s%s%s>",
1848 ((cp != NULL) && (scp != NULL)) ? ", " : "",
1851 printf(" at device %d.%d (no driver attached)\n",
1852 pci_get_slot(child), pci_get_function(child));
1853 if (pci_do_power_nodriver)
1855 (struct pci_devinfo *) device_get_ivars(child), 1);
1860 * Parse the PCI device database, if loaded, and return a pointer to a
1861 * description of the device.
1863 * The database is flat text formatted as follows:
1865 * Any line not in a valid format is ignored.
1866 * Lines are terminated with newline '\n' characters.
1868 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then
1871 * A DEVICE line is entered immediately below the corresponding VENDOR ID.
1872 * - devices cannot be listed without a corresponding VENDOR line.
1873 * A DEVICE line consists of a TAB, the 4 digit (hex) device code,
1874 * another TAB, then the device name.
1878 * Assuming (ptr) points to the beginning of a line in the database,
1879 * return the vendor or device and description of the next entry.
1880 * The value of (vendor) or (device) inappropriate for the entry type
1881 * is set to -1. Returns nonzero at the end of the database.
1883 * Note that this is slightly unrobust in the face of corrupt data;
1884 * we attempt to safeguard against this by spamming the end of the
1885 * database with a newline when we initialise.
1888 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc)
1897 left = pci_vendordata_size - (cp - pci_vendordata);
1905 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2)
1909 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2)
1912 /* skip to next line */
1913 while (*cp != '\n' && left > 0) {
1922 /* skip to next line */
1923 while (*cp != '\n' && left > 0) {
1927 if (*cp == '\n' && left > 0)
1934 pci_describe_device(device_t dev)
1937 char *desc, *vp, *dp, *line;
1939 desc = vp = dp = NULL;
1942 * If we have no vendor data, we can't do anything.
1944 if (pci_vendordata == NULL)
1948 * Scan the vendor data looking for this device
1950 line = pci_vendordata;
1951 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
1954 if (pci_describe_parse_line(&line, &vendor, &device, &vp))
1956 if (vendor == pci_get_vendor(dev))
1959 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
1962 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) {
1970 if (device == pci_get_device(dev))
1974 snprintf(dp, 80, "0x%x", pci_get_device(dev));
1975 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) !=
1977 sprintf(desc, "%s, %s", vp, dp);
1987 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1989 struct pci_devinfo *dinfo;
1992 dinfo = device_get_ivars(child);
1996 case PCI_IVAR_ETHADDR:
1998 * The generic accessor doesn't deal with failure, so
1999 * we set the return value, then return an error.
2001 *((uint8_t **) result) = NULL;
2003 case PCI_IVAR_SUBVENDOR:
2004 *result = cfg->subvendor;
2006 case PCI_IVAR_SUBDEVICE:
2007 *result = cfg->subdevice;
2009 case PCI_IVAR_VENDOR:
2010 *result = cfg->vendor;
2012 case PCI_IVAR_DEVICE:
2013 *result = cfg->device;
2015 case PCI_IVAR_DEVID:
2016 *result = (cfg->device << 16) | cfg->vendor;
2018 case PCI_IVAR_CLASS:
2019 *result = cfg->baseclass;
2021 case PCI_IVAR_SUBCLASS:
2022 *result = cfg->subclass;
2024 case PCI_IVAR_PROGIF:
2025 *result = cfg->progif;
2027 case PCI_IVAR_REVID:
2028 *result = cfg->revid;
2030 case PCI_IVAR_INTPIN:
2031 *result = cfg->intpin;
2034 *result = cfg->intline;
2040 *result = cfg->slot;
2042 case PCI_IVAR_FUNCTION:
2043 *result = cfg->func;
2045 case PCI_IVAR_CMDREG:
2046 *result = cfg->cmdreg;
2048 case PCI_IVAR_CACHELNSZ:
2049 *result = cfg->cachelnsz;
2051 case PCI_IVAR_MINGNT:
2052 *result = cfg->mingnt;
2054 case PCI_IVAR_MAXLAT:
2055 *result = cfg->maxlat;
2057 case PCI_IVAR_LATTIMER:
2058 *result = cfg->lattimer;
2067 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
2069 struct pci_devinfo *dinfo;
2071 dinfo = device_get_ivars(child);
2074 case PCI_IVAR_INTPIN:
2075 dinfo->cfg.intpin = value;
2077 case PCI_IVAR_ETHADDR:
2078 case PCI_IVAR_SUBVENDOR:
2079 case PCI_IVAR_SUBDEVICE:
2080 case PCI_IVAR_VENDOR:
2081 case PCI_IVAR_DEVICE:
2082 case PCI_IVAR_DEVID:
2083 case PCI_IVAR_CLASS:
2084 case PCI_IVAR_SUBCLASS:
2085 case PCI_IVAR_PROGIF:
2086 case PCI_IVAR_REVID:
2090 case PCI_IVAR_FUNCTION:
2091 return (EINVAL); /* disallow for now */
2099 #include "opt_ddb.h"
2101 #include <ddb/ddb.h>
2102 #include <sys/cons.h>
2105 * List resources based on pci map registers, used for within ddb
2108 DB_SHOW_COMMAND(pciregs, db_pci_dump)
2110 struct pci_devinfo *dinfo;
2111 struct devlist *devlist_head;
2114 int i, error, none_count;
2117 /* get the head of the device queue */
2118 devlist_head = &pci_devq;
2121 * Go through the list of devices and print out devices
2123 for (error = 0, i = 0,
2124 dinfo = STAILQ_FIRST(devlist_head);
2125 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit;
2126 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
2128 /* Populate pd_name and pd_unit */
2131 name = device_get_name(dinfo->cfg.dev);
2134 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x "
2135 "chip=0x%08x rev=0x%02x hdr=0x%02x\n",
2136 (name && *name) ? name : "none",
2137 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
2139 p->pc_sel.pc_bus, p->pc_sel.pc_dev,
2140 p->pc_sel.pc_func, (p->pc_class << 16) |
2141 (p->pc_subclass << 8) | p->pc_progif,
2142 (p->pc_subdevice << 16) | p->pc_subvendor,
2143 (p->pc_device << 16) | p->pc_vendor,
2144 p->pc_revid, p->pc_hdr);
2149 static struct resource *
2150 pci_alloc_map(device_t dev, device_t child, int type, int *rid,
2151 u_long start, u_long end, u_long count, u_int flags)
2153 struct pci_devinfo *dinfo = device_get_ivars(child);
2154 struct resource_list *rl = &dinfo->resources;
2155 struct resource_list_entry *rle;
2156 struct resource *res;
2157 pci_addr_t map, testval;
2161 * Weed out the bogons, and figure out how large the BAR/map
2162 * is. Bars that read back 0 here are bogus and unimplemented.
2163 * Note: atapci in legacy mode are special and handled elsewhere
2164 * in the code. If you have a atapci device in legacy mode and
2165 * it fails here, that other code is broken.
2168 map = pci_read_config(child, *rid, 4);
2169 pci_write_config(child, *rid, 0xffffffff, 4);
2170 testval = pci_read_config(child, *rid, 4);
2171 if (pci_maprange(testval) == 64)
2172 map |= (pci_addr_t)pci_read_config(child, *rid + 4, 4) << 32;
2173 if (pci_mapbase(testval) == 0)
2175 if (pci_maptype(testval) & PCI_MAPMEM) {
2176 if (type != SYS_RES_MEMORY) {
2179 "child %s requested type %d for rid %#x,"
2180 " but the BAR says it is an memio\n",
2181 device_get_nameunit(child), type, *rid);
2185 if (type != SYS_RES_IOPORT) {
2188 "child %s requested type %d for rid %#x,"
2189 " but the BAR says it is an ioport\n",
2190 device_get_nameunit(child), type, *rid);
2195 * For real BARs, we need to override the size that
2196 * the driver requests, because that's what the BAR
2197 * actually uses and we would otherwise have a
2198 * situation where we might allocate the excess to
2199 * another driver, which won't work.
2201 mapsize = pci_mapsize(testval);
2202 count = 1UL << mapsize;
2203 if (RF_ALIGNMENT(flags) < mapsize)
2204 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
2207 * Allocate enough resource, and then write back the
2208 * appropriate bar for that resource.
2210 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
2211 start, end, count, flags);
2213 device_printf(child,
2214 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n",
2215 count, *rid, type, start, end);
2218 resource_list_add(rl, type, *rid, start, end, count);
2219 rle = resource_list_find(rl, type, *rid);
2221 panic("pci_alloc_map: unexpectedly can't find resource.");
2223 rle->start = rman_get_start(res);
2224 rle->end = rman_get_end(res);
2227 device_printf(child,
2228 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n",
2229 count, *rid, type, rman_get_start(res));
2230 map = rman_get_start(res);
2232 pci_write_config(child, *rid, map, 4);
2233 if (pci_maprange(testval) == 64)
2234 pci_write_config(child, *rid + 4, map >> 32, 4);
2240 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
2241 u_long start, u_long end, u_long count, u_int flags)
2243 struct pci_devinfo *dinfo = device_get_ivars(child);
2244 struct resource_list *rl = &dinfo->resources;
2245 struct resource_list_entry *rle;
2246 pcicfgregs *cfg = &dinfo->cfg;
2249 * Perform lazy resource allocation
2251 if (device_get_parent(child) == dev) {
2255 * If the child device doesn't have an
2256 * interrupt routed and is deserving of an
2257 * interrupt, try to assign it one.
2259 if (!PCI_INTERRUPT_VALID(cfg->intline) &&
2261 pci_assign_interrupt(dev, child, 0);
2263 case SYS_RES_IOPORT:
2264 case SYS_RES_MEMORY:
2265 if (*rid < PCIR_BAR(cfg->nummaps)) {
2267 * Enable the I/O mode. We should
2268 * also be assigning resources too
2269 * when none are present. The
2270 * resource_list_alloc kind of sorta does
2273 if (PCI_ENABLE_IO(dev, child, type))
2276 rle = resource_list_find(rl, type, *rid);
2278 return (pci_alloc_map(dev, child, type, rid,
2279 start, end, count, flags));
2283 * If we've already allocated the resource, then
2284 * return it now. But first we may need to activate
2285 * it, since we don't allocate the resource as active
2286 * above. Normally this would be done down in the
2287 * nexus, but since we short-circuit that path we have
2288 * to do its job here. Not sure if we should free the
2289 * resource if it fails to activate.
2291 rle = resource_list_find(rl, type, *rid);
2292 if (rle != NULL && rle->res != NULL) {
2294 device_printf(child,
2295 "Reserved %#lx bytes for rid %#x type %d at %#lx\n",
2296 rman_get_size(rle->res), *rid, type,
2297 rman_get_start(rle->res));
2298 if ((flags & RF_ACTIVE) &&
2299 bus_generic_activate_resource(dev, child, type,
2300 *rid, rle->res) != 0)
2305 return (resource_list_alloc(rl, dev, child, type, rid,
2306 start, end, count, flags));
2310 pci_delete_resource(device_t dev, device_t child, int type, int rid)
2312 struct pci_devinfo *dinfo;
2313 struct resource_list *rl;
2314 struct resource_list_entry *rle;
2316 if (device_get_parent(child) != dev)
2319 dinfo = device_get_ivars(child);
2320 rl = &dinfo->resources;
2321 rle = resource_list_find(rl, type, rid);
2324 if (rman_get_device(rle->res) != dev ||
2325 rman_get_flags(rle->res) & RF_ACTIVE) {
2326 device_printf(dev, "delete_resource: "
2327 "Resource still owned by child, oops. "
2328 "(type=%d, rid=%d, addr=%lx)\n",
2329 rle->type, rle->rid,
2330 rman_get_start(rle->res));
2333 bus_release_resource(dev, type, rid, rle->res);
2335 resource_list_delete(rl, type, rid);
2338 * Why do we turn off the PCI configuration BAR when we delete a
2341 pci_write_config(child, rid, 0, 4);
2342 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid);
2345 struct resource_list *
2346 pci_get_resource_list (device_t dev, device_t child)
2348 struct pci_devinfo *dinfo = device_get_ivars(child);
2350 return (&dinfo->resources);
2354 pci_read_config_method(device_t dev, device_t child, int reg, int width)
2356 struct pci_devinfo *dinfo = device_get_ivars(child);
2357 pcicfgregs *cfg = &dinfo->cfg;
2359 return (PCIB_READ_CONFIG(device_get_parent(dev),
2360 cfg->bus, cfg->slot, cfg->func, reg, width));
2364 pci_write_config_method(device_t dev, device_t child, int reg,
2365 uint32_t val, int width)
2367 struct pci_devinfo *dinfo = device_get_ivars(child);
2368 pcicfgregs *cfg = &dinfo->cfg;
2370 PCIB_WRITE_CONFIG(device_get_parent(dev),
2371 cfg->bus, cfg->slot, cfg->func, reg, val, width);
2375 pci_child_location_str_method(device_t dev, device_t child, char *buf,
2379 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
2380 pci_get_function(child));
2385 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
2388 struct pci_devinfo *dinfo;
2391 dinfo = device_get_ivars(child);
2393 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
2394 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
2395 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
2401 pci_assign_interrupt_method(device_t dev, device_t child)
2403 struct pci_devinfo *dinfo = device_get_ivars(child);
2404 pcicfgregs *cfg = &dinfo->cfg;
2406 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
2411 pci_modevent(module_t mod, int what, void *arg)
2413 static struct cdev *pci_cdev;
2417 STAILQ_INIT(&pci_devq);
2419 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644,
2421 pci_load_vendor_data();
2425 destroy_dev(pci_cdev);
2433 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
2438 * Only do header type 0 devices. Type 1 devices are bridges,
2439 * which we know need special treatment. Type 2 devices are
2440 * cardbus bridges which also require special treatment.
2441 * Other types are unknown, and we err on the side of safety
2444 if (dinfo->cfg.hdrtype != 0)
2448 * Restore the device to full power mode. We must do this
2449 * before we restore the registers because moving from D3 to
2450 * D0 will cause the chip's BARs and some other registers to
2451 * be reset to some unknown power on reset values. Cut down
2452 * the noise on boot by doing nothing if we are already in
2455 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
2456 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
2458 for (i = 0; i < dinfo->cfg.nummaps; i++)
2459 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4);
2460 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4);
2461 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
2462 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
2463 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
2464 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
2465 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
2466 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
2467 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
2468 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
2469 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
2473 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
2480 * Only do header type 0 devices. Type 1 devices are bridges, which
2481 * we know need special treatment. Type 2 devices are cardbus bridges
2482 * which also require special treatment. Other types are unknown, and
2483 * we err on the side of safety by ignoring them. Powering down
2484 * bridges should not be undertaken lightly.
2486 if (dinfo->cfg.hdrtype != 0)
2488 for (i = 0; i < dinfo->cfg.nummaps; i++)
2489 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4);
2490 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4);
2493 * Some drivers apparently write to these registers w/o updating our
2494 * cached copy. No harm happens if we update the copy, so do so here
2495 * so we can restore them. The COMMAND register is modified by the
2496 * bus w/o updating the cache. This should represent the normally
2497 * writable portion of the 'defined' part of type 0 headers. In
2498 * theory we also need to save/restore the PCI capability structures
2499 * we know about, but apart from power we don't know any that are
2502 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
2503 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
2504 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
2505 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
2506 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
2507 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
2508 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
2509 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
2510 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
2511 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
2512 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
2513 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
2514 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
2515 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
2516 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
2519 * don't set the state for display devices, base peripherals and
2520 * memory devices since bad things happen when they are powered down.
2521 * We should (a) have drivers that can easily detach and (b) use
2522 * generic drivers for these devices so that some device actually
2523 * attaches. We need to make sure that when we implement (a) we don't
2524 * power the device down on a reattach.
2526 cls = pci_get_class(dev);
2529 switch (pci_do_power_nodriver)
2531 case 0: /* NO powerdown at all */
2533 case 1: /* Conservative about what to power down */
2534 if (cls == PCIC_STORAGE)
2537 case 2: /* Agressive about what to power down */
2538 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY ||
2539 cls == PCIC_BASEPERIPH)
2542 case 3: /* Power down everything */
2546 * PCI spec says we can only go into D3 state from D0 state.
2547 * Transition from D[12] into D0 before going to D3 state.
2549 ps = pci_get_powerstate(dev);
2550 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
2551 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
2552 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
2553 pci_set_powerstate(dev, PCI_POWERSTATE_D3);