2 * Copyright (c) 2015, 2020 Ruslan Bukin <br@bsdpad.com>
3 * Copyright (c) 2014 The FreeBSD Foundation
6 * This software was developed by Semihalf under
7 * the sponsorship of the FreeBSD Foundation.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 /* Generic ECAM PCIe driver */
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include "opt_platform.h"
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/malloc.h>
41 #include <sys/kernel.h>
43 #include <sys/module.h>
45 #include <sys/endian.h>
47 #include <dev/pci/pcivar.h>
48 #include <dev/pci/pcireg.h>
49 #include <dev/pci/pcib_private.h>
50 #include <dev/pci/pci_host_generic.h>
52 #include <machine/bus.h>
53 #include <machine/intr.h>
57 /* Forward prototypes */
59 static uint32_t generic_pcie_read_config(device_t dev, u_int bus, u_int slot,
60 u_int func, u_int reg, int bytes);
61 static void generic_pcie_write_config(device_t dev, u_int bus, u_int slot,
62 u_int func, u_int reg, uint32_t val, int bytes);
63 static int generic_pcie_maxslots(device_t dev);
64 static int generic_pcie_read_ivar(device_t dev, device_t child, int index,
66 static int generic_pcie_write_ivar(device_t dev, device_t child, int index,
70 pci_host_generic_core_attach(device_t dev)
72 struct generic_pcie_core_softc *sc;
79 sc = device_get_softc(dev);
82 /* Create the parent DMA tag to pass down the coherent flag */
83 error = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
84 1, 0, /* alignment, bounds */
85 BUS_SPACE_MAXADDR, /* lowaddr */
86 BUS_SPACE_MAXADDR, /* highaddr */
87 NULL, NULL, /* filter, filterarg */
88 BUS_SPACE_MAXSIZE, /* maxsize */
89 BUS_SPACE_UNRESTRICTED, /* nsegments */
90 BUS_SPACE_MAXSIZE, /* maxsegsize */
91 sc->coherent ? BUS_DMA_COHERENT : 0, /* flags */
92 NULL, NULL, /* lockfunc, lockarg */
98 sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
99 if (sc->res == NULL) {
100 device_printf(dev, "could not map memory.\n");
104 sc->bst = rman_get_bustag(sc->res);
105 sc->bsh = rman_get_bushandle(sc->res);
107 sc->has_pmem = false;
108 sc->pmem_rman.rm_type = RMAN_ARRAY;
109 sc->pmem_rman.rm_descr = "PCIe Prefetch Memory";
111 sc->mem_rman.rm_type = RMAN_ARRAY;
112 sc->mem_rman.rm_descr = "PCIe Memory";
114 sc->io_rman.rm_type = RMAN_ARRAY;
115 sc->io_rman.rm_descr = "PCIe IO window";
117 /* Initialize rman and allocate memory regions */
118 error = rman_init(&sc->pmem_rman);
120 device_printf(dev, "rman_init() failed. error = %d\n", error);
124 error = rman_init(&sc->mem_rman);
126 device_printf(dev, "rman_init() failed. error = %d\n", error);
130 error = rman_init(&sc->io_rman);
132 device_printf(dev, "rman_init() failed. error = %d\n", error);
136 for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) {
137 phys_base = sc->ranges[tuple].phys_base;
138 pci_base = sc->ranges[tuple].pci_base;
139 size = sc->ranges[tuple].size;
140 if (phys_base == 0 || size == 0)
141 continue; /* empty range element */
142 switch (FLAG_TYPE(sc->ranges[tuple].flags)) {
145 error = rman_manage_region(&sc->pmem_rman,
146 pci_base, pci_base + size - 1);
149 error = rman_manage_region(&sc->mem_rman,
150 pci_base, pci_base + size - 1);
153 error = rman_manage_region(&sc->io_rman,
154 pci_base, pci_base + size - 1);
160 device_printf(dev, "rman_manage_region() failed."
161 "error = %d\n", error);
162 rman_fini(&sc->pmem_rman);
163 rman_fini(&sc->mem_rman);
164 rman_fini(&sc->io_rman);
173 generic_pcie_read_config(device_t dev, u_int bus, u_int slot,
174 u_int func, u_int reg, int bytes)
176 struct generic_pcie_core_softc *sc;
177 bus_space_handle_t h;
182 sc = device_get_softc(dev);
183 if ((bus < sc->bus_start) || (bus > sc->bus_end))
185 if ((slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) ||
189 offset = PCIE_ADDR_OFFSET(bus - sc->bus_start, slot, func, reg);
195 data = bus_space_read_1(t, h, offset);
198 data = le16toh(bus_space_read_2(t, h, offset));
201 data = le32toh(bus_space_read_4(t, h, offset));
211 generic_pcie_write_config(device_t dev, u_int bus, u_int slot,
212 u_int func, u_int reg, uint32_t val, int bytes)
214 struct generic_pcie_core_softc *sc;
215 bus_space_handle_t h;
219 sc = device_get_softc(dev);
220 if ((bus < sc->bus_start) || (bus > sc->bus_end))
222 if ((slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) ||
226 offset = PCIE_ADDR_OFFSET(bus - sc->bus_start, slot, func, reg);
233 bus_space_write_1(t, h, offset, val);
236 bus_space_write_2(t, h, offset, htole16(val));
239 bus_space_write_4(t, h, offset, htole32(val));
247 generic_pcie_maxslots(device_t dev)
250 return (31); /* max slots per bus acc. to standard */
254 generic_pcie_read_ivar(device_t dev, device_t child, int index,
257 struct generic_pcie_core_softc *sc;
259 sc = device_get_softc(dev);
261 if (index == PCIB_IVAR_BUS) {
262 *result = sc->bus_start;
266 if (index == PCIB_IVAR_DOMAIN) {
272 device_printf(dev, "ERROR: Unknown index %d.\n", index);
277 generic_pcie_write_ivar(device_t dev, device_t child, int index,
285 generic_pcie_rman(struct generic_pcie_core_softc *sc, int type, int flags)
290 return (&sc->io_rman);
292 if (sc->has_pmem && (flags & RF_PREFETCHABLE) != 0)
293 return (&sc->pmem_rman);
294 return (&sc->mem_rman);
303 pci_host_generic_core_release_resource(device_t dev, device_t child, int type,
304 int rid, struct resource *res)
306 struct generic_pcie_core_softc *sc;
309 sc = device_get_softc(dev);
311 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
312 if (type == PCI_RES_BUS) {
313 return (pci_domain_release_bus(sc->ecam, child, rid, res));
317 rm = generic_pcie_rman(sc, type, rman_get_flags(res));
319 KASSERT(rman_is_region_manager(res, rm), ("rman mismatch"));
320 rman_release_resource(res);
323 return (bus_generic_release_resource(dev, child, type, rid, res));
327 generic_pcie_translate_resource(device_t dev, int type, rman_res_t start,
328 rman_res_t end, rman_res_t *new_start, rman_res_t *new_end)
330 struct generic_pcie_core_softc *sc;
337 sc = device_get_softc(dev);
338 /* Translate the address from a PCI address to a physical address */
343 for (i = 0; i < MAX_RANGES_TUPLES; i++) {
344 pci_base = sc->ranges[i].pci_base;
345 phys_base = sc->ranges[i].phys_base;
346 size = sc->ranges[i].size;
348 if (start < pci_base || start >= pci_base + size)
351 switch (FLAG_TYPE(sc->ranges[i].flags)) {
354 space = SYS_RES_MEMORY;
357 space = SYS_RES_IOPORT;
365 *new_start = start - pci_base + phys_base;
366 *new_end = end - pci_base + phys_base;
373 /* No translation for non-memory types */
384 pci_host_generic_core_alloc_resource(device_t dev, device_t child, int type,
385 int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
387 struct generic_pcie_core_softc *sc;
388 struct resource *res;
390 rman_res_t phys_start, phys_end;
392 sc = device_get_softc(dev);
394 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
395 if (type == PCI_RES_BUS) {
396 return (pci_domain_alloc_bus(sc->ecam, child, rid, start, end,
401 rm = generic_pcie_rman(sc, type, flags);
403 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
404 type, rid, start, end, count, flags));
406 /* Translate the address from a PCI address to a physical address */
407 if (!generic_pcie_translate_resource(dev, type, start, end, &phys_start,
410 "Failed to translate resource %jx-%jx type %x for %s\n",
411 (uintmax_t)start, (uintmax_t)end, type,
412 device_get_nameunit(child));
418 "rman_reserve_resource: start=%#jx, end=%#jx, count=%#jx\n",
422 res = rman_reserve_resource(rm, start, end, count, flags, child);
426 rman_set_rid(res, *rid);
428 if (flags & RF_ACTIVE)
429 if (bus_activate_resource(child, type, *rid, res)) {
430 rman_release_resource(res);
437 device_printf(dev, "%s FAIL: type=%d, rid=%d, "
438 "start=%016jx, end=%016jx, count=%016jx, flags=%x\n",
439 __func__, type, *rid, start, end, count, flags);
445 generic_pcie_activate_resource(device_t dev, device_t child, int type,
446 int rid, struct resource *r)
448 struct generic_pcie_core_softc *sc;
449 rman_res_t start, end;
452 sc = device_get_softc(dev);
454 if ((res = rman_activate_resource(r)) != 0)
457 start = rman_get_start(r);
458 end = rman_get_end(r);
459 if (!generic_pcie_translate_resource(dev, type, start, end, &start,
462 rman_set_start(r, start);
463 rman_set_end(r, end);
465 return (BUS_ACTIVATE_RESOURCE(device_get_parent(dev), child, type,
470 generic_pcie_deactivate_resource(device_t dev, device_t child, int type,
471 int rid, struct resource *r)
475 if ((res = rman_deactivate_resource(r)) != 0)
482 res = BUS_DEACTIVATE_RESOURCE(device_get_parent(dev), child,
493 generic_pcie_adjust_resource(device_t dev, device_t child, int type,
494 struct resource *res, rman_res_t start, rman_res_t end)
496 struct generic_pcie_core_softc *sc;
499 sc = device_get_softc(dev);
500 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
501 if (type == PCI_RES_BUS)
502 return (pci_domain_adjust_bus(sc->ecam, child, res, start,
506 rm = generic_pcie_rman(sc, type, rman_get_flags(res));
508 return (rman_adjust_resource(res, start, end));
509 return (bus_generic_adjust_resource(dev, child, type, res, start, end));
513 generic_pcie_get_dma_tag(device_t dev, device_t child)
515 struct generic_pcie_core_softc *sc;
517 sc = device_get_softc(dev);
521 static device_method_t generic_pcie_methods[] = {
522 DEVMETHOD(device_attach, pci_host_generic_core_attach),
523 DEVMETHOD(bus_read_ivar, generic_pcie_read_ivar),
524 DEVMETHOD(bus_write_ivar, generic_pcie_write_ivar),
525 DEVMETHOD(bus_alloc_resource, pci_host_generic_core_alloc_resource),
526 DEVMETHOD(bus_adjust_resource, generic_pcie_adjust_resource),
527 DEVMETHOD(bus_activate_resource, generic_pcie_activate_resource),
528 DEVMETHOD(bus_deactivate_resource, generic_pcie_deactivate_resource),
529 DEVMETHOD(bus_release_resource, pci_host_generic_core_release_resource),
530 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
531 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
533 DEVMETHOD(bus_get_dma_tag, generic_pcie_get_dma_tag),
536 DEVMETHOD(pcib_maxslots, generic_pcie_maxslots),
537 DEVMETHOD(pcib_read_config, generic_pcie_read_config),
538 DEVMETHOD(pcib_write_config, generic_pcie_write_config),
543 DEFINE_CLASS_0(pcib, generic_pcie_core_driver,
544 generic_pcie_methods, sizeof(struct generic_pcie_core_softc));