2 * Copyright (C) 2018 Cavium Inc.
3 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
4 * Copyright (c) 2014 The FreeBSD Foundation
7 * This software was developed by Semihalf under
8 * the sponsorship of the FreeBSD Foundation.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 /* Generic ECAM PCIe driver */
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include "opt_platform.h"
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/malloc.h>
42 #include <sys/kernel.h>
44 #include <sys/module.h>
46 #include <sys/endian.h>
47 #include <sys/cpuset.h>
48 #include <sys/rwlock.h>
50 #include <contrib/dev/acpica/include/acpi.h>
51 #include <contrib/dev/acpica/include/accommon.h>
53 #include <dev/acpica/acpivar.h>
54 #include <dev/acpica/acpi_pcibvar.h>
56 #include <dev/pci/pcivar.h>
57 #include <dev/pci/pcireg.h>
58 #include <dev/pci/pcib_private.h>
59 #include <dev/pci/pci_host_generic.h>
60 #include <dev/pci/pci_host_generic_acpi.h>
62 #include <machine/cpu.h>
63 #include <machine/bus.h>
64 #include <machine/intr.h>
67 #include "acpi_bus_if.h"
69 /* Assembling ECAM Configuration Address */
70 #define PCIE_BUS_SHIFT 20
71 #define PCIE_SLOT_SHIFT 15
72 #define PCIE_FUNC_SHIFT 12
73 #define PCIE_BUS_MASK 0xFF
74 #define PCIE_SLOT_MASK 0x1F
75 #define PCIE_FUNC_MASK 0x07
76 #define PCIE_REG_MASK 0xFFF
78 #define PCIE_ADDR_OFFSET(bus, slot, func, reg) \
79 ((((bus) & PCIE_BUS_MASK) << PCIE_BUS_SHIFT) | \
80 (((slot) & PCIE_SLOT_MASK) << PCIE_SLOT_SHIFT) | \
81 (((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT) | \
82 ((reg) & PCIE_REG_MASK))
84 #define PCI_IO_WINDOW_OFFSET 0x1000
86 #define SPACE_CODE_SHIFT 24
87 #define SPACE_CODE_MASK 0x3
88 #define SPACE_CODE_IO_SPACE 0x1
89 #define PROPS_CELL_SIZE 1
90 #define PCI_ADDR_CELL_SIZE 2
93 char oem_id[ACPI_OEM_ID_SIZE + 1];
94 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
96 } pci_acpi_quirks[] = {
97 { "MRVL ", "CN9130 ", PCIE_ECAM_DESIGNWARE_QUIRK },
98 { "MRVL ", "CN913X ", PCIE_ECAM_DESIGNWARE_QUIRK },
99 { "MVEBU ", "ARMADA7K", PCIE_ECAM_DESIGNWARE_QUIRK },
100 { "MVEBU ", "ARMADA8K", PCIE_ECAM_DESIGNWARE_QUIRK },
101 { "MVEBU ", "CN9130 ", PCIE_ECAM_DESIGNWARE_QUIRK },
102 { "MVEBU ", "CN9131 ", PCIE_ECAM_DESIGNWARE_QUIRK },
103 { "MVEBU ", "CN9132 ", PCIE_ECAM_DESIGNWARE_QUIRK },
107 /* Forward prototypes */
109 static int generic_pcie_acpi_probe(device_t dev);
110 static ACPI_STATUS pci_host_generic_acpi_parse_resource(ACPI_RESOURCE *, void *);
111 static int generic_pcie_acpi_read_ivar(device_t, device_t, int, uintptr_t *);
114 * generic_pcie_acpi_probe - look for root bridge flag
117 generic_pcie_acpi_probe(device_t dev)
119 ACPI_DEVICE_INFO *devinfo;
123 if (acpi_disabled("pcib") || (h = acpi_get_handle(dev)) == NULL ||
124 ACPI_FAILURE(AcpiGetObjectInfo(h, &devinfo)))
126 root = (devinfo->Flags & ACPI_PCI_ROOT_BRIDGE) != 0;
131 device_set_desc(dev, "Generic PCI host controller");
132 return (BUS_PROBE_GENERIC);
136 * pci_host_generic_acpi_parse_resource - parse PCI memory, IO and bus spaces
137 * 'produced' by this bridge
140 pci_host_generic_acpi_parse_resource(ACPI_RESOURCE *res, void *arg)
142 device_t dev = (device_t)arg;
143 struct generic_pcie_acpi_softc *sc;
145 rman_res_t min, max, off;
149 sc = device_get_softc(dev);
150 r = sc->base.nranges;
152 case ACPI_RESOURCE_TYPE_ADDRESS16:
153 min = res->Data.Address16.Address.Minimum;
154 max = res->Data.Address16.Address.Maximum;
156 case ACPI_RESOURCE_TYPE_ADDRESS32:
157 min = res->Data.Address32.Address.Minimum;
158 max = res->Data.Address32.Address.Maximum;
159 off = res->Data.Address32.Address.TranslationOffset;
161 case ACPI_RESOURCE_TYPE_ADDRESS64:
162 min = res->Data.Address64.Address.Minimum;
163 max = res->Data.Address64.Address.Maximum;
164 off = res->Data.Address64.Address.TranslationOffset;
170 /* Save detected ranges */
171 if (res->Data.Address.ResourceType == ACPI_MEMORY_RANGE ||
172 res->Data.Address.ResourceType == ACPI_IO_RANGE) {
173 sc->base.ranges[r].pci_base = min;
174 sc->base.ranges[r].phys_base = min + off;
175 sc->base.ranges[r].size = max - min + 1;
176 if (res->Data.Address.ResourceType == ACPI_MEMORY_RANGE)
177 sc->base.ranges[r].flags |= FLAG_TYPE_MEM;
178 else if (res->Data.Address.ResourceType == ACPI_IO_RANGE)
179 sc->base.ranges[r].flags |= FLAG_TYPE_IO;
181 } else if (res->Data.Address.ResourceType == ACPI_BUS_NUMBER_RANGE) {
182 sc->base.bus_start = min;
183 sc->base.bus_end = max;
189 pci_host_acpi_get_oem_quirks(struct generic_pcie_acpi_softc *sc,
190 ACPI_TABLE_HEADER *hdr)
194 for (i = 0; pci_acpi_quirks[i].quirks; i++) {
195 if (memcmp(hdr->OemId, pci_acpi_quirks[i].oem_id,
196 ACPI_OEM_ID_SIZE) != 0)
198 if (memcmp(hdr->OemTableId, pci_acpi_quirks[i].oem_table_id,
199 ACPI_OEM_TABLE_ID_SIZE) != 0)
201 sc->base.quirks |= pci_acpi_quirks[i].quirks;
206 pci_host_acpi_get_ecam_resource(device_t dev)
208 struct generic_pcie_acpi_softc *sc;
209 struct acpi_device *ad;
210 struct resource_list *rl;
211 ACPI_TABLE_HEADER *hdr;
212 ACPI_MCFG_ALLOCATION *mcfg_entry, *mcfg_end;
215 rman_res_t base, start, end;
218 sc = device_get_softc(dev);
219 handle = acpi_get_handle(dev);
222 status = AcpiGetTable(ACPI_SIG_MCFG, 1, &hdr);
223 if (ACPI_SUCCESS(status)) {
225 mcfg_end = (ACPI_MCFG_ALLOCATION *)((char *)hdr + hdr->Length);
226 mcfg_entry = (ACPI_MCFG_ALLOCATION *)((ACPI_TABLE_MCFG *)hdr + 1);
227 while (mcfg_entry < mcfg_end && !found) {
228 if (mcfg_entry->PciSegment == sc->base.ecam &&
229 mcfg_entry->StartBusNumber <= sc->base.bus_start &&
230 mcfg_entry->EndBusNumber >= sc->base.bus_start)
236 if (mcfg_entry->EndBusNumber < sc->base.bus_end)
237 sc->base.bus_end = mcfg_entry->EndBusNumber;
238 base = mcfg_entry->Address;
240 device_printf(dev, "MCFG exists, but does not have bus %d-%d\n",
241 sc->base.bus_start, sc->base.bus_end);
244 pci_host_acpi_get_oem_quirks(sc, hdr);
245 if (sc->base.quirks & PCIE_ECAM_DESIGNWARE_QUIRK)
246 device_set_desc(dev, "Synopsys DesignWare PCIe Controller");
248 status = acpi_GetInteger(handle, "_CBA", &val);
249 if (ACPI_SUCCESS(status))
255 /* add as MEM rid 0 */
256 ad = device_get_ivars(dev);
258 start = base + (sc->base.bus_start << PCIE_BUS_SHIFT);
259 end = base + ((sc->base.bus_end + 1) << PCIE_BUS_SHIFT) - 1;
260 resource_list_add(rl, SYS_RES_MEMORY, 0, start, end, end - start + 1);
262 device_printf(dev, "ECAM for bus %d-%d at mem %jx-%jx\n",
263 sc->base.bus_start, sc->base.bus_end, start, end);
268 pci_host_generic_acpi_init(device_t dev)
270 struct generic_pcie_acpi_softc *sc;
275 sc = device_get_softc(dev);
276 handle = acpi_get_handle(dev);
278 /* Get Start bus number for the PCI host bus is from _BBN method */
279 status = acpi_GetInteger(handle, "_BBN", &sc->base.bus_start);
280 if (ACPI_FAILURE(status)) {
281 device_printf(dev, "No _BBN, using start bus 0\n");
282 sc->base.bus_start = 0;
284 sc->base.bus_end = 255;
286 /* Get PCI Segment (domain) needed for MCFG lookup */
287 status = acpi_GetInteger(handle, "_SEG", &sc->base.ecam);
288 if (ACPI_FAILURE(status)) {
289 device_printf(dev, "No _SEG for PCI Bus, using segment 0\n");
293 /* Bus decode ranges */
294 status = AcpiWalkResources(handle, "_CRS",
295 pci_host_generic_acpi_parse_resource, (void *)dev);
296 if (ACPI_FAILURE(status))
299 /* Coherency attribute */
300 if (ACPI_FAILURE(acpi_GetInteger(handle, "_CCA", &sc->base.coherent)))
301 sc->base.coherent = 0;
303 device_printf(dev, "Bus is%s cache-coherent\n",
304 sc->base.coherent ? "" : " not");
306 /* add config space resource */
307 pci_host_acpi_get_ecam_resource(dev);
308 acpi_pcib_fetch_prt(dev, &sc->ap_prt);
310 error = pci_host_generic_core_attach(dev);
318 pci_host_generic_acpi_attach(device_t dev)
322 error = pci_host_generic_acpi_init(dev);
326 device_add_child(dev, "pci", -1);
327 return (bus_generic_attach(dev));
331 generic_pcie_acpi_read_ivar(device_t dev, device_t child, int index,
334 struct generic_pcie_acpi_softc *sc;
336 sc = device_get_softc(dev);
338 if (index == PCIB_IVAR_BUS) {
339 *result = sc->base.bus_start;
343 if (index == PCIB_IVAR_DOMAIN) {
344 *result = sc->base.ecam;
349 device_printf(dev, "ERROR: Unknown index %d.\n", index);
354 generic_pcie_acpi_route_interrupt(device_t bus, device_t dev, int pin)
356 struct generic_pcie_acpi_softc *sc;
358 sc = device_get_softc(bus);
359 return (acpi_pcib_route_interrupt(bus, dev, pin, &sc->ap_prt));
363 generic_pcie_get_xref(device_t pci, device_t child)
365 struct generic_pcie_acpi_softc *sc;
370 sc = device_get_softc(pci);
371 err = pcib_get_id(pci, child, PCI_ID_RID, &rid);
373 return (ACPI_MSI_XREF);
374 err = acpi_iort_map_pci_msi(sc->base.ecam, rid, &xref, &devid);
376 return (ACPI_MSI_XREF);
381 generic_pcie_map_id(device_t pci, device_t child, uintptr_t *id)
383 struct generic_pcie_acpi_softc *sc;
388 sc = device_get_softc(pci);
389 err = pcib_get_id(pci, child, PCI_ID_RID, &rid);
392 err = acpi_iort_map_pci_msi(sc->base.ecam, rid, &xref, &devid);
396 *id = rid; /* RID not in IORT, likely FW bug, ignore */
401 generic_pcie_acpi_alloc_msi(device_t pci, device_t child, int count,
402 int maxcount, int *irqs)
406 return (intr_alloc_msi(pci, child, generic_pcie_get_xref(pci, child),
407 count, maxcount, irqs));
414 generic_pcie_acpi_release_msi(device_t pci, device_t child, int count,
419 return (intr_release_msi(pci, child, generic_pcie_get_xref(pci, child),
427 generic_pcie_acpi_map_msi(device_t pci, device_t child, int irq, uint64_t *addr,
432 return (intr_map_msi(pci, child, generic_pcie_get_xref(pci, child), irq,
440 generic_pcie_acpi_alloc_msix(device_t pci, device_t child, int *irq)
444 return (intr_alloc_msix(pci, child, generic_pcie_get_xref(pci, child),
452 generic_pcie_acpi_release_msix(device_t pci, device_t child, int irq)
456 return (intr_release_msix(pci, child, generic_pcie_get_xref(pci, child),
464 generic_pcie_acpi_get_id(device_t pci, device_t child, enum pci_id_type type,
468 if (type == PCI_ID_MSI)
469 return (generic_pcie_map_id(pci, child, id));
471 return (pcib_get_id(pci, child, type, id));
474 static device_method_t generic_pcie_acpi_methods[] = {
475 DEVMETHOD(device_probe, generic_pcie_acpi_probe),
476 DEVMETHOD(device_attach, pci_host_generic_acpi_attach),
477 DEVMETHOD(bus_read_ivar, generic_pcie_acpi_read_ivar),
480 DEVMETHOD(pcib_route_interrupt, generic_pcie_acpi_route_interrupt),
481 DEVMETHOD(pcib_alloc_msi, generic_pcie_acpi_alloc_msi),
482 DEVMETHOD(pcib_release_msi, generic_pcie_acpi_release_msi),
483 DEVMETHOD(pcib_alloc_msix, generic_pcie_acpi_alloc_msix),
484 DEVMETHOD(pcib_release_msix, generic_pcie_acpi_release_msix),
485 DEVMETHOD(pcib_map_msi, generic_pcie_acpi_map_msi),
486 DEVMETHOD(pcib_get_id, generic_pcie_acpi_get_id),
491 DEFINE_CLASS_1(pcib, generic_pcie_acpi_driver, generic_pcie_acpi_methods,
492 sizeof(struct generic_pcie_acpi_softc), generic_pcie_core_driver);
494 static devclass_t generic_pcie_acpi_devclass;
496 DRIVER_MODULE(pcib, acpi, generic_pcie_acpi_driver, generic_pcie_acpi_devclass,