2 * Copyright (C) 2018 Cavium Inc.
3 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
4 * Copyright (c) 2014 The FreeBSD Foundation
7 * This software was developed by Semihalf under
8 * the sponsorship of the FreeBSD Foundation.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 /* Generic ECAM PCIe driver */
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include "opt_platform.h"
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/malloc.h>
42 #include <sys/kernel.h>
44 #include <sys/module.h>
46 #include <sys/endian.h>
47 #include <sys/cpuset.h>
48 #include <sys/rwlock.h>
50 #include <contrib/dev/acpica/include/acpi.h>
51 #include <contrib/dev/acpica/include/accommon.h>
53 #include <dev/acpica/acpivar.h>
54 #include <dev/acpica/acpi_pcibvar.h>
56 #include <dev/pci/pcivar.h>
57 #include <dev/pci/pcireg.h>
58 #include <dev/pci/pcib_private.h>
59 #include <dev/pci/pci_host_generic.h>
60 #include <dev/pci/pci_host_generic_acpi.h>
62 #include <machine/cpu.h>
63 #include <machine/bus.h>
64 #include <machine/intr.h>
67 #include "acpi_bus_if.h"
69 /* Assembling ECAM Configuration Address */
70 #define PCIE_BUS_SHIFT 20
71 #define PCIE_SLOT_SHIFT 15
72 #define PCIE_FUNC_SHIFT 12
73 #define PCIE_BUS_MASK 0xFF
74 #define PCIE_SLOT_MASK 0x1F
75 #define PCIE_FUNC_MASK 0x07
76 #define PCIE_REG_MASK 0xFFF
78 #define PCIE_ADDR_OFFSET(bus, slot, func, reg) \
79 ((((bus) & PCIE_BUS_MASK) << PCIE_BUS_SHIFT) | \
80 (((slot) & PCIE_SLOT_MASK) << PCIE_SLOT_SHIFT) | \
81 (((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT) | \
82 ((reg) & PCIE_REG_MASK))
84 #define PCI_IO_WINDOW_OFFSET 0x1000
86 #define SPACE_CODE_SHIFT 24
87 #define SPACE_CODE_MASK 0x3
88 #define SPACE_CODE_IO_SPACE 0x1
89 #define PROPS_CELL_SIZE 1
90 #define PCI_ADDR_CELL_SIZE 2
92 /* Forward prototypes */
94 static int generic_pcie_acpi_probe(device_t dev);
95 static ACPI_STATUS pci_host_generic_acpi_parse_resource(ACPI_RESOURCE *, void *);
96 static int generic_pcie_acpi_read_ivar(device_t, device_t, int, uintptr_t *);
99 * generic_pcie_acpi_probe - look for root bridge flag
102 generic_pcie_acpi_probe(device_t dev)
104 ACPI_DEVICE_INFO *devinfo;
108 if (acpi_disabled("pcib") || (h = acpi_get_handle(dev)) == NULL ||
109 ACPI_FAILURE(AcpiGetObjectInfo(h, &devinfo)))
111 root = (devinfo->Flags & ACPI_PCI_ROOT_BRIDGE) != 0;
116 device_set_desc(dev, "Generic PCI host controller");
117 return (BUS_PROBE_GENERIC);
121 * pci_host_generic_acpi_parse_resource - parse PCI memory, IO and bus spaces
122 * 'produced' by this bridge
125 pci_host_generic_acpi_parse_resource(ACPI_RESOURCE *res, void *arg)
127 device_t dev = (device_t)arg;
128 struct generic_pcie_acpi_softc *sc;
130 rman_res_t min, max, off;
134 sc = device_get_softc(dev);
135 r = sc->base.nranges;
137 case ACPI_RESOURCE_TYPE_ADDRESS16:
138 min = res->Data.Address16.Address.Minimum;
139 max = res->Data.Address16.Address.Maximum;
141 case ACPI_RESOURCE_TYPE_ADDRESS32:
142 min = res->Data.Address32.Address.Minimum;
143 max = res->Data.Address32.Address.Maximum;
144 off = res->Data.Address32.Address.TranslationOffset;
146 case ACPI_RESOURCE_TYPE_ADDRESS64:
147 min = res->Data.Address64.Address.Minimum;
148 max = res->Data.Address64.Address.Maximum;
149 off = res->Data.Address64.Address.TranslationOffset;
155 /* Save detected ranges */
156 if (res->Data.Address.ResourceType == ACPI_MEMORY_RANGE ||
157 res->Data.Address.ResourceType == ACPI_IO_RANGE) {
158 sc->base.ranges[r].pci_base = min;
159 sc->base.ranges[r].phys_base = min + off;
160 sc->base.ranges[r].size = max - min + 1;
161 if (res->Data.Address.ResourceType == ACPI_MEMORY_RANGE)
162 sc->base.ranges[r].flags |= FLAG_MEM;
163 else if (res->Data.Address.ResourceType == ACPI_IO_RANGE)
164 sc->base.ranges[r].flags |= FLAG_IO;
166 } else if (res->Data.Address.ResourceType == ACPI_BUS_NUMBER_RANGE) {
167 sc->base.bus_start = min;
168 sc->base.bus_end = max;
174 pci_host_acpi_get_ecam_resource(device_t dev)
176 struct generic_pcie_acpi_softc *sc;
177 struct acpi_device *ad;
178 struct resource_list *rl;
179 ACPI_TABLE_HEADER *hdr;
180 ACPI_MCFG_ALLOCATION *mcfg_entry, *mcfg_end;
183 rman_res_t base, start, end;
186 sc = device_get_softc(dev);
187 handle = acpi_get_handle(dev);
190 status = AcpiGetTable(ACPI_SIG_MCFG, 1, &hdr);
191 if (ACPI_SUCCESS(status)) {
193 mcfg_end = (ACPI_MCFG_ALLOCATION *)((char *)hdr + hdr->Length);
194 mcfg_entry = (ACPI_MCFG_ALLOCATION *)((ACPI_TABLE_MCFG *)hdr + 1);
195 while (mcfg_entry < mcfg_end && !found) {
196 if (mcfg_entry->PciSegment == sc->base.ecam &&
197 mcfg_entry->StartBusNumber <= sc->base.bus_start &&
198 mcfg_entry->EndBusNumber >= sc->base.bus_start)
204 sc->base.bus_end = mcfg_entry->EndBusNumber;
205 base = mcfg_entry->Address;
207 device_printf(dev, "MCFG exists, but does not have bus %d-%d\n",
208 sc->base.bus_start, sc->base.bus_end);
212 status = acpi_GetInteger(handle, "_CBA", &val);
213 if (ACPI_SUCCESS(status)) {
215 sc->base.bus_end = 255;
220 /* add as MEM rid 0 */
221 ad = device_get_ivars(dev);
223 start = base + (sc->base.bus_start << PCIE_BUS_SHIFT);
224 end = base + ((sc->base.bus_end + 1) << PCIE_BUS_SHIFT) - 1;
225 resource_list_add(rl, SYS_RES_MEMORY, 0, start, end, end - start + 1);
227 device_printf(dev, "ECAM for bus %d-%d at mem %jx-%jx\n",
228 sc->base.bus_start, sc->base.bus_end, start, end);
233 pci_host_generic_acpi_init(device_t dev)
235 struct generic_pcie_acpi_softc *sc;
244 sc = device_get_softc(dev);
245 handle = acpi_get_handle(dev);
247 /* Get Start bus number for the PCI host bus is from _BBN method */
248 status = acpi_GetInteger(handle, "_BBN", &sc->base.bus_start);
249 if (ACPI_FAILURE(status)) {
250 device_printf(dev, "No _BBN, using start bus 0\n");
251 sc->base.bus_start = 0;
254 /* Get PCI Segment (domain) needed for MCFG lookup */
255 status = acpi_GetInteger(handle, "_SEG", &sc->base.ecam);
256 if (ACPI_FAILURE(status)) {
257 device_printf(dev, "No _SEG for PCI Bus, using segment 0\n");
261 /* Bus decode ranges */
262 status = AcpiWalkResources(handle, "_CRS",
263 pci_host_generic_acpi_parse_resource, (void *)dev);
264 if (ACPI_FAILURE(status))
267 /* Coherency attribute */
268 if (ACPI_FAILURE(acpi_GetInteger(handle, "_CCA", &sc->base.coherent)))
269 sc->base.coherent = 0;
271 device_printf(dev, "Bus is%s cache-coherent\n",
272 sc->base.coherent ? "" : " not");
274 /* add config space resource */
275 pci_host_acpi_get_ecam_resource(dev);
276 acpi_pcib_fetch_prt(dev, &sc->ap_prt);
278 error = pci_host_generic_core_attach(dev);
282 for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) {
283 phys_base = sc->base.ranges[tuple].phys_base;
284 pci_base = sc->base.ranges[tuple].pci_base;
285 size = sc->base.ranges[tuple].size;
286 if (phys_base == 0 || size == 0)
287 continue; /* empty range element */
288 if (sc->base.ranges[tuple].flags & FLAG_MEM) {
289 error = rman_manage_region(&sc->base.mem_rman,
290 pci_base, pci_base + size - 1);
291 } else if (sc->base.ranges[tuple].flags & FLAG_IO) {
292 error = rman_manage_region(&sc->base.io_rman,
293 pci_base + PCI_IO_WINDOW_OFFSET,
294 pci_base + PCI_IO_WINDOW_OFFSET + size - 1);
298 device_printf(dev, "rman_manage_region() failed."
299 "error = %d\n", error);
300 rman_fini(&sc->base.mem_rman);
309 pci_host_generic_acpi_attach(device_t dev)
313 error = pci_host_generic_acpi_init(dev);
317 device_add_child(dev, "pci", -1);
318 return (bus_generic_attach(dev));
322 generic_pcie_acpi_read_ivar(device_t dev, device_t child, int index,
325 struct generic_pcie_acpi_softc *sc;
327 sc = device_get_softc(dev);
329 if (index == PCIB_IVAR_BUS) {
330 *result = sc->base.bus_start;
334 if (index == PCIB_IVAR_DOMAIN) {
335 *result = sc->base.ecam;
340 device_printf(dev, "ERROR: Unknown index %d.\n", index);
345 generic_pcie_acpi_route_interrupt(device_t bus, device_t dev, int pin)
347 struct generic_pcie_acpi_softc *sc;
349 sc = device_get_softc(bus);
350 return (acpi_pcib_route_interrupt(bus, dev, pin, &sc->ap_prt));
354 generic_pcie_get_xref(device_t pci, device_t child)
356 struct generic_pcie_acpi_softc *sc;
361 sc = device_get_softc(pci);
362 err = pcib_get_id(pci, child, PCI_ID_RID, &rid);
364 return (ACPI_MSI_XREF);
365 err = acpi_iort_map_pci_msi(sc->base.ecam, rid, &xref, &devid);
367 return (ACPI_MSI_XREF);
372 generic_pcie_map_id(device_t pci, device_t child, uintptr_t *id)
374 struct generic_pcie_acpi_softc *sc;
379 sc = device_get_softc(pci);
380 err = pcib_get_id(pci, child, PCI_ID_RID, &rid);
383 err = acpi_iort_map_pci_msi(sc->base.ecam, rid, &xref, &devid);
387 *id = rid; /* RID not in IORT, likely FW bug, ignore */
392 generic_pcie_acpi_alloc_msi(device_t pci, device_t child, int count,
393 int maxcount, int *irqs)
397 return (intr_alloc_msi(pci, child, generic_pcie_get_xref(pci, child),
398 count, maxcount, irqs));
405 generic_pcie_acpi_release_msi(device_t pci, device_t child, int count,
410 return (intr_release_msi(pci, child, generic_pcie_get_xref(pci, child),
418 generic_pcie_acpi_map_msi(device_t pci, device_t child, int irq, uint64_t *addr,
423 return (intr_map_msi(pci, child, generic_pcie_get_xref(pci, child), irq,
431 generic_pcie_acpi_alloc_msix(device_t pci, device_t child, int *irq)
435 return (intr_alloc_msix(pci, child, generic_pcie_get_xref(pci, child),
443 generic_pcie_acpi_release_msix(device_t pci, device_t child, int irq)
447 return (intr_release_msix(pci, child, generic_pcie_get_xref(pci, child),
455 generic_pcie_acpi_get_id(device_t pci, device_t child, enum pci_id_type type,
459 if (type == PCI_ID_MSI)
460 return (generic_pcie_map_id(pci, child, id));
462 return (pcib_get_id(pci, child, type, id));
465 static device_method_t generic_pcie_acpi_methods[] = {
466 DEVMETHOD(device_probe, generic_pcie_acpi_probe),
467 DEVMETHOD(device_attach, pci_host_generic_acpi_attach),
468 DEVMETHOD(bus_read_ivar, generic_pcie_acpi_read_ivar),
471 DEVMETHOD(pcib_route_interrupt, generic_pcie_acpi_route_interrupt),
472 DEVMETHOD(pcib_alloc_msi, generic_pcie_acpi_alloc_msi),
473 DEVMETHOD(pcib_release_msi, generic_pcie_acpi_release_msi),
474 DEVMETHOD(pcib_alloc_msix, generic_pcie_acpi_alloc_msix),
475 DEVMETHOD(pcib_release_msix, generic_pcie_acpi_release_msix),
476 DEVMETHOD(pcib_map_msi, generic_pcie_acpi_map_msi),
477 DEVMETHOD(pcib_get_id, generic_pcie_acpi_get_id),
482 DEFINE_CLASS_1(pcib, generic_pcie_acpi_driver, generic_pcie_acpi_methods,
483 sizeof(struct generic_pcie_acpi_softc), generic_pcie_core_driver);
485 static devclass_t generic_pcie_acpi_devclass;
487 DRIVER_MODULE(pcib, acpi, generic_pcie_acpi_driver, generic_pcie_acpi_devclass,