2 * Copyright (C) 2018 Cavium Inc.
3 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
4 * Copyright (c) 2014 The FreeBSD Foundation
7 * This software was developed by Semihalf under
8 * the sponsorship of the FreeBSD Foundation.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 /* Generic ECAM PCIe driver */
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include "opt_platform.h"
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/malloc.h>
42 #include <sys/kernel.h>
44 #include <sys/module.h>
46 #include <sys/endian.h>
47 #include <sys/cpuset.h>
48 #include <sys/rwlock.h>
50 #include <contrib/dev/acpica/include/acpi.h>
51 #include <contrib/dev/acpica/include/accommon.h>
53 #include <dev/acpica/acpivar.h>
54 #include <dev/acpica/acpi_pcibvar.h>
56 #include <dev/pci/pcivar.h>
57 #include <dev/pci/pcireg.h>
58 #include <dev/pci/pcib_private.h>
59 #include <dev/pci/pci_host_generic.h>
61 #include <machine/cpu.h>
62 #include <machine/bus.h>
63 #include <machine/intr.h>
66 #include "acpi_bus_if.h"
68 /* Assembling ECAM Configuration Address */
69 #define PCIE_BUS_SHIFT 20
70 #define PCIE_SLOT_SHIFT 15
71 #define PCIE_FUNC_SHIFT 12
72 #define PCIE_BUS_MASK 0xFF
73 #define PCIE_SLOT_MASK 0x1F
74 #define PCIE_FUNC_MASK 0x07
75 #define PCIE_REG_MASK 0xFFF
77 #define PCIE_ADDR_OFFSET(bus, slot, func, reg) \
78 ((((bus) & PCIE_BUS_MASK) << PCIE_BUS_SHIFT) | \
79 (((slot) & PCIE_SLOT_MASK) << PCIE_SLOT_SHIFT) | \
80 (((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT) | \
81 ((reg) & PCIE_REG_MASK))
83 #define PCI_IO_WINDOW_OFFSET 0x1000
85 #define SPACE_CODE_SHIFT 24
86 #define SPACE_CODE_MASK 0x3
87 #define SPACE_CODE_IO_SPACE 0x1
88 #define PROPS_CELL_SIZE 1
89 #define PCI_ADDR_CELL_SIZE 2
91 struct generic_pcie_acpi_softc {
92 struct generic_pcie_core_softc base;
93 ACPI_BUFFER ap_prt; /* interrupt routing table */
96 /* Forward prototypes */
98 static int generic_pcie_acpi_probe(device_t dev);
99 static ACPI_STATUS pci_host_generic_acpi_parse_resource(ACPI_RESOURCE *, void *);
100 static int generic_pcie_acpi_read_ivar(device_t, device_t, int, uintptr_t *);
103 * generic_pcie_acpi_probe - look for root bridge flag
106 generic_pcie_acpi_probe(device_t dev)
108 ACPI_DEVICE_INFO *devinfo;
112 if (acpi_disabled("pcib") || (h = acpi_get_handle(dev)) == NULL ||
113 ACPI_FAILURE(AcpiGetObjectInfo(h, &devinfo)))
115 root = (devinfo->Flags & ACPI_PCI_ROOT_BRIDGE) != 0;
120 device_set_desc(dev, "Generic PCI host controller");
121 return (BUS_PROBE_GENERIC);
125 * pci_host_generic_acpi_parse_resource - parse PCI memory, IO and bus spaces
126 * 'produced' by this bridge
129 pci_host_generic_acpi_parse_resource(ACPI_RESOURCE *res, void *arg)
131 device_t dev = (device_t)arg;
132 struct generic_pcie_acpi_softc *sc;
134 rman_res_t min, max, off;
138 sc = device_get_softc(dev);
139 r = sc->base.nranges;
141 case ACPI_RESOURCE_TYPE_ADDRESS16:
142 min = res->Data.Address16.Address.Minimum;
143 max = res->Data.Address16.Address.Maximum;
145 case ACPI_RESOURCE_TYPE_ADDRESS32:
146 min = res->Data.Address32.Address.Minimum;
147 max = res->Data.Address32.Address.Maximum;
148 off = res->Data.Address32.Address.TranslationOffset;
150 case ACPI_RESOURCE_TYPE_ADDRESS64:
151 if (res->Data.Address.ResourceType != ACPI_MEMORY_RANGE)
153 min = res->Data.Address64.Address.Minimum;
154 max = res->Data.Address64.Address.Maximum;
155 off = res->Data.Address64.Address.TranslationOffset;
161 /* Save detected ranges */
162 if (res->Data.Address.ResourceType == ACPI_MEMORY_RANGE ||
163 res->Data.Address.ResourceType == ACPI_IO_RANGE) {
164 sc->base.ranges[r].pci_base = min;
165 sc->base.ranges[r].phys_base = min + off;
166 sc->base.ranges[r].size = max - min + 1;
167 if (res->Data.Address.ResourceType == ACPI_MEMORY_RANGE)
168 sc->base.ranges[r].flags |= FLAG_MEM;
169 else if (res->Data.Address.ResourceType == ACPI_IO_RANGE)
170 sc->base.ranges[r].flags |= FLAG_IO;
172 } else if (res->Data.Address.ResourceType == ACPI_BUS_NUMBER_RANGE) {
173 sc->base.bus_start = min;
174 sc->base.bus_end = max;
180 pci_host_acpi_get_ecam_resource(device_t dev)
182 struct generic_pcie_acpi_softc *sc;
183 struct acpi_device *ad;
184 struct resource_list *rl;
185 ACPI_TABLE_HEADER *hdr;
186 ACPI_MCFG_ALLOCATION *mcfg_entry, *mcfg_end;
189 rman_res_t base, start, end;
192 sc = device_get_softc(dev);
193 handle = acpi_get_handle(dev);
196 status = AcpiGetTable(ACPI_SIG_MCFG, 1, &hdr);
197 if (ACPI_SUCCESS(status)) {
199 mcfg_end = (ACPI_MCFG_ALLOCATION *)((char *)hdr + hdr->Length);
200 mcfg_entry = (ACPI_MCFG_ALLOCATION *)((ACPI_TABLE_MCFG *)hdr + 1);
201 while (mcfg_entry < mcfg_end && !found) {
202 if (mcfg_entry->PciSegment == sc->base.ecam &&
203 mcfg_entry->StartBusNumber <= sc->base.bus_start &&
204 mcfg_entry->EndBusNumber >= sc->base.bus_start)
210 if (mcfg_entry->EndBusNumber < sc->base.bus_end) {
211 device_printf(dev, "bus end mismatch! expected %d found %d.\n",
212 sc->base.bus_end, (int)mcfg_entry->EndBusNumber);
213 sc->base.bus_end = mcfg_entry->EndBusNumber;
215 base = mcfg_entry->Address;
217 device_printf(dev, "MCFG exists, but does not have bus %d-%d\n",
218 sc->base.bus_start, sc->base.bus_end);
222 status = acpi_GetInteger(handle, "_CBA", &val);
223 if (ACPI_SUCCESS(status))
229 /* add as MEM rid 0 */
230 ad = device_get_ivars(dev);
232 start = base + (sc->base.bus_start << PCIE_BUS_SHIFT);
233 end = base + ((sc->base.bus_end + 1) << PCIE_BUS_SHIFT) - 1;
234 resource_list_add(rl, SYS_RES_MEMORY, 0, start, end, end - start + 1);
236 device_printf(dev, "ECAM for bus %d-%d at mem %jx-%jx\n",
237 sc->base.bus_start, sc->base.bus_end, start, end);
242 pci_host_generic_acpi_attach(device_t dev)
244 struct generic_pcie_acpi_softc *sc;
253 sc = device_get_softc(dev);
254 handle = acpi_get_handle(dev);
256 /* Get Start bus number for the PCI host bus is from _BBN method */
257 status = acpi_GetInteger(handle, "_BBN", &sc->base.bus_start);
258 if (ACPI_FAILURE(status)) {
259 device_printf(dev, "No _BBN, using start bus 0\n");
260 sc->base.bus_start = 0;
262 sc->base.bus_end = 255;
264 /* Get PCI Segment (domain) needed for MCFG lookup */
265 status = acpi_GetInteger(handle, "_SEG", &sc->base.ecam);
266 if (ACPI_FAILURE(status)) {
267 device_printf(dev, "No _SEG for PCI Bus, using segment 0\n");
271 /* Bus decode ranges */
272 status = AcpiWalkResources(handle, "_CRS",
273 pci_host_generic_acpi_parse_resource, (void *)dev);
274 if (ACPI_FAILURE(status))
277 /* Coherency attribute */
278 if (ACPI_FAILURE(acpi_GetInteger(handle, "_CCA", &sc->base.coherent)))
279 sc->base.coherent = 0;
281 device_printf(dev, "Bus is%s cache-coherent\n",
282 sc->base.coherent ? "" : " not");
284 /* add config space resource */
285 pci_host_acpi_get_ecam_resource(dev);
286 acpi_pcib_fetch_prt(dev, &sc->ap_prt);
288 error = pci_host_generic_core_attach(dev);
292 for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) {
293 phys_base = sc->base.ranges[tuple].phys_base;
294 pci_base = sc->base.ranges[tuple].pci_base;
295 size = sc->base.ranges[tuple].size;
296 if (phys_base == 0 || size == 0)
297 continue; /* empty range element */
298 if (sc->base.ranges[tuple].flags & FLAG_MEM) {
299 error = rman_manage_region(&sc->base.mem_rman,
300 phys_base, phys_base + size - 1);
301 } else if (sc->base.ranges[tuple].flags & FLAG_IO) {
302 error = rman_manage_region(&sc->base.io_rman,
303 pci_base + PCI_IO_WINDOW_OFFSET,
304 pci_base + PCI_IO_WINDOW_OFFSET + size - 1);
308 device_printf(dev, "rman_manage_region() failed."
309 "error = %d\n", error);
310 rman_fini(&sc->base.mem_rman);
315 device_add_child(dev, "pci", -1);
316 return (bus_generic_attach(dev));
320 generic_pcie_acpi_read_ivar(device_t dev, device_t child, int index,
323 struct generic_pcie_acpi_softc *sc;
325 sc = device_get_softc(dev);
327 if (index == PCIB_IVAR_BUS) {
328 *result = sc->base.bus_start;
332 if (index == PCIB_IVAR_DOMAIN) {
333 *result = sc->base.ecam;
338 device_printf(dev, "ERROR: Unknown index %d.\n", index);
343 generic_pcie_acpi_route_interrupt(device_t bus, device_t dev, int pin)
345 struct generic_pcie_acpi_softc *sc;
347 sc = device_get_softc(bus);
348 return (acpi_pcib_route_interrupt(bus, dev, pin, &sc->ap_prt));
352 generic_pcie_get_xref(device_t pci, device_t child)
354 struct generic_pcie_acpi_softc *sc;
359 sc = device_get_softc(pci);
360 err = pcib_get_id(pci, child, PCI_ID_RID, &rid);
362 return (ACPI_MSI_XREF);
363 err = acpi_iort_map_pci_msi(sc->base.ecam, rid, &xref, &devid);
365 return (ACPI_MSI_XREF);
370 generic_pcie_map_id(device_t pci, device_t child, uintptr_t *id)
372 struct generic_pcie_acpi_softc *sc;
377 sc = device_get_softc(pci);
378 err = pcib_get_id(pci, child, PCI_ID_RID, &rid);
381 err = acpi_iort_map_pci_msi(sc->base.ecam, rid, &xref, &devid);
385 *id = rid; /* RID not in IORT, likely FW bug, ignore */
390 generic_pcie_acpi_alloc_msi(device_t pci, device_t child, int count,
391 int maxcount, int *irqs)
395 return (intr_alloc_msi(pci, child, generic_pcie_get_xref(pci, child),
396 count, maxcount, irqs));
403 generic_pcie_acpi_release_msi(device_t pci, device_t child, int count,
408 return (intr_release_msi(pci, child, generic_pcie_get_xref(pci, child),
416 generic_pcie_acpi_map_msi(device_t pci, device_t child, int irq, uint64_t *addr,
421 return (intr_map_msi(pci, child, generic_pcie_get_xref(pci, child), irq,
429 generic_pcie_acpi_alloc_msix(device_t pci, device_t child, int *irq)
433 return (intr_alloc_msix(pci, child, generic_pcie_get_xref(pci, child),
441 generic_pcie_acpi_release_msix(device_t pci, device_t child, int irq)
445 return (intr_release_msix(pci, child, generic_pcie_get_xref(pci, child),
453 generic_pcie_acpi_get_id(device_t pci, device_t child, enum pci_id_type type,
457 if (type == PCI_ID_MSI)
458 return (generic_pcie_map_id(pci, child, id));
460 return (pcib_get_id(pci, child, type, id));
463 static device_method_t generic_pcie_acpi_methods[] = {
464 DEVMETHOD(device_probe, generic_pcie_acpi_probe),
465 DEVMETHOD(device_attach, pci_host_generic_acpi_attach),
466 DEVMETHOD(bus_read_ivar, generic_pcie_acpi_read_ivar),
469 DEVMETHOD(pcib_route_interrupt, generic_pcie_acpi_route_interrupt),
470 DEVMETHOD(pcib_alloc_msi, generic_pcie_acpi_alloc_msi),
471 DEVMETHOD(pcib_release_msi, generic_pcie_acpi_release_msi),
472 DEVMETHOD(pcib_alloc_msix, generic_pcie_acpi_alloc_msix),
473 DEVMETHOD(pcib_release_msix, generic_pcie_acpi_release_msix),
474 DEVMETHOD(pcib_map_msi, generic_pcie_acpi_map_msi),
475 DEVMETHOD(pcib_get_id, generic_pcie_acpi_get_id),
480 DEFINE_CLASS_1(pcib, generic_pcie_acpi_driver, generic_pcie_acpi_methods,
481 sizeof(struct generic_pcie_acpi_softc), generic_pcie_core_driver);
483 static devclass_t generic_pcie_acpi_devclass;
485 DRIVER_MODULE(pcib, acpi, generic_pcie_acpi_driver, generic_pcie_acpi_devclass,