2 * Copyright (C) 2018 Cavium Inc.
3 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
4 * Copyright (c) 2014 The FreeBSD Foundation
7 * This software was developed by Semihalf under
8 * the sponsorship of the FreeBSD Foundation.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 /* Generic ECAM PCIe driver */
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include "opt_platform.h"
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/malloc.h>
42 #include <sys/kernel.h>
44 #include <sys/module.h>
46 #include <sys/endian.h>
47 #include <sys/cpuset.h>
48 #include <sys/rwlock.h>
50 #include <contrib/dev/acpica/include/acpi.h>
51 #include <contrib/dev/acpica/include/accommon.h>
53 #include <dev/acpica/acpivar.h>
54 #include <dev/acpica/acpi_pcibvar.h>
56 #include <dev/pci/pcivar.h>
57 #include <dev/pci/pcireg.h>
58 #include <dev/pci/pcib_private.h>
59 #include <dev/pci/pci_host_generic.h>
61 #include <machine/cpu.h>
62 #include <machine/bus.h>
63 #include <machine/intr.h>
66 #include "acpi_bus_if.h"
68 /* Assembling ECAM Configuration Address */
69 #define PCIE_BUS_SHIFT 20
70 #define PCIE_SLOT_SHIFT 15
71 #define PCIE_FUNC_SHIFT 12
72 #define PCIE_BUS_MASK 0xFF
73 #define PCIE_SLOT_MASK 0x1F
74 #define PCIE_FUNC_MASK 0x07
75 #define PCIE_REG_MASK 0xFFF
77 #define PCIE_ADDR_OFFSET(bus, slot, func, reg) \
78 ((((bus) & PCIE_BUS_MASK) << PCIE_BUS_SHIFT) | \
79 (((slot) & PCIE_SLOT_MASK) << PCIE_SLOT_SHIFT) | \
80 (((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT) | \
81 ((reg) & PCIE_REG_MASK))
83 #define PCI_IO_WINDOW_OFFSET 0x1000
85 #define SPACE_CODE_SHIFT 24
86 #define SPACE_CODE_MASK 0x3
87 #define SPACE_CODE_IO_SPACE 0x1
88 #define PROPS_CELL_SIZE 1
89 #define PCI_ADDR_CELL_SIZE 2
91 struct generic_pcie_acpi_softc {
92 struct generic_pcie_core_softc base;
93 ACPI_BUFFER ap_prt; /* interrupt routing table */
96 /* Forward prototypes */
98 static int generic_pcie_acpi_probe(device_t dev);
99 static ACPI_STATUS pci_host_generic_acpi_parse_resource(ACPI_RESOURCE *, void *);
100 static int generic_pcie_acpi_read_ivar(device_t, device_t, int, uintptr_t *);
103 * generic_pcie_acpi_probe - look for root bridge flag
106 generic_pcie_acpi_probe(device_t dev)
108 ACPI_DEVICE_INFO *devinfo;
112 if (acpi_disabled("pcib") || (h = acpi_get_handle(dev)) == NULL ||
113 ACPI_FAILURE(AcpiGetObjectInfo(h, &devinfo)))
115 root = (devinfo->Flags & ACPI_PCI_ROOT_BRIDGE) != 0;
120 device_set_desc(dev, "Generic PCI host controller");
121 return (BUS_PROBE_GENERIC);
125 * pci_host_generic_acpi_parse_resource - parse PCI memory, IO and bus spaces
126 * 'produced' by this bridge
129 pci_host_generic_acpi_parse_resource(ACPI_RESOURCE *res, void *arg)
131 device_t dev = (device_t)arg;
132 struct generic_pcie_acpi_softc *sc;
134 rman_res_t min, max, off;
138 sc = device_get_softc(dev);
139 r = sc->base.nranges;
141 case ACPI_RESOURCE_TYPE_ADDRESS16:
142 min = res->Data.Address16.Address.Minimum;
143 max = res->Data.Address16.Address.Maximum;
145 case ACPI_RESOURCE_TYPE_ADDRESS32:
146 min = res->Data.Address32.Address.Minimum;
147 max = res->Data.Address32.Address.Maximum;
148 off = res->Data.Address32.Address.TranslationOffset;
150 case ACPI_RESOURCE_TYPE_ADDRESS64:
151 min = res->Data.Address64.Address.Minimum;
152 max = res->Data.Address64.Address.Maximum;
153 off = res->Data.Address64.Address.TranslationOffset;
159 /* Save detected ranges */
160 if (res->Data.Address.ResourceType == ACPI_MEMORY_RANGE ||
161 res->Data.Address.ResourceType == ACPI_IO_RANGE) {
162 sc->base.ranges[r].pci_base = min;
163 sc->base.ranges[r].phys_base = min + off;
164 sc->base.ranges[r].size = max - min + 1;
165 if (res->Data.Address.ResourceType == ACPI_MEMORY_RANGE)
166 sc->base.ranges[r].flags |= FLAG_MEM;
167 else if (res->Data.Address.ResourceType == ACPI_IO_RANGE)
168 sc->base.ranges[r].flags |= FLAG_IO;
170 } else if (res->Data.Address.ResourceType == ACPI_BUS_NUMBER_RANGE) {
171 sc->base.bus_start = min;
172 sc->base.bus_end = max;
178 pci_host_acpi_get_ecam_resource(device_t dev)
180 struct generic_pcie_acpi_softc *sc;
181 struct acpi_device *ad;
182 struct resource_list *rl;
183 ACPI_TABLE_HEADER *hdr;
184 ACPI_MCFG_ALLOCATION *mcfg_entry, *mcfg_end;
187 rman_res_t base, start, end;
190 sc = device_get_softc(dev);
191 handle = acpi_get_handle(dev);
194 status = AcpiGetTable(ACPI_SIG_MCFG, 1, &hdr);
195 if (ACPI_SUCCESS(status)) {
197 mcfg_end = (ACPI_MCFG_ALLOCATION *)((char *)hdr + hdr->Length);
198 mcfg_entry = (ACPI_MCFG_ALLOCATION *)((ACPI_TABLE_MCFG *)hdr + 1);
199 while (mcfg_entry < mcfg_end && !found) {
200 if (mcfg_entry->PciSegment == sc->base.ecam &&
201 mcfg_entry->StartBusNumber <= sc->base.bus_start &&
202 mcfg_entry->EndBusNumber >= sc->base.bus_start)
208 sc->base.bus_end = mcfg_entry->EndBusNumber;
209 base = mcfg_entry->Address;
211 device_printf(dev, "MCFG exists, but does not have bus %d-%d\n",
212 sc->base.bus_start, sc->base.bus_end);
216 status = acpi_GetInteger(handle, "_CBA", &val);
217 if (ACPI_SUCCESS(status)) {
219 sc->base.bus_end = 255;
224 /* add as MEM rid 0 */
225 ad = device_get_ivars(dev);
227 start = base + (sc->base.bus_start << PCIE_BUS_SHIFT);
228 end = base + ((sc->base.bus_end + 1) << PCIE_BUS_SHIFT) - 1;
229 resource_list_add(rl, SYS_RES_MEMORY, 0, start, end, end - start + 1);
231 device_printf(dev, "ECAM for bus %d-%d at mem %jx-%jx\n",
232 sc->base.bus_start, sc->base.bus_end, start, end);
237 pci_host_generic_acpi_attach(device_t dev)
239 struct generic_pcie_acpi_softc *sc;
248 sc = device_get_softc(dev);
249 handle = acpi_get_handle(dev);
251 /* Get Start bus number for the PCI host bus is from _BBN method */
252 status = acpi_GetInteger(handle, "_BBN", &sc->base.bus_start);
253 if (ACPI_FAILURE(status)) {
254 device_printf(dev, "No _BBN, using start bus 0\n");
255 sc->base.bus_start = 0;
258 /* Get PCI Segment (domain) needed for MCFG lookup */
259 status = acpi_GetInteger(handle, "_SEG", &sc->base.ecam);
260 if (ACPI_FAILURE(status)) {
261 device_printf(dev, "No _SEG for PCI Bus, using segment 0\n");
265 /* Bus decode ranges */
266 status = AcpiWalkResources(handle, "_CRS",
267 pci_host_generic_acpi_parse_resource, (void *)dev);
268 if (ACPI_FAILURE(status))
271 /* Coherency attribute */
272 if (ACPI_FAILURE(acpi_GetInteger(handle, "_CCA", &sc->base.coherent)))
273 sc->base.coherent = 0;
275 device_printf(dev, "Bus is%s cache-coherent\n",
276 sc->base.coherent ? "" : " not");
278 /* add config space resource */
279 pci_host_acpi_get_ecam_resource(dev);
280 acpi_pcib_fetch_prt(dev, &sc->ap_prt);
282 error = pci_host_generic_core_attach(dev);
286 for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) {
287 phys_base = sc->base.ranges[tuple].phys_base;
288 pci_base = sc->base.ranges[tuple].pci_base;
289 size = sc->base.ranges[tuple].size;
290 if (phys_base == 0 || size == 0)
291 continue; /* empty range element */
292 if (sc->base.ranges[tuple].flags & FLAG_MEM) {
293 error = rman_manage_region(&sc->base.mem_rman,
294 pci_base, pci_base + size - 1);
295 } else if (sc->base.ranges[tuple].flags & FLAG_IO) {
296 error = rman_manage_region(&sc->base.io_rman,
297 pci_base + PCI_IO_WINDOW_OFFSET,
298 pci_base + PCI_IO_WINDOW_OFFSET + size - 1);
302 device_printf(dev, "rman_manage_region() failed."
303 "error = %d\n", error);
304 rman_fini(&sc->base.mem_rman);
309 device_add_child(dev, "pci", -1);
310 return (bus_generic_attach(dev));
314 generic_pcie_acpi_read_ivar(device_t dev, device_t child, int index,
317 struct generic_pcie_acpi_softc *sc;
319 sc = device_get_softc(dev);
321 if (index == PCIB_IVAR_BUS) {
322 *result = sc->base.bus_start;
326 if (index == PCIB_IVAR_DOMAIN) {
327 *result = sc->base.ecam;
332 device_printf(dev, "ERROR: Unknown index %d.\n", index);
337 generic_pcie_acpi_route_interrupt(device_t bus, device_t dev, int pin)
339 struct generic_pcie_acpi_softc *sc;
341 sc = device_get_softc(bus);
342 return (acpi_pcib_route_interrupt(bus, dev, pin, &sc->ap_prt));
346 generic_pcie_get_xref(device_t pci, device_t child)
348 struct generic_pcie_acpi_softc *sc;
353 sc = device_get_softc(pci);
354 err = pcib_get_id(pci, child, PCI_ID_RID, &rid);
356 return (ACPI_MSI_XREF);
357 err = acpi_iort_map_pci_msi(sc->base.ecam, rid, &xref, &devid);
359 return (ACPI_MSI_XREF);
364 generic_pcie_map_id(device_t pci, device_t child, uintptr_t *id)
366 struct generic_pcie_acpi_softc *sc;
371 sc = device_get_softc(pci);
372 err = pcib_get_id(pci, child, PCI_ID_RID, &rid);
375 err = acpi_iort_map_pci_msi(sc->base.ecam, rid, &xref, &devid);
379 *id = rid; /* RID not in IORT, likely FW bug, ignore */
384 generic_pcie_acpi_alloc_msi(device_t pci, device_t child, int count,
385 int maxcount, int *irqs)
389 return (intr_alloc_msi(pci, child, generic_pcie_get_xref(pci, child),
390 count, maxcount, irqs));
397 generic_pcie_acpi_release_msi(device_t pci, device_t child, int count,
402 return (intr_release_msi(pci, child, generic_pcie_get_xref(pci, child),
410 generic_pcie_acpi_map_msi(device_t pci, device_t child, int irq, uint64_t *addr,
415 return (intr_map_msi(pci, child, generic_pcie_get_xref(pci, child), irq,
423 generic_pcie_acpi_alloc_msix(device_t pci, device_t child, int *irq)
427 return (intr_alloc_msix(pci, child, generic_pcie_get_xref(pci, child),
435 generic_pcie_acpi_release_msix(device_t pci, device_t child, int irq)
439 return (intr_release_msix(pci, child, generic_pcie_get_xref(pci, child),
447 generic_pcie_acpi_get_id(device_t pci, device_t child, enum pci_id_type type,
451 if (type == PCI_ID_MSI)
452 return (generic_pcie_map_id(pci, child, id));
454 return (pcib_get_id(pci, child, type, id));
457 static device_method_t generic_pcie_acpi_methods[] = {
458 DEVMETHOD(device_probe, generic_pcie_acpi_probe),
459 DEVMETHOD(device_attach, pci_host_generic_acpi_attach),
460 DEVMETHOD(bus_read_ivar, generic_pcie_acpi_read_ivar),
463 DEVMETHOD(pcib_route_interrupt, generic_pcie_acpi_route_interrupt),
464 DEVMETHOD(pcib_alloc_msi, generic_pcie_acpi_alloc_msi),
465 DEVMETHOD(pcib_release_msi, generic_pcie_acpi_release_msi),
466 DEVMETHOD(pcib_alloc_msix, generic_pcie_acpi_alloc_msix),
467 DEVMETHOD(pcib_release_msix, generic_pcie_acpi_release_msix),
468 DEVMETHOD(pcib_map_msi, generic_pcie_acpi_map_msi),
469 DEVMETHOD(pcib_get_id, generic_pcie_acpi_get_id),
474 DEFINE_CLASS_1(pcib, generic_pcie_acpi_driver, generic_pcie_acpi_methods,
475 sizeof(struct generic_pcie_acpi_softc), generic_pcie_core_driver);
477 static devclass_t generic_pcie_acpi_devclass;
479 DRIVER_MODULE(pcib, acpi, generic_pcie_acpi_driver, generic_pcie_acpi_devclass,