2 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
3 * Copyright (c) 2014,2016 The FreeBSD Foundation
6 * This software was developed by Andrew Turner under
7 * the sponsorship of the FreeBSD Foundation.
9 * This software was developed by Semihalf under
10 * the sponsorship of the FreeBSD Foundation.
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 /* Generic ECAM PCIe driver FDT attachment */
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
39 #include "opt_platform.h"
41 #include <sys/param.h>
42 #include <sys/systm.h>
44 #include <sys/kernel.h>
45 #include <sys/malloc.h>
46 #include <sys/module.h>
50 #include <machine/intr.h>
53 #include <dev/ofw/openfirm.h>
54 #include <dev/ofw/ofw_bus.h>
55 #include <dev/ofw/ofw_bus_subr.h>
56 #include <dev/ofw/ofw_pci.h>
58 #include <dev/pci/pcivar.h>
59 #include <dev/pci/pcireg.h>
60 #include <dev/pci/pcib_private.h>
61 #include <dev/pci/pci_host_generic.h>
62 #include <dev/pci/pci_host_generic_fdt.h>
64 #include <machine/intr.h>
68 #define PCI_IO_WINDOW_OFFSET 0x1000
70 #define SPACE_CODE_SHIFT 24
71 #define SPACE_CODE_MASK 0x3
72 #define SPACE_CODE_IO_SPACE 0x1
73 #define PROPS_CELL_SIZE 1
74 #define PCI_ADDR_CELL_SIZE 2
76 /* OFW bus interface */
77 struct generic_pcie_ofw_devinfo {
78 struct ofw_bus_devinfo di_dinfo;
79 struct resource_list di_rl;
82 /* Forward prototypes */
84 static int generic_pcie_fdt_probe(device_t dev);
85 static int parse_pci_mem_ranges(device_t, struct generic_pcie_core_softc *);
86 static int generic_pcie_fdt_release_resource(device_t dev, device_t child,
87 int type, int rid, struct resource *res);
88 static int generic_pcie_ofw_bus_attach(device_t);
89 static const struct ofw_bus_devinfo *generic_pcie_ofw_get_devinfo(device_t,
93 get_addr_size_cells(phandle_t node, pcell_t *addr_cells, pcell_t *size_cells)
97 /* Find address cells if present */
98 OF_getencprop(node, "#address-cells", addr_cells, sizeof(*addr_cells));
101 /* Find size cells if present */
102 OF_getencprop(node, "#size-cells", size_cells, sizeof(*size_cells));
106 generic_pcie_fdt_probe(device_t dev)
109 if (!ofw_bus_status_okay(dev))
112 if (ofw_bus_is_compatible(dev, "pci-host-ecam-generic")) {
113 device_set_desc(dev, "Generic PCI host controller");
114 return (BUS_PROBE_GENERIC);
116 if (ofw_bus_is_compatible(dev, "arm,gem5_pcie")) {
117 device_set_desc(dev, "GEM5 PCIe host controller");
118 return (BUS_PROBE_DEFAULT);
125 pci_host_generic_attach(device_t dev)
127 struct generic_pcie_fdt_softc *sc;
135 sc = device_get_softc(dev);
137 /* Retrieve 'ranges' property from FDT */
139 device_printf(dev, "parsing FDT for ECAM%d:\n", sc->base.ecam);
140 if (parse_pci_mem_ranges(dev, &sc->base))
144 if (generic_pcie_ofw_bus_attach(dev) != 0)
147 node = ofw_bus_get_node(dev);
148 if (sc->base.coherent == 0) {
149 sc->base.coherent = OF_hasprop(node, "dma-coherent");
152 device_printf(dev, "Bus is%s cache-coherent\n",
153 sc->base.coherent ? "" : " not");
155 /* TODO parse FDT bus ranges */
156 sc->base.bus_start = 0;
157 sc->base.bus_end = 0xFF;
158 error = pci_host_generic_core_attach(dev);
162 for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) {
163 phys_base = sc->base.ranges[tuple].phys_base;
164 pci_base = sc->base.ranges[tuple].pci_base;
165 size = sc->base.ranges[tuple].size;
166 if (phys_base == 0 || size == 0)
167 continue; /* empty range element */
168 if (sc->base.ranges[tuple].flags & FLAG_MEM) {
169 error = rman_manage_region(&sc->base.mem_rman,
170 phys_base, phys_base + size - 1);
171 } else if (sc->base.ranges[tuple].flags & FLAG_IO) {
172 error = rman_manage_region(&sc->base.io_rman,
173 pci_base + PCI_IO_WINDOW_OFFSET,
174 pci_base + PCI_IO_WINDOW_OFFSET + size - 1);
178 device_printf(dev, "rman_manage_region() failed."
179 "error = %d\n", error);
180 rman_fini(&sc->base.mem_rman);
185 ofw_bus_setup_iinfo(node, &sc->pci_iinfo, sizeof(cell_t));
187 device_add_child(dev, "pci", -1);
188 return (bus_generic_attach(dev));
192 parse_pci_mem_ranges(device_t dev, struct generic_pcie_core_softc *sc)
194 pcell_t pci_addr_cells, parent_addr_cells;
195 pcell_t attributes, size_cells;
202 node = ofw_bus_get_node(dev);
204 OF_getencprop(node, "#address-cells", &pci_addr_cells,
205 sizeof(pci_addr_cells));
206 OF_getencprop(node, "#size-cells", &size_cells,
208 OF_getencprop(OF_parent(node), "#address-cells", &parent_addr_cells,
209 sizeof(parent_addr_cells));
211 if (parent_addr_cells > 2 || pci_addr_cells != 3 || size_cells > 2) {
213 "Unexpected number of address or size cells in FDT\n");
217 nbase_ranges = OF_getproplen(node, "ranges");
218 sc->nranges = nbase_ranges / sizeof(cell_t) /
219 (parent_addr_cells + pci_addr_cells + size_cells);
220 base_ranges = malloc(nbase_ranges, M_DEVBUF, M_WAITOK);
221 OF_getencprop(node, "ranges", base_ranges, nbase_ranges);
223 for (i = 0, j = 0; i < sc->nranges; i++) {
224 attributes = (base_ranges[j++] >> SPACE_CODE_SHIFT) & \
226 if (attributes == SPACE_CODE_IO_SPACE) {
227 sc->ranges[i].flags |= FLAG_IO;
229 sc->ranges[i].flags |= FLAG_MEM;
232 sc->ranges[i].pci_base = 0;
233 for (k = 0; k < (pci_addr_cells - 1); k++) {
234 sc->ranges[i].pci_base <<= 32;
235 sc->ranges[i].pci_base |= base_ranges[j++];
237 sc->ranges[i].phys_base = 0;
238 for (k = 0; k < parent_addr_cells; k++) {
239 sc->ranges[i].phys_base <<= 32;
240 sc->ranges[i].phys_base |= base_ranges[j++];
242 sc->ranges[i].size = 0;
243 for (k = 0; k < size_cells; k++) {
244 sc->ranges[i].size <<= 32;
245 sc->ranges[i].size |= base_ranges[j++];
249 for (; i < MAX_RANGES_TUPLES; i++) {
250 /* zero-fill remaining tuples to mark empty elements in array */
251 sc->ranges[i].pci_base = 0;
252 sc->ranges[i].phys_base = 0;
253 sc->ranges[i].size = 0;
257 for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) {
259 "\tPCI addr: 0x%jx, CPU addr: 0x%jx, Size: 0x%jx\n",
260 sc->ranges[tuple].pci_base,
261 sc->ranges[tuple].phys_base,
262 sc->ranges[tuple].size);
266 free(base_ranges, M_DEVBUF);
271 generic_pcie_fdt_route_interrupt(device_t bus, device_t dev, int pin)
273 struct generic_pcie_fdt_softc *sc;
274 struct ofw_pci_register reg;
275 uint32_t pintr, mintr[4];
279 sc = device_get_softc(bus);
282 bzero(®, sizeof(reg));
283 reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) |
284 (pci_get_slot(dev) << OFW_PCI_PHYS_HI_DEVICESHIFT) |
285 (pci_get_function(dev) << OFW_PCI_PHYS_HI_FUNCTIONSHIFT);
287 intrcells = ofw_bus_lookup_imap(ofw_bus_get_node(dev),
288 &sc->pci_iinfo, ®, sizeof(reg), &pintr, sizeof(pintr),
289 mintr, sizeof(mintr), &iparent);
291 pintr = ofw_bus_map_intr(dev, iparent, intrcells, mintr);
295 device_printf(bus, "could not route pin %d for device %d.%d\n",
296 pin, pci_get_slot(dev), pci_get_function(dev));
297 return (PCI_INVALID_IRQ);
301 generic_pcie_fdt_release_resource(device_t dev, device_t child, int type,
302 int rid, struct resource *res)
305 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
306 if (type == PCI_RES_BUS) {
307 return (pci_host_generic_core_release_resource(dev, child, type,
312 /* For PCIe devices that do not have FDT nodes, use PCIB method */
313 if ((int)ofw_bus_get_node(child) <= 0) {
314 return (pci_host_generic_core_release_resource(dev, child, type,
318 /* For other devices use OFW method */
319 return (bus_generic_release_resource(dev, child, type, rid, res));
323 pci_host_generic_alloc_resource(device_t dev, device_t child, int type,
324 int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
326 struct generic_pcie_fdt_softc *sc;
327 struct generic_pcie_ofw_devinfo *di;
328 struct resource_list_entry *rle;
331 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
332 if (type == PCI_RES_BUS) {
333 return (pci_host_generic_core_alloc_resource(dev, child, type, rid,
334 start, end, count, flags));
338 /* For PCIe devices that do not have FDT nodes, use PCIB method */
339 if ((int)ofw_bus_get_node(child) <= 0)
340 return (pci_host_generic_core_alloc_resource(dev, child, type,
341 rid, start, end, count, flags));
343 /* For other devices use OFW method */
344 sc = device_get_softc(dev);
346 if (RMAN_IS_DEFAULT_RANGE(start, end)) {
347 if ((di = device_get_ivars(child)) == NULL)
349 if (type == SYS_RES_IOPORT)
350 type = SYS_RES_MEMORY;
352 /* Find defaults for this rid */
353 rle = resource_list_find(&di->di_rl, type, *rid);
362 if (type == SYS_RES_MEMORY) {
363 /* Remap through ranges property */
364 for (i = 0; i < MAX_RANGES_TUPLES; i++) {
365 if (start >= sc->base.ranges[i].phys_base &&
366 end < (sc->base.ranges[i].pci_base +
367 sc->base.ranges[i].size)) {
368 start -= sc->base.ranges[i].phys_base;
369 start += sc->base.ranges[i].pci_base;
370 end -= sc->base.ranges[i].phys_base;
371 end += sc->base.ranges[i].pci_base;
376 if (i == MAX_RANGES_TUPLES) {
377 device_printf(dev, "Could not map resource "
378 "%#jx-%#jx\n", start, end);
383 return (bus_generic_alloc_resource(dev, child, type, rid, start,
388 generic_pcie_fdt_alloc_msi(device_t pci, device_t child, int count,
389 int maxcount, int *irqs)
392 phandle_t msi_parent;
395 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child),
399 return (intr_alloc_msi(pci, child, msi_parent, count, maxcount,
407 generic_pcie_fdt_release_msi(device_t pci, device_t child, int count, int *irqs)
410 phandle_t msi_parent;
413 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child),
417 return (intr_release_msi(pci, child, msi_parent, count, irqs));
424 generic_pcie_fdt_map_msi(device_t pci, device_t child, int irq, uint64_t *addr,
428 phandle_t msi_parent;
431 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child),
435 return (intr_map_msi(pci, child, msi_parent, irq, addr, data));
442 generic_pcie_fdt_alloc_msix(device_t pci, device_t child, int *irq)
445 phandle_t msi_parent;
448 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child),
452 return (intr_alloc_msix(pci, child, msi_parent, irq));
459 generic_pcie_fdt_release_msix(device_t pci, device_t child, int irq)
462 phandle_t msi_parent;
465 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child),
469 return (intr_release_msix(pci, child, msi_parent, irq));
476 generic_pcie_get_id(device_t pci, device_t child, enum pci_id_type type,
484 if (type != PCI_ID_MSI)
485 return (pcib_get_id(pci, child, type, id));
487 node = ofw_bus_get_node(pci);
488 pci_rid = pci_get_rid(child);
490 err = ofw_bus_msimap(node, pci_rid, NULL, &rid);
498 static const struct ofw_bus_devinfo *
499 generic_pcie_ofw_get_devinfo(device_t bus __unused, device_t child)
501 struct generic_pcie_ofw_devinfo *di;
503 di = device_get_ivars(child);
504 return (&di->di_dinfo);
507 /* Helper functions */
510 generic_pcie_ofw_bus_attach(device_t dev)
512 struct generic_pcie_ofw_devinfo *di;
514 phandle_t parent, node;
515 pcell_t addr_cells, size_cells;
517 parent = ofw_bus_get_node(dev);
519 get_addr_size_cells(parent, &addr_cells, &size_cells);
520 /* Iterate through all bus subordinates */
521 for (node = OF_child(parent); node > 0; node = OF_peer(node)) {
523 /* Allocate and populate devinfo. */
524 di = malloc(sizeof(*di), M_DEVBUF, M_WAITOK | M_ZERO);
525 if (ofw_bus_gen_setup_devinfo(&di->di_dinfo, node) != 0) {
530 /* Initialize and populate resource list. */
531 resource_list_init(&di->di_rl);
532 ofw_bus_reg_to_rl(dev, node, addr_cells, size_cells,
534 ofw_bus_intr_to_rl(dev, node, &di->di_rl, NULL);
536 /* Add newbus device for this FDT node */
537 child = device_add_child(dev, NULL, -1);
539 resource_list_free(&di->di_rl);
540 ofw_bus_gen_destroy_devinfo(&di->di_dinfo);
545 device_set_ivars(child, di);
552 static device_method_t generic_pcie_fdt_methods[] = {
553 DEVMETHOD(device_probe, generic_pcie_fdt_probe),
554 DEVMETHOD(device_attach, pci_host_generic_attach),
555 DEVMETHOD(bus_alloc_resource, pci_host_generic_alloc_resource),
556 DEVMETHOD(bus_release_resource, generic_pcie_fdt_release_resource),
559 DEVMETHOD(pcib_route_interrupt, generic_pcie_fdt_route_interrupt),
560 DEVMETHOD(pcib_alloc_msi, generic_pcie_fdt_alloc_msi),
561 DEVMETHOD(pcib_release_msi, generic_pcie_fdt_release_msi),
562 DEVMETHOD(pcib_alloc_msix, generic_pcie_fdt_alloc_msix),
563 DEVMETHOD(pcib_release_msix, generic_pcie_fdt_release_msix),
564 DEVMETHOD(pcib_map_msi, generic_pcie_fdt_map_msi),
565 DEVMETHOD(pcib_get_id, generic_pcie_get_id),
566 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow),
568 /* ofw_bus interface */
569 DEVMETHOD(ofw_bus_get_devinfo, generic_pcie_ofw_get_devinfo),
570 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
571 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
572 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
573 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
574 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
579 DEFINE_CLASS_1(pcib, generic_pcie_fdt_driver, generic_pcie_fdt_methods,
580 sizeof(struct generic_pcie_fdt_softc), generic_pcie_core_driver);
582 static devclass_t generic_pcie_fdt_devclass;
584 DRIVER_MODULE(pcib, simplebus, generic_pcie_fdt_driver,
585 generic_pcie_fdt_devclass, 0, 0);
586 DRIVER_MODULE(pcib, ofwbus, generic_pcie_fdt_driver, generic_pcie_fdt_devclass,