2 * Copyright (c) 2013-2015 Sandvine Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
34 #include <sys/kernel.h>
35 #include <sys/systm.h>
37 #include <sys/fcntl.h>
38 #include <sys/ioccom.h>
40 #include <sys/linker.h>
41 #include <sys/malloc.h>
42 #include <sys/module.h>
43 #include <sys/pciio.h>
44 #include <sys/queue.h>
46 #include <sys/sysctl.h>
48 #include <machine/bus.h>
49 #include <machine/stdarg.h>
52 #include <sys/iov_schema.h>
54 #include <dev/pci/pcireg.h>
55 #include <dev/pci/pcivar.h>
56 #include <dev/pci/pci_iov.h>
57 #include <dev/pci/pci_private.h>
58 #include <dev/pci/pci_iov_private.h>
59 #include <dev/pci/schema_private.h>
63 static MALLOC_DEFINE(M_SRIOV, "sr_iov", "PCI SR-IOV allocations");
65 static d_ioctl_t pci_iov_ioctl;
67 static struct cdevsw iov_cdevsw = {
68 .d_version = D_VERSION,
70 .d_ioctl = pci_iov_ioctl
76 * The maximum amount of memory we will allocate for user configuration of an
77 * SR-IOV device. 1MB ought to be enough for anyone, but leave this
78 * configurable just in case.
80 static u_long pci_iov_max_config = 1024 * 1024;
81 SYSCTL_ULONG(_hw_pci, OID_AUTO, iov_max_config, CTLFLAG_RWTUN,
82 &pci_iov_max_config, 0, "Maximum allowed size of SR-IOV configuration.");
85 #define IOV_READ(d, r, w) \
86 pci_read_config((d)->cfg.dev, (d)->cfg.iov->iov_pos + r, w)
88 #define IOV_WRITE(d, r, v, w) \
89 pci_write_config((d)->cfg.dev, (d)->cfg.iov->iov_pos + r, v, w)
91 static nvlist_t *pci_iov_build_schema(nvlist_t **pf_schema,
92 nvlist_t **vf_schema);
93 static void pci_iov_build_pf_schema(nvlist_t *schema,
94 nvlist_t **driver_schema);
95 static void pci_iov_build_vf_schema(nvlist_t *schema,
96 nvlist_t **driver_schema);
97 static nvlist_t *pci_iov_get_pf_subsystem_schema(void);
98 static nvlist_t *pci_iov_get_vf_subsystem_schema(void);
101 pci_iov_attach_name(device_t dev, struct nvlist *pf_schema,
102 struct nvlist *vf_schema, const char *fmt, ...)
104 char buf[NAME_MAX + 1];
108 vsnprintf(buf, sizeof(buf), fmt, ap);
110 return (PCI_IOV_ATTACH_NAME(device_get_parent(dev), dev, pf_schema,
115 pci_iov_attach_method(device_t bus, device_t dev, nvlist_t *pf_schema,
116 nvlist_t *vf_schema, const char *name)
119 struct pci_devinfo *dinfo;
120 struct pcicfg_iov *iov;
126 dinfo = device_get_ivars(dev);
127 pcib = device_get_parent(bus);
130 error = pci_find_extcap(dev, PCIZ_SRIOV, &iov_pos);
135 version = pci_read_config(dev, iov_pos, 4);
136 if (PCI_EXTCAP_VER(version) != 1) {
139 "Unsupported version of SR-IOV (%d) detected\n",
140 PCI_EXTCAP_VER(version));
145 iov = malloc(sizeof(*dinfo->cfg.iov), M_SRIOV, M_WAITOK | M_ZERO);
148 if (dinfo->cfg.iov != NULL) {
152 iov->iov_pos = iov_pos;
154 schema = pci_iov_build_schema(&pf_schema, &vf_schema);
155 if (schema == NULL) {
160 error = pci_iov_validate_schema(schema);
163 iov->iov_schema = schema;
165 iov->iov_cdev = make_dev(&iov_cdevsw, device_get_unit(dev),
166 UID_ROOT, GID_WHEEL, 0600, "iov/%s", name);
168 if (iov->iov_cdev == NULL) {
173 dinfo->cfg.iov = iov;
174 iov->iov_cdev->si_drv1 = dinfo;
180 nvlist_destroy(schema);
181 nvlist_destroy(pf_schema);
182 nvlist_destroy(vf_schema);
189 pci_iov_detach_method(device_t bus, device_t dev)
191 struct pci_devinfo *dinfo;
192 struct pcicfg_iov *iov;
195 dinfo = device_get_ivars(dev);
196 iov = dinfo->cfg.iov;
203 if (iov->iov_num_vfs != 0 || iov->iov_flags & IOV_BUSY) {
208 dinfo->cfg.iov = NULL;
211 destroy_dev(iov->iov_cdev);
212 iov->iov_cdev = NULL;
214 nvlist_destroy(iov->iov_schema);
223 pci_iov_build_schema(nvlist_t **pf, nvlist_t **vf)
225 nvlist_t *schema, *pf_driver, *vf_driver;
227 /* We always take ownership of the schemas. */
233 schema = pci_iov_schema_alloc_node();
237 pci_iov_build_pf_schema(schema, &pf_driver);
238 pci_iov_build_vf_schema(schema, &vf_driver);
240 if (nvlist_error(schema) != 0)
246 nvlist_destroy(schema);
247 nvlist_destroy(pf_driver);
248 nvlist_destroy(vf_driver);
253 pci_iov_build_pf_schema(nvlist_t *schema, nvlist_t **driver_schema)
255 nvlist_t *pf_schema, *iov_schema;
257 pf_schema = pci_iov_schema_alloc_node();
258 if (pf_schema == NULL) {
259 nvlist_set_error(schema, ENOMEM);
263 iov_schema = pci_iov_get_pf_subsystem_schema();
266 * Note that if either *driver_schema or iov_schema is NULL, then
267 * nvlist_move_nvlist will put the schema in the error state and
268 * SR-IOV will fail to initialize later, so we don't have to explicitly
271 nvlist_move_nvlist(pf_schema, DRIVER_CONFIG_NAME, *driver_schema);
272 nvlist_move_nvlist(pf_schema, IOV_CONFIG_NAME, iov_schema);
273 nvlist_move_nvlist(schema, PF_CONFIG_NAME, pf_schema);
274 *driver_schema = NULL;
278 pci_iov_build_vf_schema(nvlist_t *schema, nvlist_t **driver_schema)
280 nvlist_t *vf_schema, *iov_schema;
282 vf_schema = pci_iov_schema_alloc_node();
283 if (vf_schema == NULL) {
284 nvlist_set_error(schema, ENOMEM);
288 iov_schema = pci_iov_get_vf_subsystem_schema();
291 * Note that if either *driver_schema or iov_schema is NULL, then
292 * nvlist_move_nvlist will put the schema in the error state and
293 * SR-IOV will fail to initialize later, so we don't have to explicitly
296 nvlist_move_nvlist(vf_schema, DRIVER_CONFIG_NAME, *driver_schema);
297 nvlist_move_nvlist(vf_schema, IOV_CONFIG_NAME, iov_schema);
298 nvlist_move_nvlist(schema, VF_SCHEMA_NAME, vf_schema);
299 *driver_schema = NULL;
303 pci_iov_get_pf_subsystem_schema(void)
307 pf = pci_iov_schema_alloc_node();
311 pci_iov_schema_add_uint16(pf, "num_vfs", IOV_SCHEMA_REQUIRED, -1);
312 pci_iov_schema_add_string(pf, "device", IOV_SCHEMA_REQUIRED, NULL);
318 pci_iov_get_vf_subsystem_schema(void)
322 vf = pci_iov_schema_alloc_node();
326 pci_iov_schema_add_bool(vf, "passthrough", IOV_SCHEMA_HASDEFAULT, 0);
332 pci_iov_alloc_bar(struct pci_devinfo *dinfo, int bar, pci_addr_t bar_shift)
334 struct resource *res;
335 struct pcicfg_iov *iov;
337 rman_res_t start, end;
341 iov = dinfo->cfg.iov;
342 dev = dinfo->cfg.dev;
343 bus = device_get_parent(dev);
344 rid = iov->iov_pos + PCIR_SRIOV_BAR(bar);
345 bar_size = 1 << bar_shift;
347 res = pci_alloc_multi_resource(bus, dev, SYS_RES_MEMORY, &rid, 0,
348 ~0, 1, iov->iov_num_vfs, RF_ACTIVE);
353 iov->iov_bar[bar].res = res;
354 iov->iov_bar[bar].bar_size = bar_size;
355 iov->iov_bar[bar].bar_shift = bar_shift;
357 start = rman_get_start(res);
358 end = rman_get_end(res);
359 return (rman_manage_region(&iov->rman, start, end));
363 pci_iov_add_bars(struct pcicfg_iov *iov, struct pci_devinfo *dinfo)
365 struct pci_iov_bar *bar;
369 for (i = 0; i <= PCIR_MAX_BAR_0; i++) {
370 bar = &iov->iov_bar[i];
371 if (bar->res != NULL) {
372 bar_start = rman_get_start(bar->res) +
373 dinfo->cfg.vf.index * bar->bar_size;
375 pci_add_bar(dinfo->cfg.dev, PCIR_BAR(i), bar_start,
382 pci_iov_parse_config(struct pcicfg_iov *iov, struct pci_iov_arg *arg,
390 packed_config = NULL;
392 if (arg->len > pci_iov_max_config) {
397 packed_config = malloc(arg->len, M_SRIOV, M_WAITOK);
399 error = copyin(arg->config, packed_config, arg->len);
403 config = nvlist_unpack(packed_config, arg->len, NV_FLAG_IGNORE_CASE);
404 if (config == NULL) {
409 error = pci_iov_schema_validate_config(iov->iov_schema, config);
413 error = nvlist_error(config);
421 nvlist_destroy(config);
422 free(packed_config, M_SRIOV);
427 * Set the ARI_EN bit in the lowest-numbered PCI function with the SR-IOV
428 * capability. This bit is only writeable on the lowest-numbered PF but
429 * affects all PFs on the device.
432 pci_iov_set_ari(device_t bus)
436 int i, error, devcount, lowest_func, lowest_pos, iov_pos, dev_func;
439 /* If ARI is disabled on the downstream port there is nothing to do. */
440 if (!PCIB_ARI_ENABLED(device_get_parent(bus)))
443 error = device_get_children(bus, &devlist, &devcount);
449 for (i = 0; i < devcount; i++) {
450 if (pci_find_extcap(devlist[i], PCIZ_SRIOV, &iov_pos) == 0) {
451 dev_func = pci_get_function(devlist[i]);
452 if (lowest == NULL || dev_func < lowest_func) {
454 lowest_func = dev_func;
455 lowest_pos = iov_pos;
459 free(devlist, M_TEMP);
462 * If we called this function some device must have the SR-IOV
465 KASSERT(lowest != NULL,
466 ("Could not find child of %s with SR-IOV capability",
467 device_get_nameunit(bus)));
469 iov_ctl = pci_read_config(lowest, lowest_pos + PCIR_SRIOV_CTL, 2);
470 iov_ctl |= PCIM_SRIOV_ARI_EN;
471 pci_write_config(lowest, lowest_pos + PCIR_SRIOV_CTL, iov_ctl, 2);
472 if ((pci_read_config(lowest, lowest_pos + PCIR_SRIOV_CTL, 2) &
473 PCIM_SRIOV_ARI_EN) == 0) {
474 device_printf(lowest, "failed to enable ARI\n");
481 pci_iov_config_page_size(struct pci_devinfo *dinfo)
483 uint32_t page_cap, page_size;
485 page_cap = IOV_READ(dinfo, PCIR_SRIOV_PAGE_CAP, 4);
488 * If the system page size is less than the smallest SR-IOV page size
489 * then round up to the smallest SR-IOV page size.
491 if (PAGE_SHIFT < PCI_SRIOV_BASE_PAGE_SHIFT)
492 page_size = (1 << 0);
494 page_size = (1 << (PAGE_SHIFT - PCI_SRIOV_BASE_PAGE_SHIFT));
496 /* Check that the device supports the system page size. */
497 if (!(page_size & page_cap))
500 IOV_WRITE(dinfo, PCIR_SRIOV_PAGE_SIZE, page_size, 4);
505 pci_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *config)
507 const nvlist_t *device, *driver_config;
509 device = nvlist_get_nvlist(config, PF_CONFIG_NAME);
510 driver_config = nvlist_get_nvlist(device, DRIVER_CONFIG_NAME);
511 return (PCI_IOV_INIT(dev, num_vfs, driver_config));
515 pci_iov_init_rman(device_t pf, struct pcicfg_iov *iov)
519 iov->rman.rm_start = 0;
520 iov->rman.rm_end = ~0;
521 iov->rman.rm_type = RMAN_ARRAY;
522 snprintf(iov->rman_name, sizeof(iov->rman_name), "%s VF I/O memory",
523 device_get_nameunit(pf));
524 iov->rman.rm_descr = iov->rman_name;
526 error = rman_init(&iov->rman);
530 iov->iov_flags |= IOV_RMAN_INITED;
535 pci_iov_alloc_bar_ea(struct pci_devinfo *dinfo, int bar)
537 struct pcicfg_iov *iov;
538 rman_res_t start, end;
539 struct resource *res;
540 struct resource_list *rl;
541 struct resource_list_entry *rle;
543 rl = &dinfo->resources;
544 iov = dinfo->cfg.iov;
546 rle = resource_list_find(rl, SYS_RES_MEMORY,
547 iov->iov_pos + PCIR_SRIOV_BAR(bar));
549 rle = resource_list_find(rl, SYS_RES_IOPORT,
550 iov->iov_pos + PCIR_SRIOV_BAR(bar));
555 iov->iov_bar[bar].res = res;
556 iov->iov_bar[bar].bar_size = rman_get_size(res) / iov->iov_num_vfs;
557 iov->iov_bar[bar].bar_shift = pci_mapsize(iov->iov_bar[bar].bar_size);
559 start = rman_get_start(res);
560 end = rman_get_end(res);
562 return (rman_manage_region(&iov->rman, start, end));
566 pci_iov_setup_bars(struct pci_devinfo *dinfo)
569 struct pcicfg_iov *iov;
570 pci_addr_t bar_value, testval;
571 int i, last_64, error;
573 iov = dinfo->cfg.iov;
574 dev = dinfo->cfg.dev;
577 pci_add_resources_ea(device_get_parent(dev), dev, 1);
579 for (i = 0; i <= PCIR_MAX_BAR_0; i++) {
580 /* First, try to use BARs allocated with EA */
581 error = pci_iov_alloc_bar_ea(dinfo, i);
585 /* Allocate legacy-BAR only if EA is not enabled */
586 if (pci_ea_is_enabled(dev, iov->iov_pos + PCIR_SRIOV_BAR(i)))
590 * If a PCI BAR is a 64-bit wide BAR, then it spans two
591 * consecutive registers. Therefore if the last BAR that
592 * we looked at was a 64-bit BAR, we need to skip this
593 * register as it's the second half of the last BAR.
597 iov->iov_pos + PCIR_SRIOV_BAR(i),
598 &bar_value, &testval, &last_64);
601 error = pci_iov_alloc_bar(dinfo, i,
602 pci_mapsize(testval));
614 pci_iov_enumerate_vfs(struct pci_devinfo *dinfo, const nvlist_t *config,
615 uint16_t first_rid, uint16_t rid_stride)
617 char device_name[VF_MAX_NAME];
618 const nvlist_t *device, *driver_config, *iov_config;
619 device_t bus, dev, vf;
620 struct pcicfg_iov *iov;
621 struct pci_devinfo *vfinfo;
623 uint16_t vid, did, next_rid;
625 iov = dinfo->cfg.iov;
626 dev = dinfo->cfg.dev;
627 bus = device_get_parent(dev);
628 next_rid = first_rid;
629 vid = pci_get_vendor(dev);
630 did = IOV_READ(dinfo, PCIR_SRIOV_VF_DID, 2);
632 for (i = 0; i < iov->iov_num_vfs; i++, next_rid += rid_stride) {
633 snprintf(device_name, sizeof(device_name), VF_PREFIX"%d", i);
634 device = nvlist_get_nvlist(config, device_name);
635 iov_config = nvlist_get_nvlist(device, IOV_CONFIG_NAME);
636 driver_config = nvlist_get_nvlist(device, DRIVER_CONFIG_NAME);
638 vf = PCI_CREATE_IOV_CHILD(bus, dev, next_rid, vid, did);
643 * If we are creating passthrough devices then force the ppt
644 * driver to attach to prevent a VF driver from claiming the
647 if (nvlist_get_bool(iov_config, "passthrough"))
648 device_set_devclass_fixed(vf, "ppt");
650 vfinfo = device_get_ivars(vf);
652 vfinfo->cfg.iov = iov;
653 vfinfo->cfg.vf.index = i;
655 pci_iov_add_bars(iov, vfinfo);
657 error = PCI_IOV_ADD_VF(dev, i, driver_config);
659 device_printf(dev, "Failed to add VF %d\n", i);
660 device_delete_child(bus, vf);
664 bus_generic_attach(bus);
668 pci_iov_config(struct cdev *cdev, struct pci_iov_arg *arg)
671 struct pci_devinfo *dinfo;
672 struct pcicfg_iov *iov;
675 uint16_t rid_off, rid_stride;
676 uint16_t first_rid, last_rid;
678 uint16_t num_vfs, total_vfs;
682 dinfo = cdev->si_drv1;
683 iov = dinfo->cfg.iov;
684 dev = dinfo->cfg.dev;
685 bus = device_get_parent(dev);
689 if ((iov->iov_flags & IOV_BUSY) || iov->iov_num_vfs != 0) {
693 iov->iov_flags |= IOV_BUSY;
695 error = pci_iov_parse_config(iov, arg, &config);
699 num_vfs = pci_iov_config_get_num_vfs(config);
700 total_vfs = IOV_READ(dinfo, PCIR_SRIOV_TOTAL_VFS, 2);
701 if (num_vfs > total_vfs) {
706 error = pci_iov_config_page_size(dinfo);
710 error = pci_iov_set_ari(bus);
714 error = pci_iov_init(dev, num_vfs, config);
719 IOV_WRITE(dinfo, PCIR_SRIOV_NUM_VFS, num_vfs, 2);
721 rid_off = IOV_READ(dinfo, PCIR_SRIOV_VF_OFF, 2);
722 rid_stride = IOV_READ(dinfo, PCIR_SRIOV_VF_STRIDE, 2);
724 first_rid = pci_get_rid(dev) + rid_off;
725 last_rid = first_rid + (num_vfs - 1) * rid_stride;
727 /* We don't yet support allocating extra bus numbers for VFs. */
728 if (pci_get_bus(dev) != PCI_RID2BUS(last_rid)) {
733 iov_ctl = IOV_READ(dinfo, PCIR_SRIOV_CTL, 2);
734 iov_ctl &= ~(PCIM_SRIOV_VF_EN | PCIM_SRIOV_VF_MSE);
735 IOV_WRITE(dinfo, PCIR_SRIOV_CTL, iov_ctl, 2);
737 error = pci_iov_init_rman(dev, iov);
741 iov->iov_num_vfs = num_vfs;
743 error = pci_iov_setup_bars(dinfo);
747 iov_ctl = IOV_READ(dinfo, PCIR_SRIOV_CTL, 2);
748 iov_ctl |= PCIM_SRIOV_VF_EN | PCIM_SRIOV_VF_MSE;
749 IOV_WRITE(dinfo, PCIR_SRIOV_CTL, iov_ctl, 2);
751 /* Per specification, we must wait 100ms before accessing VFs. */
752 pause("iov", roundup(hz, 10));
753 pci_iov_enumerate_vfs(dinfo, config, first_rid, rid_stride);
755 nvlist_destroy(config);
756 iov->iov_flags &= ~IOV_BUSY;
764 for (i = 0; i <= PCIR_MAX_BAR_0; i++) {
765 if (iov->iov_bar[i].res != NULL) {
766 pci_release_resource(bus, dev, SYS_RES_MEMORY,
767 iov->iov_pos + PCIR_SRIOV_BAR(i),
768 iov->iov_bar[i].res);
769 pci_delete_resource(bus, dev, SYS_RES_MEMORY,
770 iov->iov_pos + PCIR_SRIOV_BAR(i));
771 iov->iov_bar[i].res = NULL;
775 if (iov->iov_flags & IOV_RMAN_INITED) {
776 rman_fini(&iov->rman);
777 iov->iov_flags &= ~IOV_RMAN_INITED;
780 nvlist_destroy(config);
781 iov->iov_num_vfs = 0;
782 iov->iov_flags &= ~IOV_BUSY;
788 pci_iov_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
790 struct pcicfg_iov *iov;
792 iov = dinfo->cfg.iov;
794 IOV_WRITE(dinfo, PCIR_SRIOV_PAGE_SIZE, iov->iov_page_size, 4);
795 IOV_WRITE(dinfo, PCIR_SRIOV_NUM_VFS, iov->iov_num_vfs, 2);
796 IOV_WRITE(dinfo, PCIR_SRIOV_CTL, iov->iov_ctl, 2);
800 pci_iov_cfg_save(device_t dev, struct pci_devinfo *dinfo)
802 struct pcicfg_iov *iov;
804 iov = dinfo->cfg.iov;
806 iov->iov_page_size = IOV_READ(dinfo, PCIR_SRIOV_PAGE_SIZE, 4);
807 iov->iov_ctl = IOV_READ(dinfo, PCIR_SRIOV_CTL, 2);
810 /* Return true if child is a VF of the given PF. */
812 pci_iov_is_child_vf(struct pcicfg_iov *pf, device_t child)
814 struct pci_devinfo *vfinfo;
816 vfinfo = device_get_ivars(child);
818 if (!(vfinfo->cfg.flags & PCICFG_VF))
821 return (pf == vfinfo->cfg.iov);
825 pci_iov_delete(struct cdev *cdev)
827 device_t bus, dev, vf, *devlist;
828 struct pci_devinfo *dinfo;
829 struct pcicfg_iov *iov;
830 int i, error, devcount;
834 dinfo = cdev->si_drv1;
835 iov = dinfo->cfg.iov;
836 dev = dinfo->cfg.dev;
837 bus = device_get_parent(dev);
840 if (iov->iov_flags & IOV_BUSY) {
845 if (iov->iov_num_vfs == 0) {
850 iov->iov_flags |= IOV_BUSY;
852 error = device_get_children(bus, &devlist, &devcount);
857 for (i = 0; i < devcount; i++) {
860 if (!pci_iov_is_child_vf(iov, vf))
863 error = device_detach(vf);
866 "Could not disable SR-IOV: failed to detach VF %s\n",
867 device_get_nameunit(vf));
872 for (i = 0; i < devcount; i++) {
875 if (pci_iov_is_child_vf(iov, vf))
876 device_delete_child(bus, vf);
880 iov_ctl = IOV_READ(dinfo, PCIR_SRIOV_CTL, 2);
881 iov_ctl &= ~(PCIM_SRIOV_VF_EN | PCIM_SRIOV_VF_MSE);
882 IOV_WRITE(dinfo, PCIR_SRIOV_CTL, iov_ctl, 2);
883 IOV_WRITE(dinfo, PCIR_SRIOV_NUM_VFS, 0, 2);
885 iov->iov_num_vfs = 0;
887 for (i = 0; i <= PCIR_MAX_BAR_0; i++) {
888 if (iov->iov_bar[i].res != NULL) {
889 pci_release_resource(bus, dev, SYS_RES_MEMORY,
890 iov->iov_pos + PCIR_SRIOV_BAR(i),
891 iov->iov_bar[i].res);
892 pci_delete_resource(bus, dev, SYS_RES_MEMORY,
893 iov->iov_pos + PCIR_SRIOV_BAR(i));
894 iov->iov_bar[i].res = NULL;
898 if (iov->iov_flags & IOV_RMAN_INITED) {
899 rman_fini(&iov->rman);
900 iov->iov_flags &= ~IOV_RMAN_INITED;
905 free(devlist, M_TEMP);
906 iov->iov_flags &= ~IOV_BUSY;
912 pci_iov_get_schema_ioctl(struct cdev *cdev, struct pci_iov_schema *output)
914 struct pci_devinfo *dinfo;
916 size_t output_len, size;
922 dinfo = cdev->si_drv1;
923 packed = nvlist_pack(dinfo->cfg.iov->iov_schema, &size);
926 if (packed == NULL) {
931 output_len = output->len;
933 if (size <= output_len) {
934 error = copyout(packed, output->schema, size);
942 * If we return an error then the ioctl code won't copyout
943 * output back to userland, so we flag the error in the struct
946 output->error = EMSGSIZE;
951 free(packed, M_NVLIST);
957 pci_iov_ioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
963 return (pci_iov_config(dev, (struct pci_iov_arg *)data));
965 return (pci_iov_delete(dev));
967 return (pci_iov_get_schema_ioctl(dev,
968 (struct pci_iov_schema *)data));
975 pci_vf_alloc_mem_resource(device_t dev, device_t child, int *rid,
976 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
978 struct pci_devinfo *dinfo;
979 struct pcicfg_iov *iov;
981 struct resource *res;
982 struct resource_list_entry *rle;
983 rman_res_t bar_start, bar_end;
984 pci_addr_t bar_length;
987 dinfo = device_get_ivars(child);
988 iov = dinfo->cfg.iov;
990 map = pci_find_bar(child, *rid);
994 bar_length = 1 << map->pm_size;
995 bar_start = map->pm_value;
996 bar_end = bar_start + bar_length - 1;
998 /* Make sure that the resource fits the constraints. */
999 if (bar_start >= end || bar_end <= bar_start || count != 1)
1002 /* Clamp the resource to the constraints if necessary. */
1003 if (bar_start < start)
1007 bar_length = bar_end - bar_start + 1;
1009 res = rman_reserve_resource(&iov->rman, bar_start, bar_end,
1010 bar_length, flags, child);
1014 rle = resource_list_add(&dinfo->resources, SYS_RES_MEMORY, *rid,
1015 bar_start, bar_end, 1);
1017 rman_release_resource(res);
1021 rman_set_rid(res, *rid);
1023 if (flags & RF_ACTIVE) {
1024 error = bus_activate_resource(child, SYS_RES_MEMORY, *rid, res);
1026 resource_list_delete(&dinfo->resources, SYS_RES_MEMORY,
1028 rman_release_resource(res);
1038 pci_vf_release_mem_resource(device_t dev, device_t child, int rid,
1041 struct pci_devinfo *dinfo;
1042 struct resource_list_entry *rle;
1045 dinfo = device_get_ivars(child);
1047 if (rman_get_flags(r) & RF_ACTIVE) {
1048 error = bus_deactivate_resource(child, SYS_RES_MEMORY, rid, r);
1053 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, rid);
1056 resource_list_delete(&dinfo->resources, SYS_RES_MEMORY,
1060 return (rman_release_resource(r));