2 * Copyright (c) 2013-2015 Sandvine Inc. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
34 #include <sys/kernel.h>
35 #include <sys/systm.h>
37 #include <sys/fcntl.h>
38 #include <sys/ioccom.h>
40 #include <sys/linker.h>
41 #include <sys/malloc.h>
42 #include <sys/module.h>
43 #include <sys/pciio.h>
44 #include <sys/queue.h>
46 #include <sys/sysctl.h>
48 #include <machine/bus.h>
49 #include <machine/stdarg.h>
52 #include <sys/iov_schema.h>
54 #include <dev/pci/pcireg.h>
55 #include <dev/pci/pcivar.h>
56 #include <dev/pci/pci_private.h>
57 #include <dev/pci/pci_iov_private.h>
58 #include <dev/pci/schema_private.h>
63 static MALLOC_DEFINE(M_SRIOV, "sr_iov", "PCI SR-IOV allocations");
65 static d_ioctl_t pci_iov_ioctl;
67 static struct cdevsw iov_cdevsw = {
68 .d_version = D_VERSION,
70 .d_ioctl = pci_iov_ioctl
76 * The maximum amount of memory we will allocate for user configuration of an
77 * SR-IOV device. 1MB ought to be enough for anyone, but leave this
78 * configurable just in case.
80 static u_long pci_iov_max_config = 1024 * 1024;
81 SYSCTL_ULONG(_hw_pci, OID_AUTO, iov_max_config, CTLFLAG_RWTUN,
82 &pci_iov_max_config, 0, "Maximum allowed size of SR-IOV configuration.");
85 #define IOV_READ(d, r, w) \
86 pci_read_config((d)->cfg.dev, (d)->cfg.iov->iov_pos + r, w)
88 #define IOV_WRITE(d, r, v, w) \
89 pci_write_config((d)->cfg.dev, (d)->cfg.iov->iov_pos + r, v, w)
91 static nvlist_t *pci_iov_build_schema(nvlist_t **pf_schema,
92 nvlist_t **vf_schema);
93 static void pci_iov_build_pf_schema(nvlist_t *schema,
94 nvlist_t **driver_schema);
95 static void pci_iov_build_vf_schema(nvlist_t *schema,
96 nvlist_t **driver_schema);
97 static nvlist_t *pci_iov_get_pf_subsystem_schema(void);
98 static nvlist_t *pci_iov_get_vf_subsystem_schema(void);
101 pci_iov_attach_method(device_t bus, device_t dev, nvlist_t *pf_schema,
105 struct pci_devinfo *dinfo;
106 struct pcicfg_iov *iov;
112 dinfo = device_get_ivars(dev);
113 pcib = device_get_parent(bus);
116 error = pci_find_extcap(dev, PCIZ_SRIOV, &iov_pos);
121 version = pci_read_config(dev, iov_pos, 4);
122 if (PCI_EXTCAP_VER(version) != 1) {
125 "Unsupported version of SR-IOV (%d) detected\n",
126 PCI_EXTCAP_VER(version));
131 iov = malloc(sizeof(*dinfo->cfg.iov), M_SRIOV, M_WAITOK | M_ZERO);
134 if (dinfo->cfg.iov != NULL) {
138 iov->iov_pos = iov_pos;
140 schema = pci_iov_build_schema(&pf_schema, &vf_schema);
141 if (schema == NULL) {
145 iov->iov_schema = schema;
147 iov->iov_cdev = make_dev(&iov_cdevsw, device_get_unit(dev),
148 UID_ROOT, GID_WHEEL, 0600, "iov/%s", device_get_nameunit(dev));
150 if (iov->iov_cdev == NULL) {
155 dinfo->cfg.iov = iov;
156 iov->iov_cdev->si_drv1 = dinfo;
162 nvlist_destroy(schema);
163 nvlist_destroy(pf_schema);
164 nvlist_destroy(vf_schema);
171 pci_iov_detach_method(device_t bus, device_t dev)
173 struct pci_devinfo *dinfo;
174 struct pcicfg_iov *iov;
177 dinfo = device_get_ivars(dev);
178 iov = dinfo->cfg.iov;
185 if (iov->iov_num_vfs != 0 || iov->iov_flags & IOV_BUSY) {
190 dinfo->cfg.iov = NULL;
193 destroy_dev(iov->iov_cdev);
194 iov->iov_cdev = NULL;
196 nvlist_destroy(iov->iov_schema);
205 pci_iov_build_schema(nvlist_t **pf, nvlist_t **vf)
207 nvlist_t *schema, *pf_driver, *vf_driver;
209 /* We always take ownership of the schemas. */
215 schema = pci_iov_schema_alloc_node();
219 pci_iov_build_pf_schema(schema, &pf_driver);
220 pci_iov_build_vf_schema(schema, &vf_driver);
222 if (nvlist_error(schema) != 0)
228 nvlist_destroy(schema);
229 nvlist_destroy(pf_driver);
230 nvlist_destroy(vf_driver);
235 pci_iov_build_pf_schema(nvlist_t *schema, nvlist_t **driver_schema)
237 nvlist_t *pf_schema, *iov_schema;
239 pf_schema = pci_iov_schema_alloc_node();
240 if (pf_schema == NULL) {
241 nvlist_set_error(schema, ENOMEM);
245 iov_schema = pci_iov_get_pf_subsystem_schema();
248 * Note that if either *driver_schema or iov_schema is NULL, then
249 * nvlist_move_nvlist will put the schema in the error state and
250 * SR-IOV will fail to initialize later, so we don't have to explicitly
253 nvlist_move_nvlist(pf_schema, DRIVER_CONFIG_NAME, *driver_schema);
254 nvlist_move_nvlist(pf_schema, IOV_CONFIG_NAME, iov_schema);
255 nvlist_move_nvlist(schema, PF_CONFIG_NAME, pf_schema);
256 *driver_schema = NULL;
260 pci_iov_build_vf_schema(nvlist_t *schema, nvlist_t **driver_schema)
262 nvlist_t *vf_schema, *iov_schema;
264 vf_schema = pci_iov_schema_alloc_node();
265 if (vf_schema == NULL) {
266 nvlist_set_error(schema, ENOMEM);
270 iov_schema = pci_iov_get_vf_subsystem_schema();
273 * Note that if either *driver_schema or iov_schema is NULL, then
274 * nvlist_move_nvlist will put the schema in the error state and
275 * SR-IOV will fail to initialize later, so we don't have to explicitly
278 nvlist_move_nvlist(vf_schema, DRIVER_CONFIG_NAME, *driver_schema);
279 nvlist_move_nvlist(vf_schema, IOV_CONFIG_NAME, iov_schema);
280 nvlist_move_nvlist(schema, VF_SCHEMA_NAME, vf_schema);
281 *driver_schema = NULL;
285 pci_iov_get_pf_subsystem_schema(void)
289 pf = pci_iov_schema_alloc_node();
293 pci_iov_schema_add_uint16(pf, "num_vfs", IOV_SCHEMA_REQUIRED, -1);
294 pci_iov_schema_add_string(pf, "device", IOV_SCHEMA_REQUIRED, NULL);
300 pci_iov_get_vf_subsystem_schema(void)
304 vf = pci_iov_schema_alloc_node();
308 pci_iov_schema_add_bool(vf, "passthrough", IOV_SCHEMA_HASDEFAULT, 0);
314 pci_iov_alloc_bar(struct pci_devinfo *dinfo, int bar, pci_addr_t bar_shift)
316 struct resource *res;
317 struct pcicfg_iov *iov;
323 iov = dinfo->cfg.iov;
324 dev = dinfo->cfg.dev;
325 bus = device_get_parent(dev);
326 rid = iov->iov_pos + PCIR_SRIOV_BAR(bar);
327 bar_size = 1 << bar_shift;
329 res = pci_alloc_multi_resource(bus, dev, SYS_RES_MEMORY, &rid, 0ul,
330 ~0ul, 1, iov->iov_num_vfs, RF_ACTIVE);
335 iov->iov_bar[bar].res = res;
336 iov->iov_bar[bar].bar_size = bar_size;
337 iov->iov_bar[bar].bar_shift = bar_shift;
339 start = rman_get_start(res);
340 end = rman_get_end(res);
341 return (rman_manage_region(&iov->rman, start, end));
345 pci_iov_add_bars(struct pcicfg_iov *iov, struct pci_devinfo *dinfo)
347 struct pci_iov_bar *bar;
351 for (i = 0; i <= PCIR_MAX_BAR_0; i++) {
352 bar = &iov->iov_bar[i];
353 if (bar->res != NULL) {
354 bar_start = rman_get_start(bar->res) +
355 dinfo->cfg.vf.index * bar->bar_size;
357 pci_add_bar(dinfo->cfg.dev, PCIR_BAR(i), bar_start,
364 pci_iov_parse_config(struct pcicfg_iov *iov, struct pci_iov_arg *arg,
372 packed_config = NULL;
374 if (arg->len > pci_iov_max_config) {
379 packed_config = malloc(arg->len, M_SRIOV, M_WAITOK);
381 error = copyin(arg->config, packed_config, arg->len);
385 config = nvlist_unpack(packed_config, arg->len);
386 if (config == NULL) {
391 error = pci_iov_schema_validate_config(iov->iov_schema, config);
395 error = nvlist_error(config);
403 nvlist_destroy(config);
404 free(packed_config, M_SRIOV);
409 * Set the ARI_EN bit in the lowest-numbered PCI function with the SR-IOV
410 * capability. This bit is only writeable on the lowest-numbered PF but
411 * affects all PFs on the device.
414 pci_iov_set_ari(device_t bus)
418 int i, error, devcount, lowest_func, lowest_pos, iov_pos, dev_func;
421 /* If ARI is disabled on the downstream port there is nothing to do. */
422 if (!PCIB_ARI_ENABLED(device_get_parent(bus)))
425 error = device_get_children(bus, &devlist, &devcount);
431 for (i = 0; i < devcount; i++) {
432 if (pci_find_extcap(devlist[i], PCIZ_SRIOV, &iov_pos) == 0) {
433 dev_func = pci_get_function(devlist[i]);
434 if (lowest == NULL || dev_func < lowest_func) {
436 lowest_func = dev_func;
437 lowest_pos = iov_pos;
443 * If we called this function some device must have the SR-IOV
446 KASSERT(lowest != NULL,
447 ("Could not find child of %s with SR-IOV capability",
448 device_get_nameunit(bus)));
450 iov_ctl = pci_read_config(lowest, iov_pos + PCIR_SRIOV_CTL, 2);
451 iov_ctl |= PCIM_SRIOV_ARI_EN;
452 pci_write_config(lowest, iov_pos + PCIR_SRIOV_CTL, iov_ctl, 2);
453 free(devlist, M_TEMP);
458 pci_iov_config_page_size(struct pci_devinfo *dinfo)
460 uint32_t page_cap, page_size;
462 page_cap = IOV_READ(dinfo, PCIR_SRIOV_PAGE_CAP, 4);
465 * If the system page size is less than the smallest SR-IOV page size
466 * then round up to the smallest SR-IOV page size.
468 if (PAGE_SHIFT < PCI_SRIOV_BASE_PAGE_SHIFT)
469 page_size = (1 << 0);
471 page_size = (1 << (PAGE_SHIFT - PCI_SRIOV_BASE_PAGE_SHIFT));
473 /* Check that the device supports the system page size. */
474 if (!(page_size & page_cap))
477 IOV_WRITE(dinfo, PCIR_SRIOV_PAGE_SIZE, page_size, 4);
482 pci_init_iov(device_t dev, uint16_t num_vfs, const nvlist_t *config)
484 const nvlist_t *device, *driver_config;
486 device = nvlist_get_nvlist(config, PF_CONFIG_NAME);
487 driver_config = nvlist_get_nvlist(device, DRIVER_CONFIG_NAME);
488 return (PCI_INIT_IOV(dev, num_vfs, driver_config));
492 pci_iov_init_rman(device_t pf, struct pcicfg_iov *iov)
496 iov->rman.rm_start = 0;
497 iov->rman.rm_end = ~0ul;
498 iov->rman.rm_type = RMAN_ARRAY;
499 snprintf(iov->rman_name, sizeof(iov->rman_name), "%s VF I/O memory",
500 device_get_nameunit(pf));
501 iov->rman.rm_descr = iov->rman_name;
503 error = rman_init(&iov->rman);
507 iov->iov_flags |= IOV_RMAN_INITED;
512 pci_iov_setup_bars(struct pci_devinfo *dinfo)
515 struct pcicfg_iov *iov;
516 pci_addr_t bar_value, testval;
517 int i, last_64, error;
519 iov = dinfo->cfg.iov;
520 dev = dinfo->cfg.dev;
523 for (i = 0; i <= PCIR_MAX_BAR_0; i++) {
525 * If a PCI BAR is a 64-bit wide BAR, then it spans two
526 * consecutive registers. Therefore if the last BAR that
527 * we looked at was a 64-bit BAR, we need to skip this
528 * register as it's the second half of the last BAR.
532 iov->iov_pos + PCIR_SRIOV_BAR(i),
533 &bar_value, &testval, &last_64);
536 error = pci_iov_alloc_bar(dinfo, i,
537 pci_mapsize(testval));
549 pci_iov_enumerate_vfs(struct pci_devinfo *dinfo, const nvlist_t *config,
550 uint16_t first_rid, uint16_t rid_stride)
552 char device_name[VF_MAX_NAME];
553 const nvlist_t *device, *driver_config, *iov_config;
554 device_t bus, dev, vf;
555 struct pcicfg_iov *iov;
556 struct pci_devinfo *vfinfo;
559 uint16_t vid, did, next_rid;
561 iov = dinfo->cfg.iov;
562 dev = dinfo->cfg.dev;
563 bus = device_get_parent(dev);
564 size = dinfo->cfg.devinfo_size;
565 next_rid = first_rid;
566 vid = pci_get_vendor(dev);
567 did = IOV_READ(dinfo, PCIR_SRIOV_VF_DID, 2);
569 for (i = 0; i < iov->iov_num_vfs; i++, next_rid += rid_stride) {
570 snprintf(device_name, sizeof(device_name), VF_PREFIX"%d", i);
571 device = nvlist_get_nvlist(config, device_name);
572 iov_config = nvlist_get_nvlist(device, IOV_CONFIG_NAME);
573 driver_config = nvlist_get_nvlist(device, DRIVER_CONFIG_NAME);
575 vf = PCI_CREATE_IOV_CHILD(bus, dev, next_rid, vid, did);
580 * If we are creating passthrough devices then force the ppt
581 * driver to attach to prevent a VF driver from claiming the
584 if (nvlist_get_bool(iov_config, "passthrough"))
585 device_set_devclass(vf, "ppt");
587 vfinfo = device_get_ivars(vf);
589 vfinfo->cfg.iov = iov;
590 vfinfo->cfg.vf.index = i;
592 pci_iov_add_bars(iov, vfinfo);
594 error = PCI_ADD_VF(dev, i, driver_config);
596 device_printf(dev, "Failed to add VF %d\n", i);
597 pci_delete_child(bus, vf);
601 bus_generic_attach(bus);
605 pci_iov_config(struct cdev *cdev, struct pci_iov_arg *arg)
608 struct pci_devinfo *dinfo;
609 struct pcicfg_iov *iov;
612 uint16_t rid_off, rid_stride;
613 uint16_t first_rid, last_rid;
615 uint16_t num_vfs, total_vfs;
619 dinfo = cdev->si_drv1;
620 iov = dinfo->cfg.iov;
621 dev = dinfo->cfg.dev;
622 bus = device_get_parent(dev);
626 if ((iov->iov_flags & IOV_BUSY) || iov->iov_num_vfs != 0) {
630 iov->iov_flags |= IOV_BUSY;
632 error = pci_iov_parse_config(iov, arg, &config);
636 num_vfs = pci_iov_config_get_num_vfs(config);
637 total_vfs = IOV_READ(dinfo, PCIR_SRIOV_TOTAL_VFS, 2);
638 if (num_vfs > total_vfs) {
643 error = pci_iov_config_page_size(dinfo);
647 error = pci_iov_set_ari(bus);
651 error = pci_init_iov(dev, num_vfs, config);
656 IOV_WRITE(dinfo, PCIR_SRIOV_NUM_VFS, num_vfs, 2);
658 rid_off = IOV_READ(dinfo, PCIR_SRIOV_VF_OFF, 2);
659 rid_stride = IOV_READ(dinfo, PCIR_SRIOV_VF_STRIDE, 2);
661 first_rid = pci_get_rid(dev) + rid_off;
662 last_rid = first_rid + (num_vfs - 1) * rid_stride;
664 /* We don't yet support allocating extra bus numbers for VFs. */
665 if (pci_get_bus(dev) != PCI_RID2BUS(last_rid)) {
670 iov_ctl = IOV_READ(dinfo, PCIR_SRIOV_CTL, 2);
671 iov_ctl &= ~(PCIM_SRIOV_VF_EN | PCIM_SRIOV_VF_MSE);
672 IOV_WRITE(dinfo, PCIR_SRIOV_CTL, iov_ctl, 2);
674 error = pci_iov_init_rman(dev, iov);
678 iov->iov_num_vfs = num_vfs;
680 error = pci_iov_setup_bars(dinfo);
684 iov_ctl = IOV_READ(dinfo, PCIR_SRIOV_CTL, 2);
685 iov_ctl |= PCIM_SRIOV_VF_EN | PCIM_SRIOV_VF_MSE;
686 IOV_WRITE(dinfo, PCIR_SRIOV_CTL, iov_ctl, 2);
688 /* Per specification, we must wait 100ms before accessing VFs. */
689 pause("iov", roundup(hz, 10));
690 pci_iov_enumerate_vfs(dinfo, config, first_rid, rid_stride);
692 nvlist_destroy(config);
693 iov->iov_flags &= ~IOV_BUSY;
701 for (i = 0; i <= PCIR_MAX_BAR_0; i++) {
702 if (iov->iov_bar[i].res != NULL) {
703 pci_release_resource(bus, dev, SYS_RES_MEMORY,
704 iov->iov_pos + PCIR_SRIOV_BAR(i),
705 iov->iov_bar[i].res);
706 pci_delete_resource(bus, dev, SYS_RES_MEMORY,
707 iov->iov_pos + PCIR_SRIOV_BAR(i));
708 iov->iov_bar[i].res = NULL;
712 if (iov->iov_flags & IOV_RMAN_INITED) {
713 rman_fini(&iov->rman);
714 iov->iov_flags &= ~IOV_RMAN_INITED;
717 nvlist_destroy(config);
718 iov->iov_num_vfs = 0;
719 iov->iov_flags &= ~IOV_BUSY;
724 /* Return true if child is a VF of the given PF. */
726 pci_iov_is_child_vf(struct pcicfg_iov *pf, device_t child)
728 struct pci_devinfo *vfinfo;
730 vfinfo = device_get_ivars(child);
732 if (!(vfinfo->cfg.flags & PCICFG_VF))
735 return (pf == vfinfo->cfg.iov);
739 pci_iov_delete(struct cdev *cdev)
741 device_t bus, dev, vf, *devlist;
742 struct pci_devinfo *dinfo;
743 struct pcicfg_iov *iov;
744 int i, error, devcount;
748 dinfo = cdev->si_drv1;
749 iov = dinfo->cfg.iov;
750 dev = dinfo->cfg.dev;
751 bus = device_get_parent(dev);
754 if (iov->iov_flags & IOV_BUSY) {
759 if (iov->iov_num_vfs == 0) {
764 iov->iov_flags |= IOV_BUSY;
766 error = device_get_children(bus, &devlist, &devcount);
771 for (i = 0; i < devcount; i++) {
774 if (!pci_iov_is_child_vf(iov, vf))
777 error = device_detach(vf);
780 "Could not disable SR-IOV: failed to detach VF %s\n",
781 device_get_nameunit(vf));
786 for (i = 0; i < devcount; i++) {
789 if (pci_iov_is_child_vf(iov, vf))
790 pci_delete_child(bus, vf);
794 iov_ctl = IOV_READ(dinfo, PCIR_SRIOV_CTL, 2);
795 iov_ctl &= ~(PCIM_SRIOV_VF_EN | PCIM_SRIOV_VF_MSE);
796 IOV_WRITE(dinfo, PCIR_SRIOV_CTL, iov_ctl, 2);
797 IOV_WRITE(dinfo, PCIR_SRIOV_NUM_VFS, 0, 2);
799 iov->iov_num_vfs = 0;
801 for (i = 0; i <= PCIR_MAX_BAR_0; i++) {
802 if (iov->iov_bar[i].res != NULL) {
803 pci_release_resource(bus, dev, SYS_RES_MEMORY,
804 iov->iov_pos + PCIR_SRIOV_BAR(i),
805 iov->iov_bar[i].res);
806 pci_delete_resource(bus, dev, SYS_RES_MEMORY,
807 iov->iov_pos + PCIR_SRIOV_BAR(i));
808 iov->iov_bar[i].res = NULL;
812 if (iov->iov_flags & IOV_RMAN_INITED) {
813 rman_fini(&iov->rman);
814 iov->iov_flags &= ~IOV_RMAN_INITED;
819 free(devlist, M_TEMP);
820 iov->iov_flags &= ~IOV_BUSY;
826 pci_iov_get_schema_ioctl(struct cdev *cdev, struct pci_iov_schema *output)
828 struct pci_devinfo *dinfo;
830 size_t output_len, size;
836 dinfo = cdev->si_drv1;
837 packed = nvlist_pack(dinfo->cfg.iov->iov_schema, &size);
840 if (packed == NULL) {
845 output_len = output->len;
847 if (size <= output_len) {
848 error = copyout(packed, output->schema, size);
856 * If we return an error then the ioctl code won't copyout
857 * output back to userland, so we flag the error in the struct
860 output->error = EMSGSIZE;
865 free(packed, M_NVLIST);
871 pci_iov_ioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
877 return (pci_iov_config(dev, (struct pci_iov_arg *)data));
879 return (pci_iov_delete(dev));
881 return (pci_iov_get_schema_ioctl(dev,
882 (struct pci_iov_schema *)data));
889 pci_vf_alloc_mem_resource(device_t dev, device_t child, int *rid, u_long start,
890 u_long end, u_long count, u_int flags)
892 struct pci_devinfo *dinfo;
893 struct pcicfg_iov *iov;
895 struct resource *res;
896 struct resource_list_entry *rle;
897 u_long bar_start, bar_end;
898 pci_addr_t bar_length;
901 dinfo = device_get_ivars(child);
902 iov = dinfo->cfg.iov;
904 map = pci_find_bar(child, *rid);
908 bar_length = 1 << map->pm_size;
909 bar_start = map->pm_value;
910 bar_end = bar_start + bar_length - 1;
912 /* Make sure that the resource fits the constraints. */
913 if (bar_start >= end || bar_end <= bar_start || count != 1)
916 /* Clamp the resource to the constraints if necessary. */
917 if (bar_start < start)
921 bar_length = bar_end - bar_start + 1;
923 res = rman_reserve_resource(&iov->rman, bar_start, bar_end,
924 bar_length, flags, child);
928 rle = resource_list_add(&dinfo->resources, SYS_RES_MEMORY, *rid,
929 bar_start, bar_end, 1);
931 rman_release_resource(res);
935 rman_set_rid(res, *rid);
937 if (flags & RF_ACTIVE) {
938 error = bus_activate_resource(child, SYS_RES_MEMORY, *rid, res);
940 resource_list_delete(&dinfo->resources, SYS_RES_MEMORY,
942 rman_release_resource(res);
952 pci_vf_release_mem_resource(device_t dev, device_t child, int rid,
955 struct pci_devinfo *dinfo;
956 struct resource_list_entry *rle;
959 dinfo = device_get_ivars(child);
961 if (rman_get_flags(r) & RF_ACTIVE) {
962 error = bus_deactivate_resource(child, SYS_RES_MEMORY, rid, r);
967 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, rid);
970 resource_list_delete(&dinfo->resources, SYS_RES_MEMORY,
974 return (rman_release_resource(r));