2 * Copyright (c) 2013-2015 Sandvine Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
34 #include <sys/kernel.h>
35 #include <sys/systm.h>
37 #include <sys/fcntl.h>
38 #include <sys/ioccom.h>
40 #include <sys/linker.h>
42 #include <sys/malloc.h>
43 #include <sys/module.h>
44 #include <sys/mutex.h>
45 #include <sys/pciio.h>
46 #include <sys/queue.h>
48 #include <sys/sysctl.h>
50 #include <machine/bus.h>
51 #include <machine/stdarg.h>
54 #include <sys/iov_schema.h>
56 #include <dev/pci/pcireg.h>
57 #include <dev/pci/pcivar.h>
58 #include <dev/pci/pci_iov.h>
59 #include <dev/pci/pci_private.h>
60 #include <dev/pci/pci_iov_private.h>
61 #include <dev/pci/schema_private.h>
65 static MALLOC_DEFINE(M_SRIOV, "sr_iov", "PCI SR-IOV allocations");
67 static d_ioctl_t pci_iov_ioctl;
69 static struct cdevsw iov_cdevsw = {
70 .d_version = D_VERSION,
72 .d_ioctl = pci_iov_ioctl
78 * The maximum amount of memory we will allocate for user configuration of an
79 * SR-IOV device. 1MB ought to be enough for anyone, but leave this
80 * configurable just in case.
82 static u_long pci_iov_max_config = 1024 * 1024;
83 SYSCTL_ULONG(_hw_pci, OID_AUTO, iov_max_config, CTLFLAG_RWTUN,
84 &pci_iov_max_config, 0, "Maximum allowed size of SR-IOV configuration.");
86 #define IOV_READ(d, r, w) \
87 pci_read_config((d)->cfg.dev, (d)->cfg.iov->iov_pos + r, w)
89 #define IOV_WRITE(d, r, v, w) \
90 pci_write_config((d)->cfg.dev, (d)->cfg.iov->iov_pos + r, v, w)
92 static nvlist_t *pci_iov_build_schema(nvlist_t **pf_schema,
93 nvlist_t **vf_schema);
94 static void pci_iov_build_pf_schema(nvlist_t *schema,
95 nvlist_t **driver_schema);
96 static void pci_iov_build_vf_schema(nvlist_t *schema,
97 nvlist_t **driver_schema);
98 static nvlist_t *pci_iov_get_pf_subsystem_schema(void);
99 static nvlist_t *pci_iov_get_vf_subsystem_schema(void);
102 pci_iov_attach_name(device_t dev, struct nvlist *pf_schema,
103 struct nvlist *vf_schema, const char *fmt, ...)
105 char buf[NAME_MAX + 1];
109 vsnprintf(buf, sizeof(buf), fmt, ap);
111 return (PCI_IOV_ATTACH(device_get_parent(dev), dev, pf_schema,
116 pci_iov_attach_method(device_t bus, device_t dev, nvlist_t *pf_schema,
117 nvlist_t *vf_schema, const char *name)
120 struct pci_devinfo *dinfo;
121 struct pcicfg_iov *iov;
127 dinfo = device_get_ivars(dev);
128 pcib = device_get_parent(bus);
131 error = pci_find_extcap(dev, PCIZ_SRIOV, &iov_pos);
136 version = pci_read_config(dev, iov_pos, 4);
137 if (PCI_EXTCAP_VER(version) != 1) {
140 "Unsupported version of SR-IOV (%d) detected\n",
141 PCI_EXTCAP_VER(version));
146 iov = malloc(sizeof(*dinfo->cfg.iov), M_SRIOV, M_WAITOK | M_ZERO);
149 if (dinfo->cfg.iov != NULL) {
153 iov->iov_pos = iov_pos;
155 schema = pci_iov_build_schema(&pf_schema, &vf_schema);
156 if (schema == NULL) {
161 error = pci_iov_validate_schema(schema);
164 iov->iov_schema = schema;
166 iov->iov_cdev = make_dev(&iov_cdevsw, device_get_unit(dev),
167 UID_ROOT, GID_WHEEL, 0600, "iov/%s", name);
169 if (iov->iov_cdev == NULL) {
174 dinfo->cfg.iov = iov;
175 iov->iov_cdev->si_drv1 = dinfo;
181 nvlist_destroy(schema);
182 nvlist_destroy(pf_schema);
183 nvlist_destroy(vf_schema);
190 pci_iov_detach_method(device_t bus, device_t dev)
192 struct pci_devinfo *dinfo;
193 struct pcicfg_iov *iov;
196 dinfo = device_get_ivars(dev);
197 iov = dinfo->cfg.iov;
204 if (iov->iov_num_vfs != 0 || iov->iov_flags & IOV_BUSY) {
209 dinfo->cfg.iov = NULL;
212 destroy_dev(iov->iov_cdev);
213 iov->iov_cdev = NULL;
215 nvlist_destroy(iov->iov_schema);
224 pci_iov_build_schema(nvlist_t **pf, nvlist_t **vf)
226 nvlist_t *schema, *pf_driver, *vf_driver;
228 /* We always take ownership of the schemas. */
234 schema = pci_iov_schema_alloc_node();
238 pci_iov_build_pf_schema(schema, &pf_driver);
239 pci_iov_build_vf_schema(schema, &vf_driver);
241 if (nvlist_error(schema) != 0)
247 nvlist_destroy(schema);
248 nvlist_destroy(pf_driver);
249 nvlist_destroy(vf_driver);
254 pci_iov_build_pf_schema(nvlist_t *schema, nvlist_t **driver_schema)
256 nvlist_t *pf_schema, *iov_schema;
258 pf_schema = pci_iov_schema_alloc_node();
259 if (pf_schema == NULL) {
260 nvlist_set_error(schema, ENOMEM);
264 iov_schema = pci_iov_get_pf_subsystem_schema();
267 * Note that if either *driver_schema or iov_schema is NULL, then
268 * nvlist_move_nvlist will put the schema in the error state and
269 * SR-IOV will fail to initialize later, so we don't have to explicitly
272 nvlist_move_nvlist(pf_schema, DRIVER_CONFIG_NAME, *driver_schema);
273 nvlist_move_nvlist(pf_schema, IOV_CONFIG_NAME, iov_schema);
274 nvlist_move_nvlist(schema, PF_CONFIG_NAME, pf_schema);
275 *driver_schema = NULL;
279 pci_iov_build_vf_schema(nvlist_t *schema, nvlist_t **driver_schema)
281 nvlist_t *vf_schema, *iov_schema;
283 vf_schema = pci_iov_schema_alloc_node();
284 if (vf_schema == NULL) {
285 nvlist_set_error(schema, ENOMEM);
289 iov_schema = pci_iov_get_vf_subsystem_schema();
292 * Note that if either *driver_schema or iov_schema is NULL, then
293 * nvlist_move_nvlist will put the schema in the error state and
294 * SR-IOV will fail to initialize later, so we don't have to explicitly
297 nvlist_move_nvlist(vf_schema, DRIVER_CONFIG_NAME, *driver_schema);
298 nvlist_move_nvlist(vf_schema, IOV_CONFIG_NAME, iov_schema);
299 nvlist_move_nvlist(schema, VF_SCHEMA_NAME, vf_schema);
300 *driver_schema = NULL;
304 pci_iov_get_pf_subsystem_schema(void)
308 pf = pci_iov_schema_alloc_node();
312 pci_iov_schema_add_uint16(pf, "num_vfs", IOV_SCHEMA_REQUIRED, -1);
313 pci_iov_schema_add_string(pf, "device", IOV_SCHEMA_REQUIRED, NULL);
319 pci_iov_get_vf_subsystem_schema(void)
323 vf = pci_iov_schema_alloc_node();
327 pci_iov_schema_add_bool(vf, "passthrough", IOV_SCHEMA_HASDEFAULT, 0);
333 pci_iov_alloc_bar(struct pci_devinfo *dinfo, int bar, pci_addr_t bar_shift)
335 struct resource *res;
336 struct pcicfg_iov *iov;
338 rman_res_t start, end;
342 iov = dinfo->cfg.iov;
343 dev = dinfo->cfg.dev;
344 bus = device_get_parent(dev);
345 rid = iov->iov_pos + PCIR_SRIOV_BAR(bar);
346 bar_size = 1 << bar_shift;
348 res = pci_alloc_multi_resource(bus, dev, SYS_RES_MEMORY, &rid, 0,
349 ~0, 1, iov->iov_num_vfs, RF_ACTIVE);
354 iov->iov_bar[bar].res = res;
355 iov->iov_bar[bar].bar_size = bar_size;
356 iov->iov_bar[bar].bar_shift = bar_shift;
358 start = rman_get_start(res);
359 end = rman_get_end(res);
360 return (rman_manage_region(&iov->rman, start, end));
364 pci_iov_add_bars(struct pcicfg_iov *iov, struct pci_devinfo *dinfo)
366 struct pci_iov_bar *bar;
370 for (i = 0; i <= PCIR_MAX_BAR_0; i++) {
371 bar = &iov->iov_bar[i];
372 if (bar->res != NULL) {
373 bar_start = rman_get_start(bar->res) +
374 dinfo->cfg.vf.index * bar->bar_size;
376 pci_add_bar(dinfo->cfg.dev, PCIR_BAR(i), bar_start,
383 pci_iov_parse_config(struct pcicfg_iov *iov, struct pci_iov_arg *arg,
391 packed_config = NULL;
393 if (arg->len > pci_iov_max_config) {
398 packed_config = malloc(arg->len, M_SRIOV, M_WAITOK);
400 error = copyin(arg->config, packed_config, arg->len);
404 config = nvlist_unpack(packed_config, arg->len, NV_FLAG_IGNORE_CASE);
405 if (config == NULL) {
410 error = pci_iov_schema_validate_config(iov->iov_schema, config);
414 error = nvlist_error(config);
422 nvlist_destroy(config);
423 free(packed_config, M_SRIOV);
428 * Set the ARI_EN bit in the lowest-numbered PCI function with the SR-IOV
429 * capability. This bit is only writeable on the lowest-numbered PF but
430 * affects all PFs on the device.
433 pci_iov_set_ari(device_t bus)
437 int i, error, devcount, lowest_func, lowest_pos, iov_pos, dev_func;
440 /* If ARI is disabled on the downstream port there is nothing to do. */
441 if (!PCIB_ARI_ENABLED(device_get_parent(bus)))
444 error = device_get_children(bus, &devlist, &devcount);
450 for (i = 0; i < devcount; i++) {
451 if (pci_find_extcap(devlist[i], PCIZ_SRIOV, &iov_pos) == 0) {
452 dev_func = pci_get_function(devlist[i]);
453 if (lowest == NULL || dev_func < lowest_func) {
455 lowest_func = dev_func;
456 lowest_pos = iov_pos;
460 free(devlist, M_TEMP);
463 * If we called this function some device must have the SR-IOV
466 KASSERT(lowest != NULL,
467 ("Could not find child of %s with SR-IOV capability",
468 device_get_nameunit(bus)));
470 iov_ctl = pci_read_config(lowest, lowest_pos + PCIR_SRIOV_CTL, 2);
471 iov_ctl |= PCIM_SRIOV_ARI_EN;
472 pci_write_config(lowest, lowest_pos + PCIR_SRIOV_CTL, iov_ctl, 2);
473 if ((pci_read_config(lowest, lowest_pos + PCIR_SRIOV_CTL, 2) &
474 PCIM_SRIOV_ARI_EN) == 0) {
475 device_printf(lowest, "failed to enable ARI\n");
482 pci_iov_config_page_size(struct pci_devinfo *dinfo)
484 uint32_t page_cap, page_size;
486 page_cap = IOV_READ(dinfo, PCIR_SRIOV_PAGE_CAP, 4);
489 * If the system page size is less than the smallest SR-IOV page size
490 * then round up to the smallest SR-IOV page size.
492 if (PAGE_SHIFT < PCI_SRIOV_BASE_PAGE_SHIFT)
493 page_size = (1 << 0);
495 page_size = (1 << (PAGE_SHIFT - PCI_SRIOV_BASE_PAGE_SHIFT));
497 /* Check that the device supports the system page size. */
498 if (!(page_size & page_cap))
501 IOV_WRITE(dinfo, PCIR_SRIOV_PAGE_SIZE, page_size, 4);
506 pci_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *config)
508 const nvlist_t *device, *driver_config;
510 device = nvlist_get_nvlist(config, PF_CONFIG_NAME);
511 driver_config = nvlist_get_nvlist(device, DRIVER_CONFIG_NAME);
512 return (PCI_IOV_INIT(dev, num_vfs, driver_config));
516 pci_iov_init_rman(device_t pf, struct pcicfg_iov *iov)
520 iov->rman.rm_start = 0;
521 iov->rman.rm_end = ~0;
522 iov->rman.rm_type = RMAN_ARRAY;
523 snprintf(iov->rman_name, sizeof(iov->rman_name), "%s VF I/O memory",
524 device_get_nameunit(pf));
525 iov->rman.rm_descr = iov->rman_name;
527 error = rman_init(&iov->rman);
531 iov->iov_flags |= IOV_RMAN_INITED;
536 pci_iov_alloc_bar_ea(struct pci_devinfo *dinfo, int bar)
538 struct pcicfg_iov *iov;
539 rman_res_t start, end;
540 struct resource *res;
541 struct resource_list *rl;
542 struct resource_list_entry *rle;
544 rl = &dinfo->resources;
545 iov = dinfo->cfg.iov;
547 rle = resource_list_find(rl, SYS_RES_MEMORY,
548 iov->iov_pos + PCIR_SRIOV_BAR(bar));
550 rle = resource_list_find(rl, SYS_RES_IOPORT,
551 iov->iov_pos + PCIR_SRIOV_BAR(bar));
556 iov->iov_bar[bar].res = res;
557 iov->iov_bar[bar].bar_size = rman_get_size(res) / iov->iov_num_vfs;
558 iov->iov_bar[bar].bar_shift = pci_mapsize(iov->iov_bar[bar].bar_size);
560 start = rman_get_start(res);
561 end = rman_get_end(res);
563 return (rman_manage_region(&iov->rman, start, end));
567 pci_iov_setup_bars(struct pci_devinfo *dinfo)
570 struct pcicfg_iov *iov;
571 pci_addr_t bar_value, testval;
572 int i, last_64, error;
574 iov = dinfo->cfg.iov;
575 dev = dinfo->cfg.dev;
578 pci_add_resources_ea(device_get_parent(dev), dev, 1);
580 for (i = 0; i <= PCIR_MAX_BAR_0; i++) {
581 /* First, try to use BARs allocated with EA */
582 error = pci_iov_alloc_bar_ea(dinfo, i);
586 /* Allocate legacy-BAR only if EA is not enabled */
587 if (pci_ea_is_enabled(dev, iov->iov_pos + PCIR_SRIOV_BAR(i)))
591 * If a PCI BAR is a 64-bit wide BAR, then it spans two
592 * consecutive registers. Therefore if the last BAR that
593 * we looked at was a 64-bit BAR, we need to skip this
594 * register as it's the second half of the last BAR.
598 iov->iov_pos + PCIR_SRIOV_BAR(i),
599 &bar_value, &testval, &last_64);
602 error = pci_iov_alloc_bar(dinfo, i,
603 pci_mapsize(testval));
615 pci_iov_enumerate_vfs(struct pci_devinfo *dinfo, const nvlist_t *config,
616 uint16_t first_rid, uint16_t rid_stride)
618 char device_name[VF_MAX_NAME];
619 const nvlist_t *device, *driver_config, *iov_config;
620 device_t bus, dev, vf;
621 struct pcicfg_iov *iov;
622 struct pci_devinfo *vfinfo;
624 uint16_t vid, did, next_rid;
626 iov = dinfo->cfg.iov;
627 dev = dinfo->cfg.dev;
628 bus = device_get_parent(dev);
629 next_rid = first_rid;
630 vid = pci_get_vendor(dev);
631 did = IOV_READ(dinfo, PCIR_SRIOV_VF_DID, 2);
633 for (i = 0; i < iov->iov_num_vfs; i++, next_rid += rid_stride) {
634 snprintf(device_name, sizeof(device_name), VF_PREFIX"%d", i);
635 device = nvlist_get_nvlist(config, device_name);
636 iov_config = nvlist_get_nvlist(device, IOV_CONFIG_NAME);
637 driver_config = nvlist_get_nvlist(device, DRIVER_CONFIG_NAME);
639 vf = PCI_CREATE_IOV_CHILD(bus, dev, next_rid, vid, did);
644 * If we are creating passthrough devices then force the ppt
645 * driver to attach to prevent a VF driver from claiming the
648 if (nvlist_get_bool(iov_config, "passthrough"))
649 device_set_devclass_fixed(vf, "ppt");
651 vfinfo = device_get_ivars(vf);
653 vfinfo->cfg.iov = iov;
654 vfinfo->cfg.vf.index = i;
656 pci_iov_add_bars(iov, vfinfo);
658 error = PCI_IOV_ADD_VF(dev, i, driver_config);
660 device_printf(dev, "Failed to add VF %d\n", i);
661 device_delete_child(bus, vf);
665 bus_generic_attach(bus);
669 pci_iov_config(struct cdev *cdev, struct pci_iov_arg *arg)
672 struct pci_devinfo *dinfo;
673 struct pcicfg_iov *iov;
676 uint16_t rid_off, rid_stride;
677 uint16_t first_rid, last_rid;
679 uint16_t num_vfs, total_vfs;
683 dinfo = cdev->si_drv1;
684 iov = dinfo->cfg.iov;
685 dev = dinfo->cfg.dev;
686 bus = device_get_parent(dev);
690 if ((iov->iov_flags & IOV_BUSY) || iov->iov_num_vfs != 0) {
694 iov->iov_flags |= IOV_BUSY;
696 error = pci_iov_parse_config(iov, arg, &config);
700 num_vfs = pci_iov_config_get_num_vfs(config);
701 total_vfs = IOV_READ(dinfo, PCIR_SRIOV_TOTAL_VFS, 2);
702 if (num_vfs > total_vfs) {
707 error = pci_iov_config_page_size(dinfo);
711 error = pci_iov_set_ari(bus);
715 error = pci_iov_init(dev, num_vfs, config);
720 IOV_WRITE(dinfo, PCIR_SRIOV_NUM_VFS, num_vfs, 2);
722 rid_off = IOV_READ(dinfo, PCIR_SRIOV_VF_OFF, 2);
723 rid_stride = IOV_READ(dinfo, PCIR_SRIOV_VF_STRIDE, 2);
725 first_rid = pci_get_rid(dev) + rid_off;
726 last_rid = first_rid + (num_vfs - 1) * rid_stride;
728 /* We don't yet support allocating extra bus numbers for VFs. */
729 if (pci_get_bus(dev) != PCI_RID2BUS(last_rid)) {
734 iov_ctl = IOV_READ(dinfo, PCIR_SRIOV_CTL, 2);
735 iov_ctl &= ~(PCIM_SRIOV_VF_EN | PCIM_SRIOV_VF_MSE);
736 IOV_WRITE(dinfo, PCIR_SRIOV_CTL, iov_ctl, 2);
738 error = pci_iov_init_rman(dev, iov);
742 iov->iov_num_vfs = num_vfs;
744 error = pci_iov_setup_bars(dinfo);
748 iov_ctl = IOV_READ(dinfo, PCIR_SRIOV_CTL, 2);
749 iov_ctl |= PCIM_SRIOV_VF_EN | PCIM_SRIOV_VF_MSE;
750 IOV_WRITE(dinfo, PCIR_SRIOV_CTL, iov_ctl, 2);
752 /* Per specification, we must wait 100ms before accessing VFs. */
753 pause("iov", roundup(hz, 10));
754 pci_iov_enumerate_vfs(dinfo, config, first_rid, rid_stride);
756 nvlist_destroy(config);
757 iov->iov_flags &= ~IOV_BUSY;
765 for (i = 0; i <= PCIR_MAX_BAR_0; i++) {
766 if (iov->iov_bar[i].res != NULL) {
767 pci_release_resource(bus, dev, SYS_RES_MEMORY,
768 iov->iov_pos + PCIR_SRIOV_BAR(i),
769 iov->iov_bar[i].res);
770 pci_delete_resource(bus, dev, SYS_RES_MEMORY,
771 iov->iov_pos + PCIR_SRIOV_BAR(i));
772 iov->iov_bar[i].res = NULL;
776 if (iov->iov_flags & IOV_RMAN_INITED) {
777 rman_fini(&iov->rman);
778 iov->iov_flags &= ~IOV_RMAN_INITED;
781 nvlist_destroy(config);
782 iov->iov_num_vfs = 0;
783 iov->iov_flags &= ~IOV_BUSY;
789 pci_iov_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
791 struct pcicfg_iov *iov;
793 iov = dinfo->cfg.iov;
795 IOV_WRITE(dinfo, PCIR_SRIOV_PAGE_SIZE, iov->iov_page_size, 4);
796 IOV_WRITE(dinfo, PCIR_SRIOV_NUM_VFS, iov->iov_num_vfs, 2);
797 IOV_WRITE(dinfo, PCIR_SRIOV_CTL, iov->iov_ctl, 2);
801 pci_iov_cfg_save(device_t dev, struct pci_devinfo *dinfo)
803 struct pcicfg_iov *iov;
805 iov = dinfo->cfg.iov;
807 iov->iov_page_size = IOV_READ(dinfo, PCIR_SRIOV_PAGE_SIZE, 4);
808 iov->iov_ctl = IOV_READ(dinfo, PCIR_SRIOV_CTL, 2);
811 /* Return true if child is a VF of the given PF. */
813 pci_iov_is_child_vf(struct pcicfg_iov *pf, device_t child)
815 struct pci_devinfo *vfinfo;
817 vfinfo = device_get_ivars(child);
819 if (!(vfinfo->cfg.flags & PCICFG_VF))
822 return (pf == vfinfo->cfg.iov);
826 pci_iov_delete(struct cdev *cdev)
828 device_t bus, dev, vf, *devlist;
829 struct pci_devinfo *dinfo;
830 struct pcicfg_iov *iov;
831 int i, error, devcount;
835 dinfo = cdev->si_drv1;
836 iov = dinfo->cfg.iov;
837 dev = dinfo->cfg.dev;
838 bus = device_get_parent(dev);
841 if (iov->iov_flags & IOV_BUSY) {
846 if (iov->iov_num_vfs == 0) {
851 iov->iov_flags |= IOV_BUSY;
853 error = device_get_children(bus, &devlist, &devcount);
858 for (i = 0; i < devcount; i++) {
861 if (!pci_iov_is_child_vf(iov, vf))
864 error = device_detach(vf);
867 "Could not disable SR-IOV: failed to detach VF %s\n",
868 device_get_nameunit(vf));
873 for (i = 0; i < devcount; i++) {
876 if (pci_iov_is_child_vf(iov, vf))
877 device_delete_child(bus, vf);
881 iov_ctl = IOV_READ(dinfo, PCIR_SRIOV_CTL, 2);
882 iov_ctl &= ~(PCIM_SRIOV_VF_EN | PCIM_SRIOV_VF_MSE);
883 IOV_WRITE(dinfo, PCIR_SRIOV_CTL, iov_ctl, 2);
884 IOV_WRITE(dinfo, PCIR_SRIOV_NUM_VFS, 0, 2);
886 iov->iov_num_vfs = 0;
888 for (i = 0; i <= PCIR_MAX_BAR_0; i++) {
889 if (iov->iov_bar[i].res != NULL) {
890 pci_release_resource(bus, dev, SYS_RES_MEMORY,
891 iov->iov_pos + PCIR_SRIOV_BAR(i),
892 iov->iov_bar[i].res);
893 pci_delete_resource(bus, dev, SYS_RES_MEMORY,
894 iov->iov_pos + PCIR_SRIOV_BAR(i));
895 iov->iov_bar[i].res = NULL;
899 if (iov->iov_flags & IOV_RMAN_INITED) {
900 rman_fini(&iov->rman);
901 iov->iov_flags &= ~IOV_RMAN_INITED;
906 free(devlist, M_TEMP);
907 iov->iov_flags &= ~IOV_BUSY;
913 pci_iov_get_schema_ioctl(struct cdev *cdev, struct pci_iov_schema *output)
915 struct pci_devinfo *dinfo;
917 size_t output_len, size;
923 dinfo = cdev->si_drv1;
924 packed = nvlist_pack(dinfo->cfg.iov->iov_schema, &size);
927 if (packed == NULL) {
932 output_len = output->len;
934 if (size <= output_len) {
935 error = copyout(packed, output->schema, size);
943 * If we return an error then the ioctl code won't copyout
944 * output back to userland, so we flag the error in the struct
947 output->error = EMSGSIZE;
952 free(packed, M_NVLIST);
958 pci_iov_ioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
964 return (pci_iov_config(dev, (struct pci_iov_arg *)data));
966 return (pci_iov_delete(dev));
968 return (pci_iov_get_schema_ioctl(dev,
969 (struct pci_iov_schema *)data));
976 pci_vf_alloc_mem_resource(device_t dev, device_t child, int *rid,
977 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
979 struct pci_devinfo *dinfo;
980 struct pcicfg_iov *iov;
982 struct resource *res;
983 struct resource_list_entry *rle;
984 rman_res_t bar_start, bar_end;
985 pci_addr_t bar_length;
988 dinfo = device_get_ivars(child);
989 iov = dinfo->cfg.iov;
991 map = pci_find_bar(child, *rid);
995 bar_length = 1 << map->pm_size;
996 bar_start = map->pm_value;
997 bar_end = bar_start + bar_length - 1;
999 /* Make sure that the resource fits the constraints. */
1000 if (bar_start >= end || bar_end <= bar_start || count != 1)
1003 /* Clamp the resource to the constraints if necessary. */
1004 if (bar_start < start)
1008 bar_length = bar_end - bar_start + 1;
1010 res = rman_reserve_resource(&iov->rman, bar_start, bar_end,
1011 bar_length, flags, child);
1015 rle = resource_list_add(&dinfo->resources, SYS_RES_MEMORY, *rid,
1016 bar_start, bar_end, 1);
1018 rman_release_resource(res);
1022 rman_set_rid(res, *rid);
1024 if (flags & RF_ACTIVE) {
1025 error = bus_activate_resource(child, SYS_RES_MEMORY, *rid, res);
1027 resource_list_delete(&dinfo->resources, SYS_RES_MEMORY,
1029 rman_release_resource(res);
1039 pci_vf_release_mem_resource(device_t dev, device_t child, int rid,
1042 struct pci_devinfo *dinfo;
1043 struct resource_list_entry *rle;
1046 dinfo = device_get_ivars(child);
1048 if (rman_get_flags(r) & RF_ACTIVE) {
1049 error = bus_deactivate_resource(child, SYS_RES_MEMORY, rid, r);
1054 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, rid);
1057 resource_list_delete(&dinfo->resources, SYS_RES_MEMORY,
1061 return (rman_release_resource(r));