2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000 BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
35 * PCI:PCI bridge support.
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
43 #include <machine/bus.h>
45 #include <sys/sysctl.h>
47 #include <machine/resource.h>
49 #include <dev/pci/pcivar.h>
50 #include <dev/pci/pcireg.h>
51 #include <dev/pci/pcib_private.h>
55 static int pcib_probe(device_t dev);
57 static device_method_t pcib_methods[] = {
58 /* Device interface */
59 DEVMETHOD(device_probe, pcib_probe),
60 DEVMETHOD(device_attach, pcib_attach),
61 DEVMETHOD(device_detach, bus_generic_detach),
62 DEVMETHOD(device_shutdown, bus_generic_shutdown),
63 DEVMETHOD(device_suspend, bus_generic_suspend),
64 DEVMETHOD(device_resume, bus_generic_resume),
67 DEVMETHOD(bus_print_child, bus_generic_print_child),
68 DEVMETHOD(bus_read_ivar, pcib_read_ivar),
69 DEVMETHOD(bus_write_ivar, pcib_write_ivar),
70 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
71 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
72 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
73 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
74 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
75 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
78 DEVMETHOD(pcib_maxslots, pcib_maxslots),
79 DEVMETHOD(pcib_read_config, pcib_read_config),
80 DEVMETHOD(pcib_write_config, pcib_write_config),
81 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
86 static driver_t pcib_driver = {
89 sizeof(struct pcib_softc),
92 devclass_t pcib_devclass;
94 DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0);
97 * Generic device interface
100 pcib_probe(device_t dev)
102 if ((pci_get_class(dev) == PCIC_BRIDGE) &&
103 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) {
104 device_set_desc(dev, "PCI-PCI bridge");
111 pcib_attach_common(device_t dev)
113 struct pcib_softc *sc;
116 sc = device_get_softc(dev);
120 * Get current bridge configuration.
122 sc->command = pci_read_config(dev, PCIR_COMMAND, 1);
123 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1);
124 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1);
125 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2);
126 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
127 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1);
130 * Determine current I/O decode.
132 if (sc->command & PCIM_CMD_PORTEN) {
133 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1);
134 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
135 sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2),
136 pci_read_config(dev, PCIR_IOBASEL_1, 1));
138 sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1));
141 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1);
142 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
143 sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2),
144 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
146 sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1));
151 * Determine current memory decode.
153 if (sc->command & PCIM_CMD_MEMEN) {
154 sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2));
155 sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
156 sc->pmembase = PCI_PPBMEMBASE((pci_addr_t)pci_read_config(dev, PCIR_PMBASEH_1, 4),
157 pci_read_config(dev, PCIR_PMBASEL_1, 2));
158 sc->pmemlimit = PCI_PPBMEMLIMIT((pci_addr_t)pci_read_config(dev, PCIR_PMLIMITH_1, 4),
159 pci_read_config(dev, PCIR_PMLIMITL_1, 2));
165 switch (pci_get_devid(dev)) {
166 case 0x12258086: /* Intel 82454KX/GX (Orion) */
170 supbus = pci_read_config(dev, 0x41, 1);
171 if (supbus != 0xff) {
172 sc->secbus = supbus + 1;
173 sc->subbus = supbus + 1;
179 * The i82380FB mobile docking controller is a PCI-PCI bridge,
180 * and it is a subtractive bridge. However, the ProgIf is wrong
181 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't
182 * happen. There's also a Toshiba bridge that behaves this
185 case 0x124b8086: /* Intel 82380FB Mobile */
186 case 0x060513d7: /* Toshiba ???? */
187 sc->flags |= PCIB_SUBTRACTIVE;
190 /* Compaq R3000 BIOS sets wrong subordinate bus number. */
195 cp = getenv("smbios.planar.maker");
196 if (cp == NULL || strncmp(cp, "Compal", 6) != 0)
198 cp = getenv("smbios.planar.product");
199 if (cp == NULL || strncmp(cp, "08A0", 4) != 0)
201 if (sc->subbus < 0xa) {
202 pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1);
203 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1);
210 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges,
211 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM,
212 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese.
213 * This means they act as if they were subtractively decoding
214 * bridges and pass all transactions. Mark them and real ProgIf 1
215 * parts as subtractive.
217 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 ||
218 pci_read_config(dev, PCIR_PROGIF, 1) == 1)
219 sc->flags |= PCIB_SUBTRACTIVE;
222 device_printf(dev, " secondary bus %d\n", sc->secbus);
223 device_printf(dev, " subordinate bus %d\n", sc->subbus);
224 device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit);
225 device_printf(dev, " memory decode 0x%x-0x%x\n", sc->membase, sc->memlimit);
226 device_printf(dev, " prefetched decode 0x%x-0x%x\n", sc->pmembase, sc->pmemlimit);
227 if (sc->flags & PCIB_SUBTRACTIVE)
228 device_printf(dev, " Subtractively decoded bridge.\n");
232 * XXX If the secondary bus number is zero, we should assign a bus number
233 * since the BIOS hasn't, then initialise the bridge.
237 * XXX If the subordinate bus number is less than the secondary bus number,
238 * we should pick a better value. One sensible alternative would be to
239 * pick 255; the only tradeoff here is that configuration transactions
240 * would be more widely routed than absolutely necessary.
245 pcib_attach(device_t dev)
247 struct pcib_softc *sc;
250 pcib_attach_common(dev);
251 sc = device_get_softc(dev);
252 if (sc->secbus != 0) {
253 child = device_add_child(dev, "pci", sc->secbus);
255 return(bus_generic_attach(dev));
258 /* no secondary bus; we should have fixed this */
263 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
265 struct pcib_softc *sc = device_get_softc(dev);
269 *result = sc->secbus;
276 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
278 struct pcib_softc *sc = device_get_softc(dev);
289 * Is the prefetch window open (eg, can we allocate memory in it?)
292 pcib_is_prefetch_open(struct pcib_softc *sc)
294 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit);
298 * Is the nonprefetch window open (eg, can we allocate memory in it?)
301 pcib_is_nonprefetch_open(struct pcib_softc *sc)
303 return (sc->membase > 0 && sc->membase < sc->memlimit);
307 * Is the io window open (eg, can we allocate ports in it?)
310 pcib_is_io_open(struct pcib_softc *sc)
312 return (sc->iobase > 0 && sc->iobase < sc->iolimit);
316 * We have to trap resource allocation requests and ensure that the bridge
317 * is set up to, or capable of handling them.
320 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
321 u_long start, u_long end, u_long count, u_int flags)
323 struct pcib_softc *sc = device_get_softc(dev);
327 * Fail the allocation for this range if it's not supported.
332 if (!pcib_is_io_open(sc))
334 ok = (start >= sc->iobase && end <= sc->iolimit);
337 * Make sure we allow access to VGA I/O addresses when the
338 * bridge has the "VGA Enable" bit set.
340 if (!ok && pci_is_vga_ioport_range(start, end))
341 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
343 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
345 if (start < sc->iobase)
347 if (end > sc->iolimit)
355 if (start < sc->iobase && end > sc->iolimit) {
362 device_printf(dev, "ioport: end (%lx) < start (%lx)\n",
369 device_printf(dev, "%s requested unsupported I/O "
370 "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n",
371 device_get_nameunit(child), start, end,
372 sc->iobase, sc->iolimit);
377 "%s requested I/O range 0x%lx-0x%lx: in range\n",
378 device_get_nameunit(child), start, end);
383 if (pcib_is_nonprefetch_open(sc))
384 ok = ok || (start >= sc->membase && end <= sc->memlimit);
385 if (pcib_is_prefetch_open(sc))
386 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit);
389 * Make sure we allow access to VGA memory addresses when the
390 * bridge has the "VGA Enable" bit set.
392 if (!ok && pci_is_vga_memory_range(start, end))
393 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
395 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
398 if (flags & RF_PREFETCHABLE) {
399 if (pcib_is_prefetch_open(sc)) {
400 if (start < sc->pmembase)
401 start = sc->pmembase;
402 if (end > sc->pmemlimit)
407 } else { /* non-prefetchable */
408 if (pcib_is_nonprefetch_open(sc)) {
409 if (start < sc->membase)
411 if (end > sc->memlimit)
419 ok = 1; /* subtractive bridge: always ok */
421 if (pcib_is_nonprefetch_open(sc)) {
422 if (start < sc->membase && end > sc->memlimit) {
427 if (pcib_is_prefetch_open(sc)) {
428 if (start < sc->pmembase && end > sc->pmemlimit) {
429 start = sc->pmembase;
436 device_printf(dev, "memory: end (%lx) < start (%lx)\n",
442 if (!ok && bootverbose)
444 "%s requested unsupported memory range "
445 "0x%lx-0x%lx (decoding 0x%x-0x%x, 0x%x-0x%x)\n",
446 device_get_nameunit(child), start, end,
447 sc->membase, sc->memlimit, sc->pmembase,
452 device_printf(dev,"%s requested memory range "
453 "0x%lx-0x%lx: good\n",
454 device_get_nameunit(child), start, end);
461 * Bridge is OK decoding this resource, so pass it up.
463 return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
471 pcib_maxslots(device_t dev)
477 * Since we are a child of a PCI bus, its parent must support the pcib interface.
480 pcib_read_config(device_t dev, int b, int s, int f, int reg, int width)
482 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width));
486 pcib_write_config(device_t dev, int b, int s, int f, int reg, uint32_t val, int width)
488 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width);
492 * Route an interrupt across a PCI bridge.
495 pcib_route_interrupt(device_t pcib, device_t dev, int pin)
503 * The PCI standard defines a swizzle of the child-side device/intpin to
504 * the parent-side intpin as follows.
506 * device = device on child bus
507 * child_intpin = intpin on child bus slot (0-3)
508 * parent_intpin = intpin on parent bus slot (0-3)
510 * parent_intpin = (device + child_intpin) % 4
512 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4;
515 * Our parent is a PCI bus. Its parent must export the pcib interface
516 * which includes the ability to route interrupts.
518 bus = device_get_parent(pcib);
519 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1);
520 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) {
521 device_printf(pcib, "slot %d INT%c is routed to irq %d\n",
522 pci_get_slot(dev), 'A' + pin - 1, intnum);
528 * Try to read the bus number of a host-PCI bridge using appropriate config
532 host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func,
537 id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4);
538 if (id == 0xffffffff)
544 /* XXX This is a guess */
545 /* *busnum = read_config(bus, slot, func, 0x41, 1); */
549 /* Intel 82454KX/GX (Orion) */
550 *busnum = read_config(bus, slot, func, 0x4a, 1);
554 * For the 450nx chipset, there is a whole bundle of
555 * things pretending to be host bridges. The MIOC will
556 * be seen first and isn't really a pci bridge (the
557 * actual busses are attached to the PXB's). We need to
558 * read the registers of the MIOC to figure out the
559 * bus numbers for the PXB channels.
561 * Since the MIOC doesn't have a pci bus attached, we
562 * pretend it wasn't there.
568 /* Intel 82454NX PXB#0, Bus#A */
569 *busnum = read_config(bus, 0x10, func, 0xd0, 1);
572 /* Intel 82454NX PXB#0, Bus#B */
573 *busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1;
576 /* Intel 82454NX PXB#1, Bus#A */
577 *busnum = read_config(bus, 0x10, func, 0xd3, 1);
580 /* Intel 82454NX PXB#1, Bus#B */
581 *busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1;
586 /* ServerWorks -- vendor 0x1166 */
598 *busnum = read_config(bus, slot, func, 0x44, 1);
601 /* Compaq/HP -- vendor 0x0e11 */
603 *busnum = read_config(bus, slot, func, 0xc8, 1);
606 /* Don't know how to read bus number. */