2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
5 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
6 * Copyright (c) 2000 BSDi
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. The name of the author may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * PCI:PCI bridge support.
42 #include <sys/param.h>
44 #include <sys/kernel.h>
45 #include <sys/malloc.h>
46 #include <sys/module.h>
47 #include <sys/pciio.h>
49 #include <sys/sysctl.h>
50 #include <sys/systm.h>
51 #include <sys/taskqueue.h>
53 #include <dev/pci/pcivar.h>
54 #include <dev/pci/pcireg.h>
55 #include <dev/pci/pci_private.h>
56 #include <dev/pci/pcib_private.h>
60 static int pcib_probe(device_t dev);
61 static int pcib_suspend(device_t dev);
62 static int pcib_resume(device_t dev);
63 static int pcib_power_for_sleep(device_t pcib, device_t dev,
65 static int pcib_ari_get_id(device_t pcib, device_t dev,
66 enum pci_id_type type, uintptr_t *id);
67 static uint32_t pcib_read_config(device_t dev, u_int b, u_int s,
68 u_int f, u_int reg, int width);
69 static void pcib_write_config(device_t dev, u_int b, u_int s,
70 u_int f, u_int reg, uint32_t val, int width);
71 static int pcib_ari_maxslots(device_t dev);
72 static int pcib_ari_maxfuncs(device_t dev);
73 static int pcib_try_enable_ari(device_t pcib, device_t dev);
74 static int pcib_ari_enabled(device_t pcib);
75 static void pcib_ari_decode_rid(device_t pcib, uint16_t rid,
76 int *bus, int *slot, int *func);
78 static void pcib_pcie_ab_timeout(void *arg);
79 static void pcib_pcie_cc_timeout(void *arg);
80 static void pcib_pcie_dll_timeout(void *arg);
82 static int pcib_request_feature_default(device_t pcib, device_t dev,
83 enum pci_feature feature);
84 static int pcib_reset_child(device_t dev, device_t child, int flags);
86 static device_method_t pcib_methods[] = {
87 /* Device interface */
88 DEVMETHOD(device_probe, pcib_probe),
89 DEVMETHOD(device_attach, pcib_attach),
90 DEVMETHOD(device_detach, pcib_detach),
91 DEVMETHOD(device_shutdown, bus_generic_shutdown),
92 DEVMETHOD(device_suspend, pcib_suspend),
93 DEVMETHOD(device_resume, pcib_resume),
96 DEVMETHOD(bus_child_present, pcib_child_present),
97 DEVMETHOD(bus_read_ivar, pcib_read_ivar),
98 DEVMETHOD(bus_write_ivar, pcib_write_ivar),
99 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
101 DEVMETHOD(bus_adjust_resource, pcib_adjust_resource),
102 DEVMETHOD(bus_release_resource, pcib_release_resource),
104 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
105 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
107 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
108 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
109 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
110 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
111 DEVMETHOD(bus_reset_child, pcib_reset_child),
114 DEVMETHOD(pcib_maxslots, pcib_ari_maxslots),
115 DEVMETHOD(pcib_maxfuncs, pcib_ari_maxfuncs),
116 DEVMETHOD(pcib_read_config, pcib_read_config),
117 DEVMETHOD(pcib_write_config, pcib_write_config),
118 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
119 DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi),
120 DEVMETHOD(pcib_release_msi, pcib_release_msi),
121 DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix),
122 DEVMETHOD(pcib_release_msix, pcib_release_msix),
123 DEVMETHOD(pcib_map_msi, pcib_map_msi),
124 DEVMETHOD(pcib_power_for_sleep, pcib_power_for_sleep),
125 DEVMETHOD(pcib_get_id, pcib_ari_get_id),
126 DEVMETHOD(pcib_try_enable_ari, pcib_try_enable_ari),
127 DEVMETHOD(pcib_ari_enabled, pcib_ari_enabled),
128 DEVMETHOD(pcib_decode_rid, pcib_ari_decode_rid),
129 DEVMETHOD(pcib_request_feature, pcib_request_feature_default),
134 static devclass_t pcib_devclass;
136 DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc));
137 EARLY_DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, NULL, NULL,
140 #if defined(NEW_PCIB) || defined(PCI_HP)
141 SYSCTL_DECL(_hw_pci);
145 static int pci_clear_pcib;
146 SYSCTL_INT(_hw_pci, OID_AUTO, clear_pcib, CTLFLAG_RDTUN, &pci_clear_pcib, 0,
147 "Clear firmware-assigned resources for PCI-PCI bridge I/O windows.");
150 * Is a resource from a child device sub-allocated from one of our
154 pcib_is_resource_managed(struct pcib_softc *sc, int type, struct resource *r)
160 return (rman_is_region_manager(r, &sc->bus.rman));
163 return (rman_is_region_manager(r, &sc->io.rman));
165 /* Prefetchable resources may live in either memory rman. */
166 if (rman_get_flags(r) & RF_PREFETCHABLE &&
167 rman_is_region_manager(r, &sc->pmem.rman))
169 return (rman_is_region_manager(r, &sc->mem.rman));
175 pcib_is_window_open(struct pcib_window *pw)
178 return (pw->valid && pw->base < pw->limit);
182 * XXX: If RF_ACTIVE did not also imply allocating a bus space tag and
183 * handle for the resource, we could pass RF_ACTIVE up to the PCI bus
184 * when allocating the resource windows and rely on the PCI bus driver
188 pcib_activate_window(struct pcib_softc *sc, int type)
191 PCI_ENABLE_IO(device_get_parent(sc->dev), sc->dev, type);
195 pcib_write_windows(struct pcib_softc *sc, int mask)
201 if (sc->io.valid && mask & WIN_IO) {
202 val = pci_read_config(dev, PCIR_IOBASEL_1, 1);
203 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
204 pci_write_config(dev, PCIR_IOBASEH_1,
205 sc->io.base >> 16, 2);
206 pci_write_config(dev, PCIR_IOLIMITH_1,
207 sc->io.limit >> 16, 2);
209 pci_write_config(dev, PCIR_IOBASEL_1, sc->io.base >> 8, 1);
210 pci_write_config(dev, PCIR_IOLIMITL_1, sc->io.limit >> 8, 1);
213 if (mask & WIN_MEM) {
214 pci_write_config(dev, PCIR_MEMBASE_1, sc->mem.base >> 16, 2);
215 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->mem.limit >> 16, 2);
218 if (sc->pmem.valid && mask & WIN_PMEM) {
219 val = pci_read_config(dev, PCIR_PMBASEL_1, 2);
220 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) {
221 pci_write_config(dev, PCIR_PMBASEH_1,
222 sc->pmem.base >> 32, 4);
223 pci_write_config(dev, PCIR_PMLIMITH_1,
224 sc->pmem.limit >> 32, 4);
226 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmem.base >> 16, 2);
227 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmem.limit >> 16, 2);
232 * This is used to reject I/O port allocations that conflict with an
236 pcib_is_isa_range(struct pcib_softc *sc, rman_res_t start, rman_res_t end,
239 rman_res_t next_alias;
241 if (!(sc->bridgectl & PCIB_BCR_ISA_ENABLE))
244 /* Only check fixed ranges for overlap. */
245 if (start + count - 1 != end)
248 /* ISA aliases are only in the lower 64KB of I/O space. */
252 /* Check for overlap with 0x000 - 0x0ff as a special case. */
257 * If the start address is an alias, the range is an alias.
258 * Otherwise, compute the start of the next alias range and
259 * check if it is before the end of the candidate range.
261 if ((start & 0x300) != 0)
263 next_alias = (start & ~0x3fful) | 0x100;
264 if (next_alias <= end)
270 device_printf(sc->dev,
271 "I/O range %#jx-%#jx overlaps with an ISA alias\n", start,
277 pcib_add_window_resources(struct pcib_window *w, struct resource **res,
280 struct resource **newarray;
283 newarray = malloc(sizeof(struct resource *) * (w->count + count),
286 bcopy(w->res, newarray, sizeof(struct resource *) * w->count);
287 bcopy(res, newarray + w->count, sizeof(struct resource *) * count);
288 free(w->res, M_DEVBUF);
292 for (i = 0; i < count; i++) {
293 error = rman_manage_region(&w->rman, rman_get_start(res[i]),
294 rman_get_end(res[i]));
296 panic("Failed to add resource to rman");
300 typedef void (nonisa_callback)(rman_res_t start, rman_res_t end, void *arg);
303 pcib_walk_nonisa_ranges(rman_res_t start, rman_res_t end, nonisa_callback *cb,
309 * If start is within an ISA alias range, move up to the start
310 * of the next non-alias range. As a special case, addresses
311 * in the range 0x000 - 0x0ff should also be skipped since
312 * those are used for various system I/O devices in ISA
315 if (start <= 65535) {
316 if (start < 0x100 || (start & 0x300) != 0) {
322 /* ISA aliases are only in the lower 64KB of I/O space. */
323 while (start <= MIN(end, 65535)) {
324 next_end = MIN(start | 0xff, end);
325 cb(start, next_end, arg);
334 count_ranges(rman_res_t start, rman_res_t end, void *arg)
343 struct resource **res;
344 struct pcib_softc *sc;
349 alloc_ranges(rman_res_t start, rman_res_t end, void *arg)
351 struct alloc_state *as;
352 struct pcib_window *w;
362 device_printf(as->sc->dev,
363 "allocating non-ISA range %#jx-%#jx\n", start, end);
364 as->res[as->count] = bus_alloc_resource(as->sc->dev, SYS_RES_IOPORT,
365 &rid, start, end, end - start + 1, 0);
366 if (as->res[as->count] == NULL)
373 pcib_alloc_nonisa_ranges(struct pcib_softc *sc, rman_res_t start, rman_res_t end)
375 struct alloc_state as;
378 /* First, see how many ranges we need. */
380 pcib_walk_nonisa_ranges(start, end, count_ranges, &new_count);
382 /* Second, allocate the ranges. */
383 as.res = malloc(sizeof(struct resource *) * new_count, M_DEVBUF,
388 pcib_walk_nonisa_ranges(start, end, alloc_ranges, &as);
390 for (i = 0; i < as.count; i++)
391 bus_release_resource(sc->dev, SYS_RES_IOPORT,
392 sc->io.reg, as.res[i]);
393 free(as.res, M_DEVBUF);
396 KASSERT(as.count == new_count, ("%s: count mismatch", __func__));
398 /* Third, add the ranges to the window. */
399 pcib_add_window_resources(&sc->io, as.res, as.count);
400 free(as.res, M_DEVBUF);
405 pcib_alloc_window(struct pcib_softc *sc, struct pcib_window *w, int type,
406 int flags, pci_addr_t max_address)
408 struct resource *res;
412 if (max_address != (rman_res_t)max_address)
414 w->rman.rm_start = 0;
415 w->rman.rm_end = max_address;
416 w->rman.rm_type = RMAN_ARRAY;
417 snprintf(buf, sizeof(buf), "%s %s window",
418 device_get_nameunit(sc->dev), w->name);
419 w->rman.rm_descr = strdup(buf, M_DEVBUF);
420 error = rman_init(&w->rman);
422 panic("Failed to initialize %s %s rman",
423 device_get_nameunit(sc->dev), w->name);
425 if (!pcib_is_window_open(w))
428 if (w->base > max_address || w->limit > max_address) {
429 device_printf(sc->dev,
430 "initial %s window has too many bits, ignoring\n", w->name);
433 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE)
434 (void)pcib_alloc_nonisa_ranges(sc, w->base, w->limit);
437 res = bus_alloc_resource(sc->dev, type, &rid, w->base, w->limit,
438 w->limit - w->base + 1, flags);
440 pcib_add_window_resources(w, &res, 1);
442 if (w->res == NULL) {
443 device_printf(sc->dev,
444 "failed to allocate initial %s window: %#jx-%#jx\n",
445 w->name, (uintmax_t)w->base, (uintmax_t)w->limit);
446 w->base = max_address;
448 pcib_write_windows(sc, w->mask);
451 pcib_activate_window(sc, type);
455 * Initialize I/O windows.
458 pcib_probe_windows(struct pcib_softc *sc)
466 if (pci_clear_pcib) {
467 pcib_bridge_init(dev);
470 /* Determine if the I/O port window is implemented. */
471 val = pci_read_config(dev, PCIR_IOBASEL_1, 1);
474 * If 'val' is zero, then only 16-bits of I/O space
477 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1);
478 if (pci_read_config(dev, PCIR_IOBASEL_1, 1) != 0) {
480 pci_write_config(dev, PCIR_IOBASEL_1, 0, 1);
485 /* Read the existing I/O port window. */
487 sc->io.reg = PCIR_IOBASEL_1;
489 sc->io.mask = WIN_IO;
490 sc->io.name = "I/O port";
491 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
492 sc->io.base = PCI_PPBIOBASE(
493 pci_read_config(dev, PCIR_IOBASEH_1, 2), val);
494 sc->io.limit = PCI_PPBIOLIMIT(
495 pci_read_config(dev, PCIR_IOLIMITH_1, 2),
496 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
499 sc->io.base = PCI_PPBIOBASE(0, val);
500 sc->io.limit = PCI_PPBIOLIMIT(0,
501 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
504 pcib_alloc_window(sc, &sc->io, SYS_RES_IOPORT, 0, max);
507 /* Read the existing memory window. */
509 sc->mem.reg = PCIR_MEMBASE_1;
511 sc->mem.mask = WIN_MEM;
512 sc->mem.name = "memory";
513 sc->mem.base = PCI_PPBMEMBASE(0,
514 pci_read_config(dev, PCIR_MEMBASE_1, 2));
515 sc->mem.limit = PCI_PPBMEMLIMIT(0,
516 pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
517 pcib_alloc_window(sc, &sc->mem, SYS_RES_MEMORY, 0, 0xffffffff);
519 /* Determine if the prefetchable memory window is implemented. */
520 val = pci_read_config(dev, PCIR_PMBASEL_1, 2);
523 * If 'val' is zero, then only 32-bits of memory space
526 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2);
527 if (pci_read_config(dev, PCIR_PMBASEL_1, 2) != 0) {
529 pci_write_config(dev, PCIR_PMBASEL_1, 0, 2);
534 /* Read the existing prefetchable memory window. */
535 if (sc->pmem.valid) {
536 sc->pmem.reg = PCIR_PMBASEL_1;
538 sc->pmem.mask = WIN_PMEM;
539 sc->pmem.name = "prefetch";
540 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) {
541 sc->pmem.base = PCI_PPBMEMBASE(
542 pci_read_config(dev, PCIR_PMBASEH_1, 4), val);
543 sc->pmem.limit = PCI_PPBMEMLIMIT(
544 pci_read_config(dev, PCIR_PMLIMITH_1, 4),
545 pci_read_config(dev, PCIR_PMLIMITL_1, 2));
546 max = 0xffffffffffffffff;
548 sc->pmem.base = PCI_PPBMEMBASE(0, val);
549 sc->pmem.limit = PCI_PPBMEMLIMIT(0,
550 pci_read_config(dev, PCIR_PMLIMITL_1, 2));
553 pcib_alloc_window(sc, &sc->pmem, SYS_RES_MEMORY,
554 RF_PREFETCHABLE, max);
559 pcib_release_window(struct pcib_softc *sc, struct pcib_window *w, int type)
568 error = rman_fini(&w->rman);
570 device_printf(dev, "failed to release %s rman\n", w->name);
573 free(__DECONST(char *, w->rman.rm_descr), M_DEVBUF);
575 for (i = 0; i < w->count; i++) {
576 error = bus_free_resource(dev, type, w->res[i]);
579 "failed to release %s resource: %d\n", w->name,
582 free(w->res, M_DEVBUF);
586 pcib_free_windows(struct pcib_softc *sc)
589 pcib_release_window(sc, &sc->pmem, SYS_RES_MEMORY);
590 pcib_release_window(sc, &sc->mem, SYS_RES_MEMORY);
591 pcib_release_window(sc, &sc->io, SYS_RES_IOPORT);
596 * Allocate a suitable secondary bus for this bridge if needed and
597 * initialize the resource manager for the secondary bus range. Note
598 * that the minimum count is a desired value and this may allocate a
602 pcib_setup_secbus(device_t dev, struct pcib_secbus *bus, int min_count)
605 int error, rid, sec_reg;
607 switch (pci_read_config(dev, PCIR_HDRTYPE, 1) & PCIM_HDRTYPE) {
608 case PCIM_HDRTYPE_BRIDGE:
609 sec_reg = PCIR_SECBUS_1;
610 bus->sub_reg = PCIR_SUBBUS_1;
612 case PCIM_HDRTYPE_CARDBUS:
613 sec_reg = PCIR_SECBUS_2;
614 bus->sub_reg = PCIR_SUBBUS_2;
617 panic("not a PCI bridge");
619 bus->sec = pci_read_config(dev, sec_reg, 1);
620 bus->sub = pci_read_config(dev, bus->sub_reg, 1);
622 bus->rman.rm_start = 0;
623 bus->rman.rm_end = PCI_BUSMAX;
624 bus->rman.rm_type = RMAN_ARRAY;
625 snprintf(buf, sizeof(buf), "%s bus numbers", device_get_nameunit(dev));
626 bus->rman.rm_descr = strdup(buf, M_DEVBUF);
627 error = rman_init(&bus->rman);
629 panic("Failed to initialize %s bus number rman",
630 device_get_nameunit(dev));
633 * Allocate a bus range. This will return an existing bus range
634 * if one exists, or a new bus range if one does not.
637 bus->res = bus_alloc_resource_anywhere(dev, PCI_RES_BUS, &rid,
639 if (bus->res == NULL) {
641 * Fall back to just allocating a range of a single bus
644 bus->res = bus_alloc_resource_anywhere(dev, PCI_RES_BUS, &rid,
646 } else if (rman_get_size(bus->res) < min_count)
648 * Attempt to grow the existing range to satisfy the
649 * minimum desired count.
651 (void)bus_adjust_resource(dev, PCI_RES_BUS, bus->res,
652 rman_get_start(bus->res), rman_get_start(bus->res) +
656 * Add the initial resource to the rman.
658 if (bus->res != NULL) {
659 error = rman_manage_region(&bus->rman, rman_get_start(bus->res),
660 rman_get_end(bus->res));
662 panic("Failed to add resource to rman");
663 bus->sec = rman_get_start(bus->res);
664 bus->sub = rman_get_end(bus->res);
669 pcib_free_secbus(device_t dev, struct pcib_secbus *bus)
673 error = rman_fini(&bus->rman);
675 device_printf(dev, "failed to release bus number rman\n");
678 free(__DECONST(char *, bus->rman.rm_descr), M_DEVBUF);
680 error = bus_free_resource(dev, PCI_RES_BUS, bus->res);
683 "failed to release bus numbers resource: %d\n", error);
686 static struct resource *
687 pcib_suballoc_bus(struct pcib_secbus *bus, device_t child, int *rid,
688 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
690 struct resource *res;
692 res = rman_reserve_resource(&bus->rman, start, end, count, flags,
698 device_printf(bus->dev,
699 "allocated bus range (%ju-%ju) for rid %d of %s\n",
700 rman_get_start(res), rman_get_end(res), *rid,
701 pcib_child_name(child));
702 rman_set_rid(res, *rid);
707 * Attempt to grow the secondary bus range. This is much simpler than
708 * for I/O windows as the range can only be grown by increasing
712 pcib_grow_subbus(struct pcib_secbus *bus, rman_res_t new_end)
717 old_end = rman_get_end(bus->res);
718 KASSERT(new_end > old_end, ("attempt to shrink subbus"));
719 error = bus_adjust_resource(bus->dev, PCI_RES_BUS, bus->res,
720 rman_get_start(bus->res), new_end);
724 device_printf(bus->dev, "grew bus range to %ju-%ju\n",
725 rman_get_start(bus->res), rman_get_end(bus->res));
726 error = rman_manage_region(&bus->rman, old_end + 1,
727 rman_get_end(bus->res));
729 panic("Failed to add resource to rman");
730 bus->sub = rman_get_end(bus->res);
731 pci_write_config(bus->dev, bus->sub_reg, bus->sub, 1);
736 pcib_alloc_subbus(struct pcib_secbus *bus, device_t child, int *rid,
737 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
739 struct resource *res;
740 rman_res_t start_free, end_free, new_end;
743 * First, see if the request can be satisified by the existing
746 res = pcib_suballoc_bus(bus, child, rid, start, end, count, flags);
751 * Figure out a range to grow the bus range. First, find the
752 * first bus number after the last allocated bus in the rman and
753 * enforce that as a minimum starting point for the range.
755 if (rman_last_free_region(&bus->rman, &start_free, &end_free) != 0 ||
756 end_free != bus->sub)
757 start_free = bus->sub + 1;
758 if (start_free < start)
760 new_end = start_free + count - 1;
763 * See if this new range would satisfy the request if it
769 /* Finally, attempt to grow the existing resource. */
771 device_printf(bus->dev,
772 "attempting to grow bus range for %ju buses\n", count);
773 printf("\tback candidate range: %ju-%ju\n", start_free,
776 if (pcib_grow_subbus(bus, new_end) == 0)
777 return (pcib_suballoc_bus(bus, child, rid, start, end, count,
786 * Is the prefetch window open (eg, can we allocate memory in it?)
789 pcib_is_prefetch_open(struct pcib_softc *sc)
791 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit);
795 * Is the nonprefetch window open (eg, can we allocate memory in it?)
798 pcib_is_nonprefetch_open(struct pcib_softc *sc)
800 return (sc->membase > 0 && sc->membase < sc->memlimit);
804 * Is the io window open (eg, can we allocate ports in it?)
807 pcib_is_io_open(struct pcib_softc *sc)
809 return (sc->iobase > 0 && sc->iobase < sc->iolimit);
813 * Get current I/O decode.
816 pcib_get_io_decode(struct pcib_softc *sc)
823 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1);
824 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32)
825 sc->iobase = PCI_PPBIOBASE(
826 pci_read_config(dev, PCIR_IOBASEH_1, 2), iolow);
828 sc->iobase = PCI_PPBIOBASE(0, iolow);
830 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1);
831 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32)
832 sc->iolimit = PCI_PPBIOLIMIT(
833 pci_read_config(dev, PCIR_IOLIMITH_1, 2), iolow);
835 sc->iolimit = PCI_PPBIOLIMIT(0, iolow);
839 * Get current memory decode.
842 pcib_get_mem_decode(struct pcib_softc *sc)
849 sc->membase = PCI_PPBMEMBASE(0,
850 pci_read_config(dev, PCIR_MEMBASE_1, 2));
851 sc->memlimit = PCI_PPBMEMLIMIT(0,
852 pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
854 pmemlow = pci_read_config(dev, PCIR_PMBASEL_1, 2);
855 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64)
856 sc->pmembase = PCI_PPBMEMBASE(
857 pci_read_config(dev, PCIR_PMBASEH_1, 4), pmemlow);
859 sc->pmembase = PCI_PPBMEMBASE(0, pmemlow);
861 pmemlow = pci_read_config(dev, PCIR_PMLIMITL_1, 2);
862 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64)
863 sc->pmemlimit = PCI_PPBMEMLIMIT(
864 pci_read_config(dev, PCIR_PMLIMITH_1, 4), pmemlow);
866 sc->pmemlimit = PCI_PPBMEMLIMIT(0, pmemlow);
870 * Restore previous I/O decode.
873 pcib_set_io_decode(struct pcib_softc *sc)
880 iohi = sc->iobase >> 16;
882 pci_write_config(dev, PCIR_IOBASEH_1, iohi, 2);
883 pci_write_config(dev, PCIR_IOBASEL_1, sc->iobase >> 8, 1);
885 iohi = sc->iolimit >> 16;
887 pci_write_config(dev, PCIR_IOLIMITH_1, iohi, 2);
888 pci_write_config(dev, PCIR_IOLIMITL_1, sc->iolimit >> 8, 1);
892 * Restore previous memory decode.
895 pcib_set_mem_decode(struct pcib_softc *sc)
902 pci_write_config(dev, PCIR_MEMBASE_1, sc->membase >> 16, 2);
903 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->memlimit >> 16, 2);
905 pmemhi = sc->pmembase >> 32;
907 pci_write_config(dev, PCIR_PMBASEH_1, pmemhi, 4);
908 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmembase >> 16, 2);
910 pmemhi = sc->pmemlimit >> 32;
912 pci_write_config(dev, PCIR_PMLIMITH_1, pmemhi, 4);
913 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmemlimit >> 16, 2);
919 * PCI-express HotPlug support.
921 static int pci_enable_pcie_hp = 1;
922 SYSCTL_INT(_hw_pci, OID_AUTO, enable_pcie_hp, CTLFLAG_RDTUN,
923 &pci_enable_pcie_hp, 0,
924 "Enable support for native PCI-express HotPlug.");
927 pcib_probe_hotplug(struct pcib_softc *sc)
931 uint16_t link_sta, slot_sta;
933 if (!pci_enable_pcie_hp)
937 if (pci_find_cap(dev, PCIY_EXPRESS, NULL) != 0)
940 if (!(pcie_read_config(dev, PCIER_FLAGS, 2) & PCIEM_FLAGS_SLOT))
943 sc->pcie_slot_cap = pcie_read_config(dev, PCIER_SLOT_CAP, 4);
945 if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_HPC) == 0)
947 link_cap = pcie_read_config(dev, PCIER_LINK_CAP, 4);
948 if ((link_cap & PCIEM_LINK_CAP_DL_ACTIVE) == 0)
952 * Some devices report that they have an MRL when they actually
953 * do not. Since they always report that the MRL is open, child
954 * devices would be ignored. Try to detect these devices and
955 * ignore their claim of HotPlug support.
957 * If there is an open MRL but the Data Link Layer is active,
958 * the MRL is not real.
960 if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP) != 0) {
961 link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2);
962 slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2);
963 if ((slot_sta & PCIEM_SLOT_STA_MRLSS) != 0 &&
964 (link_sta & PCIEM_LINK_STA_DL_ACTIVE) != 0) {
970 * Now that we're sure we want to do hot plug, ask the
971 * firmware, if any, if that's OK.
973 if (pcib_request_feature(dev, PCI_FEATURE_HP) != 0) {
975 device_printf(dev, "Unable to activate hot plug feature.\n");
979 sc->flags |= PCIB_HOTPLUG;
983 * Send a HotPlug command to the slot control register. If this slot
984 * uses command completion interrupts and a previous command is still
985 * in progress, then the command is dropped. Once the previous
986 * command completes or times out, pcib_pcie_hotplug_update() will be
987 * invoked to post a new command based on the slot's state at that
991 pcib_pcie_hotplug_command(struct pcib_softc *sc, uint16_t val, uint16_t mask)
998 if (sc->flags & PCIB_HOTPLUG_CMD_PENDING)
1001 ctl = pcie_read_config(dev, PCIER_SLOT_CTL, 2);
1002 new = (ctl & ~mask) | val;
1006 device_printf(dev, "HotPlug command: %04x -> %04x\n", ctl, new);
1007 pcie_write_config(dev, PCIER_SLOT_CTL, new, 2);
1008 if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS) &&
1009 (ctl & new) & PCIEM_SLOT_CTL_CCIE) {
1010 sc->flags |= PCIB_HOTPLUG_CMD_PENDING;
1012 callout_reset(&sc->pcie_cc_timer, hz,
1013 pcib_pcie_cc_timeout, sc);
1018 pcib_pcie_hotplug_command_completed(struct pcib_softc *sc)
1025 device_printf(dev, "Command Completed\n");
1026 if (!(sc->flags & PCIB_HOTPLUG_CMD_PENDING))
1028 callout_stop(&sc->pcie_cc_timer);
1029 sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING;
1034 * Returns true if a card is fully inserted from the user's
1035 * perspective. It may not yet be ready for access, but the driver
1036 * can now start enabling access if necessary.
1039 pcib_hotplug_inserted(struct pcib_softc *sc)
1042 /* Pretend the card isn't present if a detach is forced. */
1043 if (sc->flags & PCIB_DETACHING)
1046 /* Card must be present in the slot. */
1047 if ((sc->pcie_slot_sta & PCIEM_SLOT_STA_PDS) == 0)
1050 /* A power fault implicitly turns off power to the slot. */
1051 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_PFD)
1054 /* If the MRL is disengaged, the slot is powered off. */
1055 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP &&
1056 (sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSS) != 0)
1063 * Returns -1 if the card is fully inserted, powered, and ready for
1064 * access. Otherwise, returns 0.
1067 pcib_hotplug_present(struct pcib_softc *sc)
1070 /* Card must be inserted. */
1071 if (!pcib_hotplug_inserted(sc))
1075 * Require the Electromechanical Interlock to be engaged if
1078 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_EIP &&
1079 (sc->pcie_slot_sta & PCIEM_SLOT_STA_EIS) == 0)
1082 /* Require the Data Link Layer to be active. */
1083 if (!(sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE))
1090 pcib_pcie_hotplug_update(struct pcib_softc *sc, uint16_t val, uint16_t mask,
1093 bool card_inserted, ei_engaged;
1095 /* Clear DETACHING if Presence Detect has cleared. */
1096 if ((sc->pcie_slot_sta & (PCIEM_SLOT_STA_PDC | PCIEM_SLOT_STA_PDS)) ==
1098 sc->flags &= ~PCIB_DETACHING;
1100 card_inserted = pcib_hotplug_inserted(sc);
1102 /* Turn the power indicator on if a card is inserted. */
1103 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PIP) {
1104 mask |= PCIEM_SLOT_CTL_PIC;
1106 val |= PCIEM_SLOT_CTL_PI_ON;
1107 else if (sc->flags & PCIB_DETACH_PENDING)
1108 val |= PCIEM_SLOT_CTL_PI_BLINK;
1110 val |= PCIEM_SLOT_CTL_PI_OFF;
1113 /* Turn the power on via the Power Controller if a card is inserted. */
1114 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PCP) {
1115 mask |= PCIEM_SLOT_CTL_PCC;
1117 val |= PCIEM_SLOT_CTL_PC_ON;
1119 val |= PCIEM_SLOT_CTL_PC_OFF;
1123 * If a card is inserted, enable the Electromechanical
1124 * Interlock. If a card is not inserted (or we are in the
1125 * process of detaching), disable the Electromechanical
1128 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_EIP) {
1129 mask |= PCIEM_SLOT_CTL_EIC;
1130 ei_engaged = (sc->pcie_slot_sta & PCIEM_SLOT_STA_EIS) != 0;
1131 if (card_inserted != ei_engaged)
1132 val |= PCIEM_SLOT_CTL_EIC;
1136 * Start a timer to see if the Data Link Layer times out.
1137 * Note that we only start the timer if Presence Detect or MRL Sensor
1138 * changed on this interrupt. Stop any scheduled timer if
1139 * the Data Link Layer is active.
1141 if (card_inserted &&
1142 !(sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE) &&
1144 (PCIEM_SLOT_STA_MRLSC | PCIEM_SLOT_STA_PDC)) {
1146 device_printf(sc->dev,
1147 "Data Link Layer inactive\n");
1149 callout_reset(&sc->pcie_dll_timer, hz,
1150 pcib_pcie_dll_timeout, sc);
1151 } else if (sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE)
1152 callout_stop(&sc->pcie_dll_timer);
1154 pcib_pcie_hotplug_command(sc, val, mask);
1157 * During attach the child "pci" device is added synchronously;
1158 * otherwise, the task is scheduled to manage the child
1161 if (schedule_task &&
1162 (pcib_hotplug_present(sc) != 0) != (sc->child != NULL))
1163 taskqueue_enqueue(taskqueue_thread, &sc->pcie_hp_task);
1167 pcib_pcie_intr_hotplug(void *arg)
1169 struct pcib_softc *sc;
1174 sc->pcie_slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2);
1176 /* Clear the events just reported. */
1177 pcie_write_config(dev, PCIER_SLOT_STA, sc->pcie_slot_sta, 2);
1180 device_printf(dev, "HotPlug interrupt: %#x\n",
1183 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_ABP) {
1184 if (sc->flags & PCIB_DETACH_PENDING) {
1186 "Attention Button Pressed: Detach Cancelled\n");
1187 sc->flags &= ~PCIB_DETACH_PENDING;
1188 callout_stop(&sc->pcie_ab_timer);
1191 "Attention Button Pressed: Detaching in 5 seconds\n");
1192 sc->flags |= PCIB_DETACH_PENDING;
1193 callout_reset(&sc->pcie_ab_timer, 5 * hz,
1194 pcib_pcie_ab_timeout, sc);
1197 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_PFD)
1198 device_printf(dev, "Power Fault Detected\n");
1199 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSC)
1200 device_printf(dev, "MRL Sensor Changed to %s\n",
1201 sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSS ? "open" :
1203 if (bootverbose && sc->pcie_slot_sta & PCIEM_SLOT_STA_PDC)
1204 device_printf(dev, "Presence Detect Changed to %s\n",
1205 sc->pcie_slot_sta & PCIEM_SLOT_STA_PDS ? "card present" :
1207 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_CC)
1208 pcib_pcie_hotplug_command_completed(sc);
1209 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_DLLSC) {
1210 sc->pcie_link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2);
1213 "Data Link Layer State Changed to %s\n",
1214 sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE ?
1215 "active" : "inactive");
1218 pcib_pcie_hotplug_update(sc, 0, 0, true);
1222 pcib_pcie_hotplug_task(void *context, int pending)
1224 struct pcib_softc *sc;
1230 if (pcib_hotplug_present(sc) != 0) {
1231 if (sc->child == NULL) {
1232 sc->child = device_add_child(dev, "pci", -1);
1233 bus_generic_attach(dev);
1236 if (sc->child != NULL) {
1237 if (device_delete_child(dev, sc->child) == 0)
1245 pcib_pcie_ab_timeout(void *arg)
1247 struct pcib_softc *sc;
1250 mtx_assert(&Giant, MA_OWNED);
1251 if (sc->flags & PCIB_DETACH_PENDING) {
1252 sc->flags |= PCIB_DETACHING;
1253 sc->flags &= ~PCIB_DETACH_PENDING;
1254 pcib_pcie_hotplug_update(sc, 0, 0, true);
1259 pcib_pcie_cc_timeout(void *arg)
1261 struct pcib_softc *sc;
1267 mtx_assert(&Giant, MA_OWNED);
1268 sta = pcie_read_config(dev, PCIER_SLOT_STA, 2);
1269 if (!(sta & PCIEM_SLOT_STA_CC)) {
1271 "HotPlug Command Timed Out - forcing detach\n");
1272 sc->flags &= ~(PCIB_HOTPLUG_CMD_PENDING | PCIB_DETACH_PENDING);
1273 sc->flags |= PCIB_DETACHING;
1274 pcib_pcie_hotplug_update(sc, 0, 0, true);
1277 "Missed HotPlug interrupt waiting for Command Completion\n");
1278 pcib_pcie_intr_hotplug(sc);
1283 pcib_pcie_dll_timeout(void *arg)
1285 struct pcib_softc *sc;
1291 mtx_assert(&Giant, MA_OWNED);
1292 sta = pcie_read_config(dev, PCIER_LINK_STA, 2);
1293 if (!(sta & PCIEM_LINK_STA_DL_ACTIVE)) {
1295 "Timed out waiting for Data Link Layer Active\n");
1296 sc->flags |= PCIB_DETACHING;
1297 pcib_pcie_hotplug_update(sc, 0, 0, true);
1298 } else if (sta != sc->pcie_link_sta) {
1300 "Missed HotPlug interrupt waiting for DLL Active\n");
1301 pcib_pcie_intr_hotplug(sc);
1306 pcib_alloc_pcie_irq(struct pcib_softc *sc)
1309 int count, error, rid;
1315 * For simplicity, only use MSI-X if there is a single message.
1316 * To support a device with multiple messages we would have to
1317 * use remap intr if the MSI number is not 0.
1319 count = pci_msix_count(dev);
1321 error = pci_alloc_msix(dev, &count);
1326 if (rid < 0 && pci_msi_count(dev) > 0) {
1328 error = pci_alloc_msi(dev, &count);
1336 sc->pcie_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1338 if (sc->pcie_irq == NULL) {
1340 "Failed to allocate interrupt for PCI-e events\n");
1342 pci_release_msi(dev);
1346 error = bus_setup_intr(dev, sc->pcie_irq, INTR_TYPE_MISC,
1347 NULL, pcib_pcie_intr_hotplug, sc, &sc->pcie_ihand);
1349 device_printf(dev, "Failed to setup PCI-e interrupt handler\n");
1350 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->pcie_irq);
1352 pci_release_msi(dev);
1359 pcib_release_pcie_irq(struct pcib_softc *sc)
1365 error = bus_teardown_intr(dev, sc->pcie_irq, sc->pcie_ihand);
1368 error = bus_free_resource(dev, SYS_RES_IRQ, sc->pcie_irq);
1371 return (pci_release_msi(dev));
1375 pcib_setup_hotplug(struct pcib_softc *sc)
1381 callout_init(&sc->pcie_ab_timer, 0);
1382 callout_init(&sc->pcie_cc_timer, 0);
1383 callout_init(&sc->pcie_dll_timer, 0);
1384 TASK_INIT(&sc->pcie_hp_task, 0, pcib_pcie_hotplug_task, sc);
1387 if (pcib_alloc_pcie_irq(sc) != 0)
1390 sc->pcie_link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2);
1391 sc->pcie_slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2);
1393 /* Clear any events previously pending. */
1394 pcie_write_config(dev, PCIER_SLOT_STA, sc->pcie_slot_sta, 2);
1396 /* Enable HotPlug events. */
1397 mask = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE |
1398 PCIEM_SLOT_CTL_CCIE | PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_MRLSCE |
1399 PCIEM_SLOT_CTL_PFDE | PCIEM_SLOT_CTL_ABPE;
1400 val = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE | PCIEM_SLOT_CTL_PDCE;
1401 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_APB)
1402 val |= PCIEM_SLOT_CTL_ABPE;
1403 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PCP)
1404 val |= PCIEM_SLOT_CTL_PFDE;
1405 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP)
1406 val |= PCIEM_SLOT_CTL_MRLSCE;
1407 if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS))
1408 val |= PCIEM_SLOT_CTL_CCIE;
1410 /* Turn the attention indicator off. */
1411 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_AIP) {
1412 mask |= PCIEM_SLOT_CTL_AIC;
1413 val |= PCIEM_SLOT_CTL_AI_OFF;
1416 pcib_pcie_hotplug_update(sc, val, mask, false);
1420 pcib_detach_hotplug(struct pcib_softc *sc)
1425 /* Disable the card in the slot and force it to detach. */
1426 if (sc->flags & PCIB_DETACH_PENDING) {
1427 sc->flags &= ~PCIB_DETACH_PENDING;
1428 callout_stop(&sc->pcie_ab_timer);
1430 sc->flags |= PCIB_DETACHING;
1432 if (sc->flags & PCIB_HOTPLUG_CMD_PENDING) {
1433 callout_stop(&sc->pcie_cc_timer);
1434 tsleep(sc, 0, "hpcmd", hz);
1435 sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING;
1438 /* Disable HotPlug events. */
1439 mask = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE |
1440 PCIEM_SLOT_CTL_CCIE | PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_MRLSCE |
1441 PCIEM_SLOT_CTL_PFDE | PCIEM_SLOT_CTL_ABPE;
1444 /* Turn the attention indicator off. */
1445 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_AIP) {
1446 mask |= PCIEM_SLOT_CTL_AIC;
1447 val |= PCIEM_SLOT_CTL_AI_OFF;
1450 pcib_pcie_hotplug_update(sc, val, mask, false);
1452 error = pcib_release_pcie_irq(sc);
1455 taskqueue_drain(taskqueue_thread, &sc->pcie_hp_task);
1456 callout_drain(&sc->pcie_ab_timer);
1457 callout_drain(&sc->pcie_cc_timer);
1458 callout_drain(&sc->pcie_dll_timer);
1464 * Get current bridge configuration.
1467 pcib_cfg_save(struct pcib_softc *sc)
1475 command = pci_read_config(dev, PCIR_COMMAND, 2);
1476 if (command & PCIM_CMD_PORTEN)
1477 pcib_get_io_decode(sc);
1478 if (command & PCIM_CMD_MEMEN)
1479 pcib_get_mem_decode(sc);
1484 * Restore previous bridge configuration.
1487 pcib_cfg_restore(struct pcib_softc *sc)
1494 pcib_write_windows(sc, WIN_IO | WIN_MEM | WIN_PMEM);
1496 command = pci_read_config(sc->dev, PCIR_COMMAND, 2);
1497 if (command & PCIM_CMD_PORTEN)
1498 pcib_set_io_decode(sc);
1499 if (command & PCIM_CMD_MEMEN)
1500 pcib_set_mem_decode(sc);
1505 * Generic device interface
1508 pcib_probe(device_t dev)
1510 if ((pci_get_class(dev) == PCIC_BRIDGE) &&
1511 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) {
1512 device_set_desc(dev, "PCI-PCI bridge");
1519 pcib_attach_common(device_t dev)
1521 struct pcib_softc *sc;
1522 struct sysctl_ctx_list *sctx;
1523 struct sysctl_oid *soid;
1526 sc = device_get_softc(dev);
1530 * Get current bridge configuration.
1532 sc->domain = pci_get_domain(dev);
1533 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS))
1534 sc->bus.sec = pci_read_config(dev, PCIR_SECBUS_1, 1);
1535 sc->bus.sub = pci_read_config(dev, PCIR_SUBBUS_1, 1);
1537 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
1541 * The primary bus register should always be the bus of the
1544 sc->pribus = pci_get_bus(dev);
1545 pci_write_config(dev, PCIR_PRIBUS_1, sc->pribus, 1);
1548 * Setup sysctl reporting nodes
1550 sctx = device_get_sysctl_ctx(dev);
1551 soid = device_get_sysctl_tree(dev);
1552 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain",
1553 CTLFLAG_RD, &sc->domain, 0, "Domain number");
1554 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus",
1555 CTLFLAG_RD, &sc->pribus, 0, "Primary bus number");
1556 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus",
1557 CTLFLAG_RD, &sc->bus.sec, 0, "Secondary bus number");
1558 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus",
1559 CTLFLAG_RD, &sc->bus.sub, 0, "Subordinate bus number");
1564 switch (pci_get_devid(dev)) {
1565 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS))
1566 case 0x12258086: /* Intel 82454KX/GX (Orion) */
1570 supbus = pci_read_config(dev, 0x41, 1);
1571 if (supbus != 0xff) {
1572 sc->bus.sec = supbus + 1;
1573 sc->bus.sub = supbus + 1;
1580 * The i82380FB mobile docking controller is a PCI-PCI bridge,
1581 * and it is a subtractive bridge. However, the ProgIf is wrong
1582 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't
1583 * happen. There are also Toshiba and Cavium ThunderX bridges
1584 * that behave this way.
1586 case 0xa002177d: /* Cavium ThunderX */
1587 case 0x124b8086: /* Intel 82380FB Mobile */
1588 case 0x060513d7: /* Toshiba ???? */
1589 sc->flags |= PCIB_SUBTRACTIVE;
1592 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS))
1593 /* Compaq R3000 BIOS sets wrong subordinate bus number. */
1598 if ((cp = kern_getenv("smbios.planar.maker")) == NULL)
1600 if (strncmp(cp, "Compal", 6) != 0) {
1605 if ((cp = kern_getenv("smbios.planar.product")) == NULL)
1607 if (strncmp(cp, "08A0", 4) != 0) {
1612 if (sc->bus.sub < 0xa) {
1613 pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1);
1614 sc->bus.sub = pci_read_config(dev, PCIR_SUBBUS_1, 1);
1621 if (pci_msi_device_blacklisted(dev))
1622 sc->flags |= PCIB_DISABLE_MSI;
1624 if (pci_msix_device_blacklisted(dev))
1625 sc->flags |= PCIB_DISABLE_MSIX;
1628 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges,
1629 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM,
1630 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese.
1631 * This means they act as if they were subtractively decoding
1632 * bridges and pass all transactions. Mark them and real ProgIf 1
1633 * parts as subtractive.
1635 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 ||
1636 pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_BRIDGE_PCI_SUBTRACTIVE)
1637 sc->flags |= PCIB_SUBTRACTIVE;
1640 pcib_probe_hotplug(sc);
1644 pcib_setup_secbus(dev, &sc->bus, 1);
1646 pcib_probe_windows(sc);
1649 if (sc->flags & PCIB_HOTPLUG)
1650 pcib_setup_hotplug(sc);
1653 device_printf(dev, " domain %d\n", sc->domain);
1654 device_printf(dev, " secondary bus %d\n", sc->bus.sec);
1655 device_printf(dev, " subordinate bus %d\n", sc->bus.sub);
1657 if (pcib_is_window_open(&sc->io))
1658 device_printf(dev, " I/O decode 0x%jx-0x%jx\n",
1659 (uintmax_t)sc->io.base, (uintmax_t)sc->io.limit);
1660 if (pcib_is_window_open(&sc->mem))
1661 device_printf(dev, " memory decode 0x%jx-0x%jx\n",
1662 (uintmax_t)sc->mem.base, (uintmax_t)sc->mem.limit);
1663 if (pcib_is_window_open(&sc->pmem))
1664 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n",
1665 (uintmax_t)sc->pmem.base, (uintmax_t)sc->pmem.limit);
1667 if (pcib_is_io_open(sc))
1668 device_printf(dev, " I/O decode 0x%x-0x%x\n",
1669 sc->iobase, sc->iolimit);
1670 if (pcib_is_nonprefetch_open(sc))
1671 device_printf(dev, " memory decode 0x%jx-0x%jx\n",
1672 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit);
1673 if (pcib_is_prefetch_open(sc))
1674 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n",
1675 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit);
1677 if (sc->bridgectl & (PCIB_BCR_ISA_ENABLE | PCIB_BCR_VGA_ENABLE) ||
1678 sc->flags & PCIB_SUBTRACTIVE) {
1679 device_printf(dev, " special decode ");
1681 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE) {
1685 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE) {
1686 printf("%sVGA", comma ? ", " : "");
1689 if (sc->flags & PCIB_SUBTRACTIVE)
1690 printf("%ssubtractive", comma ? ", " : "");
1696 * Always enable busmastering on bridges so that transactions
1697 * initiated on the secondary bus are passed through to the
1700 pci_enable_busmaster(dev);
1705 pcib_present(struct pcib_softc *sc)
1708 if (sc->flags & PCIB_HOTPLUG)
1709 return (pcib_hotplug_present(sc) != 0);
1715 pcib_attach_child(device_t dev)
1717 struct pcib_softc *sc;
1719 sc = device_get_softc(dev);
1720 if (sc->bus.sec == 0) {
1721 /* no secondary bus; we should have fixed this */
1726 if (!pcib_present(sc)) {
1727 /* An empty HotPlug slot, so don't add a PCI bus yet. */
1732 sc->child = device_add_child(dev, "pci", -1);
1733 return (bus_generic_attach(dev));
1737 pcib_attach(device_t dev)
1740 pcib_attach_common(dev);
1741 return (pcib_attach_child(dev));
1745 pcib_detach(device_t dev)
1747 #if defined(PCI_HP) || defined(NEW_PCIB)
1748 struct pcib_softc *sc;
1752 #if defined(PCI_HP) || defined(NEW_PCIB)
1753 sc = device_get_softc(dev);
1755 error = bus_generic_detach(dev);
1759 if (sc->flags & PCIB_HOTPLUG) {
1760 error = pcib_detach_hotplug(sc);
1765 error = device_delete_children(dev);
1769 pcib_free_windows(sc);
1771 pcib_free_secbus(dev, &sc->bus);
1778 pcib_suspend(device_t dev)
1781 pcib_cfg_save(device_get_softc(dev));
1782 return (bus_generic_suspend(dev));
1786 pcib_resume(device_t dev)
1789 pcib_cfg_restore(device_get_softc(dev));
1790 return (bus_generic_resume(dev));
1794 pcib_bridge_init(device_t dev)
1796 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1);
1797 pci_write_config(dev, PCIR_IOBASEH_1, 0xffff, 2);
1798 pci_write_config(dev, PCIR_IOLIMITL_1, 0, 1);
1799 pci_write_config(dev, PCIR_IOLIMITH_1, 0, 2);
1800 pci_write_config(dev, PCIR_MEMBASE_1, 0xffff, 2);
1801 pci_write_config(dev, PCIR_MEMLIMIT_1, 0, 2);
1802 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2);
1803 pci_write_config(dev, PCIR_PMBASEH_1, 0xffffffff, 4);
1804 pci_write_config(dev, PCIR_PMLIMITL_1, 0, 2);
1805 pci_write_config(dev, PCIR_PMLIMITH_1, 0, 4);
1809 pcib_child_present(device_t dev, device_t child)
1812 struct pcib_softc *sc = device_get_softc(dev);
1815 retval = bus_child_present(dev);
1816 if (retval != 0 && sc->flags & PCIB_HOTPLUG)
1817 retval = pcib_hotplug_present(sc);
1820 return (bus_child_present(dev));
1825 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1827 struct pcib_softc *sc = device_get_softc(dev);
1830 case PCIB_IVAR_DOMAIN:
1831 *result = sc->domain;
1834 *result = sc->bus.sec;
1841 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1845 case PCIB_IVAR_DOMAIN:
1855 * Attempt to allocate a resource from the existing resources assigned
1858 static struct resource *
1859 pcib_suballoc_resource(struct pcib_softc *sc, struct pcib_window *w,
1860 device_t child, int type, int *rid, rman_res_t start, rman_res_t end,
1861 rman_res_t count, u_int flags)
1863 struct resource *res;
1865 if (!pcib_is_window_open(w))
1868 res = rman_reserve_resource(&w->rman, start, end, count,
1869 flags & ~RF_ACTIVE, child);
1874 device_printf(sc->dev,
1875 "allocated %s range (%#jx-%#jx) for rid %x of %s\n",
1876 w->name, rman_get_start(res), rman_get_end(res), *rid,
1877 pcib_child_name(child));
1878 rman_set_rid(res, *rid);
1881 * If the resource should be active, pass that request up the
1882 * tree. This assumes the parent drivers can handle
1883 * activating sub-allocated resources.
1885 if (flags & RF_ACTIVE) {
1886 if (bus_activate_resource(child, type, *rid, res) != 0) {
1887 rman_release_resource(res);
1895 /* Allocate a fresh resource range for an unconfigured window. */
1897 pcib_alloc_new_window(struct pcib_softc *sc, struct pcib_window *w, int type,
1898 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
1900 struct resource *res;
1901 rman_res_t base, limit, wmask;
1905 * If this is an I/O window on a bridge with ISA enable set
1906 * and the start address is below 64k, then try to allocate an
1907 * initial window of 0x1000 bytes long starting at address
1908 * 0xf000 and walking down. Note that if the original request
1909 * was larger than the non-aliased range size of 0x100 our
1910 * caller would have raised the start address up to 64k
1913 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE &&
1915 for (base = 0xf000; (long)base >= 0; base -= 0x1000) {
1916 limit = base + 0xfff;
1919 * Skip ranges that wouldn't work for the
1920 * original request. Note that the actual
1921 * window that overlaps are the non-alias
1922 * ranges within [base, limit], so this isn't
1923 * quite a simple comparison.
1925 if (start + count > limit - 0x400)
1929 * The first open region for the window at
1932 if (end - count + 1 < 0x400)
1935 if (end - count + 1 < base)
1939 if (pcib_alloc_nonisa_ranges(sc, base, limit) == 0) {
1948 wmask = ((rman_res_t)1 << w->step) - 1;
1949 if (RF_ALIGNMENT(flags) < w->step) {
1950 flags &= ~RF_ALIGNMENT_MASK;
1951 flags |= RF_ALIGNMENT_LOG2(w->step);
1955 count = roundup2(count, (rman_res_t)1 << w->step);
1957 res = bus_alloc_resource(sc->dev, type, &rid, start, end, count,
1958 flags & ~RF_ACTIVE);
1961 pcib_add_window_resources(w, &res, 1);
1962 pcib_activate_window(sc, type);
1963 w->base = rman_get_start(res);
1964 w->limit = rman_get_end(res);
1968 /* Try to expand an existing window to the requested base and limit. */
1970 pcib_expand_window(struct pcib_softc *sc, struct pcib_window *w, int type,
1971 rman_res_t base, rman_res_t limit)
1973 struct resource *res;
1974 int error, i, force_64k_base;
1976 KASSERT(base <= w->base && limit >= w->limit,
1977 ("attempting to shrink window"));
1980 * XXX: pcib_grow_window() doesn't try to do this anyway and
1981 * the error handling for all the edge cases would be tedious.
1983 KASSERT(limit == w->limit || base == w->base,
1984 ("attempting to grow both ends of a window"));
1987 * Yet more special handling for requests to expand an I/O
1988 * window behind an ISA-enabled bridge. Since I/O windows
1989 * have to grow in 0x1000 increments and the end of the 0xffff
1990 * range is an alias, growing a window below 64k will always
1991 * result in allocating new resources and never adjusting an
1992 * existing resource.
1994 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE &&
1995 (limit <= 65535 || (base <= 65535 && base != w->base))) {
1996 KASSERT(limit == w->limit || limit <= 65535,
1997 ("attempting to grow both ends across 64k ISA alias"));
1999 if (base != w->base)
2000 error = pcib_alloc_nonisa_ranges(sc, base, w->base - 1);
2002 error = pcib_alloc_nonisa_ranges(sc, w->limit + 1,
2012 * Find the existing resource to adjust. Usually there is only one,
2013 * but for an ISA-enabled bridge we might be growing the I/O window
2014 * above 64k and need to find the existing resource that maps all
2015 * of the area above 64k.
2017 for (i = 0; i < w->count; i++) {
2018 if (rman_get_end(w->res[i]) == w->limit)
2021 KASSERT(i != w->count, ("did not find existing resource"));
2025 * Usually the resource we found should match the window's
2026 * existing range. The one exception is the ISA-enabled case
2027 * mentioned above in which case the resource should start at
2030 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE &&
2032 KASSERT(rman_get_start(res) == 65536,
2033 ("existing resource mismatch"));
2036 KASSERT(w->base == rman_get_start(res),
2037 ("existing resource mismatch"));
2041 error = bus_adjust_resource(sc->dev, type, res, force_64k_base ?
2042 rman_get_start(res) : base, limit);
2046 /* Add the newly allocated region to the resource manager. */
2047 if (w->base != base) {
2048 error = rman_manage_region(&w->rman, base, w->base - 1);
2051 error = rman_manage_region(&w->rman, w->limit + 1, limit);
2056 device_printf(sc->dev,
2057 "failed to expand %s resource manager\n", w->name);
2058 (void)bus_adjust_resource(sc->dev, type, res, force_64k_base ?
2059 rman_get_start(res) : w->base, w->limit);
2065 * Attempt to grow a window to make room for a given resource request.
2068 pcib_grow_window(struct pcib_softc *sc, struct pcib_window *w, int type,
2069 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
2071 rman_res_t align, start_free, end_free, front, back, wmask;
2075 * Clamp the desired resource range to the maximum address
2076 * this window supports. Reject impossible requests.
2078 * For I/O port requests behind a bridge with the ISA enable
2079 * bit set, force large allocations to start above 64k.
2083 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE && count > 0x100 &&
2086 if (end > w->rman.rm_end)
2087 end = w->rman.rm_end;
2088 if (start + count - 1 > end || start + count < start)
2090 wmask = ((rman_res_t)1 << w->step) - 1;
2093 * If there is no resource at all, just try to allocate enough
2094 * aligned space for this resource.
2096 if (w->res == NULL) {
2097 error = pcib_alloc_new_window(sc, w, type, start, end, count,
2101 device_printf(sc->dev,
2102 "failed to allocate initial %s window (%#jx-%#jx,%#jx)\n",
2103 w->name, start, end, count);
2107 device_printf(sc->dev,
2108 "allocated initial %s window of %#jx-%#jx\n",
2109 w->name, (uintmax_t)w->base, (uintmax_t)w->limit);
2114 * See if growing the window would help. Compute the minimum
2115 * amount of address space needed on both the front and back
2116 * ends of the existing window to satisfy the allocation.
2118 * For each end, build a candidate region adjusting for the
2119 * required alignment, etc. If there is a free region at the
2120 * edge of the window, grow from the inner edge of the free
2121 * region. Otherwise grow from the window boundary.
2123 * Growing an I/O window below 64k for a bridge with the ISA
2124 * enable bit doesn't require any special magic as the step
2125 * size of an I/O window (1k) always includes multiple
2126 * non-alias ranges when it is grown in either direction.
2128 * XXX: Special case: if w->res is completely empty and the
2129 * request size is larger than w->res, we should find the
2130 * optimal aligned buffer containing w->res and allocate that.
2133 device_printf(sc->dev,
2134 "attempting to grow %s window for (%#jx-%#jx,%#jx)\n",
2135 w->name, start, end, count);
2136 align = (rman_res_t)1 << RF_ALIGNMENT(flags);
2137 if (start < w->base) {
2138 if (rman_first_free_region(&w->rman, &start_free, &end_free) !=
2139 0 || start_free != w->base)
2144 /* Move end_free down until it is properly aligned. */
2145 end_free &= ~(align - 1);
2147 front = end_free - (count - 1);
2150 * The resource would now be allocated at (front,
2151 * end_free). Ensure that fits in the (start, end)
2152 * bounds. end_free is checked above. If 'front' is
2153 * ok, ensure it is properly aligned for this window.
2154 * Also check for underflow.
2156 if (front >= start && front <= end_free) {
2158 printf("\tfront candidate range: %#jx-%#jx\n",
2161 front = w->base - front;
2166 if (end > w->limit) {
2167 if (rman_last_free_region(&w->rman, &start_free, &end_free) !=
2168 0 || end_free != w->limit)
2169 start_free = w->limit + 1;
2170 if (start_free < start)
2173 /* Move start_free up until it is properly aligned. */
2174 start_free = roundup2(start_free, align);
2175 back = start_free + count - 1;
2178 * The resource would now be allocated at (start_free,
2179 * back). Ensure that fits in the (start, end)
2180 * bounds. start_free is checked above. If 'back' is
2181 * ok, ensure it is properly aligned for this window.
2182 * Also check for overflow.
2184 if (back <= end && start_free <= back) {
2186 printf("\tback candidate range: %#jx-%#jx\n",
2196 * Try to allocate the smallest needed region first.
2197 * If that fails, fall back to the other region.
2200 while (front != 0 || back != 0) {
2201 if (front != 0 && (front <= back || back == 0)) {
2202 error = pcib_expand_window(sc, w, type, w->base - front,
2208 error = pcib_expand_window(sc, w, type, w->base,
2219 device_printf(sc->dev, "grew %s window to %#jx-%#jx\n",
2220 w->name, (uintmax_t)w->base, (uintmax_t)w->limit);
2223 /* Write the new window. */
2224 KASSERT((w->base & wmask) == 0, ("start address is not aligned"));
2225 KASSERT((w->limit & wmask) == wmask, ("end address is not aligned"));
2226 pcib_write_windows(sc, w->mask);
2231 * We have to trap resource allocation requests and ensure that the bridge
2232 * is set up to, or capable of handling them.
2235 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
2236 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
2238 struct pcib_softc *sc;
2241 sc = device_get_softc(dev);
2244 * VGA resources are decoded iff the VGA enable bit is set in
2245 * the bridge control register. VGA resources do not fall into
2246 * the resource windows and are passed up to the parent.
2248 if ((type == SYS_RES_IOPORT && pci_is_vga_ioport_range(start, end)) ||
2249 (type == SYS_RES_MEMORY && pci_is_vga_memory_range(start, end))) {
2250 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE)
2251 return (bus_generic_alloc_resource(dev, child, type,
2252 rid, start, end, count, flags));
2260 return (pcib_alloc_subbus(&sc->bus, child, rid, start, end,
2263 case SYS_RES_IOPORT:
2264 if (pcib_is_isa_range(sc, start, end, count))
2266 r = pcib_suballoc_resource(sc, &sc->io, child, type, rid, start,
2268 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0)
2270 if (pcib_grow_window(sc, &sc->io, type, start, end, count,
2272 r = pcib_suballoc_resource(sc, &sc->io, child, type,
2273 rid, start, end, count, flags);
2275 case SYS_RES_MEMORY:
2277 * For prefetchable resources, prefer the prefetchable
2278 * memory window, but fall back to the regular memory
2279 * window if that fails. Try both windows before
2280 * attempting to grow a window in case the firmware
2281 * has used a range in the regular memory window to
2282 * map a prefetchable BAR.
2284 if (flags & RF_PREFETCHABLE) {
2285 r = pcib_suballoc_resource(sc, &sc->pmem, child, type,
2286 rid, start, end, count, flags);
2290 r = pcib_suballoc_resource(sc, &sc->mem, child, type, rid,
2291 start, end, count, flags);
2292 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0)
2294 if (flags & RF_PREFETCHABLE) {
2295 if (pcib_grow_window(sc, &sc->pmem, type, start, end,
2296 count, flags) == 0) {
2297 r = pcib_suballoc_resource(sc, &sc->pmem, child,
2298 type, rid, start, end, count, flags);
2303 if (pcib_grow_window(sc, &sc->mem, type, start, end, count,
2304 flags & ~RF_PREFETCHABLE) == 0)
2305 r = pcib_suballoc_resource(sc, &sc->mem, child, type,
2306 rid, start, end, count, flags);
2309 return (bus_generic_alloc_resource(dev, child, type, rid,
2310 start, end, count, flags));
2314 * If attempts to suballocate from the window fail but this is a
2315 * subtractive bridge, pass the request up the tree.
2317 if (sc->flags & PCIB_SUBTRACTIVE && r == NULL)
2318 return (bus_generic_alloc_resource(dev, child, type, rid,
2319 start, end, count, flags));
2324 pcib_adjust_resource(device_t bus, device_t child, int type, struct resource *r,
2325 rman_res_t start, rman_res_t end)
2327 struct pcib_softc *sc;
2329 sc = device_get_softc(bus);
2330 if (pcib_is_resource_managed(sc, type, r))
2331 return (rman_adjust_resource(r, start, end));
2332 return (bus_generic_adjust_resource(bus, child, type, r, start, end));
2336 pcib_release_resource(device_t dev, device_t child, int type, int rid,
2339 struct pcib_softc *sc;
2342 sc = device_get_softc(dev);
2343 if (pcib_is_resource_managed(sc, type, r)) {
2344 if (rman_get_flags(r) & RF_ACTIVE) {
2345 error = bus_deactivate_resource(child, type, rid, r);
2349 return (rman_release_resource(r));
2351 return (bus_generic_release_resource(dev, child, type, rid, r));
2355 * We have to trap resource allocation requests and ensure that the bridge
2356 * is set up to, or capable of handling them.
2359 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
2360 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
2362 struct pcib_softc *sc = device_get_softc(dev);
2363 const char *name, *suffix;
2367 * Fail the allocation for this range if it's not supported.
2369 name = device_get_nameunit(child);
2376 case SYS_RES_IOPORT:
2378 if (!pcib_is_io_open(sc))
2380 ok = (start >= sc->iobase && end <= sc->iolimit);
2383 * Make sure we allow access to VGA I/O addresses when the
2384 * bridge has the "VGA Enable" bit set.
2386 if (!ok && pci_is_vga_ioport_range(start, end))
2387 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
2389 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
2391 if (start < sc->iobase)
2393 if (end > sc->iolimit)
2402 * If we overlap with the subtractive range, then
2403 * pick the upper range to use.
2405 if (start < sc->iolimit && end > sc->iobase)
2406 start = sc->iolimit + 1;
2410 device_printf(dev, "ioport: end (%jx) < start (%jx)\n",
2417 device_printf(dev, "%s%srequested unsupported I/O "
2418 "range 0x%jx-0x%jx (decoding 0x%x-0x%x)\n",
2419 name, suffix, start, end, sc->iobase, sc->iolimit);
2424 "%s%srequested I/O range 0x%jx-0x%jx: in range\n",
2425 name, suffix, start, end);
2428 case SYS_RES_MEMORY:
2430 if (pcib_is_nonprefetch_open(sc))
2431 ok = ok || (start >= sc->membase && end <= sc->memlimit);
2432 if (pcib_is_prefetch_open(sc))
2433 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit);
2436 * Make sure we allow access to VGA memory addresses when the
2437 * bridge has the "VGA Enable" bit set.
2439 if (!ok && pci_is_vga_memory_range(start, end))
2440 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
2442 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
2445 if (flags & RF_PREFETCHABLE) {
2446 if (pcib_is_prefetch_open(sc)) {
2447 if (start < sc->pmembase)
2448 start = sc->pmembase;
2449 if (end > sc->pmemlimit)
2450 end = sc->pmemlimit;
2454 } else { /* non-prefetchable */
2455 if (pcib_is_nonprefetch_open(sc)) {
2456 if (start < sc->membase)
2457 start = sc->membase;
2458 if (end > sc->memlimit)
2466 ok = 1; /* subtractive bridge: always ok */
2468 if (pcib_is_nonprefetch_open(sc)) {
2469 if (start < sc->memlimit && end > sc->membase)
2470 start = sc->memlimit + 1;
2472 if (pcib_is_prefetch_open(sc)) {
2473 if (start < sc->pmemlimit && end > sc->pmembase)
2474 start = sc->pmemlimit + 1;
2479 device_printf(dev, "memory: end (%jx) < start (%jx)\n",
2485 if (!ok && bootverbose)
2487 "%s%srequested unsupported memory range %#jx-%#jx "
2488 "(decoding %#jx-%#jx, %#jx-%#jx)\n",
2489 name, suffix, start, end,
2490 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit,
2491 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit);
2495 device_printf(dev,"%s%srequested memory range "
2496 "0x%jx-0x%jx: good\n",
2497 name, suffix, start, end);
2504 * Bridge is OK decoding this resource, so pass it up.
2506 return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
2512 * If ARI is enabled on this downstream port, translate the function number
2513 * to the non-ARI slot/function. The downstream port will convert it back in
2514 * hardware. If ARI is not enabled slot and func are not modified.
2516 static __inline void
2517 pcib_xlate_ari(device_t pcib, int bus, int *slot, int *func)
2519 struct pcib_softc *sc;
2522 sc = device_get_softc(pcib);
2525 if (sc->flags & PCIB_ENABLE_ARI) {
2527 ("Non-zero slot number with ARI enabled!"));
2528 *slot = PCIE_ARI_SLOT(ari_func);
2529 *func = PCIE_ARI_FUNC(ari_func);
2535 pcib_enable_ari(struct pcib_softc *sc, uint32_t pcie_pos)
2539 ctl2 = pci_read_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, 4);
2540 ctl2 |= PCIEM_CTL2_ARI;
2541 pci_write_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, ctl2, 4);
2543 sc->flags |= PCIB_ENABLE_ARI;
2550 pcib_maxslots(device_t dev)
2552 #if !defined(__amd64__) && !defined(__i386__)
2557 * If this is a PCIe rootport or downstream switch port, there's only
2558 * one slot permitted.
2560 if (pci_find_cap(dev, PCIY_EXPRESS, &pcie_pos) == 0) {
2561 val = pci_read_config(dev, pcie_pos + PCIER_FLAGS, 2);
2562 val &= PCIEM_FLAGS_TYPE;
2563 if (val == PCIEM_TYPE_ROOT_PORT ||
2564 val == PCIEM_TYPE_DOWNSTREAM_PORT)
2568 return (PCI_SLOTMAX);
2572 pcib_ari_maxslots(device_t dev)
2574 struct pcib_softc *sc;
2576 sc = device_get_softc(dev);
2578 if (sc->flags & PCIB_ENABLE_ARI)
2579 return (PCIE_ARI_SLOTMAX);
2581 return (pcib_maxslots(dev));
2585 pcib_ari_maxfuncs(device_t dev)
2587 struct pcib_softc *sc;
2589 sc = device_get_softc(dev);
2591 if (sc->flags & PCIB_ENABLE_ARI)
2592 return (PCIE_ARI_FUNCMAX);
2594 return (PCI_FUNCMAX);
2598 pcib_ari_decode_rid(device_t pcib, uint16_t rid, int *bus, int *slot,
2601 struct pcib_softc *sc;
2603 sc = device_get_softc(pcib);
2605 *bus = PCI_RID2BUS(rid);
2606 if (sc->flags & PCIB_ENABLE_ARI) {
2607 *slot = PCIE_ARI_RID2SLOT(rid);
2608 *func = PCIE_ARI_RID2FUNC(rid);
2610 *slot = PCI_RID2SLOT(rid);
2611 *func = PCI_RID2FUNC(rid);
2616 * Since we are a child of a PCI bus, its parent must support the pcib interface.
2619 pcib_read_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, int width)
2622 struct pcib_softc *sc;
2624 sc = device_get_softc(dev);
2625 if (!pcib_present(sc)) {
2632 return (0xffffffff);
2636 pcib_xlate_ari(dev, b, &s, &f);
2637 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s,
2642 pcib_write_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, int width)
2645 struct pcib_softc *sc;
2647 sc = device_get_softc(dev);
2648 if (!pcib_present(sc))
2651 pcib_xlate_ari(dev, b, &s, &f);
2652 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f,
2657 * Route an interrupt across a PCI bridge.
2660 pcib_route_interrupt(device_t pcib, device_t dev, int pin)
2668 * The PCI standard defines a swizzle of the child-side device/intpin to
2669 * the parent-side intpin as follows.
2671 * device = device on child bus
2672 * child_intpin = intpin on child bus slot (0-3)
2673 * parent_intpin = intpin on parent bus slot (0-3)
2675 * parent_intpin = (device + child_intpin) % 4
2677 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4;
2680 * Our parent is a PCI bus. Its parent must export the pcib interface
2681 * which includes the ability to route interrupts.
2683 bus = device_get_parent(pcib);
2684 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1);
2685 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) {
2686 device_printf(pcib, "slot %d INT%c is routed to irq %d\n",
2687 pci_get_slot(dev), 'A' + pin - 1, intnum);
2692 /* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */
2694 pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs)
2696 struct pcib_softc *sc = device_get_softc(pcib);
2699 if (sc->flags & PCIB_DISABLE_MSI)
2701 bus = device_get_parent(pcib);
2702 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount,
2706 /* Pass request to release MSI/MSI-X messages up to the parent bridge. */
2708 pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs)
2712 bus = device_get_parent(pcib);
2713 return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs));
2716 /* Pass request to alloc an MSI-X message up to the parent bridge. */
2718 pcib_alloc_msix(device_t pcib, device_t dev, int *irq)
2720 struct pcib_softc *sc = device_get_softc(pcib);
2723 if (sc->flags & PCIB_DISABLE_MSIX)
2725 bus = device_get_parent(pcib);
2726 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq));
2729 /* Pass request to release an MSI-X message up to the parent bridge. */
2731 pcib_release_msix(device_t pcib, device_t dev, int irq)
2735 bus = device_get_parent(pcib);
2736 return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq));
2739 /* Pass request to map MSI/MSI-X message up to parent bridge. */
2741 pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
2747 bus = device_get_parent(pcib);
2748 error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data);
2752 pci_ht_map_msi(pcib, *addr);
2756 /* Pass request for device power state up to parent bridge. */
2758 pcib_power_for_sleep(device_t pcib, device_t dev, int *pstate)
2762 bus = device_get_parent(pcib);
2763 return (PCIB_POWER_FOR_SLEEP(bus, dev, pstate));
2767 pcib_ari_enabled(device_t pcib)
2769 struct pcib_softc *sc;
2771 sc = device_get_softc(pcib);
2773 return ((sc->flags & PCIB_ENABLE_ARI) != 0);
2777 pcib_ari_get_id(device_t pcib, device_t dev, enum pci_id_type type,
2780 struct pcib_softc *sc;
2782 uint8_t bus, slot, func;
2784 if (type != PCI_ID_RID) {
2785 bus_dev = device_get_parent(pcib);
2786 return (PCIB_GET_ID(device_get_parent(bus_dev), dev, type, id));
2789 sc = device_get_softc(pcib);
2791 if (sc->flags & PCIB_ENABLE_ARI) {
2792 bus = pci_get_bus(dev);
2793 func = pci_get_function(dev);
2795 *id = (PCI_ARI_RID(bus, func));
2797 bus = pci_get_bus(dev);
2798 slot = pci_get_slot(dev);
2799 func = pci_get_function(dev);
2801 *id = (PCI_RID(bus, slot, func));
2808 * Check that the downstream port (pcib) and the endpoint device (dev) both
2809 * support ARI. If so, enable it and return 0, otherwise return an error.
2812 pcib_try_enable_ari(device_t pcib, device_t dev)
2814 struct pcib_softc *sc;
2821 sc = device_get_softc(pcib);
2824 * ARI is controlled in a register in the PCIe capability structure.
2825 * If the downstream port does not have the PCIe capability structure
2826 * then it does not support ARI.
2828 error = pci_find_cap(pcib, PCIY_EXPRESS, &pcie_pos);
2832 /* Check that the PCIe port advertises ARI support. */
2833 cap2 = pci_read_config(pcib, pcie_pos + PCIER_DEVICE_CAP2, 4);
2834 if (!(cap2 & PCIEM_CAP2_ARI))
2838 * Check that the endpoint device advertises ARI support via the ARI
2839 * extended capability structure.
2841 error = pci_find_extcap(dev, PCIZ_ARI, &ari_cap_off);
2846 * Finally, check that the endpoint device supports the same version
2847 * of ARI that we do.
2849 ari_ver = pci_read_config(dev, ari_cap_off, 4);
2850 if (PCI_EXTCAP_VER(ari_ver) != PCIB_SUPPORTED_ARI_VER) {
2853 "Unsupported version of ARI (%d) detected\n",
2854 PCI_EXTCAP_VER(ari_ver));
2859 pcib_enable_ari(sc, pcie_pos);
2865 pcib_request_feature_allow(device_t pcib, device_t dev,
2866 enum pci_feature feature)
2869 * No host firmware we have to negotiate with, so we allow
2870 * every valid feature requested.
2873 case PCI_FEATURE_AER:
2874 case PCI_FEATURE_HP:
2884 pcib_request_feature(device_t dev, enum pci_feature feature)
2888 * Invoke PCIB_REQUEST_FEATURE of this bridge first in case
2889 * the firmware overrides the method of PCI-PCI bridges.
2891 return (PCIB_REQUEST_FEATURE(dev, dev, feature));
2895 * Pass the request to use this PCI feature up the tree. Either there's a
2896 * firmware like ACPI that's using this feature that will approve (or deny) the
2897 * request to take it over, or the platform has no such firmware, in which case
2898 * the request will be approved. If the request is approved, the OS is expected
2899 * to make use of the feature or render it harmless.
2902 pcib_request_feature_default(device_t pcib, device_t dev,
2903 enum pci_feature feature)
2908 * Our parent is necessarily a pci bus. Its parent will either be
2909 * another pci bridge (which passes it up) or a host bridge that can
2910 * approve or reject the request.
2912 bus = device_get_parent(pcib);
2913 return (PCIB_REQUEST_FEATURE(device_get_parent(bus), dev, feature));
2917 pcib_reset_child(device_t dev, device_t child, int flags)
2919 struct pci_devinfo *pdinfo;
2923 if (dev == NULL || device_get_parent(child) != dev)
2926 if (device_get_devclass(child) != devclass_find("pci"))
2928 pdinfo = device_get_ivars(dev);
2929 if (pdinfo->cfg.pcie.pcie_location != 0 &&
2930 (pdinfo->cfg.pcie.pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT ||
2931 pdinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT)) {
2932 error = bus_helper_reset_prepare(child, flags);
2934 error = pcie_link_reset(dev,
2935 pdinfo->cfg.pcie.pcie_location);
2936 /* XXXKIB call _post even if error != 0 ? */
2937 bus_helper_reset_post(child, flags);