2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
5 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
6 * Copyright (c) 2000 BSDi
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. The name of the author may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * PCI:PCI bridge support.
42 #include <sys/param.h>
44 #include <sys/kernel.h>
45 #include <sys/malloc.h>
46 #include <sys/module.h>
48 #include <sys/sysctl.h>
49 #include <sys/systm.h>
50 #include <sys/taskqueue.h>
52 #include <dev/pci/pcivar.h>
53 #include <dev/pci/pcireg.h>
54 #include <dev/pci/pci_private.h>
55 #include <dev/pci/pcib_private.h>
59 static int pcib_probe(device_t dev);
60 static int pcib_suspend(device_t dev);
61 static int pcib_resume(device_t dev);
62 static int pcib_power_for_sleep(device_t pcib, device_t dev,
64 static int pcib_ari_get_id(device_t pcib, device_t dev,
65 enum pci_id_type type, uintptr_t *id);
66 static uint32_t pcib_read_config(device_t dev, u_int b, u_int s,
67 u_int f, u_int reg, int width);
68 static void pcib_write_config(device_t dev, u_int b, u_int s,
69 u_int f, u_int reg, uint32_t val, int width);
70 static int pcib_ari_maxslots(device_t dev);
71 static int pcib_ari_maxfuncs(device_t dev);
72 static int pcib_try_enable_ari(device_t pcib, device_t dev);
73 static int pcib_ari_enabled(device_t pcib);
74 static void pcib_ari_decode_rid(device_t pcib, uint16_t rid,
75 int *bus, int *slot, int *func);
77 static void pcib_pcie_ab_timeout(void *arg);
78 static void pcib_pcie_cc_timeout(void *arg);
79 static void pcib_pcie_dll_timeout(void *arg);
81 static int pcib_request_feature_default(device_t pcib, device_t dev,
82 enum pci_feature feature);
84 static device_method_t pcib_methods[] = {
85 /* Device interface */
86 DEVMETHOD(device_probe, pcib_probe),
87 DEVMETHOD(device_attach, pcib_attach),
88 DEVMETHOD(device_detach, pcib_detach),
89 DEVMETHOD(device_shutdown, bus_generic_shutdown),
90 DEVMETHOD(device_suspend, pcib_suspend),
91 DEVMETHOD(device_resume, pcib_resume),
94 DEVMETHOD(bus_child_present, pcib_child_present),
95 DEVMETHOD(bus_read_ivar, pcib_read_ivar),
96 DEVMETHOD(bus_write_ivar, pcib_write_ivar),
97 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
99 DEVMETHOD(bus_adjust_resource, pcib_adjust_resource),
100 DEVMETHOD(bus_release_resource, pcib_release_resource),
102 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
103 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
105 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
106 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
107 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
108 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
111 DEVMETHOD(pcib_maxslots, pcib_ari_maxslots),
112 DEVMETHOD(pcib_maxfuncs, pcib_ari_maxfuncs),
113 DEVMETHOD(pcib_read_config, pcib_read_config),
114 DEVMETHOD(pcib_write_config, pcib_write_config),
115 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
116 DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi),
117 DEVMETHOD(pcib_release_msi, pcib_release_msi),
118 DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix),
119 DEVMETHOD(pcib_release_msix, pcib_release_msix),
120 DEVMETHOD(pcib_map_msi, pcib_map_msi),
121 DEVMETHOD(pcib_power_for_sleep, pcib_power_for_sleep),
122 DEVMETHOD(pcib_get_id, pcib_ari_get_id),
123 DEVMETHOD(pcib_try_enable_ari, pcib_try_enable_ari),
124 DEVMETHOD(pcib_ari_enabled, pcib_ari_enabled),
125 DEVMETHOD(pcib_decode_rid, pcib_ari_decode_rid),
126 DEVMETHOD(pcib_request_feature, pcib_request_feature_default),
131 static devclass_t pcib_devclass;
133 DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc));
134 DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, NULL, NULL);
136 #if defined(NEW_PCIB) || defined(PCI_HP)
137 SYSCTL_DECL(_hw_pci);
141 static int pci_clear_pcib;
142 SYSCTL_INT(_hw_pci, OID_AUTO, clear_pcib, CTLFLAG_RDTUN, &pci_clear_pcib, 0,
143 "Clear firmware-assigned resources for PCI-PCI bridge I/O windows.");
146 * Is a resource from a child device sub-allocated from one of our
150 pcib_is_resource_managed(struct pcib_softc *sc, int type, struct resource *r)
156 return (rman_is_region_manager(r, &sc->bus.rman));
159 return (rman_is_region_manager(r, &sc->io.rman));
161 /* Prefetchable resources may live in either memory rman. */
162 if (rman_get_flags(r) & RF_PREFETCHABLE &&
163 rman_is_region_manager(r, &sc->pmem.rman))
165 return (rman_is_region_manager(r, &sc->mem.rman));
171 pcib_is_window_open(struct pcib_window *pw)
174 return (pw->valid && pw->base < pw->limit);
178 * XXX: If RF_ACTIVE did not also imply allocating a bus space tag and
179 * handle for the resource, we could pass RF_ACTIVE up to the PCI bus
180 * when allocating the resource windows and rely on the PCI bus driver
184 pcib_activate_window(struct pcib_softc *sc, int type)
187 PCI_ENABLE_IO(device_get_parent(sc->dev), sc->dev, type);
191 pcib_write_windows(struct pcib_softc *sc, int mask)
197 if (sc->io.valid && mask & WIN_IO) {
198 val = pci_read_config(dev, PCIR_IOBASEL_1, 1);
199 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
200 pci_write_config(dev, PCIR_IOBASEH_1,
201 sc->io.base >> 16, 2);
202 pci_write_config(dev, PCIR_IOLIMITH_1,
203 sc->io.limit >> 16, 2);
205 pci_write_config(dev, PCIR_IOBASEL_1, sc->io.base >> 8, 1);
206 pci_write_config(dev, PCIR_IOLIMITL_1, sc->io.limit >> 8, 1);
209 if (mask & WIN_MEM) {
210 pci_write_config(dev, PCIR_MEMBASE_1, sc->mem.base >> 16, 2);
211 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->mem.limit >> 16, 2);
214 if (sc->pmem.valid && mask & WIN_PMEM) {
215 val = pci_read_config(dev, PCIR_PMBASEL_1, 2);
216 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) {
217 pci_write_config(dev, PCIR_PMBASEH_1,
218 sc->pmem.base >> 32, 4);
219 pci_write_config(dev, PCIR_PMLIMITH_1,
220 sc->pmem.limit >> 32, 4);
222 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmem.base >> 16, 2);
223 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmem.limit >> 16, 2);
228 * This is used to reject I/O port allocations that conflict with an
232 pcib_is_isa_range(struct pcib_softc *sc, rman_res_t start, rman_res_t end,
235 rman_res_t next_alias;
237 if (!(sc->bridgectl & PCIB_BCR_ISA_ENABLE))
240 /* Only check fixed ranges for overlap. */
241 if (start + count - 1 != end)
244 /* ISA aliases are only in the lower 64KB of I/O space. */
248 /* Check for overlap with 0x000 - 0x0ff as a special case. */
253 * If the start address is an alias, the range is an alias.
254 * Otherwise, compute the start of the next alias range and
255 * check if it is before the end of the candidate range.
257 if ((start & 0x300) != 0)
259 next_alias = (start & ~0x3fful) | 0x100;
260 if (next_alias <= end)
266 device_printf(sc->dev,
267 "I/O range %#jx-%#jx overlaps with an ISA alias\n", start,
273 pcib_add_window_resources(struct pcib_window *w, struct resource **res,
276 struct resource **newarray;
279 newarray = malloc(sizeof(struct resource *) * (w->count + count),
282 bcopy(w->res, newarray, sizeof(struct resource *) * w->count);
283 bcopy(res, newarray + w->count, sizeof(struct resource *) * count);
284 free(w->res, M_DEVBUF);
288 for (i = 0; i < count; i++) {
289 error = rman_manage_region(&w->rman, rman_get_start(res[i]),
290 rman_get_end(res[i]));
292 panic("Failed to add resource to rman");
296 typedef void (nonisa_callback)(rman_res_t start, rman_res_t end, void *arg);
299 pcib_walk_nonisa_ranges(rman_res_t start, rman_res_t end, nonisa_callback *cb,
305 * If start is within an ISA alias range, move up to the start
306 * of the next non-alias range. As a special case, addresses
307 * in the range 0x000 - 0x0ff should also be skipped since
308 * those are used for various system I/O devices in ISA
311 if (start <= 65535) {
312 if (start < 0x100 || (start & 0x300) != 0) {
318 /* ISA aliases are only in the lower 64KB of I/O space. */
319 while (start <= MIN(end, 65535)) {
320 next_end = MIN(start | 0xff, end);
321 cb(start, next_end, arg);
330 count_ranges(rman_res_t start, rman_res_t end, void *arg)
339 struct resource **res;
340 struct pcib_softc *sc;
345 alloc_ranges(rman_res_t start, rman_res_t end, void *arg)
347 struct alloc_state *as;
348 struct pcib_window *w;
358 device_printf(as->sc->dev,
359 "allocating non-ISA range %#jx-%#jx\n", start, end);
360 as->res[as->count] = bus_alloc_resource(as->sc->dev, SYS_RES_IOPORT,
361 &rid, start, end, end - start + 1, 0);
362 if (as->res[as->count] == NULL)
369 pcib_alloc_nonisa_ranges(struct pcib_softc *sc, rman_res_t start, rman_res_t end)
371 struct alloc_state as;
374 /* First, see how many ranges we need. */
376 pcib_walk_nonisa_ranges(start, end, count_ranges, &new_count);
378 /* Second, allocate the ranges. */
379 as.res = malloc(sizeof(struct resource *) * new_count, M_DEVBUF,
384 pcib_walk_nonisa_ranges(start, end, alloc_ranges, &as);
386 for (i = 0; i < as.count; i++)
387 bus_release_resource(sc->dev, SYS_RES_IOPORT,
388 sc->io.reg, as.res[i]);
389 free(as.res, M_DEVBUF);
392 KASSERT(as.count == new_count, ("%s: count mismatch", __func__));
394 /* Third, add the ranges to the window. */
395 pcib_add_window_resources(&sc->io, as.res, as.count);
396 free(as.res, M_DEVBUF);
401 pcib_alloc_window(struct pcib_softc *sc, struct pcib_window *w, int type,
402 int flags, pci_addr_t max_address)
404 struct resource *res;
408 if (max_address != (rman_res_t)max_address)
410 w->rman.rm_start = 0;
411 w->rman.rm_end = max_address;
412 w->rman.rm_type = RMAN_ARRAY;
413 snprintf(buf, sizeof(buf), "%s %s window",
414 device_get_nameunit(sc->dev), w->name);
415 w->rman.rm_descr = strdup(buf, M_DEVBUF);
416 error = rman_init(&w->rman);
418 panic("Failed to initialize %s %s rman",
419 device_get_nameunit(sc->dev), w->name);
421 if (!pcib_is_window_open(w))
424 if (w->base > max_address || w->limit > max_address) {
425 device_printf(sc->dev,
426 "initial %s window has too many bits, ignoring\n", w->name);
429 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE)
430 (void)pcib_alloc_nonisa_ranges(sc, w->base, w->limit);
433 res = bus_alloc_resource(sc->dev, type, &rid, w->base, w->limit,
434 w->limit - w->base + 1, flags);
436 pcib_add_window_resources(w, &res, 1);
438 if (w->res == NULL) {
439 device_printf(sc->dev,
440 "failed to allocate initial %s window: %#jx-%#jx\n",
441 w->name, (uintmax_t)w->base, (uintmax_t)w->limit);
442 w->base = max_address;
444 pcib_write_windows(sc, w->mask);
447 pcib_activate_window(sc, type);
451 * Initialize I/O windows.
454 pcib_probe_windows(struct pcib_softc *sc)
462 if (pci_clear_pcib) {
463 pcib_bridge_init(dev);
466 /* Determine if the I/O port window is implemented. */
467 val = pci_read_config(dev, PCIR_IOBASEL_1, 1);
470 * If 'val' is zero, then only 16-bits of I/O space
473 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1);
474 if (pci_read_config(dev, PCIR_IOBASEL_1, 1) != 0) {
476 pci_write_config(dev, PCIR_IOBASEL_1, 0, 1);
481 /* Read the existing I/O port window. */
483 sc->io.reg = PCIR_IOBASEL_1;
485 sc->io.mask = WIN_IO;
486 sc->io.name = "I/O port";
487 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
488 sc->io.base = PCI_PPBIOBASE(
489 pci_read_config(dev, PCIR_IOBASEH_1, 2), val);
490 sc->io.limit = PCI_PPBIOLIMIT(
491 pci_read_config(dev, PCIR_IOLIMITH_1, 2),
492 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
495 sc->io.base = PCI_PPBIOBASE(0, val);
496 sc->io.limit = PCI_PPBIOLIMIT(0,
497 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
500 pcib_alloc_window(sc, &sc->io, SYS_RES_IOPORT, 0, max);
503 /* Read the existing memory window. */
505 sc->mem.reg = PCIR_MEMBASE_1;
507 sc->mem.mask = WIN_MEM;
508 sc->mem.name = "memory";
509 sc->mem.base = PCI_PPBMEMBASE(0,
510 pci_read_config(dev, PCIR_MEMBASE_1, 2));
511 sc->mem.limit = PCI_PPBMEMLIMIT(0,
512 pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
513 pcib_alloc_window(sc, &sc->mem, SYS_RES_MEMORY, 0, 0xffffffff);
515 /* Determine if the prefetchable memory window is implemented. */
516 val = pci_read_config(dev, PCIR_PMBASEL_1, 2);
519 * If 'val' is zero, then only 32-bits of memory space
522 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2);
523 if (pci_read_config(dev, PCIR_PMBASEL_1, 2) != 0) {
525 pci_write_config(dev, PCIR_PMBASEL_1, 0, 2);
530 /* Read the existing prefetchable memory window. */
531 if (sc->pmem.valid) {
532 sc->pmem.reg = PCIR_PMBASEL_1;
534 sc->pmem.mask = WIN_PMEM;
535 sc->pmem.name = "prefetch";
536 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) {
537 sc->pmem.base = PCI_PPBMEMBASE(
538 pci_read_config(dev, PCIR_PMBASEH_1, 4), val);
539 sc->pmem.limit = PCI_PPBMEMLIMIT(
540 pci_read_config(dev, PCIR_PMLIMITH_1, 4),
541 pci_read_config(dev, PCIR_PMLIMITL_1, 2));
542 max = 0xffffffffffffffff;
544 sc->pmem.base = PCI_PPBMEMBASE(0, val);
545 sc->pmem.limit = PCI_PPBMEMLIMIT(0,
546 pci_read_config(dev, PCIR_PMLIMITL_1, 2));
549 pcib_alloc_window(sc, &sc->pmem, SYS_RES_MEMORY,
550 RF_PREFETCHABLE, max);
555 pcib_release_window(struct pcib_softc *sc, struct pcib_window *w, int type)
564 error = rman_fini(&w->rman);
566 device_printf(dev, "failed to release %s rman\n", w->name);
569 free(__DECONST(char *, w->rman.rm_descr), M_DEVBUF);
571 for (i = 0; i < w->count; i++) {
572 error = bus_free_resource(dev, type, w->res[i]);
575 "failed to release %s resource: %d\n", w->name,
578 free(w->res, M_DEVBUF);
582 pcib_free_windows(struct pcib_softc *sc)
585 pcib_release_window(sc, &sc->pmem, SYS_RES_MEMORY);
586 pcib_release_window(sc, &sc->mem, SYS_RES_MEMORY);
587 pcib_release_window(sc, &sc->io, SYS_RES_IOPORT);
592 * Allocate a suitable secondary bus for this bridge if needed and
593 * initialize the resource manager for the secondary bus range. Note
594 * that the minimum count is a desired value and this may allocate a
598 pcib_setup_secbus(device_t dev, struct pcib_secbus *bus, int min_count)
601 int error, rid, sec_reg;
603 switch (pci_read_config(dev, PCIR_HDRTYPE, 1) & PCIM_HDRTYPE) {
604 case PCIM_HDRTYPE_BRIDGE:
605 sec_reg = PCIR_SECBUS_1;
606 bus->sub_reg = PCIR_SUBBUS_1;
608 case PCIM_HDRTYPE_CARDBUS:
609 sec_reg = PCIR_SECBUS_2;
610 bus->sub_reg = PCIR_SUBBUS_2;
613 panic("not a PCI bridge");
615 bus->sec = pci_read_config(dev, sec_reg, 1);
616 bus->sub = pci_read_config(dev, bus->sub_reg, 1);
618 bus->rman.rm_start = 0;
619 bus->rman.rm_end = PCI_BUSMAX;
620 bus->rman.rm_type = RMAN_ARRAY;
621 snprintf(buf, sizeof(buf), "%s bus numbers", device_get_nameunit(dev));
622 bus->rman.rm_descr = strdup(buf, M_DEVBUF);
623 error = rman_init(&bus->rman);
625 panic("Failed to initialize %s bus number rman",
626 device_get_nameunit(dev));
629 * Allocate a bus range. This will return an existing bus range
630 * if one exists, or a new bus range if one does not.
633 bus->res = bus_alloc_resource_anywhere(dev, PCI_RES_BUS, &rid,
635 if (bus->res == NULL) {
637 * Fall back to just allocating a range of a single bus
640 bus->res = bus_alloc_resource_anywhere(dev, PCI_RES_BUS, &rid,
642 } else if (rman_get_size(bus->res) < min_count)
644 * Attempt to grow the existing range to satisfy the
645 * minimum desired count.
647 (void)bus_adjust_resource(dev, PCI_RES_BUS, bus->res,
648 rman_get_start(bus->res), rman_get_start(bus->res) +
652 * Add the initial resource to the rman.
654 if (bus->res != NULL) {
655 error = rman_manage_region(&bus->rman, rman_get_start(bus->res),
656 rman_get_end(bus->res));
658 panic("Failed to add resource to rman");
659 bus->sec = rman_get_start(bus->res);
660 bus->sub = rman_get_end(bus->res);
665 pcib_free_secbus(device_t dev, struct pcib_secbus *bus)
669 error = rman_fini(&bus->rman);
671 device_printf(dev, "failed to release bus number rman\n");
674 free(__DECONST(char *, bus->rman.rm_descr), M_DEVBUF);
676 error = bus_free_resource(dev, PCI_RES_BUS, bus->res);
679 "failed to release bus numbers resource: %d\n", error);
682 static struct resource *
683 pcib_suballoc_bus(struct pcib_secbus *bus, device_t child, int *rid,
684 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
686 struct resource *res;
688 res = rman_reserve_resource(&bus->rman, start, end, count, flags,
694 device_printf(bus->dev,
695 "allocated bus range (%ju-%ju) for rid %d of %s\n",
696 rman_get_start(res), rman_get_end(res), *rid,
697 pcib_child_name(child));
698 rman_set_rid(res, *rid);
703 * Attempt to grow the secondary bus range. This is much simpler than
704 * for I/O windows as the range can only be grown by increasing
708 pcib_grow_subbus(struct pcib_secbus *bus, rman_res_t new_end)
713 old_end = rman_get_end(bus->res);
714 KASSERT(new_end > old_end, ("attempt to shrink subbus"));
715 error = bus_adjust_resource(bus->dev, PCI_RES_BUS, bus->res,
716 rman_get_start(bus->res), new_end);
720 device_printf(bus->dev, "grew bus range to %ju-%ju\n",
721 rman_get_start(bus->res), rman_get_end(bus->res));
722 error = rman_manage_region(&bus->rman, old_end + 1,
723 rman_get_end(bus->res));
725 panic("Failed to add resource to rman");
726 bus->sub = rman_get_end(bus->res);
727 pci_write_config(bus->dev, bus->sub_reg, bus->sub, 1);
732 pcib_alloc_subbus(struct pcib_secbus *bus, device_t child, int *rid,
733 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
735 struct resource *res;
736 rman_res_t start_free, end_free, new_end;
739 * First, see if the request can be satisified by the existing
742 res = pcib_suballoc_bus(bus, child, rid, start, end, count, flags);
747 * Figure out a range to grow the bus range. First, find the
748 * first bus number after the last allocated bus in the rman and
749 * enforce that as a minimum starting point for the range.
751 if (rman_last_free_region(&bus->rman, &start_free, &end_free) != 0 ||
752 end_free != bus->sub)
753 start_free = bus->sub + 1;
754 if (start_free < start)
756 new_end = start_free + count - 1;
759 * See if this new range would satisfy the request if it
765 /* Finally, attempt to grow the existing resource. */
767 device_printf(bus->dev,
768 "attempting to grow bus range for %ju buses\n", count);
769 printf("\tback candidate range: %ju-%ju\n", start_free,
772 if (pcib_grow_subbus(bus, new_end) == 0)
773 return (pcib_suballoc_bus(bus, child, rid, start, end, count,
782 * Is the prefetch window open (eg, can we allocate memory in it?)
785 pcib_is_prefetch_open(struct pcib_softc *sc)
787 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit);
791 * Is the nonprefetch window open (eg, can we allocate memory in it?)
794 pcib_is_nonprefetch_open(struct pcib_softc *sc)
796 return (sc->membase > 0 && sc->membase < sc->memlimit);
800 * Is the io window open (eg, can we allocate ports in it?)
803 pcib_is_io_open(struct pcib_softc *sc)
805 return (sc->iobase > 0 && sc->iobase < sc->iolimit);
809 * Get current I/O decode.
812 pcib_get_io_decode(struct pcib_softc *sc)
819 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1);
820 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32)
821 sc->iobase = PCI_PPBIOBASE(
822 pci_read_config(dev, PCIR_IOBASEH_1, 2), iolow);
824 sc->iobase = PCI_PPBIOBASE(0, iolow);
826 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1);
827 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32)
828 sc->iolimit = PCI_PPBIOLIMIT(
829 pci_read_config(dev, PCIR_IOLIMITH_1, 2), iolow);
831 sc->iolimit = PCI_PPBIOLIMIT(0, iolow);
835 * Get current memory decode.
838 pcib_get_mem_decode(struct pcib_softc *sc)
845 sc->membase = PCI_PPBMEMBASE(0,
846 pci_read_config(dev, PCIR_MEMBASE_1, 2));
847 sc->memlimit = PCI_PPBMEMLIMIT(0,
848 pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
850 pmemlow = pci_read_config(dev, PCIR_PMBASEL_1, 2);
851 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64)
852 sc->pmembase = PCI_PPBMEMBASE(
853 pci_read_config(dev, PCIR_PMBASEH_1, 4), pmemlow);
855 sc->pmembase = PCI_PPBMEMBASE(0, pmemlow);
857 pmemlow = pci_read_config(dev, PCIR_PMLIMITL_1, 2);
858 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64)
859 sc->pmemlimit = PCI_PPBMEMLIMIT(
860 pci_read_config(dev, PCIR_PMLIMITH_1, 4), pmemlow);
862 sc->pmemlimit = PCI_PPBMEMLIMIT(0, pmemlow);
866 * Restore previous I/O decode.
869 pcib_set_io_decode(struct pcib_softc *sc)
876 iohi = sc->iobase >> 16;
878 pci_write_config(dev, PCIR_IOBASEH_1, iohi, 2);
879 pci_write_config(dev, PCIR_IOBASEL_1, sc->iobase >> 8, 1);
881 iohi = sc->iolimit >> 16;
883 pci_write_config(dev, PCIR_IOLIMITH_1, iohi, 2);
884 pci_write_config(dev, PCIR_IOLIMITL_1, sc->iolimit >> 8, 1);
888 * Restore previous memory decode.
891 pcib_set_mem_decode(struct pcib_softc *sc)
898 pci_write_config(dev, PCIR_MEMBASE_1, sc->membase >> 16, 2);
899 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->memlimit >> 16, 2);
901 pmemhi = sc->pmembase >> 32;
903 pci_write_config(dev, PCIR_PMBASEH_1, pmemhi, 4);
904 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmembase >> 16, 2);
906 pmemhi = sc->pmemlimit >> 32;
908 pci_write_config(dev, PCIR_PMLIMITH_1, pmemhi, 4);
909 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmemlimit >> 16, 2);
915 * PCI-express HotPlug support.
917 static int pci_enable_pcie_hp = 1;
918 SYSCTL_INT(_hw_pci, OID_AUTO, enable_pcie_hp, CTLFLAG_RDTUN,
919 &pci_enable_pcie_hp, 0,
920 "Enable support for native PCI-express HotPlug.");
923 pcib_probe_hotplug(struct pcib_softc *sc)
927 uint16_t link_sta, slot_sta;
929 if (!pci_enable_pcie_hp)
933 if (pci_find_cap(dev, PCIY_EXPRESS, NULL) != 0)
936 if (!(pcie_read_config(dev, PCIER_FLAGS, 2) & PCIEM_FLAGS_SLOT))
939 sc->pcie_slot_cap = pcie_read_config(dev, PCIER_SLOT_CAP, 4);
941 if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_HPC) == 0)
943 link_cap = pcie_read_config(dev, PCIER_LINK_CAP, 4);
944 if ((link_cap & PCIEM_LINK_CAP_DL_ACTIVE) == 0)
948 * Some devices report that they have an MRL when they actually
949 * do not. Since they always report that the MRL is open, child
950 * devices would be ignored. Try to detect these devices and
951 * ignore their claim of HotPlug support.
953 * If there is an open MRL but the Data Link Layer is active,
954 * the MRL is not real.
956 if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP) != 0) {
957 link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2);
958 slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2);
959 if ((slot_sta & PCIEM_SLOT_STA_MRLSS) != 0 &&
960 (link_sta & PCIEM_LINK_STA_DL_ACTIVE) != 0) {
966 * Now that we're sure we want to do hot plug, ask the
967 * firmware, if any, if that's OK.
969 if (pcib_request_feature(dev, PCI_FEATURE_HP) != 0) {
971 device_printf(dev, "Unable to activate hot plug feature.\n");
975 sc->flags |= PCIB_HOTPLUG;
979 * Send a HotPlug command to the slot control register. If this slot
980 * uses command completion interrupts and a previous command is still
981 * in progress, then the command is dropped. Once the previous
982 * command completes or times out, pcib_pcie_hotplug_update() will be
983 * invoked to post a new command based on the slot's state at that
987 pcib_pcie_hotplug_command(struct pcib_softc *sc, uint16_t val, uint16_t mask)
994 if (sc->flags & PCIB_HOTPLUG_CMD_PENDING)
997 ctl = pcie_read_config(dev, PCIER_SLOT_CTL, 2);
998 new = (ctl & ~mask) | val;
1002 device_printf(dev, "HotPlug command: %04x -> %04x\n", ctl, new);
1003 pcie_write_config(dev, PCIER_SLOT_CTL, new, 2);
1004 if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS) &&
1005 (ctl & new) & PCIEM_SLOT_CTL_CCIE) {
1006 sc->flags |= PCIB_HOTPLUG_CMD_PENDING;
1008 callout_reset(&sc->pcie_cc_timer, hz,
1009 pcib_pcie_cc_timeout, sc);
1014 pcib_pcie_hotplug_command_completed(struct pcib_softc *sc)
1021 device_printf(dev, "Command Completed\n");
1022 if (!(sc->flags & PCIB_HOTPLUG_CMD_PENDING))
1024 callout_stop(&sc->pcie_cc_timer);
1025 sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING;
1030 * Returns true if a card is fully inserted from the user's
1031 * perspective. It may not yet be ready for access, but the driver
1032 * can now start enabling access if necessary.
1035 pcib_hotplug_inserted(struct pcib_softc *sc)
1038 /* Pretend the card isn't present if a detach is forced. */
1039 if (sc->flags & PCIB_DETACHING)
1042 /* Card must be present in the slot. */
1043 if ((sc->pcie_slot_sta & PCIEM_SLOT_STA_PDS) == 0)
1046 /* A power fault implicitly turns off power to the slot. */
1047 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_PFD)
1050 /* If the MRL is disengaged, the slot is powered off. */
1051 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP &&
1052 (sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSS) != 0)
1059 * Returns -1 if the card is fully inserted, powered, and ready for
1060 * access. Otherwise, returns 0.
1063 pcib_hotplug_present(struct pcib_softc *sc)
1066 /* Card must be inserted. */
1067 if (!pcib_hotplug_inserted(sc))
1071 * Require the Electromechanical Interlock to be engaged if
1074 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_EIP &&
1075 (sc->pcie_slot_sta & PCIEM_SLOT_STA_EIS) == 0)
1078 /* Require the Data Link Layer to be active. */
1079 if (!(sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE))
1086 pcib_pcie_hotplug_update(struct pcib_softc *sc, uint16_t val, uint16_t mask,
1089 bool card_inserted, ei_engaged;
1091 /* Clear DETACHING if Presence Detect has cleared. */
1092 if ((sc->pcie_slot_sta & (PCIEM_SLOT_STA_PDC | PCIEM_SLOT_STA_PDS)) ==
1094 sc->flags &= ~PCIB_DETACHING;
1096 card_inserted = pcib_hotplug_inserted(sc);
1098 /* Turn the power indicator on if a card is inserted. */
1099 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PIP) {
1100 mask |= PCIEM_SLOT_CTL_PIC;
1102 val |= PCIEM_SLOT_CTL_PI_ON;
1103 else if (sc->flags & PCIB_DETACH_PENDING)
1104 val |= PCIEM_SLOT_CTL_PI_BLINK;
1106 val |= PCIEM_SLOT_CTL_PI_OFF;
1109 /* Turn the power on via the Power Controller if a card is inserted. */
1110 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PCP) {
1111 mask |= PCIEM_SLOT_CTL_PCC;
1113 val |= PCIEM_SLOT_CTL_PC_ON;
1115 val |= PCIEM_SLOT_CTL_PC_OFF;
1119 * If a card is inserted, enable the Electromechanical
1120 * Interlock. If a card is not inserted (or we are in the
1121 * process of detaching), disable the Electromechanical
1124 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_EIP) {
1125 mask |= PCIEM_SLOT_CTL_EIC;
1126 ei_engaged = (sc->pcie_slot_sta & PCIEM_SLOT_STA_EIS) != 0;
1127 if (card_inserted != ei_engaged)
1128 val |= PCIEM_SLOT_CTL_EIC;
1132 * Start a timer to see if the Data Link Layer times out.
1133 * Note that we only start the timer if Presence Detect or MRL Sensor
1134 * changed on this interrupt. Stop any scheduled timer if
1135 * the Data Link Layer is active.
1137 if (card_inserted &&
1138 !(sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE) &&
1140 (PCIEM_SLOT_STA_MRLSC | PCIEM_SLOT_STA_PDC)) {
1142 device_printf(sc->dev,
1143 "Data Link Layer inactive\n");
1145 callout_reset(&sc->pcie_dll_timer, hz,
1146 pcib_pcie_dll_timeout, sc);
1147 } else if (sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE)
1148 callout_stop(&sc->pcie_dll_timer);
1150 pcib_pcie_hotplug_command(sc, val, mask);
1153 * During attach the child "pci" device is added synchronously;
1154 * otherwise, the task is scheduled to manage the child
1157 if (schedule_task &&
1158 (pcib_hotplug_present(sc) != 0) != (sc->child != NULL))
1159 taskqueue_enqueue(taskqueue_thread, &sc->pcie_hp_task);
1163 pcib_pcie_intr_hotplug(void *arg)
1165 struct pcib_softc *sc;
1170 sc->pcie_slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2);
1172 /* Clear the events just reported. */
1173 pcie_write_config(dev, PCIER_SLOT_STA, sc->pcie_slot_sta, 2);
1176 device_printf(dev, "HotPlug interrupt: %#x\n",
1179 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_ABP) {
1180 if (sc->flags & PCIB_DETACH_PENDING) {
1182 "Attention Button Pressed: Detach Cancelled\n");
1183 sc->flags &= ~PCIB_DETACH_PENDING;
1184 callout_stop(&sc->pcie_ab_timer);
1187 "Attention Button Pressed: Detaching in 5 seconds\n");
1188 sc->flags |= PCIB_DETACH_PENDING;
1189 callout_reset(&sc->pcie_ab_timer, 5 * hz,
1190 pcib_pcie_ab_timeout, sc);
1193 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_PFD)
1194 device_printf(dev, "Power Fault Detected\n");
1195 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSC)
1196 device_printf(dev, "MRL Sensor Changed to %s\n",
1197 sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSS ? "open" :
1199 if (bootverbose && sc->pcie_slot_sta & PCIEM_SLOT_STA_PDC)
1200 device_printf(dev, "Presence Detect Changed to %s\n",
1201 sc->pcie_slot_sta & PCIEM_SLOT_STA_PDS ? "card present" :
1203 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_CC)
1204 pcib_pcie_hotplug_command_completed(sc);
1205 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_DLLSC) {
1206 sc->pcie_link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2);
1209 "Data Link Layer State Changed to %s\n",
1210 sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE ?
1211 "active" : "inactive");
1214 pcib_pcie_hotplug_update(sc, 0, 0, true);
1218 pcib_pcie_hotplug_task(void *context, int pending)
1220 struct pcib_softc *sc;
1226 if (pcib_hotplug_present(sc) != 0) {
1227 if (sc->child == NULL) {
1228 sc->child = device_add_child(dev, "pci", -1);
1229 bus_generic_attach(dev);
1232 if (sc->child != NULL) {
1233 if (device_delete_child(dev, sc->child) == 0)
1241 pcib_pcie_ab_timeout(void *arg)
1243 struct pcib_softc *sc;
1246 mtx_assert(&Giant, MA_OWNED);
1247 if (sc->flags & PCIB_DETACH_PENDING) {
1248 sc->flags |= PCIB_DETACHING;
1249 sc->flags &= ~PCIB_DETACH_PENDING;
1250 pcib_pcie_hotplug_update(sc, 0, 0, true);
1255 pcib_pcie_cc_timeout(void *arg)
1257 struct pcib_softc *sc;
1263 mtx_assert(&Giant, MA_OWNED);
1264 sta = pcie_read_config(dev, PCIER_SLOT_STA, 2);
1265 if (!(sta & PCIEM_SLOT_STA_CC)) {
1267 "HotPlug Command Timed Out - forcing detach\n");
1268 sc->flags &= ~(PCIB_HOTPLUG_CMD_PENDING | PCIB_DETACH_PENDING);
1269 sc->flags |= PCIB_DETACHING;
1270 pcib_pcie_hotplug_update(sc, 0, 0, true);
1273 "Missed HotPlug interrupt waiting for Command Completion\n");
1274 pcib_pcie_intr_hotplug(sc);
1279 pcib_pcie_dll_timeout(void *arg)
1281 struct pcib_softc *sc;
1287 mtx_assert(&Giant, MA_OWNED);
1288 sta = pcie_read_config(dev, PCIER_LINK_STA, 2);
1289 if (!(sta & PCIEM_LINK_STA_DL_ACTIVE)) {
1291 "Timed out waiting for Data Link Layer Active\n");
1292 sc->flags |= PCIB_DETACHING;
1293 pcib_pcie_hotplug_update(sc, 0, 0, true);
1294 } else if (sta != sc->pcie_link_sta) {
1296 "Missed HotPlug interrupt waiting for DLL Active\n");
1297 pcib_pcie_intr_hotplug(sc);
1302 pcib_alloc_pcie_irq(struct pcib_softc *sc)
1305 int count, error, rid;
1311 * For simplicity, only use MSI-X if there is a single message.
1312 * To support a device with multiple messages we would have to
1313 * use remap intr if the MSI number is not 0.
1315 count = pci_msix_count(dev);
1317 error = pci_alloc_msix(dev, &count);
1322 if (rid < 0 && pci_msi_count(dev) > 0) {
1324 error = pci_alloc_msi(dev, &count);
1332 sc->pcie_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1334 if (sc->pcie_irq == NULL) {
1336 "Failed to allocate interrupt for PCI-e events\n");
1338 pci_release_msi(dev);
1342 error = bus_setup_intr(dev, sc->pcie_irq, INTR_TYPE_MISC,
1343 NULL, pcib_pcie_intr_hotplug, sc, &sc->pcie_ihand);
1345 device_printf(dev, "Failed to setup PCI-e interrupt handler\n");
1346 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->pcie_irq);
1348 pci_release_msi(dev);
1355 pcib_release_pcie_irq(struct pcib_softc *sc)
1361 error = bus_teardown_intr(dev, sc->pcie_irq, sc->pcie_ihand);
1364 error = bus_free_resource(dev, SYS_RES_IRQ, sc->pcie_irq);
1367 return (pci_release_msi(dev));
1371 pcib_setup_hotplug(struct pcib_softc *sc)
1377 callout_init(&sc->pcie_ab_timer, 0);
1378 callout_init(&sc->pcie_cc_timer, 0);
1379 callout_init(&sc->pcie_dll_timer, 0);
1380 TASK_INIT(&sc->pcie_hp_task, 0, pcib_pcie_hotplug_task, sc);
1383 if (pcib_alloc_pcie_irq(sc) != 0)
1386 sc->pcie_link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2);
1387 sc->pcie_slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2);
1389 /* Clear any events previously pending. */
1390 pcie_write_config(dev, PCIER_SLOT_STA, sc->pcie_slot_sta, 2);
1392 /* Enable HotPlug events. */
1393 mask = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE |
1394 PCIEM_SLOT_CTL_CCIE | PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_MRLSCE |
1395 PCIEM_SLOT_CTL_PFDE | PCIEM_SLOT_CTL_ABPE;
1396 val = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE | PCIEM_SLOT_CTL_PDCE;
1397 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_APB)
1398 val |= PCIEM_SLOT_CTL_ABPE;
1399 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PCP)
1400 val |= PCIEM_SLOT_CTL_PFDE;
1401 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP)
1402 val |= PCIEM_SLOT_CTL_MRLSCE;
1403 if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS))
1404 val |= PCIEM_SLOT_CTL_CCIE;
1406 /* Turn the attention indicator off. */
1407 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_AIP) {
1408 mask |= PCIEM_SLOT_CTL_AIC;
1409 val |= PCIEM_SLOT_CTL_AI_OFF;
1412 pcib_pcie_hotplug_update(sc, val, mask, false);
1416 pcib_detach_hotplug(struct pcib_softc *sc)
1421 /* Disable the card in the slot and force it to detach. */
1422 if (sc->flags & PCIB_DETACH_PENDING) {
1423 sc->flags &= ~PCIB_DETACH_PENDING;
1424 callout_stop(&sc->pcie_ab_timer);
1426 sc->flags |= PCIB_DETACHING;
1428 if (sc->flags & PCIB_HOTPLUG_CMD_PENDING) {
1429 callout_stop(&sc->pcie_cc_timer);
1430 tsleep(sc, 0, "hpcmd", hz);
1431 sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING;
1434 /* Disable HotPlug events. */
1435 mask = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE |
1436 PCIEM_SLOT_CTL_CCIE | PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_MRLSCE |
1437 PCIEM_SLOT_CTL_PFDE | PCIEM_SLOT_CTL_ABPE;
1440 /* Turn the attention indicator off. */
1441 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_AIP) {
1442 mask |= PCIEM_SLOT_CTL_AIC;
1443 val |= PCIEM_SLOT_CTL_AI_OFF;
1446 pcib_pcie_hotplug_update(sc, val, mask, false);
1448 error = pcib_release_pcie_irq(sc);
1451 taskqueue_drain(taskqueue_thread, &sc->pcie_hp_task);
1452 callout_drain(&sc->pcie_ab_timer);
1453 callout_drain(&sc->pcie_cc_timer);
1454 callout_drain(&sc->pcie_dll_timer);
1460 * Get current bridge configuration.
1463 pcib_cfg_save(struct pcib_softc *sc)
1471 command = pci_read_config(dev, PCIR_COMMAND, 2);
1472 if (command & PCIM_CMD_PORTEN)
1473 pcib_get_io_decode(sc);
1474 if (command & PCIM_CMD_MEMEN)
1475 pcib_get_mem_decode(sc);
1480 * Restore previous bridge configuration.
1483 pcib_cfg_restore(struct pcib_softc *sc)
1490 pcib_write_windows(sc, WIN_IO | WIN_MEM | WIN_PMEM);
1492 command = pci_read_config(sc->dev, PCIR_COMMAND, 2);
1493 if (command & PCIM_CMD_PORTEN)
1494 pcib_set_io_decode(sc);
1495 if (command & PCIM_CMD_MEMEN)
1496 pcib_set_mem_decode(sc);
1501 * Generic device interface
1504 pcib_probe(device_t dev)
1506 if ((pci_get_class(dev) == PCIC_BRIDGE) &&
1507 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) {
1508 device_set_desc(dev, "PCI-PCI bridge");
1515 pcib_attach_common(device_t dev)
1517 struct pcib_softc *sc;
1518 struct sysctl_ctx_list *sctx;
1519 struct sysctl_oid *soid;
1522 sc = device_get_softc(dev);
1526 * Get current bridge configuration.
1528 sc->domain = pci_get_domain(dev);
1529 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS))
1530 sc->bus.sec = pci_read_config(dev, PCIR_SECBUS_1, 1);
1531 sc->bus.sub = pci_read_config(dev, PCIR_SUBBUS_1, 1);
1533 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
1537 * The primary bus register should always be the bus of the
1540 sc->pribus = pci_get_bus(dev);
1541 pci_write_config(dev, PCIR_PRIBUS_1, sc->pribus, 1);
1544 * Setup sysctl reporting nodes
1546 sctx = device_get_sysctl_ctx(dev);
1547 soid = device_get_sysctl_tree(dev);
1548 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain",
1549 CTLFLAG_RD, &sc->domain, 0, "Domain number");
1550 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus",
1551 CTLFLAG_RD, &sc->pribus, 0, "Primary bus number");
1552 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus",
1553 CTLFLAG_RD, &sc->bus.sec, 0, "Secondary bus number");
1554 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus",
1555 CTLFLAG_RD, &sc->bus.sub, 0, "Subordinate bus number");
1560 switch (pci_get_devid(dev)) {
1561 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS))
1562 case 0x12258086: /* Intel 82454KX/GX (Orion) */
1566 supbus = pci_read_config(dev, 0x41, 1);
1567 if (supbus != 0xff) {
1568 sc->bus.sec = supbus + 1;
1569 sc->bus.sub = supbus + 1;
1576 * The i82380FB mobile docking controller is a PCI-PCI bridge,
1577 * and it is a subtractive bridge. However, the ProgIf is wrong
1578 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't
1579 * happen. There are also Toshiba and Cavium ThunderX bridges
1580 * that behave this way.
1582 case 0xa002177d: /* Cavium ThunderX */
1583 case 0x124b8086: /* Intel 82380FB Mobile */
1584 case 0x060513d7: /* Toshiba ???? */
1585 sc->flags |= PCIB_SUBTRACTIVE;
1588 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS))
1589 /* Compaq R3000 BIOS sets wrong subordinate bus number. */
1594 if ((cp = kern_getenv("smbios.planar.maker")) == NULL)
1596 if (strncmp(cp, "Compal", 6) != 0) {
1601 if ((cp = kern_getenv("smbios.planar.product")) == NULL)
1603 if (strncmp(cp, "08A0", 4) != 0) {
1608 if (sc->bus.sub < 0xa) {
1609 pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1);
1610 sc->bus.sub = pci_read_config(dev, PCIR_SUBBUS_1, 1);
1617 if (pci_msi_device_blacklisted(dev))
1618 sc->flags |= PCIB_DISABLE_MSI;
1620 if (pci_msix_device_blacklisted(dev))
1621 sc->flags |= PCIB_DISABLE_MSIX;
1624 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges,
1625 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM,
1626 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese.
1627 * This means they act as if they were subtractively decoding
1628 * bridges and pass all transactions. Mark them and real ProgIf 1
1629 * parts as subtractive.
1631 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 ||
1632 pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_BRIDGE_PCI_SUBTRACTIVE)
1633 sc->flags |= PCIB_SUBTRACTIVE;
1636 pcib_probe_hotplug(sc);
1640 pcib_setup_secbus(dev, &sc->bus, 1);
1642 pcib_probe_windows(sc);
1645 if (sc->flags & PCIB_HOTPLUG)
1646 pcib_setup_hotplug(sc);
1649 device_printf(dev, " domain %d\n", sc->domain);
1650 device_printf(dev, " secondary bus %d\n", sc->bus.sec);
1651 device_printf(dev, " subordinate bus %d\n", sc->bus.sub);
1653 if (pcib_is_window_open(&sc->io))
1654 device_printf(dev, " I/O decode 0x%jx-0x%jx\n",
1655 (uintmax_t)sc->io.base, (uintmax_t)sc->io.limit);
1656 if (pcib_is_window_open(&sc->mem))
1657 device_printf(dev, " memory decode 0x%jx-0x%jx\n",
1658 (uintmax_t)sc->mem.base, (uintmax_t)sc->mem.limit);
1659 if (pcib_is_window_open(&sc->pmem))
1660 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n",
1661 (uintmax_t)sc->pmem.base, (uintmax_t)sc->pmem.limit);
1663 if (pcib_is_io_open(sc))
1664 device_printf(dev, " I/O decode 0x%x-0x%x\n",
1665 sc->iobase, sc->iolimit);
1666 if (pcib_is_nonprefetch_open(sc))
1667 device_printf(dev, " memory decode 0x%jx-0x%jx\n",
1668 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit);
1669 if (pcib_is_prefetch_open(sc))
1670 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n",
1671 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit);
1673 if (sc->bridgectl & (PCIB_BCR_ISA_ENABLE | PCIB_BCR_VGA_ENABLE) ||
1674 sc->flags & PCIB_SUBTRACTIVE) {
1675 device_printf(dev, " special decode ");
1677 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE) {
1681 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE) {
1682 printf("%sVGA", comma ? ", " : "");
1685 if (sc->flags & PCIB_SUBTRACTIVE)
1686 printf("%ssubtractive", comma ? ", " : "");
1692 * Always enable busmastering on bridges so that transactions
1693 * initiated on the secondary bus are passed through to the
1696 pci_enable_busmaster(dev);
1701 pcib_present(struct pcib_softc *sc)
1704 if (sc->flags & PCIB_HOTPLUG)
1705 return (pcib_hotplug_present(sc) != 0);
1711 pcib_attach_child(device_t dev)
1713 struct pcib_softc *sc;
1715 sc = device_get_softc(dev);
1716 if (sc->bus.sec == 0) {
1717 /* no secondary bus; we should have fixed this */
1722 if (!pcib_present(sc)) {
1723 /* An empty HotPlug slot, so don't add a PCI bus yet. */
1728 sc->child = device_add_child(dev, "pci", -1);
1729 return (bus_generic_attach(dev));
1733 pcib_attach(device_t dev)
1736 pcib_attach_common(dev);
1737 return (pcib_attach_child(dev));
1741 pcib_detach(device_t dev)
1743 #if defined(PCI_HP) || defined(NEW_PCIB)
1744 struct pcib_softc *sc;
1748 #if defined(PCI_HP) || defined(NEW_PCIB)
1749 sc = device_get_softc(dev);
1751 error = bus_generic_detach(dev);
1755 if (sc->flags & PCIB_HOTPLUG) {
1756 error = pcib_detach_hotplug(sc);
1761 error = device_delete_children(dev);
1765 pcib_free_windows(sc);
1767 pcib_free_secbus(dev, &sc->bus);
1774 pcib_suspend(device_t dev)
1777 pcib_cfg_save(device_get_softc(dev));
1778 return (bus_generic_suspend(dev));
1782 pcib_resume(device_t dev)
1785 pcib_cfg_restore(device_get_softc(dev));
1786 return (bus_generic_resume(dev));
1790 pcib_bridge_init(device_t dev)
1792 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1);
1793 pci_write_config(dev, PCIR_IOBASEH_1, 0xffff, 2);
1794 pci_write_config(dev, PCIR_IOLIMITL_1, 0, 1);
1795 pci_write_config(dev, PCIR_IOLIMITH_1, 0, 2);
1796 pci_write_config(dev, PCIR_MEMBASE_1, 0xffff, 2);
1797 pci_write_config(dev, PCIR_MEMLIMIT_1, 0, 2);
1798 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2);
1799 pci_write_config(dev, PCIR_PMBASEH_1, 0xffffffff, 4);
1800 pci_write_config(dev, PCIR_PMLIMITL_1, 0, 2);
1801 pci_write_config(dev, PCIR_PMLIMITH_1, 0, 4);
1805 pcib_child_present(device_t dev, device_t child)
1808 struct pcib_softc *sc = device_get_softc(dev);
1811 retval = bus_child_present(dev);
1812 if (retval != 0 && sc->flags & PCIB_HOTPLUG)
1813 retval = pcib_hotplug_present(sc);
1816 return (bus_child_present(dev));
1821 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1823 struct pcib_softc *sc = device_get_softc(dev);
1826 case PCIB_IVAR_DOMAIN:
1827 *result = sc->domain;
1830 *result = sc->bus.sec;
1837 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1841 case PCIB_IVAR_DOMAIN:
1851 * Attempt to allocate a resource from the existing resources assigned
1854 static struct resource *
1855 pcib_suballoc_resource(struct pcib_softc *sc, struct pcib_window *w,
1856 device_t child, int type, int *rid, rman_res_t start, rman_res_t end,
1857 rman_res_t count, u_int flags)
1859 struct resource *res;
1861 if (!pcib_is_window_open(w))
1864 res = rman_reserve_resource(&w->rman, start, end, count,
1865 flags & ~RF_ACTIVE, child);
1870 device_printf(sc->dev,
1871 "allocated %s range (%#jx-%#jx) for rid %x of %s\n",
1872 w->name, rman_get_start(res), rman_get_end(res), *rid,
1873 pcib_child_name(child));
1874 rman_set_rid(res, *rid);
1877 * If the resource should be active, pass that request up the
1878 * tree. This assumes the parent drivers can handle
1879 * activating sub-allocated resources.
1881 if (flags & RF_ACTIVE) {
1882 if (bus_activate_resource(child, type, *rid, res) != 0) {
1883 rman_release_resource(res);
1891 /* Allocate a fresh resource range for an unconfigured window. */
1893 pcib_alloc_new_window(struct pcib_softc *sc, struct pcib_window *w, int type,
1894 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
1896 struct resource *res;
1897 rman_res_t base, limit, wmask;
1901 * If this is an I/O window on a bridge with ISA enable set
1902 * and the start address is below 64k, then try to allocate an
1903 * initial window of 0x1000 bytes long starting at address
1904 * 0xf000 and walking down. Note that if the original request
1905 * was larger than the non-aliased range size of 0x100 our
1906 * caller would have raised the start address up to 64k
1909 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE &&
1911 for (base = 0xf000; (long)base >= 0; base -= 0x1000) {
1912 limit = base + 0xfff;
1915 * Skip ranges that wouldn't work for the
1916 * original request. Note that the actual
1917 * window that overlaps are the non-alias
1918 * ranges within [base, limit], so this isn't
1919 * quite a simple comparison.
1921 if (start + count > limit - 0x400)
1925 * The first open region for the window at
1928 if (end - count + 1 < 0x400)
1931 if (end - count + 1 < base)
1935 if (pcib_alloc_nonisa_ranges(sc, base, limit) == 0) {
1944 wmask = ((rman_res_t)1 << w->step) - 1;
1945 if (RF_ALIGNMENT(flags) < w->step) {
1946 flags &= ~RF_ALIGNMENT_MASK;
1947 flags |= RF_ALIGNMENT_LOG2(w->step);
1951 count = roundup2(count, (rman_res_t)1 << w->step);
1953 res = bus_alloc_resource(sc->dev, type, &rid, start, end, count,
1954 flags & ~RF_ACTIVE);
1957 pcib_add_window_resources(w, &res, 1);
1958 pcib_activate_window(sc, type);
1959 w->base = rman_get_start(res);
1960 w->limit = rman_get_end(res);
1964 /* Try to expand an existing window to the requested base and limit. */
1966 pcib_expand_window(struct pcib_softc *sc, struct pcib_window *w, int type,
1967 rman_res_t base, rman_res_t limit)
1969 struct resource *res;
1970 int error, i, force_64k_base;
1972 KASSERT(base <= w->base && limit >= w->limit,
1973 ("attempting to shrink window"));
1976 * XXX: pcib_grow_window() doesn't try to do this anyway and
1977 * the error handling for all the edge cases would be tedious.
1979 KASSERT(limit == w->limit || base == w->base,
1980 ("attempting to grow both ends of a window"));
1983 * Yet more special handling for requests to expand an I/O
1984 * window behind an ISA-enabled bridge. Since I/O windows
1985 * have to grow in 0x1000 increments and the end of the 0xffff
1986 * range is an alias, growing a window below 64k will always
1987 * result in allocating new resources and never adjusting an
1988 * existing resource.
1990 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE &&
1991 (limit <= 65535 || (base <= 65535 && base != w->base))) {
1992 KASSERT(limit == w->limit || limit <= 65535,
1993 ("attempting to grow both ends across 64k ISA alias"));
1995 if (base != w->base)
1996 error = pcib_alloc_nonisa_ranges(sc, base, w->base - 1);
1998 error = pcib_alloc_nonisa_ranges(sc, w->limit + 1,
2008 * Find the existing resource to adjust. Usually there is only one,
2009 * but for an ISA-enabled bridge we might be growing the I/O window
2010 * above 64k and need to find the existing resource that maps all
2011 * of the area above 64k.
2013 for (i = 0; i < w->count; i++) {
2014 if (rman_get_end(w->res[i]) == w->limit)
2017 KASSERT(i != w->count, ("did not find existing resource"));
2021 * Usually the resource we found should match the window's
2022 * existing range. The one exception is the ISA-enabled case
2023 * mentioned above in which case the resource should start at
2026 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE &&
2028 KASSERT(rman_get_start(res) == 65536,
2029 ("existing resource mismatch"));
2032 KASSERT(w->base == rman_get_start(res),
2033 ("existing resource mismatch"));
2037 error = bus_adjust_resource(sc->dev, type, res, force_64k_base ?
2038 rman_get_start(res) : base, limit);
2042 /* Add the newly allocated region to the resource manager. */
2043 if (w->base != base) {
2044 error = rman_manage_region(&w->rman, base, w->base - 1);
2047 error = rman_manage_region(&w->rman, w->limit + 1, limit);
2052 device_printf(sc->dev,
2053 "failed to expand %s resource manager\n", w->name);
2054 (void)bus_adjust_resource(sc->dev, type, res, force_64k_base ?
2055 rman_get_start(res) : w->base, w->limit);
2061 * Attempt to grow a window to make room for a given resource request.
2064 pcib_grow_window(struct pcib_softc *sc, struct pcib_window *w, int type,
2065 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
2067 rman_res_t align, start_free, end_free, front, back, wmask;
2071 * Clamp the desired resource range to the maximum address
2072 * this window supports. Reject impossible requests.
2074 * For I/O port requests behind a bridge with the ISA enable
2075 * bit set, force large allocations to start above 64k.
2079 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE && count > 0x100 &&
2082 if (end > w->rman.rm_end)
2083 end = w->rman.rm_end;
2084 if (start + count - 1 > end || start + count < start)
2086 wmask = ((rman_res_t)1 << w->step) - 1;
2089 * If there is no resource at all, just try to allocate enough
2090 * aligned space for this resource.
2092 if (w->res == NULL) {
2093 error = pcib_alloc_new_window(sc, w, type, start, end, count,
2097 device_printf(sc->dev,
2098 "failed to allocate initial %s window (%#jx-%#jx,%#jx)\n",
2099 w->name, start, end, count);
2103 device_printf(sc->dev,
2104 "allocated initial %s window of %#jx-%#jx\n",
2105 w->name, (uintmax_t)w->base, (uintmax_t)w->limit);
2110 * See if growing the window would help. Compute the minimum
2111 * amount of address space needed on both the front and back
2112 * ends of the existing window to satisfy the allocation.
2114 * For each end, build a candidate region adjusting for the
2115 * required alignment, etc. If there is a free region at the
2116 * edge of the window, grow from the inner edge of the free
2117 * region. Otherwise grow from the window boundary.
2119 * Growing an I/O window below 64k for a bridge with the ISA
2120 * enable bit doesn't require any special magic as the step
2121 * size of an I/O window (1k) always includes multiple
2122 * non-alias ranges when it is grown in either direction.
2124 * XXX: Special case: if w->res is completely empty and the
2125 * request size is larger than w->res, we should find the
2126 * optimal aligned buffer containing w->res and allocate that.
2129 device_printf(sc->dev,
2130 "attempting to grow %s window for (%#jx-%#jx,%#jx)\n",
2131 w->name, start, end, count);
2132 align = (rman_res_t)1 << RF_ALIGNMENT(flags);
2133 if (start < w->base) {
2134 if (rman_first_free_region(&w->rman, &start_free, &end_free) !=
2135 0 || start_free != w->base)
2140 /* Move end_free down until it is properly aligned. */
2141 end_free &= ~(align - 1);
2143 front = end_free - (count - 1);
2146 * The resource would now be allocated at (front,
2147 * end_free). Ensure that fits in the (start, end)
2148 * bounds. end_free is checked above. If 'front' is
2149 * ok, ensure it is properly aligned for this window.
2150 * Also check for underflow.
2152 if (front >= start && front <= end_free) {
2154 printf("\tfront candidate range: %#jx-%#jx\n",
2157 front = w->base - front;
2162 if (end > w->limit) {
2163 if (rman_last_free_region(&w->rman, &start_free, &end_free) !=
2164 0 || end_free != w->limit)
2165 start_free = w->limit + 1;
2166 if (start_free < start)
2169 /* Move start_free up until it is properly aligned. */
2170 start_free = roundup2(start_free, align);
2171 back = start_free + count - 1;
2174 * The resource would now be allocated at (start_free,
2175 * back). Ensure that fits in the (start, end)
2176 * bounds. start_free is checked above. If 'back' is
2177 * ok, ensure it is properly aligned for this window.
2178 * Also check for overflow.
2180 if (back <= end && start_free <= back) {
2182 printf("\tback candidate range: %#jx-%#jx\n",
2192 * Try to allocate the smallest needed region first.
2193 * If that fails, fall back to the other region.
2196 while (front != 0 || back != 0) {
2197 if (front != 0 && (front <= back || back == 0)) {
2198 error = pcib_expand_window(sc, w, type, w->base - front,
2204 error = pcib_expand_window(sc, w, type, w->base,
2215 device_printf(sc->dev, "grew %s window to %#jx-%#jx\n",
2216 w->name, (uintmax_t)w->base, (uintmax_t)w->limit);
2219 /* Write the new window. */
2220 KASSERT((w->base & wmask) == 0, ("start address is not aligned"));
2221 KASSERT((w->limit & wmask) == wmask, ("end address is not aligned"));
2222 pcib_write_windows(sc, w->mask);
2227 * We have to trap resource allocation requests and ensure that the bridge
2228 * is set up to, or capable of handling them.
2231 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
2232 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
2234 struct pcib_softc *sc;
2237 sc = device_get_softc(dev);
2240 * VGA resources are decoded iff the VGA enable bit is set in
2241 * the bridge control register. VGA resources do not fall into
2242 * the resource windows and are passed up to the parent.
2244 if ((type == SYS_RES_IOPORT && pci_is_vga_ioport_range(start, end)) ||
2245 (type == SYS_RES_MEMORY && pci_is_vga_memory_range(start, end))) {
2246 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE)
2247 return (bus_generic_alloc_resource(dev, child, type,
2248 rid, start, end, count, flags));
2256 return (pcib_alloc_subbus(&sc->bus, child, rid, start, end,
2259 case SYS_RES_IOPORT:
2260 if (pcib_is_isa_range(sc, start, end, count))
2262 r = pcib_suballoc_resource(sc, &sc->io, child, type, rid, start,
2264 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0)
2266 if (pcib_grow_window(sc, &sc->io, type, start, end, count,
2268 r = pcib_suballoc_resource(sc, &sc->io, child, type,
2269 rid, start, end, count, flags);
2271 case SYS_RES_MEMORY:
2273 * For prefetchable resources, prefer the prefetchable
2274 * memory window, but fall back to the regular memory
2275 * window if that fails. Try both windows before
2276 * attempting to grow a window in case the firmware
2277 * has used a range in the regular memory window to
2278 * map a prefetchable BAR.
2280 if (flags & RF_PREFETCHABLE) {
2281 r = pcib_suballoc_resource(sc, &sc->pmem, child, type,
2282 rid, start, end, count, flags);
2286 r = pcib_suballoc_resource(sc, &sc->mem, child, type, rid,
2287 start, end, count, flags);
2288 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0)
2290 if (flags & RF_PREFETCHABLE) {
2291 if (pcib_grow_window(sc, &sc->pmem, type, start, end,
2292 count, flags) == 0) {
2293 r = pcib_suballoc_resource(sc, &sc->pmem, child,
2294 type, rid, start, end, count, flags);
2299 if (pcib_grow_window(sc, &sc->mem, type, start, end, count,
2300 flags & ~RF_PREFETCHABLE) == 0)
2301 r = pcib_suballoc_resource(sc, &sc->mem, child, type,
2302 rid, start, end, count, flags);
2305 return (bus_generic_alloc_resource(dev, child, type, rid,
2306 start, end, count, flags));
2310 * If attempts to suballocate from the window fail but this is a
2311 * subtractive bridge, pass the request up the tree.
2313 if (sc->flags & PCIB_SUBTRACTIVE && r == NULL)
2314 return (bus_generic_alloc_resource(dev, child, type, rid,
2315 start, end, count, flags));
2320 pcib_adjust_resource(device_t bus, device_t child, int type, struct resource *r,
2321 rman_res_t start, rman_res_t end)
2323 struct pcib_softc *sc;
2325 sc = device_get_softc(bus);
2326 if (pcib_is_resource_managed(sc, type, r))
2327 return (rman_adjust_resource(r, start, end));
2328 return (bus_generic_adjust_resource(bus, child, type, r, start, end));
2332 pcib_release_resource(device_t dev, device_t child, int type, int rid,
2335 struct pcib_softc *sc;
2338 sc = device_get_softc(dev);
2339 if (pcib_is_resource_managed(sc, type, r)) {
2340 if (rman_get_flags(r) & RF_ACTIVE) {
2341 error = bus_deactivate_resource(child, type, rid, r);
2345 return (rman_release_resource(r));
2347 return (bus_generic_release_resource(dev, child, type, rid, r));
2351 * We have to trap resource allocation requests and ensure that the bridge
2352 * is set up to, or capable of handling them.
2355 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
2356 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
2358 struct pcib_softc *sc = device_get_softc(dev);
2359 const char *name, *suffix;
2363 * Fail the allocation for this range if it's not supported.
2365 name = device_get_nameunit(child);
2372 case SYS_RES_IOPORT:
2374 if (!pcib_is_io_open(sc))
2376 ok = (start >= sc->iobase && end <= sc->iolimit);
2379 * Make sure we allow access to VGA I/O addresses when the
2380 * bridge has the "VGA Enable" bit set.
2382 if (!ok && pci_is_vga_ioport_range(start, end))
2383 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
2385 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
2387 if (start < sc->iobase)
2389 if (end > sc->iolimit)
2398 * If we overlap with the subtractive range, then
2399 * pick the upper range to use.
2401 if (start < sc->iolimit && end > sc->iobase)
2402 start = sc->iolimit + 1;
2406 device_printf(dev, "ioport: end (%jx) < start (%jx)\n",
2413 device_printf(dev, "%s%srequested unsupported I/O "
2414 "range 0x%jx-0x%jx (decoding 0x%x-0x%x)\n",
2415 name, suffix, start, end, sc->iobase, sc->iolimit);
2420 "%s%srequested I/O range 0x%jx-0x%jx: in range\n",
2421 name, suffix, start, end);
2424 case SYS_RES_MEMORY:
2426 if (pcib_is_nonprefetch_open(sc))
2427 ok = ok || (start >= sc->membase && end <= sc->memlimit);
2428 if (pcib_is_prefetch_open(sc))
2429 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit);
2432 * Make sure we allow access to VGA memory addresses when the
2433 * bridge has the "VGA Enable" bit set.
2435 if (!ok && pci_is_vga_memory_range(start, end))
2436 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
2438 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
2441 if (flags & RF_PREFETCHABLE) {
2442 if (pcib_is_prefetch_open(sc)) {
2443 if (start < sc->pmembase)
2444 start = sc->pmembase;
2445 if (end > sc->pmemlimit)
2446 end = sc->pmemlimit;
2450 } else { /* non-prefetchable */
2451 if (pcib_is_nonprefetch_open(sc)) {
2452 if (start < sc->membase)
2453 start = sc->membase;
2454 if (end > sc->memlimit)
2462 ok = 1; /* subtractive bridge: always ok */
2464 if (pcib_is_nonprefetch_open(sc)) {
2465 if (start < sc->memlimit && end > sc->membase)
2466 start = sc->memlimit + 1;
2468 if (pcib_is_prefetch_open(sc)) {
2469 if (start < sc->pmemlimit && end > sc->pmembase)
2470 start = sc->pmemlimit + 1;
2475 device_printf(dev, "memory: end (%jx) < start (%jx)\n",
2481 if (!ok && bootverbose)
2483 "%s%srequested unsupported memory range %#jx-%#jx "
2484 "(decoding %#jx-%#jx, %#jx-%#jx)\n",
2485 name, suffix, start, end,
2486 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit,
2487 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit);
2491 device_printf(dev,"%s%srequested memory range "
2492 "0x%jx-0x%jx: good\n",
2493 name, suffix, start, end);
2500 * Bridge is OK decoding this resource, so pass it up.
2502 return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
2508 * If ARI is enabled on this downstream port, translate the function number
2509 * to the non-ARI slot/function. The downstream port will convert it back in
2510 * hardware. If ARI is not enabled slot and func are not modified.
2512 static __inline void
2513 pcib_xlate_ari(device_t pcib, int bus, int *slot, int *func)
2515 struct pcib_softc *sc;
2518 sc = device_get_softc(pcib);
2521 if (sc->flags & PCIB_ENABLE_ARI) {
2523 ("Non-zero slot number with ARI enabled!"));
2524 *slot = PCIE_ARI_SLOT(ari_func);
2525 *func = PCIE_ARI_FUNC(ari_func);
2531 pcib_enable_ari(struct pcib_softc *sc, uint32_t pcie_pos)
2535 ctl2 = pci_read_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, 4);
2536 ctl2 |= PCIEM_CTL2_ARI;
2537 pci_write_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, ctl2, 4);
2539 sc->flags |= PCIB_ENABLE_ARI;
2546 pcib_maxslots(device_t dev)
2548 #if !defined(__amd64__) && !defined(__i386__)
2553 * If this is a PCIe rootport or downstream switch port, there's only
2554 * one slot permitted.
2556 if (pci_find_cap(dev, PCIY_EXPRESS, &pcie_pos) == 0) {
2557 val = pci_read_config(dev, pcie_pos + PCIER_FLAGS, 2);
2558 val &= PCIEM_FLAGS_TYPE;
2559 if (val == PCIEM_TYPE_ROOT_PORT ||
2560 val == PCIEM_TYPE_DOWNSTREAM_PORT)
2564 return (PCI_SLOTMAX);
2568 pcib_ari_maxslots(device_t dev)
2570 struct pcib_softc *sc;
2572 sc = device_get_softc(dev);
2574 if (sc->flags & PCIB_ENABLE_ARI)
2575 return (PCIE_ARI_SLOTMAX);
2577 return (pcib_maxslots(dev));
2581 pcib_ari_maxfuncs(device_t dev)
2583 struct pcib_softc *sc;
2585 sc = device_get_softc(dev);
2587 if (sc->flags & PCIB_ENABLE_ARI)
2588 return (PCIE_ARI_FUNCMAX);
2590 return (PCI_FUNCMAX);
2594 pcib_ari_decode_rid(device_t pcib, uint16_t rid, int *bus, int *slot,
2597 struct pcib_softc *sc;
2599 sc = device_get_softc(pcib);
2601 *bus = PCI_RID2BUS(rid);
2602 if (sc->flags & PCIB_ENABLE_ARI) {
2603 *slot = PCIE_ARI_RID2SLOT(rid);
2604 *func = PCIE_ARI_RID2FUNC(rid);
2606 *slot = PCI_RID2SLOT(rid);
2607 *func = PCI_RID2FUNC(rid);
2612 * Since we are a child of a PCI bus, its parent must support the pcib interface.
2615 pcib_read_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, int width)
2618 struct pcib_softc *sc;
2620 sc = device_get_softc(dev);
2621 if (!pcib_present(sc)) {
2628 return (0xffffffff);
2632 pcib_xlate_ari(dev, b, &s, &f);
2633 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s,
2638 pcib_write_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, int width)
2641 struct pcib_softc *sc;
2643 sc = device_get_softc(dev);
2644 if (!pcib_present(sc))
2647 pcib_xlate_ari(dev, b, &s, &f);
2648 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f,
2653 * Route an interrupt across a PCI bridge.
2656 pcib_route_interrupt(device_t pcib, device_t dev, int pin)
2664 * The PCI standard defines a swizzle of the child-side device/intpin to
2665 * the parent-side intpin as follows.
2667 * device = device on child bus
2668 * child_intpin = intpin on child bus slot (0-3)
2669 * parent_intpin = intpin on parent bus slot (0-3)
2671 * parent_intpin = (device + child_intpin) % 4
2673 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4;
2676 * Our parent is a PCI bus. Its parent must export the pcib interface
2677 * which includes the ability to route interrupts.
2679 bus = device_get_parent(pcib);
2680 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1);
2681 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) {
2682 device_printf(pcib, "slot %d INT%c is routed to irq %d\n",
2683 pci_get_slot(dev), 'A' + pin - 1, intnum);
2688 /* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */
2690 pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs)
2692 struct pcib_softc *sc = device_get_softc(pcib);
2695 if (sc->flags & PCIB_DISABLE_MSI)
2697 bus = device_get_parent(pcib);
2698 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount,
2702 /* Pass request to release MSI/MSI-X messages up to the parent bridge. */
2704 pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs)
2708 bus = device_get_parent(pcib);
2709 return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs));
2712 /* Pass request to alloc an MSI-X message up to the parent bridge. */
2714 pcib_alloc_msix(device_t pcib, device_t dev, int *irq)
2716 struct pcib_softc *sc = device_get_softc(pcib);
2719 if (sc->flags & PCIB_DISABLE_MSIX)
2721 bus = device_get_parent(pcib);
2722 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq));
2725 /* Pass request to release an MSI-X message up to the parent bridge. */
2727 pcib_release_msix(device_t pcib, device_t dev, int irq)
2731 bus = device_get_parent(pcib);
2732 return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq));
2735 /* Pass request to map MSI/MSI-X message up to parent bridge. */
2737 pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
2743 bus = device_get_parent(pcib);
2744 error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data);
2748 pci_ht_map_msi(pcib, *addr);
2752 /* Pass request for device power state up to parent bridge. */
2754 pcib_power_for_sleep(device_t pcib, device_t dev, int *pstate)
2758 bus = device_get_parent(pcib);
2759 return (PCIB_POWER_FOR_SLEEP(bus, dev, pstate));
2763 pcib_ari_enabled(device_t pcib)
2765 struct pcib_softc *sc;
2767 sc = device_get_softc(pcib);
2769 return ((sc->flags & PCIB_ENABLE_ARI) != 0);
2773 pcib_ari_get_id(device_t pcib, device_t dev, enum pci_id_type type,
2776 struct pcib_softc *sc;
2778 uint8_t bus, slot, func;
2780 if (type != PCI_ID_RID) {
2781 bus_dev = device_get_parent(pcib);
2782 return (PCIB_GET_ID(device_get_parent(bus_dev), dev, type, id));
2785 sc = device_get_softc(pcib);
2787 if (sc->flags & PCIB_ENABLE_ARI) {
2788 bus = pci_get_bus(dev);
2789 func = pci_get_function(dev);
2791 *id = (PCI_ARI_RID(bus, func));
2793 bus = pci_get_bus(dev);
2794 slot = pci_get_slot(dev);
2795 func = pci_get_function(dev);
2797 *id = (PCI_RID(bus, slot, func));
2804 * Check that the downstream port (pcib) and the endpoint device (dev) both
2805 * support ARI. If so, enable it and return 0, otherwise return an error.
2808 pcib_try_enable_ari(device_t pcib, device_t dev)
2810 struct pcib_softc *sc;
2817 sc = device_get_softc(pcib);
2820 * ARI is controlled in a register in the PCIe capability structure.
2821 * If the downstream port does not have the PCIe capability structure
2822 * then it does not support ARI.
2824 error = pci_find_cap(pcib, PCIY_EXPRESS, &pcie_pos);
2828 /* Check that the PCIe port advertises ARI support. */
2829 cap2 = pci_read_config(pcib, pcie_pos + PCIER_DEVICE_CAP2, 4);
2830 if (!(cap2 & PCIEM_CAP2_ARI))
2834 * Check that the endpoint device advertises ARI support via the ARI
2835 * extended capability structure.
2837 error = pci_find_extcap(dev, PCIZ_ARI, &ari_cap_off);
2842 * Finally, check that the endpoint device supports the same version
2843 * of ARI that we do.
2845 ari_ver = pci_read_config(dev, ari_cap_off, 4);
2846 if (PCI_EXTCAP_VER(ari_ver) != PCIB_SUPPORTED_ARI_VER) {
2849 "Unsupported version of ARI (%d) detected\n",
2850 PCI_EXTCAP_VER(ari_ver));
2855 pcib_enable_ari(sc, pcie_pos);
2861 pcib_request_feature_allow(device_t pcib, device_t dev,
2862 enum pci_feature feature)
2865 * No host firmware we have to negotiate with, so we allow
2866 * every valid feature requested.
2869 case PCI_FEATURE_AER:
2870 case PCI_FEATURE_HP:
2880 pcib_request_feature(device_t dev, enum pci_feature feature)
2884 * Invoke PCIB_REQUEST_FEATURE of this bridge first in case
2885 * the firmware overrides the method of PCI-PCI bridges.
2887 return (PCIB_REQUEST_FEATURE(dev, dev, feature));
2891 * Pass the request to use this PCI feature up the tree. Either there's a
2892 * firmware like ACPI that's using this feature that will approve (or deny) the
2893 * request to take it over, or the platform has no such firmware, in which case
2894 * the request will be approved. If the request is approved, the OS is expected
2895 * to make use of the feature or render it harmless.
2898 pcib_request_feature_default(device_t pcib, device_t dev,
2899 enum pci_feature feature)
2904 * Our parent is necessarily a pci bus. Its parent will either be
2905 * another pci bridge (which passes it up) or a host bridge that can
2906 * approve or reject the request.
2908 bus = device_get_parent(pcib);
2909 return (PCIB_REQUEST_FEATURE(device_get_parent(bus), dev, feature));