2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000 BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
35 * PCI:PCI bridge support.
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
43 #include <machine/bus.h>
45 #include <sys/sysctl.h>
47 #include <machine/resource.h>
49 #include <dev/pci/pcivar.h>
50 #include <dev/pci/pcireg.h>
51 #include <dev/pci/pcib_private.h>
55 static int pcib_probe(device_t dev);
57 static device_method_t pcib_methods[] = {
58 /* Device interface */
59 DEVMETHOD(device_probe, pcib_probe),
60 DEVMETHOD(device_attach, pcib_attach),
61 DEVMETHOD(device_shutdown, bus_generic_shutdown),
62 DEVMETHOD(device_suspend, bus_generic_suspend),
63 DEVMETHOD(device_resume, bus_generic_resume),
66 DEVMETHOD(bus_print_child, bus_generic_print_child),
67 DEVMETHOD(bus_read_ivar, pcib_read_ivar),
68 DEVMETHOD(bus_write_ivar, pcib_write_ivar),
69 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
70 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
71 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
72 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
73 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
74 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
77 DEVMETHOD(pcib_maxslots, pcib_maxslots),
78 DEVMETHOD(pcib_read_config, pcib_read_config),
79 DEVMETHOD(pcib_write_config, pcib_write_config),
80 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
85 static driver_t pcib_driver = {
88 sizeof(struct pcib_softc),
91 devclass_t pcib_devclass;
93 DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0);
96 * Generic device interface
99 pcib_probe(device_t dev)
101 if ((pci_get_class(dev) == PCIC_BRIDGE) &&
102 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) {
103 device_set_desc(dev, "PCI-PCI bridge");
110 pcib_attach_common(device_t dev)
112 struct pcib_softc *sc;
115 sc = device_get_softc(dev);
119 * Get current bridge configuration.
121 sc->command = pci_read_config(dev, PCIR_COMMAND, 1);
122 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1);
123 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1);
124 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2);
125 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
126 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1);
129 * Determine current I/O decode.
131 if (sc->command & PCIM_CMD_PORTEN) {
132 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1);
133 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
134 sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2),
135 pci_read_config(dev, PCIR_IOBASEL_1, 1));
137 sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1));
140 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1);
141 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
142 sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2),
143 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
145 sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1));
150 * Determine current memory decode.
152 if (sc->command & PCIM_CMD_MEMEN) {
153 sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2));
154 sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
155 sc->pmembase = PCI_PPBMEMBASE((pci_addr_t)pci_read_config(dev, PCIR_PMBASEH_1, 4),
156 pci_read_config(dev, PCIR_PMBASEL_1, 2));
157 sc->pmemlimit = PCI_PPBMEMLIMIT((pci_addr_t)pci_read_config(dev, PCIR_PMLIMITH_1, 4),
158 pci_read_config(dev, PCIR_PMLIMITL_1, 2));
164 switch (pci_get_devid(dev)) {
165 case 0x12258086: /* Intel 82454KX/GX (Orion) */
169 supbus = pci_read_config(dev, 0x41, 1);
170 if (supbus != 0xff) {
171 sc->secbus = supbus + 1;
172 sc->subbus = supbus + 1;
178 * The i82380FB mobile docking controller is a PCI-PCI bridge,
179 * and it is a subtractive bridge. However, the ProgIf is wrong
180 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't
181 * happen. There's also a Toshiba bridge that behaves this
184 case 0x124b8086: /* Intel 82380FB Mobile */
185 case 0x060513d7: /* Toshiba ???? */
186 sc->flags |= PCIB_SUBTRACTIVE;
191 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges,
192 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM,
193 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese.
194 * This means they act as if they were subtractively decoding
195 * bridges and pass all transactions. Mark them and real ProgIf 1
196 * parts as subtractive.
198 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 ||
199 pci_read_config(dev, PCIR_PROGIF, 1) == 1)
200 sc->flags |= PCIB_SUBTRACTIVE;
203 device_printf(dev, " secondary bus %d\n", sc->secbus);
204 device_printf(dev, " subordinate bus %d\n", sc->subbus);
205 device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit);
206 device_printf(dev, " memory decode 0x%x-0x%x\n", sc->membase, sc->memlimit);
207 device_printf(dev, " prefetched decode 0x%x-0x%x\n", sc->pmembase, sc->pmemlimit);
208 if (sc->flags & PCIB_SUBTRACTIVE)
209 device_printf(dev, " Subtractively decoded bridge.\n");
213 * XXX If the secondary bus number is zero, we should assign a bus number
214 * since the BIOS hasn't, then initialise the bridge.
218 * XXX If the subordinate bus number is less than the secondary bus number,
219 * we should pick a better value. One sensible alternative would be to
220 * pick 255; the only tradeoff here is that configuration transactions
221 * would be more widely routed than absolutely necessary.
226 pcib_attach(device_t dev)
228 struct pcib_softc *sc;
231 pcib_attach_common(dev);
232 sc = device_get_softc(dev);
233 if (sc->secbus != 0) {
234 child = device_add_child(dev, "pci", sc->secbus);
236 return(bus_generic_attach(dev));
239 /* no secondary bus; we should have fixed this */
244 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
246 struct pcib_softc *sc = device_get_softc(dev);
250 *result = sc->secbus;
257 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
259 struct pcib_softc *sc = device_get_softc(dev);
270 * Is the prefetch window open (eg, can we allocate memory in it?)
273 pcib_is_prefetch_open(struct pcib_softc *sc)
275 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit);
279 * Is the nonprefetch window open (eg, can we allocate memory in it?)
282 pcib_is_nonprefetch_open(struct pcib_softc *sc)
284 return (sc->membase > 0 && sc->membase < sc->memlimit);
288 * Is the io window open (eg, can we allocate ports in it?)
291 pcib_is_io_open(struct pcib_softc *sc)
293 return (sc->iobase > 0 && sc->iobase < sc->iolimit);
297 * We have to trap resource allocation requests and ensure that the bridge
298 * is set up to, or capable of handling them.
301 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
302 u_long start, u_long end, u_long count, u_int flags)
304 struct pcib_softc *sc = device_get_softc(dev);
308 * Fail the allocation for this range if it's not supported.
313 if (!pcib_is_io_open(sc))
315 ok = (start >= sc->iobase && end <= sc->iolimit);
316 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
318 if (start < sc->iobase)
320 if (end > sc->iolimit)
328 if (start < sc->iobase && end > sc->iolimit) {
335 device_printf(dev, "ioport: end (%lx) < start (%lx)\n",
342 device_printf(dev, "%s requested unsupported I/O "
343 "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n",
344 device_get_nameunit(child), start, end,
345 sc->iobase, sc->iolimit);
350 "%s requested I/O range 0x%lx-0x%lx: in range\n",
351 device_get_nameunit(child), start, end);
356 if (pcib_is_nonprefetch_open(sc))
357 ok = ok || (start >= sc->membase && end <= sc->memlimit);
358 if (pcib_is_prefetch_open(sc))
359 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit);
360 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
363 if (flags & RF_PREFETCHABLE) {
364 if (pcib_is_prefetch_open(sc)) {
365 if (start < sc->pmembase)
366 start = sc->pmembase;
367 if (end > sc->pmemlimit)
372 } else { /* non-prefetchable */
373 if (pcib_is_nonprefetch_open(sc)) {
374 if (start < sc->membase)
376 if (end > sc->memlimit)
384 ok = 1; /* subtractive bridge: always ok */
386 if (pcib_is_nonprefetch_open(sc)) {
387 if (start < sc->membase && end > sc->memlimit) {
392 if (pcib_is_prefetch_open(sc)) {
393 if (start < sc->pmembase && end > sc->pmemlimit) {
394 start = sc->pmembase;
401 device_printf(dev, "memory: end (%lx) < start (%lx)\n",
407 if (!ok && bootverbose)
409 "%s requested unsupported memory range "
410 "0x%lx-0x%lx (decoding 0x%x-0x%x, 0x%x-0x%x)\n",
411 device_get_nameunit(child), start, end,
412 sc->membase, sc->memlimit, sc->pmembase,
417 device_printf(dev,"%s requested memory range "
418 "0x%lx-0x%lx: good\n",
419 device_get_nameunit(child), start, end);
426 * Bridge is OK decoding this resource, so pass it up.
428 return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
436 pcib_maxslots(device_t dev)
442 * Since we are a child of a PCI bus, its parent must support the pcib interface.
445 pcib_read_config(device_t dev, int b, int s, int f, int reg, int width)
447 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width));
451 pcib_write_config(device_t dev, int b, int s, int f, int reg, uint32_t val, int width)
453 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width);
457 * Route an interrupt across a PCI bridge.
460 pcib_route_interrupt(device_t pcib, device_t dev, int pin)
468 * The PCI standard defines a swizzle of the child-side device/intpin to
469 * the parent-side intpin as follows.
471 * device = device on child bus
472 * child_intpin = intpin on child bus slot (0-3)
473 * parent_intpin = intpin on parent bus slot (0-3)
475 * parent_intpin = (device + child_intpin) % 4
477 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4;
480 * Our parent is a PCI bus. Its parent must export the pcib interface
481 * which includes the ability to route interrupts.
483 bus = device_get_parent(pcib);
484 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1);
485 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) {
486 device_printf(pcib, "slot %d INT%c is routed to irq %d\n",
487 pci_get_slot(dev), 'A' + pin - 1, intnum);
493 * Try to read the bus number of a host-PCI bridge using appropriate config
497 host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func,
502 id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4);
503 if (id == 0xffffffff)
509 /* XXX This is a guess */
510 /* *busnum = read_config(bus, slot, func, 0x41, 1); */
514 /* Intel 82454KX/GX (Orion) */
515 *busnum = read_config(bus, slot, func, 0x4a, 1);
519 * For the 450nx chipset, there is a whole bundle of
520 * things pretending to be host bridges. The MIOC will
521 * be seen first and isn't really a pci bridge (the
522 * actual busses are attached to the PXB's). We need to
523 * read the registers of the MIOC to figure out the
524 * bus numbers for the PXB channels.
526 * Since the MIOC doesn't have a pci bus attached, we
527 * pretend it wasn't there.
533 /* Intel 82454NX PXB#0, Bus#A */
534 *busnum = read_config(bus, 0x10, func, 0xd0, 1);
537 /* Intel 82454NX PXB#0, Bus#B */
538 *busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1;
541 /* Intel 82454NX PXB#1, Bus#A */
542 *busnum = read_config(bus, 0x10, func, 0xd3, 1);
545 /* Intel 82454NX PXB#1, Bus#B */
546 *busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1;
551 /* ServerWorks -- vendor 0x1166 */
563 *busnum = read_config(bus, slot, func, 0x44, 1);
566 /* Compaq/HP -- vendor 0x0e11 */
568 *busnum = read_config(bus, slot, func, 0xc8, 1);
571 /* Don't know how to read bus number. */