2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000 BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
35 * PCI:PCI bridge support.
40 #include <sys/param.h>
42 #include <sys/kernel.h>
43 #include <sys/malloc.h>
44 #include <sys/module.h>
46 #include <sys/sysctl.h>
47 #include <sys/systm.h>
48 #include <sys/taskqueue.h>
50 #include <dev/pci/pcivar.h>
51 #include <dev/pci/pcireg.h>
52 #include <dev/pci/pci_private.h>
53 #include <dev/pci/pcib_private.h>
57 static int pcib_probe(device_t dev);
58 static int pcib_suspend(device_t dev);
59 static int pcib_resume(device_t dev);
60 static int pcib_power_for_sleep(device_t pcib, device_t dev,
62 static int pcib_ari_get_id(device_t pcib, device_t dev,
63 enum pci_id_type type, uintptr_t *id);
64 static uint32_t pcib_read_config(device_t dev, u_int b, u_int s,
65 u_int f, u_int reg, int width);
66 static void pcib_write_config(device_t dev, u_int b, u_int s,
67 u_int f, u_int reg, uint32_t val, int width);
68 static int pcib_ari_maxslots(device_t dev);
69 static int pcib_ari_maxfuncs(device_t dev);
70 static int pcib_try_enable_ari(device_t pcib, device_t dev);
71 static int pcib_ari_enabled(device_t pcib);
72 static void pcib_ari_decode_rid(device_t pcib, uint16_t rid,
73 int *bus, int *slot, int *func);
75 static void pcib_pcie_ab_timeout(void *arg);
76 static void pcib_pcie_cc_timeout(void *arg);
77 static void pcib_pcie_dll_timeout(void *arg);
80 static device_method_t pcib_methods[] = {
81 /* Device interface */
82 DEVMETHOD(device_probe, pcib_probe),
83 DEVMETHOD(device_attach, pcib_attach),
84 DEVMETHOD(device_detach, pcib_detach),
85 DEVMETHOD(device_shutdown, bus_generic_shutdown),
86 DEVMETHOD(device_suspend, pcib_suspend),
87 DEVMETHOD(device_resume, pcib_resume),
90 DEVMETHOD(bus_child_present, pcib_child_present),
91 DEVMETHOD(bus_read_ivar, pcib_read_ivar),
92 DEVMETHOD(bus_write_ivar, pcib_write_ivar),
93 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
95 DEVMETHOD(bus_adjust_resource, pcib_adjust_resource),
96 DEVMETHOD(bus_release_resource, pcib_release_resource),
98 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
99 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
101 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
102 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
103 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
104 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
107 DEVMETHOD(pcib_maxslots, pcib_ari_maxslots),
108 DEVMETHOD(pcib_maxfuncs, pcib_ari_maxfuncs),
109 DEVMETHOD(pcib_read_config, pcib_read_config),
110 DEVMETHOD(pcib_write_config, pcib_write_config),
111 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
112 DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi),
113 DEVMETHOD(pcib_release_msi, pcib_release_msi),
114 DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix),
115 DEVMETHOD(pcib_release_msix, pcib_release_msix),
116 DEVMETHOD(pcib_map_msi, pcib_map_msi),
117 DEVMETHOD(pcib_power_for_sleep, pcib_power_for_sleep),
118 DEVMETHOD(pcib_get_id, pcib_ari_get_id),
119 DEVMETHOD(pcib_try_enable_ari, pcib_try_enable_ari),
120 DEVMETHOD(pcib_ari_enabled, pcib_ari_enabled),
121 DEVMETHOD(pcib_decode_rid, pcib_ari_decode_rid),
126 static devclass_t pcib_devclass;
128 DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc));
129 DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, NULL, NULL);
131 #if defined(NEW_PCIB) || defined(PCI_HP)
132 SYSCTL_DECL(_hw_pci);
136 static int pci_clear_pcib;
137 SYSCTL_INT(_hw_pci, OID_AUTO, clear_pcib, CTLFLAG_RDTUN, &pci_clear_pcib, 0,
138 "Clear firmware-assigned resources for PCI-PCI bridge I/O windows.");
141 * Is a resource from a child device sub-allocated from one of our
145 pcib_is_resource_managed(struct pcib_softc *sc, int type, struct resource *r)
151 return (rman_is_region_manager(r, &sc->bus.rman));
154 return (rman_is_region_manager(r, &sc->io.rman));
156 /* Prefetchable resources may live in either memory rman. */
157 if (rman_get_flags(r) & RF_PREFETCHABLE &&
158 rman_is_region_manager(r, &sc->pmem.rman))
160 return (rman_is_region_manager(r, &sc->mem.rman));
166 pcib_is_window_open(struct pcib_window *pw)
169 return (pw->valid && pw->base < pw->limit);
173 * XXX: If RF_ACTIVE did not also imply allocating a bus space tag and
174 * handle for the resource, we could pass RF_ACTIVE up to the PCI bus
175 * when allocating the resource windows and rely on the PCI bus driver
179 pcib_activate_window(struct pcib_softc *sc, int type)
182 PCI_ENABLE_IO(device_get_parent(sc->dev), sc->dev, type);
186 pcib_write_windows(struct pcib_softc *sc, int mask)
192 if (sc->io.valid && mask & WIN_IO) {
193 val = pci_read_config(dev, PCIR_IOBASEL_1, 1);
194 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
195 pci_write_config(dev, PCIR_IOBASEH_1,
196 sc->io.base >> 16, 2);
197 pci_write_config(dev, PCIR_IOLIMITH_1,
198 sc->io.limit >> 16, 2);
200 pci_write_config(dev, PCIR_IOBASEL_1, sc->io.base >> 8, 1);
201 pci_write_config(dev, PCIR_IOLIMITL_1, sc->io.limit >> 8, 1);
204 if (mask & WIN_MEM) {
205 pci_write_config(dev, PCIR_MEMBASE_1, sc->mem.base >> 16, 2);
206 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->mem.limit >> 16, 2);
209 if (sc->pmem.valid && mask & WIN_PMEM) {
210 val = pci_read_config(dev, PCIR_PMBASEL_1, 2);
211 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) {
212 pci_write_config(dev, PCIR_PMBASEH_1,
213 sc->pmem.base >> 32, 4);
214 pci_write_config(dev, PCIR_PMLIMITH_1,
215 sc->pmem.limit >> 32, 4);
217 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmem.base >> 16, 2);
218 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmem.limit >> 16, 2);
223 * This is used to reject I/O port allocations that conflict with an
227 pcib_is_isa_range(struct pcib_softc *sc, rman_res_t start, rman_res_t end,
230 rman_res_t next_alias;
232 if (!(sc->bridgectl & PCIB_BCR_ISA_ENABLE))
235 /* Only check fixed ranges for overlap. */
236 if (start + count - 1 != end)
239 /* ISA aliases are only in the lower 64KB of I/O space. */
243 /* Check for overlap with 0x000 - 0x0ff as a special case. */
248 * If the start address is an alias, the range is an alias.
249 * Otherwise, compute the start of the next alias range and
250 * check if it is before the end of the candidate range.
252 if ((start & 0x300) != 0)
254 next_alias = (start & ~0x3fful) | 0x100;
255 if (next_alias <= end)
261 device_printf(sc->dev,
262 "I/O range %#jx-%#jx overlaps with an ISA alias\n", start,
268 pcib_add_window_resources(struct pcib_window *w, struct resource **res,
271 struct resource **newarray;
274 newarray = malloc(sizeof(struct resource *) * (w->count + count),
277 bcopy(w->res, newarray, sizeof(struct resource *) * w->count);
278 bcopy(res, newarray + w->count, sizeof(struct resource *) * count);
279 free(w->res, M_DEVBUF);
283 for (i = 0; i < count; i++) {
284 error = rman_manage_region(&w->rman, rman_get_start(res[i]),
285 rman_get_end(res[i]));
287 panic("Failed to add resource to rman");
291 typedef void (nonisa_callback)(rman_res_t start, rman_res_t end, void *arg);
294 pcib_walk_nonisa_ranges(rman_res_t start, rman_res_t end, nonisa_callback *cb,
300 * If start is within an ISA alias range, move up to the start
301 * of the next non-alias range. As a special case, addresses
302 * in the range 0x000 - 0x0ff should also be skipped since
303 * those are used for various system I/O devices in ISA
306 if (start <= 65535) {
307 if (start < 0x100 || (start & 0x300) != 0) {
313 /* ISA aliases are only in the lower 64KB of I/O space. */
314 while (start <= MIN(end, 65535)) {
315 next_end = MIN(start | 0xff, end);
316 cb(start, next_end, arg);
325 count_ranges(rman_res_t start, rman_res_t end, void *arg)
334 struct resource **res;
335 struct pcib_softc *sc;
340 alloc_ranges(rman_res_t start, rman_res_t end, void *arg)
342 struct alloc_state *as;
343 struct pcib_window *w;
353 device_printf(as->sc->dev,
354 "allocating non-ISA range %#jx-%#jx\n", start, end);
355 as->res[as->count] = bus_alloc_resource(as->sc->dev, SYS_RES_IOPORT,
356 &rid, start, end, end - start + 1, 0);
357 if (as->res[as->count] == NULL)
364 pcib_alloc_nonisa_ranges(struct pcib_softc *sc, rman_res_t start, rman_res_t end)
366 struct alloc_state as;
369 /* First, see how many ranges we need. */
371 pcib_walk_nonisa_ranges(start, end, count_ranges, &new_count);
373 /* Second, allocate the ranges. */
374 as.res = malloc(sizeof(struct resource *) * new_count, M_DEVBUF,
379 pcib_walk_nonisa_ranges(start, end, alloc_ranges, &as);
381 for (i = 0; i < as.count; i++)
382 bus_release_resource(sc->dev, SYS_RES_IOPORT,
383 sc->io.reg, as.res[i]);
384 free(as.res, M_DEVBUF);
387 KASSERT(as.count == new_count, ("%s: count mismatch", __func__));
389 /* Third, add the ranges to the window. */
390 pcib_add_window_resources(&sc->io, as.res, as.count);
391 free(as.res, M_DEVBUF);
396 pcib_alloc_window(struct pcib_softc *sc, struct pcib_window *w, int type,
397 int flags, pci_addr_t max_address)
399 struct resource *res;
403 if (max_address != (rman_res_t)max_address)
405 w->rman.rm_start = 0;
406 w->rman.rm_end = max_address;
407 w->rman.rm_type = RMAN_ARRAY;
408 snprintf(buf, sizeof(buf), "%s %s window",
409 device_get_nameunit(sc->dev), w->name);
410 w->rman.rm_descr = strdup(buf, M_DEVBUF);
411 error = rman_init(&w->rman);
413 panic("Failed to initialize %s %s rman",
414 device_get_nameunit(sc->dev), w->name);
416 if (!pcib_is_window_open(w))
419 if (w->base > max_address || w->limit > max_address) {
420 device_printf(sc->dev,
421 "initial %s window has too many bits, ignoring\n", w->name);
424 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE)
425 (void)pcib_alloc_nonisa_ranges(sc, w->base, w->limit);
428 res = bus_alloc_resource(sc->dev, type, &rid, w->base, w->limit,
429 w->limit - w->base + 1, flags);
431 pcib_add_window_resources(w, &res, 1);
433 if (w->res == NULL) {
434 device_printf(sc->dev,
435 "failed to allocate initial %s window: %#jx-%#jx\n",
436 w->name, (uintmax_t)w->base, (uintmax_t)w->limit);
437 w->base = max_address;
439 pcib_write_windows(sc, w->mask);
442 pcib_activate_window(sc, type);
446 * Initialize I/O windows.
449 pcib_probe_windows(struct pcib_softc *sc)
457 if (pci_clear_pcib) {
458 pcib_bridge_init(dev);
461 /* Determine if the I/O port window is implemented. */
462 val = pci_read_config(dev, PCIR_IOBASEL_1, 1);
465 * If 'val' is zero, then only 16-bits of I/O space
468 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1);
469 if (pci_read_config(dev, PCIR_IOBASEL_1, 1) != 0) {
471 pci_write_config(dev, PCIR_IOBASEL_1, 0, 1);
476 /* Read the existing I/O port window. */
478 sc->io.reg = PCIR_IOBASEL_1;
480 sc->io.mask = WIN_IO;
481 sc->io.name = "I/O port";
482 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
483 sc->io.base = PCI_PPBIOBASE(
484 pci_read_config(dev, PCIR_IOBASEH_1, 2), val);
485 sc->io.limit = PCI_PPBIOLIMIT(
486 pci_read_config(dev, PCIR_IOLIMITH_1, 2),
487 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
490 sc->io.base = PCI_PPBIOBASE(0, val);
491 sc->io.limit = PCI_PPBIOLIMIT(0,
492 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
495 pcib_alloc_window(sc, &sc->io, SYS_RES_IOPORT, 0, max);
498 /* Read the existing memory window. */
500 sc->mem.reg = PCIR_MEMBASE_1;
502 sc->mem.mask = WIN_MEM;
503 sc->mem.name = "memory";
504 sc->mem.base = PCI_PPBMEMBASE(0,
505 pci_read_config(dev, PCIR_MEMBASE_1, 2));
506 sc->mem.limit = PCI_PPBMEMLIMIT(0,
507 pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
508 pcib_alloc_window(sc, &sc->mem, SYS_RES_MEMORY, 0, 0xffffffff);
510 /* Determine if the prefetchable memory window is implemented. */
511 val = pci_read_config(dev, PCIR_PMBASEL_1, 2);
514 * If 'val' is zero, then only 32-bits of memory space
517 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2);
518 if (pci_read_config(dev, PCIR_PMBASEL_1, 2) != 0) {
520 pci_write_config(dev, PCIR_PMBASEL_1, 0, 2);
525 /* Read the existing prefetchable memory window. */
526 if (sc->pmem.valid) {
527 sc->pmem.reg = PCIR_PMBASEL_1;
529 sc->pmem.mask = WIN_PMEM;
530 sc->pmem.name = "prefetch";
531 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) {
532 sc->pmem.base = PCI_PPBMEMBASE(
533 pci_read_config(dev, PCIR_PMBASEH_1, 4), val);
534 sc->pmem.limit = PCI_PPBMEMLIMIT(
535 pci_read_config(dev, PCIR_PMLIMITH_1, 4),
536 pci_read_config(dev, PCIR_PMLIMITL_1, 2));
537 max = 0xffffffffffffffff;
539 sc->pmem.base = PCI_PPBMEMBASE(0, val);
540 sc->pmem.limit = PCI_PPBMEMLIMIT(0,
541 pci_read_config(dev, PCIR_PMLIMITL_1, 2));
544 pcib_alloc_window(sc, &sc->pmem, SYS_RES_MEMORY,
545 RF_PREFETCHABLE, max);
550 pcib_release_window(struct pcib_softc *sc, struct pcib_window *w, int type)
559 error = rman_fini(&w->rman);
561 device_printf(dev, "failed to release %s rman\n", w->name);
564 free(__DECONST(char *, w->rman.rm_descr), M_DEVBUF);
566 for (i = 0; i < w->count; i++) {
567 error = bus_free_resource(dev, type, w->res[i]);
570 "failed to release %s resource: %d\n", w->name,
573 free(w->res, M_DEVBUF);
577 pcib_free_windows(struct pcib_softc *sc)
580 pcib_release_window(sc, &sc->pmem, SYS_RES_MEMORY);
581 pcib_release_window(sc, &sc->mem, SYS_RES_MEMORY);
582 pcib_release_window(sc, &sc->io, SYS_RES_IOPORT);
587 * Allocate a suitable secondary bus for this bridge if needed and
588 * initialize the resource manager for the secondary bus range. Note
589 * that the minimum count is a desired value and this may allocate a
593 pcib_setup_secbus(device_t dev, struct pcib_secbus *bus, int min_count)
596 int error, rid, sec_reg;
598 switch (pci_read_config(dev, PCIR_HDRTYPE, 1) & PCIM_HDRTYPE) {
599 case PCIM_HDRTYPE_BRIDGE:
600 sec_reg = PCIR_SECBUS_1;
601 bus->sub_reg = PCIR_SUBBUS_1;
603 case PCIM_HDRTYPE_CARDBUS:
604 sec_reg = PCIR_SECBUS_2;
605 bus->sub_reg = PCIR_SUBBUS_2;
608 panic("not a PCI bridge");
610 bus->sec = pci_read_config(dev, sec_reg, 1);
611 bus->sub = pci_read_config(dev, bus->sub_reg, 1);
613 bus->rman.rm_start = 0;
614 bus->rman.rm_end = PCI_BUSMAX;
615 bus->rman.rm_type = RMAN_ARRAY;
616 snprintf(buf, sizeof(buf), "%s bus numbers", device_get_nameunit(dev));
617 bus->rman.rm_descr = strdup(buf, M_DEVBUF);
618 error = rman_init(&bus->rman);
620 panic("Failed to initialize %s bus number rman",
621 device_get_nameunit(dev));
624 * Allocate a bus range. This will return an existing bus range
625 * if one exists, or a new bus range if one does not.
628 bus->res = bus_alloc_resource_anywhere(dev, PCI_RES_BUS, &rid,
630 if (bus->res == NULL) {
632 * Fall back to just allocating a range of a single bus
635 bus->res = bus_alloc_resource_anywhere(dev, PCI_RES_BUS, &rid,
637 } else if (rman_get_size(bus->res) < min_count)
639 * Attempt to grow the existing range to satisfy the
640 * minimum desired count.
642 (void)bus_adjust_resource(dev, PCI_RES_BUS, bus->res,
643 rman_get_start(bus->res), rman_get_start(bus->res) +
647 * Add the initial resource to the rman.
649 if (bus->res != NULL) {
650 error = rman_manage_region(&bus->rman, rman_get_start(bus->res),
651 rman_get_end(bus->res));
653 panic("Failed to add resource to rman");
654 bus->sec = rman_get_start(bus->res);
655 bus->sub = rman_get_end(bus->res);
660 pcib_free_secbus(device_t dev, struct pcib_secbus *bus)
664 error = rman_fini(&bus->rman);
666 device_printf(dev, "failed to release bus number rman\n");
669 free(__DECONST(char *, bus->rman.rm_descr), M_DEVBUF);
671 error = bus_free_resource(dev, PCI_RES_BUS, bus->res);
674 "failed to release bus numbers resource: %d\n", error);
677 static struct resource *
678 pcib_suballoc_bus(struct pcib_secbus *bus, device_t child, int *rid,
679 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
681 struct resource *res;
683 res = rman_reserve_resource(&bus->rman, start, end, count, flags,
689 device_printf(bus->dev,
690 "allocated bus range (%ju-%ju) for rid %d of %s\n",
691 rman_get_start(res), rman_get_end(res), *rid,
692 pcib_child_name(child));
693 rman_set_rid(res, *rid);
698 * Attempt to grow the secondary bus range. This is much simpler than
699 * for I/O windows as the range can only be grown by increasing
703 pcib_grow_subbus(struct pcib_secbus *bus, rman_res_t new_end)
708 old_end = rman_get_end(bus->res);
709 KASSERT(new_end > old_end, ("attempt to shrink subbus"));
710 error = bus_adjust_resource(bus->dev, PCI_RES_BUS, bus->res,
711 rman_get_start(bus->res), new_end);
715 device_printf(bus->dev, "grew bus range to %ju-%ju\n",
716 rman_get_start(bus->res), rman_get_end(bus->res));
717 error = rman_manage_region(&bus->rman, old_end + 1,
718 rman_get_end(bus->res));
720 panic("Failed to add resource to rman");
721 bus->sub = rman_get_end(bus->res);
722 pci_write_config(bus->dev, bus->sub_reg, bus->sub, 1);
727 pcib_alloc_subbus(struct pcib_secbus *bus, device_t child, int *rid,
728 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
730 struct resource *res;
731 rman_res_t start_free, end_free, new_end;
734 * First, see if the request can be satisified by the existing
737 res = pcib_suballoc_bus(bus, child, rid, start, end, count, flags);
742 * Figure out a range to grow the bus range. First, find the
743 * first bus number after the last allocated bus in the rman and
744 * enforce that as a minimum starting point for the range.
746 if (rman_last_free_region(&bus->rman, &start_free, &end_free) != 0 ||
747 end_free != bus->sub)
748 start_free = bus->sub + 1;
749 if (start_free < start)
751 new_end = start_free + count - 1;
754 * See if this new range would satisfy the request if it
760 /* Finally, attempt to grow the existing resource. */
762 device_printf(bus->dev,
763 "attempting to grow bus range for %ju buses\n", count);
764 printf("\tback candidate range: %ju-%ju\n", start_free,
767 if (pcib_grow_subbus(bus, new_end) == 0)
768 return (pcib_suballoc_bus(bus, child, rid, start, end, count,
777 * Is the prefetch window open (eg, can we allocate memory in it?)
780 pcib_is_prefetch_open(struct pcib_softc *sc)
782 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit);
786 * Is the nonprefetch window open (eg, can we allocate memory in it?)
789 pcib_is_nonprefetch_open(struct pcib_softc *sc)
791 return (sc->membase > 0 && sc->membase < sc->memlimit);
795 * Is the io window open (eg, can we allocate ports in it?)
798 pcib_is_io_open(struct pcib_softc *sc)
800 return (sc->iobase > 0 && sc->iobase < sc->iolimit);
804 * Get current I/O decode.
807 pcib_get_io_decode(struct pcib_softc *sc)
814 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1);
815 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32)
816 sc->iobase = PCI_PPBIOBASE(
817 pci_read_config(dev, PCIR_IOBASEH_1, 2), iolow);
819 sc->iobase = PCI_PPBIOBASE(0, iolow);
821 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1);
822 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32)
823 sc->iolimit = PCI_PPBIOLIMIT(
824 pci_read_config(dev, PCIR_IOLIMITH_1, 2), iolow);
826 sc->iolimit = PCI_PPBIOLIMIT(0, iolow);
830 * Get current memory decode.
833 pcib_get_mem_decode(struct pcib_softc *sc)
840 sc->membase = PCI_PPBMEMBASE(0,
841 pci_read_config(dev, PCIR_MEMBASE_1, 2));
842 sc->memlimit = PCI_PPBMEMLIMIT(0,
843 pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
845 pmemlow = pci_read_config(dev, PCIR_PMBASEL_1, 2);
846 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64)
847 sc->pmembase = PCI_PPBMEMBASE(
848 pci_read_config(dev, PCIR_PMBASEH_1, 4), pmemlow);
850 sc->pmembase = PCI_PPBMEMBASE(0, pmemlow);
852 pmemlow = pci_read_config(dev, PCIR_PMLIMITL_1, 2);
853 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64)
854 sc->pmemlimit = PCI_PPBMEMLIMIT(
855 pci_read_config(dev, PCIR_PMLIMITH_1, 4), pmemlow);
857 sc->pmemlimit = PCI_PPBMEMLIMIT(0, pmemlow);
861 * Restore previous I/O decode.
864 pcib_set_io_decode(struct pcib_softc *sc)
871 iohi = sc->iobase >> 16;
873 pci_write_config(dev, PCIR_IOBASEH_1, iohi, 2);
874 pci_write_config(dev, PCIR_IOBASEL_1, sc->iobase >> 8, 1);
876 iohi = sc->iolimit >> 16;
878 pci_write_config(dev, PCIR_IOLIMITH_1, iohi, 2);
879 pci_write_config(dev, PCIR_IOLIMITL_1, sc->iolimit >> 8, 1);
883 * Restore previous memory decode.
886 pcib_set_mem_decode(struct pcib_softc *sc)
893 pci_write_config(dev, PCIR_MEMBASE_1, sc->membase >> 16, 2);
894 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->memlimit >> 16, 2);
896 pmemhi = sc->pmembase >> 32;
898 pci_write_config(dev, PCIR_PMBASEH_1, pmemhi, 4);
899 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmembase >> 16, 2);
901 pmemhi = sc->pmemlimit >> 32;
903 pci_write_config(dev, PCIR_PMLIMITH_1, pmemhi, 4);
904 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmemlimit >> 16, 2);
910 * PCI-express HotPlug support.
912 static int pci_enable_pcie_hp = 1;
913 SYSCTL_INT(_hw_pci, OID_AUTO, enable_pcie_hp, CTLFLAG_RDTUN,
914 &pci_enable_pcie_hp, 0,
915 "Enable support for native PCI-express HotPlug.");
918 pcib_probe_hotplug(struct pcib_softc *sc)
922 if (!pci_enable_pcie_hp)
926 if (pci_find_cap(dev, PCIY_EXPRESS, NULL) != 0)
929 if (!(pcie_read_config(dev, PCIER_FLAGS, 2) & PCIEM_FLAGS_SLOT))
932 sc->pcie_link_cap = pcie_read_config(dev, PCIER_LINK_CAP, 4);
933 sc->pcie_slot_cap = pcie_read_config(dev, PCIER_SLOT_CAP, 4);
936 * XXX: Handling of slots with a power controller needs to be
937 * reexamined. Ignore hotplug on such slots for now.
939 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PCP)
942 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_HPC)
943 sc->flags |= PCIB_HOTPLUG;
947 * Send a HotPlug command to the slot control register. If this slot
948 * uses command completion interrupts and a previous command is still
949 * in progress, then the command is dropped. Once the previous
950 * command completes or times out, pcib_pcie_hotplug_update() will be
951 * invoked to post a new command based on the slot's state at that
955 pcib_pcie_hotplug_command(struct pcib_softc *sc, uint16_t val, uint16_t mask)
962 if (sc->flags & PCIB_HOTPLUG_CMD_PENDING)
965 ctl = pcie_read_config(dev, PCIER_SLOT_CTL, 2);
966 new = (ctl & ~mask) | val;
969 pcie_write_config(dev, PCIER_SLOT_CTL, new, 2);
970 if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS) &&
971 (ctl & new) & PCIEM_SLOT_CTL_CCIE) {
972 sc->flags |= PCIB_HOTPLUG_CMD_PENDING;
974 callout_reset(&sc->pcie_cc_timer, hz,
975 pcib_pcie_cc_timeout, sc);
980 pcib_pcie_hotplug_command_completed(struct pcib_softc *sc)
987 device_printf(dev, "Command Completed\n");
988 if (!(sc->flags & PCIB_HOTPLUG_CMD_PENDING))
990 callout_stop(&sc->pcie_cc_timer);
991 sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING;
996 * Returns true if a card is fully inserted from the user's
997 * perspective. It may not yet be ready for access, but the driver
998 * can now start enabling access if necessary.
1001 pcib_hotplug_inserted(struct pcib_softc *sc)
1004 /* Pretend the card isn't present if a detach is forced. */
1005 if (sc->flags & PCIB_DETACHING)
1008 /* Card must be present in the slot. */
1009 if ((sc->pcie_slot_sta & PCIEM_SLOT_STA_PDS) == 0)
1012 /* A power fault implicitly turns off power to the slot. */
1013 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_PFD)
1016 /* If the MRL is disengaged, the slot is powered off. */
1017 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP &&
1018 (sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSS) != 0)
1025 * Returns -1 if the card is fully inserted, powered, and ready for
1026 * access. Otherwise, returns 0.
1029 pcib_hotplug_present(struct pcib_softc *sc)
1035 /* Card must be inserted. */
1036 if (!pcib_hotplug_inserted(sc))
1040 * Require the Electromechanical Interlock to be engaged if
1043 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_EIP &&
1044 (sc->pcie_slot_sta & PCIEM_SLOT_STA_EIS) == 0)
1047 /* Require the Data Link Layer to be active. */
1048 if (sc->pcie_link_cap & PCIEM_LINK_CAP_DL_ACTIVE) {
1049 if (!(sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE))
1057 pcib_pcie_hotplug_update(struct pcib_softc *sc, uint16_t val, uint16_t mask,
1060 bool card_inserted, ei_engaged;
1062 /* Clear DETACHING if Present Detect has cleared. */
1063 if ((sc->pcie_slot_sta & (PCIEM_SLOT_STA_PDC | PCIEM_SLOT_STA_PDS)) ==
1065 sc->flags &= ~PCIB_DETACHING;
1067 card_inserted = pcib_hotplug_inserted(sc);
1069 /* Turn the power indicator on if a card is inserted. */
1070 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PIP) {
1071 mask |= PCIEM_SLOT_CTL_PIC;
1073 val |= PCIEM_SLOT_CTL_PI_ON;
1074 else if (sc->flags & PCIB_DETACH_PENDING)
1075 val |= PCIEM_SLOT_CTL_PI_BLINK;
1077 val |= PCIEM_SLOT_CTL_PI_OFF;
1080 /* Turn the power on via the Power Controller if a card is inserted. */
1081 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PCP) {
1082 mask |= PCIEM_SLOT_CTL_PCC;
1084 val |= PCIEM_SLOT_CTL_PC_ON;
1086 val |= PCIEM_SLOT_CTL_PC_OFF;
1090 * If a card is inserted, enable the Electromechanical
1091 * Interlock. If a card is not inserted (or we are in the
1092 * process of detaching), disable the Electromechanical
1095 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_EIP) {
1096 mask |= PCIEM_SLOT_CTL_EIC;
1097 ei_engaged = (sc->pcie_slot_sta & PCIEM_SLOT_STA_EIS) != 0;
1098 if (card_inserted != ei_engaged)
1099 val |= PCIEM_SLOT_CTL_EIC;
1103 * Start a timer to see if the Data Link Layer times out.
1104 * Note that we only start the timer if Presence Detect
1105 * changed on this interrupt. Stop any scheduled timer if
1106 * the Data Link Layer is active.
1108 if (sc->pcie_link_cap & PCIEM_LINK_CAP_DL_ACTIVE) {
1109 if (card_inserted &&
1110 !(sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE) &&
1111 sc->pcie_slot_sta & PCIEM_SLOT_STA_PDC) {
1113 device_printf(sc->dev,
1114 "Data Link Layer inactive\n");
1116 callout_reset(&sc->pcie_dll_timer, hz,
1117 pcib_pcie_dll_timeout, sc);
1118 } else if (sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE)
1119 callout_stop(&sc->pcie_dll_timer);
1122 pcib_pcie_hotplug_command(sc, val, mask);
1125 * During attach the child "pci" device is added synchronously;
1126 * otherwise, the task is scheduled to manage the child
1129 if (schedule_task &&
1130 (pcib_hotplug_present(sc) != 0) != (sc->child != NULL))
1131 taskqueue_enqueue(taskqueue_thread, &sc->pcie_hp_task);
1135 pcib_pcie_intr(void *arg)
1137 struct pcib_softc *sc;
1142 sc->pcie_slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2);
1144 /* Clear the events just reported. */
1145 pcie_write_config(dev, PCIER_SLOT_STA, sc->pcie_slot_sta, 2);
1147 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_ABP) {
1148 if (sc->flags & PCIB_DETACH_PENDING) {
1150 "Attention Button Pressed: Detach Cancelled\n");
1151 sc->flags &= ~PCIB_DETACH_PENDING;
1152 callout_stop(&sc->pcie_ab_timer);
1155 "Attention Button Pressed: Detaching in 5 seconds\n");
1156 sc->flags |= PCIB_DETACH_PENDING;
1157 callout_reset(&sc->pcie_ab_timer, 5 * hz,
1158 pcib_pcie_ab_timeout, sc);
1161 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_PFD)
1162 device_printf(dev, "Power Fault Detected\n");
1163 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSC)
1164 device_printf(dev, "MRL Sensor Changed to %s\n",
1165 sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSS ? "open" :
1167 if (bootverbose && sc->pcie_slot_sta & PCIEM_SLOT_STA_PDC)
1168 device_printf(dev, "Present Detect Changed to %s\n",
1169 sc->pcie_slot_sta & PCIEM_SLOT_STA_PDS ? "card present" :
1171 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_CC)
1172 pcib_pcie_hotplug_command_completed(sc);
1173 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_DLLSC) {
1174 sc->pcie_link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2);
1177 "Data Link Layer State Changed to %s\n",
1178 sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE ?
1179 "active" : "inactive");
1182 pcib_pcie_hotplug_update(sc, 0, 0, true);
1186 pcib_pcie_hotplug_task(void *context, int pending)
1188 struct pcib_softc *sc;
1194 if (pcib_hotplug_present(sc) != 0) {
1195 if (sc->child == NULL) {
1196 sc->child = device_add_child(dev, "pci", -1);
1197 bus_generic_attach(dev);
1200 if (sc->child != NULL) {
1201 if (device_delete_child(dev, sc->child) == 0)
1209 pcib_pcie_ab_timeout(void *arg)
1211 struct pcib_softc *sc;
1216 mtx_assert(&Giant, MA_OWNED);
1217 if (sc->flags & PCIB_DETACH_PENDING) {
1218 sc->flags |= PCIB_DETACHING;
1219 sc->flags &= ~PCIB_DETACH_PENDING;
1220 pcib_pcie_hotplug_update(sc, 0, 0, true);
1225 pcib_pcie_cc_timeout(void *arg)
1227 struct pcib_softc *sc;
1233 mtx_assert(&Giant, MA_OWNED);
1234 sta = pcie_read_config(dev, PCIER_SLOT_STA, 2);
1235 if (!(sta & PCIEM_SLOT_STA_CC)) {
1237 "Hotplug Command Timed Out - forcing detach\n");
1238 sc->flags &= ~(PCIB_HOTPLUG_CMD_PENDING | PCIB_DETACH_PENDING);
1239 sc->flags |= PCIB_DETACHING;
1240 pcib_pcie_hotplug_update(sc, 0, 0, true);
1243 "Missed HotPlug interrupt waiting for Command Completion\n");
1249 pcib_pcie_dll_timeout(void *arg)
1251 struct pcib_softc *sc;
1257 mtx_assert(&Giant, MA_OWNED);
1258 sta = pcie_read_config(dev, PCIER_LINK_STA, 2);
1259 if (!(sta & PCIEM_LINK_STA_DL_ACTIVE)) {
1261 "Timed out waiting for Data Link Layer Active\n");
1262 sc->flags |= PCIB_DETACHING;
1263 pcib_pcie_hotplug_update(sc, 0, 0, true);
1264 } else if (sta != sc->pcie_link_sta) {
1266 "Missed HotPlug interrupt waiting for DLL Active\n");
1272 pcib_alloc_pcie_irq(struct pcib_softc *sc)
1275 int count, error, rid;
1281 * For simplicity, only use MSI-X if there is a single message.
1282 * To support a device with multiple messages we would have to
1283 * use remap intr if the MSI number is not 0.
1285 count = pci_msix_count(dev);
1287 error = pci_alloc_msix(dev, &count);
1292 if (rid < 0 && pci_msi_count(dev) > 0) {
1294 error = pci_alloc_msi(dev, &count);
1302 sc->pcie_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1304 if (sc->pcie_irq == NULL) {
1306 "Failed to allocate interrupt for PCI-e events\n");
1308 pci_release_msi(dev);
1312 error = bus_setup_intr(dev, sc->pcie_irq, INTR_TYPE_MISC,
1313 NULL, pcib_pcie_intr, sc, &sc->pcie_ihand);
1315 device_printf(dev, "Failed to setup PCI-e interrupt handler\n");
1316 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->pcie_irq);
1318 pci_release_msi(dev);
1325 pcib_release_pcie_irq(struct pcib_softc *sc)
1331 error = bus_teardown_intr(dev, sc->pcie_irq, sc->pcie_ihand);
1334 error = bus_free_resource(dev, SYS_RES_IRQ, sc->pcie_irq);
1337 return (pci_release_msi(dev));
1341 pcib_setup_hotplug(struct pcib_softc *sc)
1347 callout_init(&sc->pcie_ab_timer, 0);
1348 callout_init(&sc->pcie_cc_timer, 0);
1349 callout_init(&sc->pcie_dll_timer, 0);
1350 TASK_INIT(&sc->pcie_hp_task, 0, pcib_pcie_hotplug_task, sc);
1353 if (pcib_alloc_pcie_irq(sc) != 0)
1356 sc->pcie_link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2);
1357 sc->pcie_slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2);
1359 /* Clear any events previously pending. */
1360 pcie_write_config(dev, PCIER_SLOT_STA, sc->pcie_slot_sta, 2);
1362 /* Enable HotPlug events. */
1363 mask = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE |
1364 PCIEM_SLOT_CTL_CCIE | PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_MRLSCE |
1365 PCIEM_SLOT_CTL_PFDE | PCIEM_SLOT_CTL_ABPE;
1366 val = PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_HPIE;
1367 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_APB)
1368 val |= PCIEM_SLOT_CTL_ABPE;
1369 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PCP)
1370 val |= PCIEM_SLOT_CTL_PFDE;
1371 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP)
1372 val |= PCIEM_SLOT_CTL_MRLSCE;
1373 if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS))
1374 val |= PCIEM_SLOT_CTL_CCIE;
1375 if (sc->pcie_link_cap & PCIEM_LINK_CAP_DL_ACTIVE)
1376 val |= PCIEM_SLOT_CTL_DLLSCE;
1378 /* Turn the attention indicator off. */
1379 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_AIP) {
1380 mask |= PCIEM_SLOT_CTL_AIC;
1381 val |= PCIEM_SLOT_CTL_AI_OFF;
1384 pcib_pcie_hotplug_update(sc, val, mask, false);
1388 pcib_detach_hotplug(struct pcib_softc *sc)
1393 /* Disable the card in the slot and force it to detach. */
1394 if (sc->flags & PCIB_DETACH_PENDING) {
1395 sc->flags &= ~PCIB_DETACH_PENDING;
1396 callout_stop(&sc->pcie_ab_timer);
1398 sc->flags |= PCIB_DETACHING;
1400 if (sc->flags & PCIB_HOTPLUG_CMD_PENDING) {
1401 callout_stop(&sc->pcie_cc_timer);
1402 tsleep(sc, 0, "hpcmd", hz);
1403 sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING;
1406 /* Disable HotPlug events. */
1407 mask = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE |
1408 PCIEM_SLOT_CTL_CCIE | PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_MRLSCE |
1409 PCIEM_SLOT_CTL_PFDE | PCIEM_SLOT_CTL_ABPE;
1412 /* Turn the attention indicator off. */
1413 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_AIP) {
1414 mask |= PCIEM_SLOT_CTL_AIC;
1415 val |= PCIEM_SLOT_CTL_AI_OFF;
1418 pcib_pcie_hotplug_update(sc, val, mask, false);
1420 error = pcib_release_pcie_irq(sc);
1423 taskqueue_drain(taskqueue_thread, &sc->pcie_hp_task);
1424 callout_drain(&sc->pcie_ab_timer);
1425 callout_drain(&sc->pcie_cc_timer);
1426 callout_drain(&sc->pcie_dll_timer);
1432 * Get current bridge configuration.
1435 pcib_cfg_save(struct pcib_softc *sc)
1443 command = pci_read_config(dev, PCIR_COMMAND, 2);
1444 if (command & PCIM_CMD_PORTEN)
1445 pcib_get_io_decode(sc);
1446 if (command & PCIM_CMD_MEMEN)
1447 pcib_get_mem_decode(sc);
1452 * Restore previous bridge configuration.
1455 pcib_cfg_restore(struct pcib_softc *sc)
1464 pcib_write_windows(sc, WIN_IO | WIN_MEM | WIN_PMEM);
1466 command = pci_read_config(dev, PCIR_COMMAND, 2);
1467 if (command & PCIM_CMD_PORTEN)
1468 pcib_set_io_decode(sc);
1469 if (command & PCIM_CMD_MEMEN)
1470 pcib_set_mem_decode(sc);
1475 * Generic device interface
1478 pcib_probe(device_t dev)
1480 if ((pci_get_class(dev) == PCIC_BRIDGE) &&
1481 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) {
1482 device_set_desc(dev, "PCI-PCI bridge");
1489 pcib_attach_common(device_t dev)
1491 struct pcib_softc *sc;
1492 struct sysctl_ctx_list *sctx;
1493 struct sysctl_oid *soid;
1496 sc = device_get_softc(dev);
1500 * Get current bridge configuration.
1502 sc->domain = pci_get_domain(dev);
1503 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS))
1504 sc->bus.sec = pci_read_config(dev, PCIR_SECBUS_1, 1);
1505 sc->bus.sub = pci_read_config(dev, PCIR_SUBBUS_1, 1);
1507 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
1511 * The primary bus register should always be the bus of the
1514 sc->pribus = pci_get_bus(dev);
1515 pci_write_config(dev, PCIR_PRIBUS_1, sc->pribus, 1);
1518 * Setup sysctl reporting nodes
1520 sctx = device_get_sysctl_ctx(dev);
1521 soid = device_get_sysctl_tree(dev);
1522 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain",
1523 CTLFLAG_RD, &sc->domain, 0, "Domain number");
1524 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus",
1525 CTLFLAG_RD, &sc->pribus, 0, "Primary bus number");
1526 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus",
1527 CTLFLAG_RD, &sc->bus.sec, 0, "Secondary bus number");
1528 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus",
1529 CTLFLAG_RD, &sc->bus.sub, 0, "Subordinate bus number");
1534 switch (pci_get_devid(dev)) {
1535 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS))
1536 case 0x12258086: /* Intel 82454KX/GX (Orion) */
1540 supbus = pci_read_config(dev, 0x41, 1);
1541 if (supbus != 0xff) {
1542 sc->bus.sec = supbus + 1;
1543 sc->bus.sub = supbus + 1;
1550 * The i82380FB mobile docking controller is a PCI-PCI bridge,
1551 * and it is a subtractive bridge. However, the ProgIf is wrong
1552 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't
1553 * happen. There are also Toshiba and Cavium ThunderX bridges
1554 * that behave this way.
1556 case 0xa002177d: /* Cavium ThunderX */
1557 case 0x124b8086: /* Intel 82380FB Mobile */
1558 case 0x060513d7: /* Toshiba ???? */
1559 sc->flags |= PCIB_SUBTRACTIVE;
1562 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS))
1563 /* Compaq R3000 BIOS sets wrong subordinate bus number. */
1568 if ((cp = kern_getenv("smbios.planar.maker")) == NULL)
1570 if (strncmp(cp, "Compal", 6) != 0) {
1575 if ((cp = kern_getenv("smbios.planar.product")) == NULL)
1577 if (strncmp(cp, "08A0", 4) != 0) {
1582 if (sc->bus.sub < 0xa) {
1583 pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1);
1584 sc->bus.sub = pci_read_config(dev, PCIR_SUBBUS_1, 1);
1591 if (pci_msi_device_blacklisted(dev))
1592 sc->flags |= PCIB_DISABLE_MSI;
1594 if (pci_msix_device_blacklisted(dev))
1595 sc->flags |= PCIB_DISABLE_MSIX;
1598 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges,
1599 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM,
1600 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese.
1601 * This means they act as if they were subtractively decoding
1602 * bridges and pass all transactions. Mark them and real ProgIf 1
1603 * parts as subtractive.
1605 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 ||
1606 pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_BRIDGE_PCI_SUBTRACTIVE)
1607 sc->flags |= PCIB_SUBTRACTIVE;
1610 pcib_probe_hotplug(sc);
1614 pcib_setup_secbus(dev, &sc->bus, 1);
1616 pcib_probe_windows(sc);
1619 if (sc->flags & PCIB_HOTPLUG)
1620 pcib_setup_hotplug(sc);
1623 device_printf(dev, " domain %d\n", sc->domain);
1624 device_printf(dev, " secondary bus %d\n", sc->bus.sec);
1625 device_printf(dev, " subordinate bus %d\n", sc->bus.sub);
1627 if (pcib_is_window_open(&sc->io))
1628 device_printf(dev, " I/O decode 0x%jx-0x%jx\n",
1629 (uintmax_t)sc->io.base, (uintmax_t)sc->io.limit);
1630 if (pcib_is_window_open(&sc->mem))
1631 device_printf(dev, " memory decode 0x%jx-0x%jx\n",
1632 (uintmax_t)sc->mem.base, (uintmax_t)sc->mem.limit);
1633 if (pcib_is_window_open(&sc->pmem))
1634 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n",
1635 (uintmax_t)sc->pmem.base, (uintmax_t)sc->pmem.limit);
1637 if (pcib_is_io_open(sc))
1638 device_printf(dev, " I/O decode 0x%x-0x%x\n",
1639 sc->iobase, sc->iolimit);
1640 if (pcib_is_nonprefetch_open(sc))
1641 device_printf(dev, " memory decode 0x%jx-0x%jx\n",
1642 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit);
1643 if (pcib_is_prefetch_open(sc))
1644 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n",
1645 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit);
1647 if (sc->bridgectl & (PCIB_BCR_ISA_ENABLE | PCIB_BCR_VGA_ENABLE) ||
1648 sc->flags & PCIB_SUBTRACTIVE) {
1649 device_printf(dev, " special decode ");
1651 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE) {
1655 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE) {
1656 printf("%sVGA", comma ? ", " : "");
1659 if (sc->flags & PCIB_SUBTRACTIVE)
1660 printf("%ssubtractive", comma ? ", " : "");
1666 * Always enable busmastering on bridges so that transactions
1667 * initiated on the secondary bus are passed through to the
1670 pci_enable_busmaster(dev);
1675 pcib_present(struct pcib_softc *sc)
1678 if (sc->flags & PCIB_HOTPLUG)
1679 return (pcib_hotplug_present(sc) != 0);
1685 pcib_attach_child(device_t dev)
1687 struct pcib_softc *sc;
1689 sc = device_get_softc(dev);
1690 if (sc->bus.sec == 0) {
1691 /* no secondary bus; we should have fixed this */
1696 if (!pcib_present(sc)) {
1697 /* An empty HotPlug slot, so don't add a PCI bus yet. */
1702 sc->child = device_add_child(dev, "pci", -1);
1703 return (bus_generic_attach(dev));
1707 pcib_attach(device_t dev)
1710 pcib_attach_common(dev);
1711 return (pcib_attach_child(dev));
1715 pcib_detach(device_t dev)
1717 #if defined(PCI_HP) || defined(NEW_PCIB)
1718 struct pcib_softc *sc;
1722 #if defined(PCI_HP) || defined(NEW_PCIB)
1723 sc = device_get_softc(dev);
1725 error = bus_generic_detach(dev);
1729 if (sc->flags & PCIB_HOTPLUG) {
1730 error = pcib_detach_hotplug(sc);
1735 error = device_delete_children(dev);
1739 pcib_free_windows(sc);
1741 pcib_free_secbus(dev, &sc->bus);
1748 pcib_suspend(device_t dev)
1751 pcib_cfg_save(device_get_softc(dev));
1752 return (bus_generic_suspend(dev));
1756 pcib_resume(device_t dev)
1759 pcib_cfg_restore(device_get_softc(dev));
1760 return (bus_generic_resume(dev));
1764 pcib_bridge_init(device_t dev)
1766 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1);
1767 pci_write_config(dev, PCIR_IOBASEH_1, 0xffff, 2);
1768 pci_write_config(dev, PCIR_IOLIMITL_1, 0, 1);
1769 pci_write_config(dev, PCIR_IOLIMITH_1, 0, 2);
1770 pci_write_config(dev, PCIR_MEMBASE_1, 0xffff, 2);
1771 pci_write_config(dev, PCIR_MEMLIMIT_1, 0, 2);
1772 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2);
1773 pci_write_config(dev, PCIR_PMBASEH_1, 0xffffffff, 4);
1774 pci_write_config(dev, PCIR_PMLIMITL_1, 0, 2);
1775 pci_write_config(dev, PCIR_PMLIMITH_1, 0, 4);
1779 pcib_child_present(device_t dev, device_t child)
1782 struct pcib_softc *sc = device_get_softc(dev);
1785 retval = bus_child_present(dev);
1786 if (retval != 0 && sc->flags & PCIB_HOTPLUG)
1787 retval = pcib_hotplug_present(sc);
1790 return (bus_child_present(dev));
1795 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1797 struct pcib_softc *sc = device_get_softc(dev);
1800 case PCIB_IVAR_DOMAIN:
1801 *result = sc->domain;
1804 *result = sc->bus.sec;
1811 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1815 case PCIB_IVAR_DOMAIN:
1825 * Attempt to allocate a resource from the existing resources assigned
1828 static struct resource *
1829 pcib_suballoc_resource(struct pcib_softc *sc, struct pcib_window *w,
1830 device_t child, int type, int *rid, rman_res_t start, rman_res_t end,
1831 rman_res_t count, u_int flags)
1833 struct resource *res;
1835 if (!pcib_is_window_open(w))
1838 res = rman_reserve_resource(&w->rman, start, end, count,
1839 flags & ~RF_ACTIVE, child);
1844 device_printf(sc->dev,
1845 "allocated %s range (%#jx-%#jx) for rid %x of %s\n",
1846 w->name, rman_get_start(res), rman_get_end(res), *rid,
1847 pcib_child_name(child));
1848 rman_set_rid(res, *rid);
1851 * If the resource should be active, pass that request up the
1852 * tree. This assumes the parent drivers can handle
1853 * activating sub-allocated resources.
1855 if (flags & RF_ACTIVE) {
1856 if (bus_activate_resource(child, type, *rid, res) != 0) {
1857 rman_release_resource(res);
1865 /* Allocate a fresh resource range for an unconfigured window. */
1867 pcib_alloc_new_window(struct pcib_softc *sc, struct pcib_window *w, int type,
1868 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
1870 struct resource *res;
1871 rman_res_t base, limit, wmask;
1875 * If this is an I/O window on a bridge with ISA enable set
1876 * and the start address is below 64k, then try to allocate an
1877 * initial window of 0x1000 bytes long starting at address
1878 * 0xf000 and walking down. Note that if the original request
1879 * was larger than the non-aliased range size of 0x100 our
1880 * caller would have raised the start address up to 64k
1883 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE &&
1885 for (base = 0xf000; (long)base >= 0; base -= 0x1000) {
1886 limit = base + 0xfff;
1889 * Skip ranges that wouldn't work for the
1890 * original request. Note that the actual
1891 * window that overlaps are the non-alias
1892 * ranges within [base, limit], so this isn't
1893 * quite a simple comparison.
1895 if (start + count > limit - 0x400)
1899 * The first open region for the window at
1902 if (end - count + 1 < 0x400)
1905 if (end - count + 1 < base)
1909 if (pcib_alloc_nonisa_ranges(sc, base, limit) == 0) {
1918 wmask = ((rman_res_t)1 << w->step) - 1;
1919 if (RF_ALIGNMENT(flags) < w->step) {
1920 flags &= ~RF_ALIGNMENT_MASK;
1921 flags |= RF_ALIGNMENT_LOG2(w->step);
1925 count = roundup2(count, (rman_res_t)1 << w->step);
1927 res = bus_alloc_resource(sc->dev, type, &rid, start, end, count,
1928 flags & ~RF_ACTIVE);
1931 pcib_add_window_resources(w, &res, 1);
1932 pcib_activate_window(sc, type);
1933 w->base = rman_get_start(res);
1934 w->limit = rman_get_end(res);
1938 /* Try to expand an existing window to the requested base and limit. */
1940 pcib_expand_window(struct pcib_softc *sc, struct pcib_window *w, int type,
1941 rman_res_t base, rman_res_t limit)
1943 struct resource *res;
1944 int error, i, force_64k_base;
1946 KASSERT(base <= w->base && limit >= w->limit,
1947 ("attempting to shrink window"));
1950 * XXX: pcib_grow_window() doesn't try to do this anyway and
1951 * the error handling for all the edge cases would be tedious.
1953 KASSERT(limit == w->limit || base == w->base,
1954 ("attempting to grow both ends of a window"));
1957 * Yet more special handling for requests to expand an I/O
1958 * window behind an ISA-enabled bridge. Since I/O windows
1959 * have to grow in 0x1000 increments and the end of the 0xffff
1960 * range is an alias, growing a window below 64k will always
1961 * result in allocating new resources and never adjusting an
1962 * existing resource.
1964 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE &&
1965 (limit <= 65535 || (base <= 65535 && base != w->base))) {
1966 KASSERT(limit == w->limit || limit <= 65535,
1967 ("attempting to grow both ends across 64k ISA alias"));
1969 if (base != w->base)
1970 error = pcib_alloc_nonisa_ranges(sc, base, w->base - 1);
1972 error = pcib_alloc_nonisa_ranges(sc, w->limit + 1,
1982 * Find the existing resource to adjust. Usually there is only one,
1983 * but for an ISA-enabled bridge we might be growing the I/O window
1984 * above 64k and need to find the existing resource that maps all
1985 * of the area above 64k.
1987 for (i = 0; i < w->count; i++) {
1988 if (rman_get_end(w->res[i]) == w->limit)
1991 KASSERT(i != w->count, ("did not find existing resource"));
1995 * Usually the resource we found should match the window's
1996 * existing range. The one exception is the ISA-enabled case
1997 * mentioned above in which case the resource should start at
2000 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE &&
2002 KASSERT(rman_get_start(res) == 65536,
2003 ("existing resource mismatch"));
2006 KASSERT(w->base == rman_get_start(res),
2007 ("existing resource mismatch"));
2011 error = bus_adjust_resource(sc->dev, type, res, force_64k_base ?
2012 rman_get_start(res) : base, limit);
2016 /* Add the newly allocated region to the resource manager. */
2017 if (w->base != base) {
2018 error = rman_manage_region(&w->rman, base, w->base - 1);
2021 error = rman_manage_region(&w->rman, w->limit + 1, limit);
2026 device_printf(sc->dev,
2027 "failed to expand %s resource manager\n", w->name);
2028 (void)bus_adjust_resource(sc->dev, type, res, force_64k_base ?
2029 rman_get_start(res) : w->base, w->limit);
2035 * Attempt to grow a window to make room for a given resource request.
2038 pcib_grow_window(struct pcib_softc *sc, struct pcib_window *w, int type,
2039 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
2041 rman_res_t align, start_free, end_free, front, back, wmask;
2045 * Clamp the desired resource range to the maximum address
2046 * this window supports. Reject impossible requests.
2048 * For I/O port requests behind a bridge with the ISA enable
2049 * bit set, force large allocations to start above 64k.
2053 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE && count > 0x100 &&
2056 if (end > w->rman.rm_end)
2057 end = w->rman.rm_end;
2058 if (start + count - 1 > end || start + count < start)
2060 wmask = ((rman_res_t)1 << w->step) - 1;
2063 * If there is no resource at all, just try to allocate enough
2064 * aligned space for this resource.
2066 if (w->res == NULL) {
2067 error = pcib_alloc_new_window(sc, w, type, start, end, count,
2071 device_printf(sc->dev,
2072 "failed to allocate initial %s window (%#jx-%#jx,%#jx)\n",
2073 w->name, start, end, count);
2077 device_printf(sc->dev,
2078 "allocated initial %s window of %#jx-%#jx\n",
2079 w->name, (uintmax_t)w->base, (uintmax_t)w->limit);
2084 * See if growing the window would help. Compute the minimum
2085 * amount of address space needed on both the front and back
2086 * ends of the existing window to satisfy the allocation.
2088 * For each end, build a candidate region adjusting for the
2089 * required alignment, etc. If there is a free region at the
2090 * edge of the window, grow from the inner edge of the free
2091 * region. Otherwise grow from the window boundary.
2093 * Growing an I/O window below 64k for a bridge with the ISA
2094 * enable bit doesn't require any special magic as the step
2095 * size of an I/O window (1k) always includes multiple
2096 * non-alias ranges when it is grown in either direction.
2098 * XXX: Special case: if w->res is completely empty and the
2099 * request size is larger than w->res, we should find the
2100 * optimal aligned buffer containing w->res and allocate that.
2103 device_printf(sc->dev,
2104 "attempting to grow %s window for (%#jx-%#jx,%#jx)\n",
2105 w->name, start, end, count);
2106 align = (rman_res_t)1 << RF_ALIGNMENT(flags);
2107 if (start < w->base) {
2108 if (rman_first_free_region(&w->rman, &start_free, &end_free) !=
2109 0 || start_free != w->base)
2114 /* Move end_free down until it is properly aligned. */
2115 end_free &= ~(align - 1);
2117 front = end_free - (count - 1);
2120 * The resource would now be allocated at (front,
2121 * end_free). Ensure that fits in the (start, end)
2122 * bounds. end_free is checked above. If 'front' is
2123 * ok, ensure it is properly aligned for this window.
2124 * Also check for underflow.
2126 if (front >= start && front <= end_free) {
2128 printf("\tfront candidate range: %#jx-%#jx\n",
2131 front = w->base - front;
2136 if (end > w->limit) {
2137 if (rman_last_free_region(&w->rman, &start_free, &end_free) !=
2138 0 || end_free != w->limit)
2139 start_free = w->limit + 1;
2140 if (start_free < start)
2143 /* Move start_free up until it is properly aligned. */
2144 start_free = roundup2(start_free, align);
2145 back = start_free + count - 1;
2148 * The resource would now be allocated at (start_free,
2149 * back). Ensure that fits in the (start, end)
2150 * bounds. start_free is checked above. If 'back' is
2151 * ok, ensure it is properly aligned for this window.
2152 * Also check for overflow.
2154 if (back <= end && start_free <= back) {
2156 printf("\tback candidate range: %#jx-%#jx\n",
2166 * Try to allocate the smallest needed region first.
2167 * If that fails, fall back to the other region.
2170 while (front != 0 || back != 0) {
2171 if (front != 0 && (front <= back || back == 0)) {
2172 error = pcib_expand_window(sc, w, type, w->base - front,
2178 error = pcib_expand_window(sc, w, type, w->base,
2189 device_printf(sc->dev, "grew %s window to %#jx-%#jx\n",
2190 w->name, (uintmax_t)w->base, (uintmax_t)w->limit);
2193 /* Write the new window. */
2194 KASSERT((w->base & wmask) == 0, ("start address is not aligned"));
2195 KASSERT((w->limit & wmask) == wmask, ("end address is not aligned"));
2196 pcib_write_windows(sc, w->mask);
2201 * We have to trap resource allocation requests and ensure that the bridge
2202 * is set up to, or capable of handling them.
2205 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
2206 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
2208 struct pcib_softc *sc;
2211 sc = device_get_softc(dev);
2214 * VGA resources are decoded iff the VGA enable bit is set in
2215 * the bridge control register. VGA resources do not fall into
2216 * the resource windows and are passed up to the parent.
2218 if ((type == SYS_RES_IOPORT && pci_is_vga_ioport_range(start, end)) ||
2219 (type == SYS_RES_MEMORY && pci_is_vga_memory_range(start, end))) {
2220 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE)
2221 return (bus_generic_alloc_resource(dev, child, type,
2222 rid, start, end, count, flags));
2230 return (pcib_alloc_subbus(&sc->bus, child, rid, start, end,
2233 case SYS_RES_IOPORT:
2234 if (pcib_is_isa_range(sc, start, end, count))
2236 r = pcib_suballoc_resource(sc, &sc->io, child, type, rid, start,
2238 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0)
2240 if (pcib_grow_window(sc, &sc->io, type, start, end, count,
2242 r = pcib_suballoc_resource(sc, &sc->io, child, type,
2243 rid, start, end, count, flags);
2245 case SYS_RES_MEMORY:
2247 * For prefetchable resources, prefer the prefetchable
2248 * memory window, but fall back to the regular memory
2249 * window if that fails. Try both windows before
2250 * attempting to grow a window in case the firmware
2251 * has used a range in the regular memory window to
2252 * map a prefetchable BAR.
2254 if (flags & RF_PREFETCHABLE) {
2255 r = pcib_suballoc_resource(sc, &sc->pmem, child, type,
2256 rid, start, end, count, flags);
2260 r = pcib_suballoc_resource(sc, &sc->mem, child, type, rid,
2261 start, end, count, flags);
2262 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0)
2264 if (flags & RF_PREFETCHABLE) {
2265 if (pcib_grow_window(sc, &sc->pmem, type, start, end,
2266 count, flags) == 0) {
2267 r = pcib_suballoc_resource(sc, &sc->pmem, child,
2268 type, rid, start, end, count, flags);
2273 if (pcib_grow_window(sc, &sc->mem, type, start, end, count,
2274 flags & ~RF_PREFETCHABLE) == 0)
2275 r = pcib_suballoc_resource(sc, &sc->mem, child, type,
2276 rid, start, end, count, flags);
2279 return (bus_generic_alloc_resource(dev, child, type, rid,
2280 start, end, count, flags));
2284 * If attempts to suballocate from the window fail but this is a
2285 * subtractive bridge, pass the request up the tree.
2287 if (sc->flags & PCIB_SUBTRACTIVE && r == NULL)
2288 return (bus_generic_alloc_resource(dev, child, type, rid,
2289 start, end, count, flags));
2294 pcib_adjust_resource(device_t bus, device_t child, int type, struct resource *r,
2295 rman_res_t start, rman_res_t end)
2297 struct pcib_softc *sc;
2299 sc = device_get_softc(bus);
2300 if (pcib_is_resource_managed(sc, type, r))
2301 return (rman_adjust_resource(r, start, end));
2302 return (bus_generic_adjust_resource(bus, child, type, r, start, end));
2306 pcib_release_resource(device_t dev, device_t child, int type, int rid,
2309 struct pcib_softc *sc;
2312 sc = device_get_softc(dev);
2313 if (pcib_is_resource_managed(sc, type, r)) {
2314 if (rman_get_flags(r) & RF_ACTIVE) {
2315 error = bus_deactivate_resource(child, type, rid, r);
2319 return (rman_release_resource(r));
2321 return (bus_generic_release_resource(dev, child, type, rid, r));
2325 * We have to trap resource allocation requests and ensure that the bridge
2326 * is set up to, or capable of handling them.
2329 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
2330 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
2332 struct pcib_softc *sc = device_get_softc(dev);
2333 const char *name, *suffix;
2337 * Fail the allocation for this range if it's not supported.
2339 name = device_get_nameunit(child);
2346 case SYS_RES_IOPORT:
2348 if (!pcib_is_io_open(sc))
2350 ok = (start >= sc->iobase && end <= sc->iolimit);
2353 * Make sure we allow access to VGA I/O addresses when the
2354 * bridge has the "VGA Enable" bit set.
2356 if (!ok && pci_is_vga_ioport_range(start, end))
2357 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
2359 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
2361 if (start < sc->iobase)
2363 if (end > sc->iolimit)
2372 * If we overlap with the subtractive range, then
2373 * pick the upper range to use.
2375 if (start < sc->iolimit && end > sc->iobase)
2376 start = sc->iolimit + 1;
2380 device_printf(dev, "ioport: end (%jx) < start (%jx)\n",
2387 device_printf(dev, "%s%srequested unsupported I/O "
2388 "range 0x%jx-0x%jx (decoding 0x%x-0x%x)\n",
2389 name, suffix, start, end, sc->iobase, sc->iolimit);
2394 "%s%srequested I/O range 0x%jx-0x%jx: in range\n",
2395 name, suffix, start, end);
2398 case SYS_RES_MEMORY:
2400 if (pcib_is_nonprefetch_open(sc))
2401 ok = ok || (start >= sc->membase && end <= sc->memlimit);
2402 if (pcib_is_prefetch_open(sc))
2403 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit);
2406 * Make sure we allow access to VGA memory addresses when the
2407 * bridge has the "VGA Enable" bit set.
2409 if (!ok && pci_is_vga_memory_range(start, end))
2410 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
2412 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
2415 if (flags & RF_PREFETCHABLE) {
2416 if (pcib_is_prefetch_open(sc)) {
2417 if (start < sc->pmembase)
2418 start = sc->pmembase;
2419 if (end > sc->pmemlimit)
2420 end = sc->pmemlimit;
2424 } else { /* non-prefetchable */
2425 if (pcib_is_nonprefetch_open(sc)) {
2426 if (start < sc->membase)
2427 start = sc->membase;
2428 if (end > sc->memlimit)
2436 ok = 1; /* subtractive bridge: always ok */
2438 if (pcib_is_nonprefetch_open(sc)) {
2439 if (start < sc->memlimit && end > sc->membase)
2440 start = sc->memlimit + 1;
2442 if (pcib_is_prefetch_open(sc)) {
2443 if (start < sc->pmemlimit && end > sc->pmembase)
2444 start = sc->pmemlimit + 1;
2449 device_printf(dev, "memory: end (%jx) < start (%jx)\n",
2455 if (!ok && bootverbose)
2457 "%s%srequested unsupported memory range %#jx-%#jx "
2458 "(decoding %#jx-%#jx, %#jx-%#jx)\n",
2459 name, suffix, start, end,
2460 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit,
2461 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit);
2465 device_printf(dev,"%s%srequested memory range "
2466 "0x%jx-0x%jx: good\n",
2467 name, suffix, start, end);
2474 * Bridge is OK decoding this resource, so pass it up.
2476 return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
2482 * If ARI is enabled on this downstream port, translate the function number
2483 * to the non-ARI slot/function. The downstream port will convert it back in
2484 * hardware. If ARI is not enabled slot and func are not modified.
2486 static __inline void
2487 pcib_xlate_ari(device_t pcib, int bus, int *slot, int *func)
2489 struct pcib_softc *sc;
2492 sc = device_get_softc(pcib);
2495 if (sc->flags & PCIB_ENABLE_ARI) {
2497 ("Non-zero slot number with ARI enabled!"));
2498 *slot = PCIE_ARI_SLOT(ari_func);
2499 *func = PCIE_ARI_FUNC(ari_func);
2505 pcib_enable_ari(struct pcib_softc *sc, uint32_t pcie_pos)
2509 ctl2 = pci_read_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, 4);
2510 ctl2 |= PCIEM_CTL2_ARI;
2511 pci_write_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, ctl2, 4);
2513 sc->flags |= PCIB_ENABLE_ARI;
2520 pcib_maxslots(device_t dev)
2522 return (PCI_SLOTMAX);
2526 pcib_ari_maxslots(device_t dev)
2528 struct pcib_softc *sc;
2530 sc = device_get_softc(dev);
2532 if (sc->flags & PCIB_ENABLE_ARI)
2533 return (PCIE_ARI_SLOTMAX);
2535 return (PCI_SLOTMAX);
2539 pcib_ari_maxfuncs(device_t dev)
2541 struct pcib_softc *sc;
2543 sc = device_get_softc(dev);
2545 if (sc->flags & PCIB_ENABLE_ARI)
2546 return (PCIE_ARI_FUNCMAX);
2548 return (PCI_FUNCMAX);
2552 pcib_ari_decode_rid(device_t pcib, uint16_t rid, int *bus, int *slot,
2555 struct pcib_softc *sc;
2557 sc = device_get_softc(pcib);
2559 *bus = PCI_RID2BUS(rid);
2560 if (sc->flags & PCIB_ENABLE_ARI) {
2561 *slot = PCIE_ARI_RID2SLOT(rid);
2562 *func = PCIE_ARI_RID2FUNC(rid);
2564 *slot = PCI_RID2SLOT(rid);
2565 *func = PCI_RID2FUNC(rid);
2570 * Since we are a child of a PCI bus, its parent must support the pcib interface.
2573 pcib_read_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, int width)
2576 struct pcib_softc *sc;
2578 sc = device_get_softc(dev);
2579 if (!pcib_present(sc)) {
2586 return (0xffffffff);
2590 pcib_xlate_ari(dev, b, &s, &f);
2591 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s,
2596 pcib_write_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, int width)
2599 struct pcib_softc *sc;
2601 sc = device_get_softc(dev);
2602 if (!pcib_present(sc))
2605 pcib_xlate_ari(dev, b, &s, &f);
2606 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f,
2611 * Route an interrupt across a PCI bridge.
2614 pcib_route_interrupt(device_t pcib, device_t dev, int pin)
2622 * The PCI standard defines a swizzle of the child-side device/intpin to
2623 * the parent-side intpin as follows.
2625 * device = device on child bus
2626 * child_intpin = intpin on child bus slot (0-3)
2627 * parent_intpin = intpin on parent bus slot (0-3)
2629 * parent_intpin = (device + child_intpin) % 4
2631 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4;
2634 * Our parent is a PCI bus. Its parent must export the pcib interface
2635 * which includes the ability to route interrupts.
2637 bus = device_get_parent(pcib);
2638 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1);
2639 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) {
2640 device_printf(pcib, "slot %d INT%c is routed to irq %d\n",
2641 pci_get_slot(dev), 'A' + pin - 1, intnum);
2646 /* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */
2648 pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs)
2650 struct pcib_softc *sc = device_get_softc(pcib);
2653 if (sc->flags & PCIB_DISABLE_MSI)
2655 bus = device_get_parent(pcib);
2656 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount,
2660 /* Pass request to release MSI/MSI-X messages up to the parent bridge. */
2662 pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs)
2666 bus = device_get_parent(pcib);
2667 return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs));
2670 /* Pass request to alloc an MSI-X message up to the parent bridge. */
2672 pcib_alloc_msix(device_t pcib, device_t dev, int *irq)
2674 struct pcib_softc *sc = device_get_softc(pcib);
2677 if (sc->flags & PCIB_DISABLE_MSIX)
2679 bus = device_get_parent(pcib);
2680 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq));
2683 /* Pass request to release an MSI-X message up to the parent bridge. */
2685 pcib_release_msix(device_t pcib, device_t dev, int irq)
2689 bus = device_get_parent(pcib);
2690 return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq));
2693 /* Pass request to map MSI/MSI-X message up to parent bridge. */
2695 pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
2701 bus = device_get_parent(pcib);
2702 error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data);
2706 pci_ht_map_msi(pcib, *addr);
2710 /* Pass request for device power state up to parent bridge. */
2712 pcib_power_for_sleep(device_t pcib, device_t dev, int *pstate)
2716 bus = device_get_parent(pcib);
2717 return (PCIB_POWER_FOR_SLEEP(bus, dev, pstate));
2721 pcib_ari_enabled(device_t pcib)
2723 struct pcib_softc *sc;
2725 sc = device_get_softc(pcib);
2727 return ((sc->flags & PCIB_ENABLE_ARI) != 0);
2731 pcib_ari_get_id(device_t pcib, device_t dev, enum pci_id_type type,
2734 struct pcib_softc *sc;
2736 uint8_t bus, slot, func;
2738 if (type != PCI_ID_RID) {
2739 bus_dev = device_get_parent(pcib);
2740 return (PCIB_GET_ID(device_get_parent(bus_dev), dev, type, id));
2743 sc = device_get_softc(pcib);
2745 if (sc->flags & PCIB_ENABLE_ARI) {
2746 bus = pci_get_bus(dev);
2747 func = pci_get_function(dev);
2749 *id = (PCI_ARI_RID(bus, func));
2751 bus = pci_get_bus(dev);
2752 slot = pci_get_slot(dev);
2753 func = pci_get_function(dev);
2755 *id = (PCI_RID(bus, slot, func));
2762 * Check that the downstream port (pcib) and the endpoint device (dev) both
2763 * support ARI. If so, enable it and return 0, otherwise return an error.
2766 pcib_try_enable_ari(device_t pcib, device_t dev)
2768 struct pcib_softc *sc;
2775 sc = device_get_softc(pcib);
2778 * ARI is controlled in a register in the PCIe capability structure.
2779 * If the downstream port does not have the PCIe capability structure
2780 * then it does not support ARI.
2782 error = pci_find_cap(pcib, PCIY_EXPRESS, &pcie_pos);
2786 /* Check that the PCIe port advertises ARI support. */
2787 cap2 = pci_read_config(pcib, pcie_pos + PCIER_DEVICE_CAP2, 4);
2788 if (!(cap2 & PCIEM_CAP2_ARI))
2792 * Check that the endpoint device advertises ARI support via the ARI
2793 * extended capability structure.
2795 error = pci_find_extcap(dev, PCIZ_ARI, &ari_cap_off);
2800 * Finally, check that the endpoint device supports the same version
2801 * of ARI that we do.
2803 ari_ver = pci_read_config(dev, ari_cap_off, 4);
2804 if (PCI_EXTCAP_VER(ari_ver) != PCIB_SUPPORTED_ARI_VER) {
2807 "Unsupported version of ARI (%d) detected\n",
2808 PCI_EXTCAP_VER(ari_ver));
2813 pcib_enable_ari(sc, pcie_pos);