2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000 BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * PCI:PCI bridge support.
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/kernel.h>
41 #include <sys/sysctl.h>
43 #include <machine/resource.h>
45 #include <pci/pcivar.h>
46 #include <pci/pcireg.h>
47 #include <pci/pcib_private.h>
51 static int pcib_probe(device_t dev);
52 static int pcib_route_interrupt(device_t pcib, device_t dev, int pin);
54 static device_method_t pcib_methods[] = {
55 /* Device interface */
56 DEVMETHOD(device_probe, pcib_probe),
57 DEVMETHOD(device_attach, pcib_attach),
58 DEVMETHOD(device_shutdown, bus_generic_shutdown),
59 DEVMETHOD(device_suspend, bus_generic_suspend),
60 DEVMETHOD(device_resume, bus_generic_resume),
63 DEVMETHOD(bus_print_child, bus_generic_print_child),
64 DEVMETHOD(bus_read_ivar, pcib_read_ivar),
65 DEVMETHOD(bus_write_ivar, pcib_write_ivar),
66 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
67 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
68 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
69 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
70 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
71 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
74 DEVMETHOD(pcib_maxslots, pcib_maxslots),
75 DEVMETHOD(pcib_read_config, pcib_read_config),
76 DEVMETHOD(pcib_write_config, pcib_write_config),
77 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
82 static driver_t pcib_driver = {
85 sizeof(struct pcib_softc),
88 devclass_t pcib_devclass;
90 DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0);
93 * sysctl and tunable vars
95 static int pci_allow_unsupported_io_range = 0;
96 TUNABLE_INT("hw.pci.allow_unsupported_io_range",
97 (int *)&pci_allow_unsupported_io_range);
99 SYSCTL_INT(_hw_pci, OID_AUTO, allow_unsupported_io_range, CTLFLAG_RD,
100 &pci_allow_unsupported_io_range, 0,
101 "Allows the PCI Bridge to pass through an unsupported memory range "
102 "assigned by the BIOS.");
105 * Generic device interface
108 pcib_probe(device_t dev)
110 if ((pci_get_class(dev) == PCIC_BRIDGE) &&
111 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) {
112 device_set_desc(dev, "PCI-PCI bridge");
119 pcib_attach_common(device_t dev)
121 struct pcib_softc *sc;
124 sc = device_get_softc(dev);
128 * Get current bridge configuration.
130 sc->command = pci_read_config(dev, PCIR_COMMAND, 1);
131 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1);
132 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1);
133 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2);
134 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
135 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1);
138 * Determine current I/O decode.
140 if (sc->command & PCIM_CMD_PORTEN) {
141 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1);
142 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
143 sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2),
144 pci_read_config(dev, PCIR_IOBASEL_1, 1));
146 sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1));
149 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1);
150 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
151 sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2),
152 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
154 sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1));
159 * Determine current memory decode.
161 if (sc->command & PCIM_CMD_MEMEN) {
162 sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2));
163 sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
164 sc->pmembase = PCI_PPBMEMBASE((pci_addr_t)pci_read_config(dev, PCIR_PMBASEH_1, 4),
165 pci_read_config(dev, PCIR_PMBASEL_1, 2));
166 sc->pmemlimit = PCI_PPBMEMLIMIT((pci_addr_t)pci_read_config(dev, PCIR_PMLIMITH_1, 4),
167 pci_read_config(dev, PCIR_PMLIMITL_1, 2));
173 switch (pci_get_devid(dev)) {
174 case 0x12258086: /* Intel 82454KX/GX (Orion) */
178 supbus = pci_read_config(dev, 0x41, 1);
179 if (supbus != 0xff) {
180 sc->secbus = supbus + 1;
181 sc->subbus = supbus + 1;
188 device_printf(dev, " secondary bus %d\n", sc->secbus);
189 device_printf(dev, " subordinate bus %d\n", sc->subbus);
190 device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit);
191 device_printf(dev, " memory decode 0x%x-0x%x\n", sc->membase, sc->memlimit);
192 device_printf(dev, " prefetched decode 0x%x-0x%x\n", sc->pmembase, sc->pmemlimit);
196 * XXX If the secondary bus number is zero, we should assign a bus number
197 * since the BIOS hasn't, then initialise the bridge.
201 * XXX If the subordinate bus number is less than the secondary bus number,
202 * we should pick a better value. One sensible alternative would be to
203 * pick 255; the only tradeoff here is that configuration transactions
204 * would be more widely routed than absolutely necessary.
209 pcib_attach(device_t dev)
211 struct pcib_softc *sc;
214 pcib_attach_common(dev);
215 sc = device_get_softc(dev);
216 if (sc->secbus != 0) {
217 child = device_add_child(dev, "pci", sc->secbus);
219 return(bus_generic_attach(dev));
222 /* no secondary bus; we should have fixed this */
227 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
229 struct pcib_softc *sc = device_get_softc(dev);
233 *result = sc->secbus;
240 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
242 struct pcib_softc *sc = device_get_softc(dev);
253 * Is this a decoded ISA I/O port address? Note, we need to do the mask that
254 * we do below because of the ISA alias addresses. I'm not 100% sure that
258 pcib_is_isa_io(u_long start)
260 if ((start & 0xfffUL) > 0x3ffUL || start == 0)
266 * Is this a decoded ISA memory address?
269 pcib_is_isa_mem(u_long start)
271 if (start > 0xfffffUL || start == 0)
277 * We have to trap resource allocation requests and ensure that the bridge
278 * is set up to, or capable of handling them.
281 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
282 u_long start, u_long end, u_long count, u_int flags)
284 struct pcib_softc *sc = device_get_softc(dev);
287 * If this is a "default" allocation against this rid, we can't work
288 * out where it's coming from (we should actually never see these) so we
291 if ((start == 0) && (end == ~0)) {
292 device_printf(dev, "can't decode default resource id %d for %s%d, bypassing\n",
293 *rid, device_get_name(child), device_get_unit(child));
296 * Fail the allocation for this range if it's not supported.
298 * XXX we should probably just fix up the bridge decode and soldier on.
302 if (!pcib_is_isa_io(start)) {
303 if (!pci_allow_unsupported_io_range) {
304 if (start < sc->iobase)
306 if (end > sc->iolimit)
311 if (start < sc->iobase)
312 printf("start (%lx) < sc->iobase (%x)\n", start,
314 if (end > sc->iolimit)
315 printf("end (%lx) > sc->iolimit (%x)\n",
318 printf("end (%lx) < start (%lx)\n", end, start);
321 if (!pcib_is_isa_io(start) &&
322 ((start < sc->iobase) || (end > sc->iolimit))) {
323 device_printf(dev, "device %s%d requested unsupported I/O range 0x%lx-0x%lx"
324 " (decoding 0x%x-0x%x)\n",
325 device_get_name(child), device_get_unit(child), start, end,
326 sc->iobase, sc->iolimit);
330 device_printf(sc->dev, "device %s%d requested decoded I/O range 0x%lx-0x%lx\n",
331 device_get_name(child), device_get_unit(child), start, end);
335 * XXX will have to decide whether the device making the request is asking
336 * for prefetchable memory or not. If it's coming from another bridge
337 * down the line, do we assume not, or ask the bridge to pass in another
338 * flag as the request bubbles up?
341 if (!pcib_is_isa_mem(start)) {
342 if (!pci_allow_unsupported_io_range) {
343 if (start < sc->membase && end >= sc->membase)
345 if (end > sc->memlimit)
350 if (start < sc->membase && end > sc->membase)
351 printf("start (%lx) < sc->membase (%x)\n",
353 if (end > sc->memlimit)
354 printf("end (%lx) > sc->memlimit (%x)\n",
357 printf("end (%lx) < start (%lx)\n", end, start);
360 if (!pcib_is_isa_mem(start) &&
361 (((start < sc->membase) || (end > sc->memlimit)) &&
362 ((start < sc->pmembase) || (end > sc->pmemlimit)))) {
365 "device %s%d requested unsupported memory range "
366 "0x%lx-0x%lx (decoding 0x%x-0x%x, 0x%x-0x%x)\n",
367 device_get_name(child), device_get_unit(child), start,
368 end, sc->membase, sc->memlimit, sc->pmembase,
370 if (!pci_allow_unsupported_io_range)
374 device_printf(sc->dev, "device %s%d requested decoded memory range 0x%lx-0x%lx\n",
375 device_get_name(child), device_get_unit(child), start, end);
384 * Bridge is OK decoding this resource, so pass it up.
386 return(bus_generic_alloc_resource(dev, child, type, rid, start, end, count, flags));
393 pcib_maxslots(device_t dev)
399 * Since we are a child of a PCI bus, its parent must support the pcib interface.
402 pcib_read_config(device_t dev, int b, int s, int f, int reg, int width)
404 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width));
408 pcib_write_config(device_t dev, int b, int s, int f, int reg, u_int32_t val, int width)
410 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width);
414 * Route an interrupt across a PCI bridge.
417 pcib_route_interrupt(device_t pcib, device_t dev, int pin)
425 * The PCI standard defines a swizzle of the child-side device/intpin to
426 * the parent-side intpin as follows.
428 * device = device on child bus
429 * child_intpin = intpin on child bus slot (0-3)
430 * parent_intpin = intpin on parent bus slot (0-3)
432 * parent_intpin = (device + child_intpin) % 4
434 parent_intpin = (pci_get_slot(pcib) + (pin - 1)) % 4;
437 * Our parent is a PCI bus. Its parent must export the pcib interface
438 * which includes the ability to route interrupts.
440 bus = device_get_parent(pcib);
441 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1);
442 if (PCI_INTERRUPT_VALID(intnum)) {
443 device_printf(pcib, "slot %d INT%c is routed to irq %d\n",
444 pci_get_slot(dev), 'A' + pin - 1, intnum);