2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000 BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
35 * PCI:PCI bridge support.
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
43 #include <machine/bus.h>
45 #include <sys/sysctl.h>
47 #include <machine/resource.h>
49 #include <dev/pci/pcivar.h>
50 #include <dev/pci/pcireg.h>
51 #include <dev/pci/pcib_private.h>
55 static int pcib_probe(device_t dev);
57 static device_method_t pcib_methods[] = {
58 /* Device interface */
59 DEVMETHOD(device_probe, pcib_probe),
60 DEVMETHOD(device_attach, pcib_attach),
61 DEVMETHOD(device_detach, bus_generic_detach),
62 DEVMETHOD(device_shutdown, bus_generic_shutdown),
63 DEVMETHOD(device_suspend, bus_generic_suspend),
64 DEVMETHOD(device_resume, bus_generic_resume),
67 DEVMETHOD(bus_print_child, bus_generic_print_child),
68 DEVMETHOD(bus_read_ivar, pcib_read_ivar),
69 DEVMETHOD(bus_write_ivar, pcib_write_ivar),
70 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
71 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
72 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
73 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
74 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
75 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
78 DEVMETHOD(pcib_maxslots, pcib_maxslots),
79 DEVMETHOD(pcib_read_config, pcib_read_config),
80 DEVMETHOD(pcib_write_config, pcib_write_config),
81 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
86 static devclass_t pcib_devclass;
88 DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc));
89 DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0);
92 * Generic device interface
95 pcib_probe(device_t dev)
97 if ((pci_get_class(dev) == PCIC_BRIDGE) &&
98 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) {
99 device_set_desc(dev, "PCI-PCI bridge");
106 pcib_attach_common(device_t dev)
108 struct pcib_softc *sc;
111 sc = device_get_softc(dev);
115 * Get current bridge configuration.
117 sc->command = pci_read_config(dev, PCIR_COMMAND, 1);
118 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1);
119 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1);
120 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2);
121 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
122 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1);
125 * Determine current I/O decode.
127 if (sc->command & PCIM_CMD_PORTEN) {
128 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1);
129 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
130 sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2),
131 pci_read_config(dev, PCIR_IOBASEL_1, 1));
133 sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1));
136 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1);
137 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
138 sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2),
139 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
141 sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1));
146 * Determine current memory decode.
148 if (sc->command & PCIM_CMD_MEMEN) {
149 sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2));
150 sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
151 sc->pmembase = PCI_PPBMEMBASE((pci_addr_t)pci_read_config(dev, PCIR_PMBASEH_1, 4),
152 pci_read_config(dev, PCIR_PMBASEL_1, 2));
153 sc->pmemlimit = PCI_PPBMEMLIMIT((pci_addr_t)pci_read_config(dev, PCIR_PMLIMITH_1, 4),
154 pci_read_config(dev, PCIR_PMLIMITL_1, 2));
160 switch (pci_get_devid(dev)) {
161 case 0x12258086: /* Intel 82454KX/GX (Orion) */
165 supbus = pci_read_config(dev, 0x41, 1);
166 if (supbus != 0xff) {
167 sc->secbus = supbus + 1;
168 sc->subbus = supbus + 1;
174 * The i82380FB mobile docking controller is a PCI-PCI bridge,
175 * and it is a subtractive bridge. However, the ProgIf is wrong
176 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't
177 * happen. There's also a Toshiba bridge that behaves this
180 case 0x124b8086: /* Intel 82380FB Mobile */
181 case 0x060513d7: /* Toshiba ???? */
182 sc->flags |= PCIB_SUBTRACTIVE;
185 /* Compaq R3000 BIOS sets wrong subordinate bus number. */
190 cp = getenv("smbios.planar.maker");
191 if (cp == NULL || strncmp(cp, "Compal", 6) != 0)
193 cp = getenv("smbios.planar.product");
194 if (cp == NULL || strncmp(cp, "08A0", 4) != 0)
196 if (sc->subbus < 0xa) {
197 pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1);
198 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1);
205 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges,
206 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM,
207 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese.
208 * This means they act as if they were subtractively decoding
209 * bridges and pass all transactions. Mark them and real ProgIf 1
210 * parts as subtractive.
212 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 ||
213 pci_read_config(dev, PCIR_PROGIF, 1) == 1)
214 sc->flags |= PCIB_SUBTRACTIVE;
217 device_printf(dev, " secondary bus %d\n", sc->secbus);
218 device_printf(dev, " subordinate bus %d\n", sc->subbus);
219 device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit);
220 device_printf(dev, " memory decode 0x%x-0x%x\n", sc->membase, sc->memlimit);
221 device_printf(dev, " prefetched decode 0x%x-0x%x\n", sc->pmembase, sc->pmemlimit);
222 if (sc->flags & PCIB_SUBTRACTIVE)
223 device_printf(dev, " Subtractively decoded bridge.\n");
227 * XXX If the secondary bus number is zero, we should assign a bus number
228 * since the BIOS hasn't, then initialise the bridge.
232 * XXX If the subordinate bus number is less than the secondary bus number,
233 * we should pick a better value. One sensible alternative would be to
234 * pick 255; the only tradeoff here is that configuration transactions
235 * would be more widely routed than absolutely necessary.
240 pcib_attach(device_t dev)
242 struct pcib_softc *sc;
245 pcib_attach_common(dev);
246 sc = device_get_softc(dev);
247 if (sc->secbus != 0) {
248 child = device_add_child(dev, "pci", sc->secbus);
250 return(bus_generic_attach(dev));
253 /* no secondary bus; we should have fixed this */
258 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
260 struct pcib_softc *sc = device_get_softc(dev);
264 *result = sc->secbus;
271 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
273 struct pcib_softc *sc = device_get_softc(dev);
284 * Is the prefetch window open (eg, can we allocate memory in it?)
287 pcib_is_prefetch_open(struct pcib_softc *sc)
289 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit);
293 * Is the nonprefetch window open (eg, can we allocate memory in it?)
296 pcib_is_nonprefetch_open(struct pcib_softc *sc)
298 return (sc->membase > 0 && sc->membase < sc->memlimit);
302 * Is the io window open (eg, can we allocate ports in it?)
305 pcib_is_io_open(struct pcib_softc *sc)
307 return (sc->iobase > 0 && sc->iobase < sc->iolimit);
311 * We have to trap resource allocation requests and ensure that the bridge
312 * is set up to, or capable of handling them.
315 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
316 u_long start, u_long end, u_long count, u_int flags)
318 struct pcib_softc *sc = device_get_softc(dev);
322 * Fail the allocation for this range if it's not supported.
327 if (!pcib_is_io_open(sc))
329 ok = (start >= sc->iobase && end <= sc->iolimit);
332 * Make sure we allow access to VGA I/O addresses when the
333 * bridge has the "VGA Enable" bit set.
335 if (!ok && pci_is_vga_ioport_range(start, end))
336 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
338 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
340 if (start < sc->iobase)
342 if (end > sc->iolimit)
350 if (start < sc->iobase && end > sc->iolimit) {
357 device_printf(dev, "ioport: end (%lx) < start (%lx)\n",
364 device_printf(dev, "%s requested unsupported I/O "
365 "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n",
366 device_get_nameunit(child), start, end,
367 sc->iobase, sc->iolimit);
372 "%s requested I/O range 0x%lx-0x%lx: in range\n",
373 device_get_nameunit(child), start, end);
378 if (pcib_is_nonprefetch_open(sc))
379 ok = ok || (start >= sc->membase && end <= sc->memlimit);
380 if (pcib_is_prefetch_open(sc))
381 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit);
384 * Make sure we allow access to VGA memory addresses when the
385 * bridge has the "VGA Enable" bit set.
387 if (!ok && pci_is_vga_memory_range(start, end))
388 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
390 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
393 if (flags & RF_PREFETCHABLE) {
394 if (pcib_is_prefetch_open(sc)) {
395 if (start < sc->pmembase)
396 start = sc->pmembase;
397 if (end > sc->pmemlimit)
402 } else { /* non-prefetchable */
403 if (pcib_is_nonprefetch_open(sc)) {
404 if (start < sc->membase)
406 if (end > sc->memlimit)
414 ok = 1; /* subtractive bridge: always ok */
416 if (pcib_is_nonprefetch_open(sc)) {
417 if (start < sc->membase && end > sc->memlimit) {
422 if (pcib_is_prefetch_open(sc)) {
423 if (start < sc->pmembase && end > sc->pmemlimit) {
424 start = sc->pmembase;
431 device_printf(dev, "memory: end (%lx) < start (%lx)\n",
437 if (!ok && bootverbose)
439 "%s requested unsupported memory range "
440 "0x%lx-0x%lx (decoding 0x%x-0x%x, 0x%x-0x%x)\n",
441 device_get_nameunit(child), start, end,
442 sc->membase, sc->memlimit, sc->pmembase,
447 device_printf(dev,"%s requested memory range "
448 "0x%lx-0x%lx: good\n",
449 device_get_nameunit(child), start, end);
456 * Bridge is OK decoding this resource, so pass it up.
458 return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
466 pcib_maxslots(device_t dev)
472 * Since we are a child of a PCI bus, its parent must support the pcib interface.
475 pcib_read_config(device_t dev, int b, int s, int f, int reg, int width)
477 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width));
481 pcib_write_config(device_t dev, int b, int s, int f, int reg, uint32_t val, int width)
483 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width);
487 * Route an interrupt across a PCI bridge.
490 pcib_route_interrupt(device_t pcib, device_t dev, int pin)
498 * The PCI standard defines a swizzle of the child-side device/intpin to
499 * the parent-side intpin as follows.
501 * device = device on child bus
502 * child_intpin = intpin on child bus slot (0-3)
503 * parent_intpin = intpin on parent bus slot (0-3)
505 * parent_intpin = (device + child_intpin) % 4
507 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4;
510 * Our parent is a PCI bus. Its parent must export the pcib interface
511 * which includes the ability to route interrupts.
513 bus = device_get_parent(pcib);
514 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1);
515 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) {
516 device_printf(pcib, "slot %d INT%c is routed to irq %d\n",
517 pci_get_slot(dev), 'A' + pin - 1, intnum);
523 * Try to read the bus number of a host-PCI bridge using appropriate config
527 host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func,
532 id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4);
533 if (id == 0xffffffff)
539 /* XXX This is a guess */
540 /* *busnum = read_config(bus, slot, func, 0x41, 1); */
544 /* Intel 82454KX/GX (Orion) */
545 *busnum = read_config(bus, slot, func, 0x4a, 1);
549 * For the 450nx chipset, there is a whole bundle of
550 * things pretending to be host bridges. The MIOC will
551 * be seen first and isn't really a pci bridge (the
552 * actual busses are attached to the PXB's). We need to
553 * read the registers of the MIOC to figure out the
554 * bus numbers for the PXB channels.
556 * Since the MIOC doesn't have a pci bus attached, we
557 * pretend it wasn't there.
563 /* Intel 82454NX PXB#0, Bus#A */
564 *busnum = read_config(bus, 0x10, func, 0xd0, 1);
567 /* Intel 82454NX PXB#0, Bus#B */
568 *busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1;
571 /* Intel 82454NX PXB#1, Bus#A */
572 *busnum = read_config(bus, 0x10, func, 0xd3, 1);
575 /* Intel 82454NX PXB#1, Bus#B */
576 *busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1;
581 /* ServerWorks -- vendor 0x1166 */
593 *busnum = read_config(bus, slot, func, 0x44, 1);
596 /* Compaq/HP -- vendor 0x0e11 */
598 *busnum = read_config(bus, slot, func, 0xc8, 1);
601 /* Don't know how to read bus number. */