2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000 BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
35 * PCI:PCI bridge support.
40 #include <sys/param.h>
42 #include <sys/kernel.h>
43 #include <sys/malloc.h>
44 #include <sys/module.h>
46 #include <sys/sysctl.h>
47 #include <sys/systm.h>
48 #include <sys/taskqueue.h>
50 #include <dev/pci/pcivar.h>
51 #include <dev/pci/pcireg.h>
52 #include <dev/pci/pci_private.h>
53 #include <dev/pci/pcib_private.h>
57 static int pcib_probe(device_t dev);
58 static int pcib_suspend(device_t dev);
59 static int pcib_resume(device_t dev);
60 static int pcib_power_for_sleep(device_t pcib, device_t dev,
62 static int pcib_ari_get_id(device_t pcib, device_t dev,
63 enum pci_id_type type, uintptr_t *id);
64 static uint32_t pcib_read_config(device_t dev, u_int b, u_int s,
65 u_int f, u_int reg, int width);
66 static void pcib_write_config(device_t dev, u_int b, u_int s,
67 u_int f, u_int reg, uint32_t val, int width);
68 static int pcib_ari_maxslots(device_t dev);
69 static int pcib_ari_maxfuncs(device_t dev);
70 static int pcib_try_enable_ari(device_t pcib, device_t dev);
71 static int pcib_ari_enabled(device_t pcib);
72 static void pcib_ari_decode_rid(device_t pcib, uint16_t rid,
73 int *bus, int *slot, int *func);
75 static void pcib_pcie_ab_timeout(void *arg);
76 static void pcib_pcie_cc_timeout(void *arg);
77 static void pcib_pcie_dll_timeout(void *arg);
80 static device_method_t pcib_methods[] = {
81 /* Device interface */
82 DEVMETHOD(device_probe, pcib_probe),
83 DEVMETHOD(device_attach, pcib_attach),
84 DEVMETHOD(device_detach, pcib_detach),
85 DEVMETHOD(device_shutdown, bus_generic_shutdown),
86 DEVMETHOD(device_suspend, pcib_suspend),
87 DEVMETHOD(device_resume, pcib_resume),
90 DEVMETHOD(bus_child_present, pcib_child_present),
91 DEVMETHOD(bus_read_ivar, pcib_read_ivar),
92 DEVMETHOD(bus_write_ivar, pcib_write_ivar),
93 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
95 DEVMETHOD(bus_adjust_resource, pcib_adjust_resource),
96 DEVMETHOD(bus_release_resource, pcib_release_resource),
98 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
99 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
101 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
102 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
103 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
104 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
107 DEVMETHOD(pcib_maxslots, pcib_ari_maxslots),
108 DEVMETHOD(pcib_maxfuncs, pcib_ari_maxfuncs),
109 DEVMETHOD(pcib_read_config, pcib_read_config),
110 DEVMETHOD(pcib_write_config, pcib_write_config),
111 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
112 DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi),
113 DEVMETHOD(pcib_release_msi, pcib_release_msi),
114 DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix),
115 DEVMETHOD(pcib_release_msix, pcib_release_msix),
116 DEVMETHOD(pcib_map_msi, pcib_map_msi),
117 DEVMETHOD(pcib_power_for_sleep, pcib_power_for_sleep),
118 DEVMETHOD(pcib_get_id, pcib_ari_get_id),
119 DEVMETHOD(pcib_try_enable_ari, pcib_try_enable_ari),
120 DEVMETHOD(pcib_ari_enabled, pcib_ari_enabled),
121 DEVMETHOD(pcib_decode_rid, pcib_ari_decode_rid),
126 static devclass_t pcib_devclass;
128 DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc));
129 DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, NULL, NULL);
132 SYSCTL_DECL(_hw_pci);
134 static int pci_clear_pcib;
135 SYSCTL_INT(_hw_pci, OID_AUTO, clear_pcib, CTLFLAG_RDTUN, &pci_clear_pcib, 0,
136 "Clear firmware-assigned resources for PCI-PCI bridge I/O windows.");
139 * Is a resource from a child device sub-allocated from one of our
143 pcib_is_resource_managed(struct pcib_softc *sc, int type, struct resource *r)
149 return (rman_is_region_manager(r, &sc->bus.rman));
152 return (rman_is_region_manager(r, &sc->io.rman));
154 /* Prefetchable resources may live in either memory rman. */
155 if (rman_get_flags(r) & RF_PREFETCHABLE &&
156 rman_is_region_manager(r, &sc->pmem.rman))
158 return (rman_is_region_manager(r, &sc->mem.rman));
164 pcib_is_window_open(struct pcib_window *pw)
167 return (pw->valid && pw->base < pw->limit);
171 * XXX: If RF_ACTIVE did not also imply allocating a bus space tag and
172 * handle for the resource, we could pass RF_ACTIVE up to the PCI bus
173 * when allocating the resource windows and rely on the PCI bus driver
177 pcib_activate_window(struct pcib_softc *sc, int type)
180 PCI_ENABLE_IO(device_get_parent(sc->dev), sc->dev, type);
184 pcib_write_windows(struct pcib_softc *sc, int mask)
190 if (sc->io.valid && mask & WIN_IO) {
191 val = pci_read_config(dev, PCIR_IOBASEL_1, 1);
192 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
193 pci_write_config(dev, PCIR_IOBASEH_1,
194 sc->io.base >> 16, 2);
195 pci_write_config(dev, PCIR_IOLIMITH_1,
196 sc->io.limit >> 16, 2);
198 pci_write_config(dev, PCIR_IOBASEL_1, sc->io.base >> 8, 1);
199 pci_write_config(dev, PCIR_IOLIMITL_1, sc->io.limit >> 8, 1);
202 if (mask & WIN_MEM) {
203 pci_write_config(dev, PCIR_MEMBASE_1, sc->mem.base >> 16, 2);
204 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->mem.limit >> 16, 2);
207 if (sc->pmem.valid && mask & WIN_PMEM) {
208 val = pci_read_config(dev, PCIR_PMBASEL_1, 2);
209 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) {
210 pci_write_config(dev, PCIR_PMBASEH_1,
211 sc->pmem.base >> 32, 4);
212 pci_write_config(dev, PCIR_PMLIMITH_1,
213 sc->pmem.limit >> 32, 4);
215 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmem.base >> 16, 2);
216 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmem.limit >> 16, 2);
221 * This is used to reject I/O port allocations that conflict with an
225 pcib_is_isa_range(struct pcib_softc *sc, rman_res_t start, rman_res_t end,
228 rman_res_t next_alias;
230 if (!(sc->bridgectl & PCIB_BCR_ISA_ENABLE))
233 /* Only check fixed ranges for overlap. */
234 if (start + count - 1 != end)
237 /* ISA aliases are only in the lower 64KB of I/O space. */
241 /* Check for overlap with 0x000 - 0x0ff as a special case. */
246 * If the start address is an alias, the range is an alias.
247 * Otherwise, compute the start of the next alias range and
248 * check if it is before the end of the candidate range.
250 if ((start & 0x300) != 0)
252 next_alias = (start & ~0x3fful) | 0x100;
253 if (next_alias <= end)
259 device_printf(sc->dev,
260 "I/O range %#jx-%#jx overlaps with an ISA alias\n", start,
266 pcib_add_window_resources(struct pcib_window *w, struct resource **res,
269 struct resource **newarray;
272 newarray = malloc(sizeof(struct resource *) * (w->count + count),
275 bcopy(w->res, newarray, sizeof(struct resource *) * w->count);
276 bcopy(res, newarray + w->count, sizeof(struct resource *) * count);
277 free(w->res, M_DEVBUF);
281 for (i = 0; i < count; i++) {
282 error = rman_manage_region(&w->rman, rman_get_start(res[i]),
283 rman_get_end(res[i]));
285 panic("Failed to add resource to rman");
289 typedef void (nonisa_callback)(rman_res_t start, rman_res_t end, void *arg);
292 pcib_walk_nonisa_ranges(rman_res_t start, rman_res_t end, nonisa_callback *cb,
298 * If start is within an ISA alias range, move up to the start
299 * of the next non-alias range. As a special case, addresses
300 * in the range 0x000 - 0x0ff should also be skipped since
301 * those are used for various system I/O devices in ISA
304 if (start <= 65535) {
305 if (start < 0x100 || (start & 0x300) != 0) {
311 /* ISA aliases are only in the lower 64KB of I/O space. */
312 while (start <= MIN(end, 65535)) {
313 next_end = MIN(start | 0xff, end);
314 cb(start, next_end, arg);
323 count_ranges(rman_res_t start, rman_res_t end, void *arg)
332 struct resource **res;
333 struct pcib_softc *sc;
338 alloc_ranges(rman_res_t start, rman_res_t end, void *arg)
340 struct alloc_state *as;
341 struct pcib_window *w;
351 device_printf(as->sc->dev,
352 "allocating non-ISA range %#jx-%#jx\n", start, end);
353 as->res[as->count] = bus_alloc_resource(as->sc->dev, SYS_RES_IOPORT,
354 &rid, start, end, end - start + 1, 0);
355 if (as->res[as->count] == NULL)
362 pcib_alloc_nonisa_ranges(struct pcib_softc *sc, rman_res_t start, rman_res_t end)
364 struct alloc_state as;
367 /* First, see how many ranges we need. */
369 pcib_walk_nonisa_ranges(start, end, count_ranges, &new_count);
371 /* Second, allocate the ranges. */
372 as.res = malloc(sizeof(struct resource *) * new_count, M_DEVBUF,
377 pcib_walk_nonisa_ranges(start, end, alloc_ranges, &as);
379 for (i = 0; i < as.count; i++)
380 bus_release_resource(sc->dev, SYS_RES_IOPORT,
381 sc->io.reg, as.res[i]);
382 free(as.res, M_DEVBUF);
385 KASSERT(as.count == new_count, ("%s: count mismatch", __func__));
387 /* Third, add the ranges to the window. */
388 pcib_add_window_resources(&sc->io, as.res, as.count);
389 free(as.res, M_DEVBUF);
394 pcib_alloc_window(struct pcib_softc *sc, struct pcib_window *w, int type,
395 int flags, pci_addr_t max_address)
397 struct resource *res;
401 if (max_address != (rman_res_t)max_address)
403 w->rman.rm_start = 0;
404 w->rman.rm_end = max_address;
405 w->rman.rm_type = RMAN_ARRAY;
406 snprintf(buf, sizeof(buf), "%s %s window",
407 device_get_nameunit(sc->dev), w->name);
408 w->rman.rm_descr = strdup(buf, M_DEVBUF);
409 error = rman_init(&w->rman);
411 panic("Failed to initialize %s %s rman",
412 device_get_nameunit(sc->dev), w->name);
414 if (!pcib_is_window_open(w))
417 if (w->base > max_address || w->limit > max_address) {
418 device_printf(sc->dev,
419 "initial %s window has too many bits, ignoring\n", w->name);
422 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE)
423 (void)pcib_alloc_nonisa_ranges(sc, w->base, w->limit);
426 res = bus_alloc_resource(sc->dev, type, &rid, w->base, w->limit,
427 w->limit - w->base + 1, flags);
429 pcib_add_window_resources(w, &res, 1);
431 if (w->res == NULL) {
432 device_printf(sc->dev,
433 "failed to allocate initial %s window: %#jx-%#jx\n",
434 w->name, (uintmax_t)w->base, (uintmax_t)w->limit);
435 w->base = max_address;
437 pcib_write_windows(sc, w->mask);
440 pcib_activate_window(sc, type);
444 * Initialize I/O windows.
447 pcib_probe_windows(struct pcib_softc *sc)
455 if (pci_clear_pcib) {
456 pcib_bridge_init(dev);
459 /* Determine if the I/O port window is implemented. */
460 val = pci_read_config(dev, PCIR_IOBASEL_1, 1);
463 * If 'val' is zero, then only 16-bits of I/O space
466 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1);
467 if (pci_read_config(dev, PCIR_IOBASEL_1, 1) != 0) {
469 pci_write_config(dev, PCIR_IOBASEL_1, 0, 1);
474 /* Read the existing I/O port window. */
476 sc->io.reg = PCIR_IOBASEL_1;
478 sc->io.mask = WIN_IO;
479 sc->io.name = "I/O port";
480 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
481 sc->io.base = PCI_PPBIOBASE(
482 pci_read_config(dev, PCIR_IOBASEH_1, 2), val);
483 sc->io.limit = PCI_PPBIOLIMIT(
484 pci_read_config(dev, PCIR_IOLIMITH_1, 2),
485 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
488 sc->io.base = PCI_PPBIOBASE(0, val);
489 sc->io.limit = PCI_PPBIOLIMIT(0,
490 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
493 pcib_alloc_window(sc, &sc->io, SYS_RES_IOPORT, 0, max);
496 /* Read the existing memory window. */
498 sc->mem.reg = PCIR_MEMBASE_1;
500 sc->mem.mask = WIN_MEM;
501 sc->mem.name = "memory";
502 sc->mem.base = PCI_PPBMEMBASE(0,
503 pci_read_config(dev, PCIR_MEMBASE_1, 2));
504 sc->mem.limit = PCI_PPBMEMLIMIT(0,
505 pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
506 pcib_alloc_window(sc, &sc->mem, SYS_RES_MEMORY, 0, 0xffffffff);
508 /* Determine if the prefetchable memory window is implemented. */
509 val = pci_read_config(dev, PCIR_PMBASEL_1, 2);
512 * If 'val' is zero, then only 32-bits of memory space
515 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2);
516 if (pci_read_config(dev, PCIR_PMBASEL_1, 2) != 0) {
518 pci_write_config(dev, PCIR_PMBASEL_1, 0, 2);
523 /* Read the existing prefetchable memory window. */
524 if (sc->pmem.valid) {
525 sc->pmem.reg = PCIR_PMBASEL_1;
527 sc->pmem.mask = WIN_PMEM;
528 sc->pmem.name = "prefetch";
529 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) {
530 sc->pmem.base = PCI_PPBMEMBASE(
531 pci_read_config(dev, PCIR_PMBASEH_1, 4), val);
532 sc->pmem.limit = PCI_PPBMEMLIMIT(
533 pci_read_config(dev, PCIR_PMLIMITH_1, 4),
534 pci_read_config(dev, PCIR_PMLIMITL_1, 2));
535 max = 0xffffffffffffffff;
537 sc->pmem.base = PCI_PPBMEMBASE(0, val);
538 sc->pmem.limit = PCI_PPBMEMLIMIT(0,
539 pci_read_config(dev, PCIR_PMLIMITL_1, 2));
542 pcib_alloc_window(sc, &sc->pmem, SYS_RES_MEMORY,
543 RF_PREFETCHABLE, max);
548 pcib_release_window(struct pcib_softc *sc, struct pcib_window *w, int type)
557 error = rman_fini(&w->rman);
559 device_printf(dev, "failed to release %s rman\n", w->name);
562 free(__DECONST(char *, w->rman.rm_descr), M_DEVBUF);
564 for (i = 0; i < w->count; i++) {
565 error = bus_free_resource(dev, type, w->res[i]);
568 "failed to release %s resource: %d\n", w->name,
571 free(w->res, M_DEVBUF);
575 pcib_free_windows(struct pcib_softc *sc)
578 pcib_release_window(sc, &sc->pmem, SYS_RES_MEMORY);
579 pcib_release_window(sc, &sc->mem, SYS_RES_MEMORY);
580 pcib_release_window(sc, &sc->io, SYS_RES_IOPORT);
585 * Allocate a suitable secondary bus for this bridge if needed and
586 * initialize the resource manager for the secondary bus range. Note
587 * that the minimum count is a desired value and this may allocate a
591 pcib_setup_secbus(device_t dev, struct pcib_secbus *bus, int min_count)
594 int error, rid, sec_reg;
596 switch (pci_read_config(dev, PCIR_HDRTYPE, 1) & PCIM_HDRTYPE) {
597 case PCIM_HDRTYPE_BRIDGE:
598 sec_reg = PCIR_SECBUS_1;
599 bus->sub_reg = PCIR_SUBBUS_1;
601 case PCIM_HDRTYPE_CARDBUS:
602 sec_reg = PCIR_SECBUS_2;
603 bus->sub_reg = PCIR_SUBBUS_2;
606 panic("not a PCI bridge");
608 bus->sec = pci_read_config(dev, sec_reg, 1);
609 bus->sub = pci_read_config(dev, bus->sub_reg, 1);
611 bus->rman.rm_start = 0;
612 bus->rman.rm_end = PCI_BUSMAX;
613 bus->rman.rm_type = RMAN_ARRAY;
614 snprintf(buf, sizeof(buf), "%s bus numbers", device_get_nameunit(dev));
615 bus->rman.rm_descr = strdup(buf, M_DEVBUF);
616 error = rman_init(&bus->rman);
618 panic("Failed to initialize %s bus number rman",
619 device_get_nameunit(dev));
622 * Allocate a bus range. This will return an existing bus range
623 * if one exists, or a new bus range if one does not.
626 bus->res = bus_alloc_resource_anywhere(dev, PCI_RES_BUS, &rid,
628 if (bus->res == NULL) {
630 * Fall back to just allocating a range of a single bus
633 bus->res = bus_alloc_resource_anywhere(dev, PCI_RES_BUS, &rid,
635 } else if (rman_get_size(bus->res) < min_count)
637 * Attempt to grow the existing range to satisfy the
638 * minimum desired count.
640 (void)bus_adjust_resource(dev, PCI_RES_BUS, bus->res,
641 rman_get_start(bus->res), rman_get_start(bus->res) +
645 * Add the initial resource to the rman.
647 if (bus->res != NULL) {
648 error = rman_manage_region(&bus->rman, rman_get_start(bus->res),
649 rman_get_end(bus->res));
651 panic("Failed to add resource to rman");
652 bus->sec = rman_get_start(bus->res);
653 bus->sub = rman_get_end(bus->res);
658 pcib_free_secbus(device_t dev, struct pcib_secbus *bus)
662 error = rman_fini(&bus->rman);
664 device_printf(dev, "failed to release bus number rman\n");
667 free(__DECONST(char *, bus->rman.rm_descr), M_DEVBUF);
669 error = bus_free_resource(dev, PCI_RES_BUS, bus->res);
672 "failed to release bus numbers resource: %d\n", error);
675 static struct resource *
676 pcib_suballoc_bus(struct pcib_secbus *bus, device_t child, int *rid,
677 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
679 struct resource *res;
681 res = rman_reserve_resource(&bus->rman, start, end, count, flags,
687 device_printf(bus->dev,
688 "allocated bus range (%ju-%ju) for rid %d of %s\n",
689 rman_get_start(res), rman_get_end(res), *rid,
690 pcib_child_name(child));
691 rman_set_rid(res, *rid);
696 * Attempt to grow the secondary bus range. This is much simpler than
697 * for I/O windows as the range can only be grown by increasing
701 pcib_grow_subbus(struct pcib_secbus *bus, rman_res_t new_end)
706 old_end = rman_get_end(bus->res);
707 KASSERT(new_end > old_end, ("attempt to shrink subbus"));
708 error = bus_adjust_resource(bus->dev, PCI_RES_BUS, bus->res,
709 rman_get_start(bus->res), new_end);
713 device_printf(bus->dev, "grew bus range to %ju-%ju\n",
714 rman_get_start(bus->res), rman_get_end(bus->res));
715 error = rman_manage_region(&bus->rman, old_end + 1,
716 rman_get_end(bus->res));
718 panic("Failed to add resource to rman");
719 bus->sub = rman_get_end(bus->res);
720 pci_write_config(bus->dev, bus->sub_reg, bus->sub, 1);
725 pcib_alloc_subbus(struct pcib_secbus *bus, device_t child, int *rid,
726 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
728 struct resource *res;
729 rman_res_t start_free, end_free, new_end;
732 * First, see if the request can be satisified by the existing
735 res = pcib_suballoc_bus(bus, child, rid, start, end, count, flags);
740 * Figure out a range to grow the bus range. First, find the
741 * first bus number after the last allocated bus in the rman and
742 * enforce that as a minimum starting point for the range.
744 if (rman_last_free_region(&bus->rman, &start_free, &end_free) != 0 ||
745 end_free != bus->sub)
746 start_free = bus->sub + 1;
747 if (start_free < start)
749 new_end = start_free + count - 1;
752 * See if this new range would satisfy the request if it
758 /* Finally, attempt to grow the existing resource. */
760 device_printf(bus->dev,
761 "attempting to grow bus range for %ju buses\n", count);
762 printf("\tback candidate range: %ju-%ju\n", start_free,
765 if (pcib_grow_subbus(bus, new_end) == 0)
766 return (pcib_suballoc_bus(bus, child, rid, start, end, count,
775 * Is the prefetch window open (eg, can we allocate memory in it?)
778 pcib_is_prefetch_open(struct pcib_softc *sc)
780 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit);
784 * Is the nonprefetch window open (eg, can we allocate memory in it?)
787 pcib_is_nonprefetch_open(struct pcib_softc *sc)
789 return (sc->membase > 0 && sc->membase < sc->memlimit);
793 * Is the io window open (eg, can we allocate ports in it?)
796 pcib_is_io_open(struct pcib_softc *sc)
798 return (sc->iobase > 0 && sc->iobase < sc->iolimit);
802 * Get current I/O decode.
805 pcib_get_io_decode(struct pcib_softc *sc)
812 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1);
813 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32)
814 sc->iobase = PCI_PPBIOBASE(
815 pci_read_config(dev, PCIR_IOBASEH_1, 2), iolow);
817 sc->iobase = PCI_PPBIOBASE(0, iolow);
819 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1);
820 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32)
821 sc->iolimit = PCI_PPBIOLIMIT(
822 pci_read_config(dev, PCIR_IOLIMITH_1, 2), iolow);
824 sc->iolimit = PCI_PPBIOLIMIT(0, iolow);
828 * Get current memory decode.
831 pcib_get_mem_decode(struct pcib_softc *sc)
838 sc->membase = PCI_PPBMEMBASE(0,
839 pci_read_config(dev, PCIR_MEMBASE_1, 2));
840 sc->memlimit = PCI_PPBMEMLIMIT(0,
841 pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
843 pmemlow = pci_read_config(dev, PCIR_PMBASEL_1, 2);
844 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64)
845 sc->pmembase = PCI_PPBMEMBASE(
846 pci_read_config(dev, PCIR_PMBASEH_1, 4), pmemlow);
848 sc->pmembase = PCI_PPBMEMBASE(0, pmemlow);
850 pmemlow = pci_read_config(dev, PCIR_PMLIMITL_1, 2);
851 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64)
852 sc->pmemlimit = PCI_PPBMEMLIMIT(
853 pci_read_config(dev, PCIR_PMLIMITH_1, 4), pmemlow);
855 sc->pmemlimit = PCI_PPBMEMLIMIT(0, pmemlow);
859 * Restore previous I/O decode.
862 pcib_set_io_decode(struct pcib_softc *sc)
869 iohi = sc->iobase >> 16;
871 pci_write_config(dev, PCIR_IOBASEH_1, iohi, 2);
872 pci_write_config(dev, PCIR_IOBASEL_1, sc->iobase >> 8, 1);
874 iohi = sc->iolimit >> 16;
876 pci_write_config(dev, PCIR_IOLIMITH_1, iohi, 2);
877 pci_write_config(dev, PCIR_IOLIMITL_1, sc->iolimit >> 8, 1);
881 * Restore previous memory decode.
884 pcib_set_mem_decode(struct pcib_softc *sc)
891 pci_write_config(dev, PCIR_MEMBASE_1, sc->membase >> 16, 2);
892 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->memlimit >> 16, 2);
894 pmemhi = sc->pmembase >> 32;
896 pci_write_config(dev, PCIR_PMBASEH_1, pmemhi, 4);
897 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmembase >> 16, 2);
899 pmemhi = sc->pmemlimit >> 32;
901 pci_write_config(dev, PCIR_PMLIMITH_1, pmemhi, 4);
902 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmemlimit >> 16, 2);
908 * PCI-express HotPlug support.
911 pcib_probe_hotplug(struct pcib_softc *sc)
916 if (pci_find_cap(dev, PCIY_EXPRESS, NULL) != 0)
919 if (!(pcie_read_config(dev, PCIER_FLAGS, 2) & PCIEM_FLAGS_SLOT))
922 sc->pcie_link_cap = pcie_read_config(dev, PCIER_LINK_CAP, 4);
923 sc->pcie_slot_cap = pcie_read_config(dev, PCIER_SLOT_CAP, 4);
925 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_HPC)
926 sc->flags |= PCIB_HOTPLUG;
930 * Send a HotPlug command to the slot control register. If this slot
931 * uses command completion interrupts and a previous command is still
932 * in progress, then the command is dropped. Once the previous
933 * command completes or times out, pcib_pcie_hotplug_update() will be
934 * invoked to post a new command based on the slot's state at that
938 pcib_pcie_hotplug_command(struct pcib_softc *sc, uint16_t val, uint16_t mask)
945 if (sc->flags & PCIB_HOTPLUG_CMD_PENDING)
948 ctl = pcie_read_config(dev, PCIER_SLOT_CTL, 2);
949 new = (ctl & ~mask) | val;
952 pcie_write_config(dev, PCIER_SLOT_CTL, new, 2);
953 if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS) &&
954 (ctl & new) & PCIEM_SLOT_CTL_CCIE) {
955 sc->flags |= PCIB_HOTPLUG_CMD_PENDING;
957 callout_reset(&sc->pcie_cc_timer, hz,
958 pcib_pcie_cc_timeout, sc);
963 pcib_pcie_hotplug_command_completed(struct pcib_softc *sc)
970 device_printf(dev, "Command Completed\n");
971 if (!(sc->flags & PCIB_HOTPLUG_CMD_PENDING))
973 callout_stop(&sc->pcie_cc_timer);
974 sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING;
979 * Returns true if a card is fully inserted from the user's
980 * perspective. It may not yet be ready for access, but the driver
981 * can now start enabling access if necessary.
984 pcib_hotplug_inserted(struct pcib_softc *sc)
987 /* Pretend the card isn't present if a detach is forced. */
988 if (sc->flags & PCIB_DETACHING)
991 /* Card must be present in the slot. */
992 if ((sc->pcie_slot_sta & PCIEM_SLOT_STA_PDS) == 0)
995 /* A power fault implicitly turns off power to the slot. */
996 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_PFD)
999 /* If the MRL is disengaged, the slot is powered off. */
1000 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP &&
1001 (sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSS) != 0)
1008 * Returns -1 if the card is fully inserted, powered, and ready for
1009 * access. Otherwise, returns 0.
1012 pcib_hotplug_present(struct pcib_softc *sc)
1018 /* Card must be inserted. */
1019 if (!pcib_hotplug_inserted(sc))
1023 * Require the Electromechanical Interlock to be engaged if
1026 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_EIP &&
1027 (sc->pcie_slot_sta & PCIEM_SLOT_STA_EIS) == 0)
1030 /* Require the Data Link Layer to be active. */
1031 if (sc->pcie_link_cap & PCIEM_LINK_CAP_DL_ACTIVE) {
1032 if (!(sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE))
1040 pcib_pcie_hotplug_update(struct pcib_softc *sc, uint16_t val, uint16_t mask,
1045 /* Clear DETACHING if Present Detect has cleared. */
1046 if ((sc->pcie_slot_sta & (PCIEM_SLOT_STA_PDC | PCIEM_SLOT_STA_PDS)) ==
1048 sc->flags &= ~PCIB_DETACHING;
1050 card_inserted = pcib_hotplug_inserted(sc);
1052 /* Turn the power indicator on if a card is inserted. */
1053 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PIP) {
1054 mask |= PCIEM_SLOT_CTL_PIC;
1056 val |= PCIEM_SLOT_CTL_PI_ON;
1057 else if (sc->flags & PCIB_DETACH_PENDING)
1058 val |= PCIEM_SLOT_CTL_PI_BLINK;
1060 val |= PCIEM_SLOT_CTL_PI_OFF;
1063 /* Turn the power on via the Power Controller if a card is inserted. */
1064 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PCP) {
1065 mask |= PCIEM_SLOT_CTL_PCC;
1067 val |= PCIEM_SLOT_CTL_PC_ON;
1069 val |= PCIEM_SLOT_CTL_PC_OFF;
1073 * If a card is inserted, enable the Electromechanical
1074 * Interlock. If a card is not inserted (or we are in the
1075 * process of detaching), disable the Electromechanical
1078 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_EIP) {
1079 mask |= PCIEM_SLOT_CTL_EIC;
1080 if (card_inserted !=
1081 !(sc->pcie_slot_sta & PCIEM_SLOT_STA_EIS))
1082 val |= PCIEM_SLOT_CTL_EIC;
1086 * Start a timer to see if the Data Link Layer times out.
1087 * Note that we only start the timer if Presence Detect
1088 * changed on this interrupt. Stop any scheduled timer if
1089 * the Data Link Layer is active.
1091 if (sc->pcie_link_cap & PCIEM_LINK_CAP_DL_ACTIVE) {
1092 if (card_inserted &&
1093 !(sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE) &&
1094 sc->pcie_slot_sta & PCIEM_SLOT_STA_PDC) {
1096 device_printf(sc->dev,
1097 "Data Link Layer inactive\n");
1099 callout_reset(&sc->pcie_dll_timer, hz,
1100 pcib_pcie_dll_timeout, sc);
1101 } else if (sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE)
1102 callout_stop(&sc->pcie_dll_timer);
1105 pcib_pcie_hotplug_command(sc, val, mask);
1108 * During attach the child "pci" device is added sychronously;
1109 * otherwise, the task is scheduled to manage the child
1112 if (schedule_task &&
1113 (pcib_hotplug_present(sc) != 0) != (sc->child != NULL))
1114 taskqueue_enqueue(taskqueue_thread, &sc->pcie_hp_task);
1118 pcib_pcie_intr(void *arg)
1120 struct pcib_softc *sc;
1125 sc->pcie_slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2);
1127 /* Clear the events just reported. */
1128 pcie_write_config(dev, PCIER_SLOT_STA, sc->pcie_slot_sta, 2);
1130 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_ABP) {
1131 if (sc->flags & PCIB_DETACH_PENDING) {
1133 "Attention Button Pressed: Detach Cancelled\n");
1134 sc->flags &= ~PCIB_DETACH_PENDING;
1135 callout_stop(&sc->pcie_ab_timer);
1138 "Attention Button Pressed: Detaching in 5 seconds\n");
1139 sc->flags |= PCIB_DETACH_PENDING;
1140 callout_reset(&sc->pcie_ab_timer, 5 * hz,
1141 pcib_pcie_ab_timeout, sc);
1144 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_PFD)
1145 device_printf(dev, "Power Fault Detected\n");
1146 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSC)
1147 device_printf(dev, "MRL Sensor Changed to %s\n",
1148 sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSS ? "open" :
1150 if (bootverbose && sc->pcie_slot_sta & PCIEM_SLOT_STA_PDC)
1151 device_printf(dev, "Present Detect Changed to %s\n",
1152 sc->pcie_slot_sta & PCIEM_SLOT_STA_PDS ? "card present" :
1154 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_CC)
1155 pcib_pcie_hotplug_command_completed(sc);
1156 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_DLLSC) {
1157 sc->pcie_link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2);
1160 "Data Link Layer State Changed to %s\n",
1161 sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE ?
1162 "active" : "inactive");
1165 pcib_pcie_hotplug_update(sc, 0, 0, true);
1169 pcib_pcie_hotplug_task(void *context, int pending)
1171 struct pcib_softc *sc;
1177 if (pcib_hotplug_present(sc) != 0) {
1178 if (sc->child == NULL) {
1179 sc->child = device_add_child(dev, "pci", -1);
1180 bus_generic_attach(dev);
1183 if (sc->child != NULL) {
1184 if (device_delete_child(dev, sc->child) == 0)
1192 pcib_pcie_ab_timeout(void *arg)
1194 struct pcib_softc *sc;
1199 mtx_assert(&Giant, MA_OWNED);
1200 if (sc->flags & PCIB_DETACH_PENDING) {
1201 sc->flags |= PCIB_DETACHING;
1202 sc->flags &= ~PCIB_DETACH_PENDING;
1203 pcib_pcie_hotplug_update(sc, 0, 0, true);
1208 pcib_pcie_cc_timeout(void *arg)
1210 struct pcib_softc *sc;
1216 mtx_assert(&Giant, MA_OWNED);
1217 sta = pcie_read_config(dev, PCIER_SLOT_STA, 2);
1218 if (!(sta & PCIEM_SLOT_STA_CC)) {
1220 "Hotplug Command Timed Out - forcing detach\n");
1221 sc->flags &= ~(PCIB_HOTPLUG_CMD_PENDING | PCIB_DETACH_PENDING);
1222 sc->flags |= PCIB_DETACHING;
1223 pcib_pcie_hotplug_update(sc, 0, 0, true);
1226 "Missed HotPlug interrupt waiting for Command Completion\n");
1232 pcib_pcie_dll_timeout(void *arg)
1234 struct pcib_softc *sc;
1240 mtx_assert(&Giant, MA_OWNED);
1241 sta = pcie_read_config(dev, PCIER_LINK_STA, 2);
1242 if (!(sta & PCIEM_LINK_STA_DL_ACTIVE)) {
1244 "Timed out waiting for Data Link Layer Active\n");
1245 sc->flags |= PCIB_DETACHING;
1246 pcib_pcie_hotplug_update(sc, 0, 0, true);
1247 } else if (sta != sc->pcie_link_sta) {
1249 "Missed HotPlug interrupt waiting for DLL Active\n");
1255 pcib_alloc_pcie_irq(struct pcib_softc *sc)
1258 int count, error, rid;
1264 * For simplicity, only use MSI-X if there is a single message.
1265 * To support a device with multiple messages we would have to
1266 * use remap intr if the MSI number is not 0.
1268 count = pci_msix_count(dev);
1270 error = pci_alloc_msix(dev, &count);
1275 if (rid < 0 && pci_msi_count(dev) > 0) {
1277 error = pci_alloc_msi(dev, &count);
1285 sc->pcie_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1287 if (sc->pcie_irq == NULL) {
1289 "Failed to allocate interrupt for PCI-e events\n");
1291 pci_release_msi(dev);
1295 error = bus_setup_intr(dev, sc->pcie_irq, INTR_TYPE_MISC,
1296 NULL, pcib_pcie_intr, sc, &sc->pcie_ihand);
1298 device_printf(dev, "Failed to setup PCI-e interrupt handler\n");
1299 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->pcie_irq);
1301 pci_release_msi(dev);
1308 pcib_release_pcie_irq(struct pcib_softc *sc)
1314 error = bus_teardown_intr(dev, sc->pcie_irq, sc->pcie_ihand);
1317 error = bus_free_resource(dev, SYS_RES_IRQ, sc->pcie_irq);
1320 return (pci_release_msi(dev));
1324 pcib_setup_hotplug(struct pcib_softc *sc)
1330 callout_init(&sc->pcie_ab_timer, 0);
1331 callout_init(&sc->pcie_cc_timer, 0);
1332 callout_init(&sc->pcie_dll_timer, 0);
1333 TASK_INIT(&sc->pcie_hp_task, 0, pcib_pcie_hotplug_task, sc);
1336 if (pcib_alloc_pcie_irq(sc) != 0)
1339 sc->pcie_link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2);
1340 sc->pcie_slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2);
1342 /* Clear any events previously pending. */
1343 pcie_write_config(dev, PCIER_SLOT_STA, sc->pcie_slot_sta, 2);
1345 /* Enable HotPlug events. */
1346 mask = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE |
1347 PCIEM_SLOT_CTL_CCIE | PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_MRLSCE |
1348 PCIEM_SLOT_CTL_PFDE | PCIEM_SLOT_CTL_ABPE;
1349 val = PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_HPIE;
1350 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_APB)
1351 val |= PCIEM_SLOT_CTL_ABPE;
1352 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PCP)
1353 val |= PCIEM_SLOT_CTL_PFDE;
1354 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP)
1355 val |= PCIEM_SLOT_CTL_MRLSCE;
1356 if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS))
1357 val |= PCIEM_SLOT_CTL_CCIE;
1358 if (sc->pcie_link_cap & PCIEM_LINK_CAP_DL_ACTIVE)
1359 val |= PCIEM_SLOT_CTL_DLLSCE;
1361 /* Turn the attention indicator off. */
1362 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_AIP) {
1363 mask |= PCIEM_SLOT_CTL_AIC;
1364 val |= PCIEM_SLOT_CTL_AI_OFF;
1367 pcib_pcie_hotplug_update(sc, val, mask, false);
1371 pcib_detach_hotplug(struct pcib_softc *sc)
1376 /* Disable the card in the slot and force it to detach. */
1377 if (sc->flags & PCIB_DETACH_PENDING) {
1378 sc->flags &= ~PCIB_DETACH_PENDING;
1379 callout_stop(&sc->pcie_ab_timer);
1381 sc->flags |= PCIB_DETACHING;
1383 if (sc->flags & PCIB_HOTPLUG_CMD_PENDING) {
1384 callout_stop(&sc->pcie_cc_timer);
1385 tsleep(sc, 0, "hpcmd", hz);
1386 sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING;
1389 /* Disable HotPlug events. */
1390 mask = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE |
1391 PCIEM_SLOT_CTL_CCIE | PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_MRLSCE |
1392 PCIEM_SLOT_CTL_PFDE | PCIEM_SLOT_CTL_ABPE;
1395 /* Turn the attention indicator off. */
1396 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_AIP) {
1397 mask |= PCIEM_SLOT_CTL_AIC;
1398 val |= PCIEM_SLOT_CTL_AI_OFF;
1401 pcib_pcie_hotplug_update(sc, val, mask, false);
1403 error = pcib_release_pcie_irq(sc);
1406 taskqueue_drain(taskqueue_thread, &sc->pcie_hp_task);
1407 callout_drain(&sc->pcie_ab_timer);
1408 callout_drain(&sc->pcie_cc_timer);
1409 callout_drain(&sc->pcie_dll_timer);
1415 * Get current bridge configuration.
1418 pcib_cfg_save(struct pcib_softc *sc)
1426 command = pci_read_config(dev, PCIR_COMMAND, 2);
1427 if (command & PCIM_CMD_PORTEN)
1428 pcib_get_io_decode(sc);
1429 if (command & PCIM_CMD_MEMEN)
1430 pcib_get_mem_decode(sc);
1435 * Restore previous bridge configuration.
1438 pcib_cfg_restore(struct pcib_softc *sc)
1447 pcib_write_windows(sc, WIN_IO | WIN_MEM | WIN_PMEM);
1449 command = pci_read_config(dev, PCIR_COMMAND, 2);
1450 if (command & PCIM_CMD_PORTEN)
1451 pcib_set_io_decode(sc);
1452 if (command & PCIM_CMD_MEMEN)
1453 pcib_set_mem_decode(sc);
1458 * Generic device interface
1461 pcib_probe(device_t dev)
1463 if ((pci_get_class(dev) == PCIC_BRIDGE) &&
1464 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) {
1465 device_set_desc(dev, "PCI-PCI bridge");
1472 pcib_attach_common(device_t dev)
1474 struct pcib_softc *sc;
1475 struct sysctl_ctx_list *sctx;
1476 struct sysctl_oid *soid;
1479 sc = device_get_softc(dev);
1483 * Get current bridge configuration.
1485 sc->domain = pci_get_domain(dev);
1486 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS))
1487 sc->bus.sec = pci_read_config(dev, PCIR_SECBUS_1, 1);
1488 sc->bus.sub = pci_read_config(dev, PCIR_SUBBUS_1, 1);
1490 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
1494 * The primary bus register should always be the bus of the
1497 sc->pribus = pci_get_bus(dev);
1498 pci_write_config(dev, PCIR_PRIBUS_1, sc->pribus, 1);
1501 * Setup sysctl reporting nodes
1503 sctx = device_get_sysctl_ctx(dev);
1504 soid = device_get_sysctl_tree(dev);
1505 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain",
1506 CTLFLAG_RD, &sc->domain, 0, "Domain number");
1507 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus",
1508 CTLFLAG_RD, &sc->pribus, 0, "Primary bus number");
1509 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus",
1510 CTLFLAG_RD, &sc->bus.sec, 0, "Secondary bus number");
1511 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus",
1512 CTLFLAG_RD, &sc->bus.sub, 0, "Subordinate bus number");
1517 switch (pci_get_devid(dev)) {
1518 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS))
1519 case 0x12258086: /* Intel 82454KX/GX (Orion) */
1523 supbus = pci_read_config(dev, 0x41, 1);
1524 if (supbus != 0xff) {
1525 sc->bus.sec = supbus + 1;
1526 sc->bus.sub = supbus + 1;
1533 * The i82380FB mobile docking controller is a PCI-PCI bridge,
1534 * and it is a subtractive bridge. However, the ProgIf is wrong
1535 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't
1536 * happen. There are also Toshiba and Cavium ThunderX bridges
1537 * that behave this way.
1539 case 0xa002177d: /* Cavium ThunderX */
1540 case 0x124b8086: /* Intel 82380FB Mobile */
1541 case 0x060513d7: /* Toshiba ???? */
1542 sc->flags |= PCIB_SUBTRACTIVE;
1545 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS))
1546 /* Compaq R3000 BIOS sets wrong subordinate bus number. */
1551 if ((cp = kern_getenv("smbios.planar.maker")) == NULL)
1553 if (strncmp(cp, "Compal", 6) != 0) {
1558 if ((cp = kern_getenv("smbios.planar.product")) == NULL)
1560 if (strncmp(cp, "08A0", 4) != 0) {
1565 if (sc->bus.sub < 0xa) {
1566 pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1);
1567 sc->bus.sub = pci_read_config(dev, PCIR_SUBBUS_1, 1);
1574 if (pci_msi_device_blacklisted(dev))
1575 sc->flags |= PCIB_DISABLE_MSI;
1577 if (pci_msix_device_blacklisted(dev))
1578 sc->flags |= PCIB_DISABLE_MSIX;
1581 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges,
1582 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM,
1583 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese.
1584 * This means they act as if they were subtractively decoding
1585 * bridges and pass all transactions. Mark them and real ProgIf 1
1586 * parts as subtractive.
1588 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 ||
1589 pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_BRIDGE_PCI_SUBTRACTIVE)
1590 sc->flags |= PCIB_SUBTRACTIVE;
1593 pcib_probe_hotplug(sc);
1597 pcib_setup_secbus(dev, &sc->bus, 1);
1599 pcib_probe_windows(sc);
1602 if (sc->flags & PCIB_HOTPLUG)
1603 pcib_setup_hotplug(sc);
1606 device_printf(dev, " domain %d\n", sc->domain);
1607 device_printf(dev, " secondary bus %d\n", sc->bus.sec);
1608 device_printf(dev, " subordinate bus %d\n", sc->bus.sub);
1610 if (pcib_is_window_open(&sc->io))
1611 device_printf(dev, " I/O decode 0x%jx-0x%jx\n",
1612 (uintmax_t)sc->io.base, (uintmax_t)sc->io.limit);
1613 if (pcib_is_window_open(&sc->mem))
1614 device_printf(dev, " memory decode 0x%jx-0x%jx\n",
1615 (uintmax_t)sc->mem.base, (uintmax_t)sc->mem.limit);
1616 if (pcib_is_window_open(&sc->pmem))
1617 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n",
1618 (uintmax_t)sc->pmem.base, (uintmax_t)sc->pmem.limit);
1620 if (pcib_is_io_open(sc))
1621 device_printf(dev, " I/O decode 0x%x-0x%x\n",
1622 sc->iobase, sc->iolimit);
1623 if (pcib_is_nonprefetch_open(sc))
1624 device_printf(dev, " memory decode 0x%jx-0x%jx\n",
1625 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit);
1626 if (pcib_is_prefetch_open(sc))
1627 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n",
1628 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit);
1630 if (sc->bridgectl & (PCIB_BCR_ISA_ENABLE | PCIB_BCR_VGA_ENABLE) ||
1631 sc->flags & PCIB_SUBTRACTIVE) {
1632 device_printf(dev, " special decode ");
1634 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE) {
1638 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE) {
1639 printf("%sVGA", comma ? ", " : "");
1642 if (sc->flags & PCIB_SUBTRACTIVE)
1643 printf("%ssubtractive", comma ? ", " : "");
1649 * Always enable busmastering on bridges so that transactions
1650 * initiated on the secondary bus are passed through to the
1653 pci_enable_busmaster(dev);
1658 pcib_present(struct pcib_softc *sc)
1661 if (sc->flags & PCIB_HOTPLUG)
1662 return (pcib_hotplug_present(sc) != 0);
1668 pcib_attach_child(device_t dev)
1670 struct pcib_softc *sc;
1672 sc = device_get_softc(dev);
1673 if (sc->bus.sec == 0) {
1674 /* no secondary bus; we should have fixed this */
1679 if (!pcib_present(sc)) {
1680 /* An empty HotPlug slot, so don't add a PCI bus yet. */
1685 sc->child = device_add_child(dev, "pci", -1);
1686 return (bus_generic_attach(dev));
1690 pcib_attach(device_t dev)
1693 pcib_attach_common(dev);
1694 return (pcib_attach_child(dev));
1698 pcib_detach(device_t dev)
1700 #if defined(PCI_HP) || defined(NEW_PCIB)
1701 struct pcib_softc *sc;
1705 #if defined(PCI_HP) || defined(NEW_PCIB)
1706 sc = device_get_softc(dev);
1708 error = bus_generic_detach(dev);
1712 if (sc->flags & PCIB_HOTPLUG) {
1713 error = pcib_detach_hotplug(sc);
1718 error = device_delete_children(dev);
1722 pcib_free_windows(sc);
1724 pcib_free_secbus(dev, &sc->bus);
1731 pcib_suspend(device_t dev)
1734 pcib_cfg_save(device_get_softc(dev));
1735 return (bus_generic_suspend(dev));
1739 pcib_resume(device_t dev)
1742 pcib_cfg_restore(device_get_softc(dev));
1743 return (bus_generic_resume(dev));
1747 pcib_bridge_init(device_t dev)
1749 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1);
1750 pci_write_config(dev, PCIR_IOBASEH_1, 0xffff, 2);
1751 pci_write_config(dev, PCIR_IOLIMITL_1, 0, 1);
1752 pci_write_config(dev, PCIR_IOLIMITH_1, 0, 2);
1753 pci_write_config(dev, PCIR_MEMBASE_1, 0xffff, 2);
1754 pci_write_config(dev, PCIR_MEMLIMIT_1, 0, 2);
1755 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2);
1756 pci_write_config(dev, PCIR_PMBASEH_1, 0xffffffff, 4);
1757 pci_write_config(dev, PCIR_PMLIMITL_1, 0, 2);
1758 pci_write_config(dev, PCIR_PMLIMITH_1, 0, 4);
1762 pcib_child_present(device_t dev, device_t child)
1765 struct pcib_softc *sc = device_get_softc(dev);
1768 retval = bus_child_present(dev);
1769 if (retval != 0 && sc->flags & PCIB_HOTPLUG)
1770 retval = pcib_hotplug_present(sc);
1773 return (bus_child_present(dev));
1778 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1780 struct pcib_softc *sc = device_get_softc(dev);
1783 case PCIB_IVAR_DOMAIN:
1784 *result = sc->domain;
1787 *result = sc->bus.sec;
1794 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1798 case PCIB_IVAR_DOMAIN:
1808 * Attempt to allocate a resource from the existing resources assigned
1811 static struct resource *
1812 pcib_suballoc_resource(struct pcib_softc *sc, struct pcib_window *w,
1813 device_t child, int type, int *rid, rman_res_t start, rman_res_t end,
1814 rman_res_t count, u_int flags)
1816 struct resource *res;
1818 if (!pcib_is_window_open(w))
1821 res = rman_reserve_resource(&w->rman, start, end, count,
1822 flags & ~RF_ACTIVE, child);
1827 device_printf(sc->dev,
1828 "allocated %s range (%#jx-%#jx) for rid %x of %s\n",
1829 w->name, rman_get_start(res), rman_get_end(res), *rid,
1830 pcib_child_name(child));
1831 rman_set_rid(res, *rid);
1834 * If the resource should be active, pass that request up the
1835 * tree. This assumes the parent drivers can handle
1836 * activating sub-allocated resources.
1838 if (flags & RF_ACTIVE) {
1839 if (bus_activate_resource(child, type, *rid, res) != 0) {
1840 rman_release_resource(res);
1848 /* Allocate a fresh resource range for an unconfigured window. */
1850 pcib_alloc_new_window(struct pcib_softc *sc, struct pcib_window *w, int type,
1851 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
1853 struct resource *res;
1854 rman_res_t base, limit, wmask;
1858 * If this is an I/O window on a bridge with ISA enable set
1859 * and the start address is below 64k, then try to allocate an
1860 * initial window of 0x1000 bytes long starting at address
1861 * 0xf000 and walking down. Note that if the original request
1862 * was larger than the non-aliased range size of 0x100 our
1863 * caller would have raised the start address up to 64k
1866 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE &&
1868 for (base = 0xf000; (long)base >= 0; base -= 0x1000) {
1869 limit = base + 0xfff;
1872 * Skip ranges that wouldn't work for the
1873 * original request. Note that the actual
1874 * window that overlaps are the non-alias
1875 * ranges within [base, limit], so this isn't
1876 * quite a simple comparison.
1878 if (start + count > limit - 0x400)
1882 * The first open region for the window at
1885 if (end - count + 1 < 0x400)
1888 if (end - count + 1 < base)
1892 if (pcib_alloc_nonisa_ranges(sc, base, limit) == 0) {
1901 wmask = ((rman_res_t)1 << w->step) - 1;
1902 if (RF_ALIGNMENT(flags) < w->step) {
1903 flags &= ~RF_ALIGNMENT_MASK;
1904 flags |= RF_ALIGNMENT_LOG2(w->step);
1908 count = roundup2(count, (rman_res_t)1 << w->step);
1910 res = bus_alloc_resource(sc->dev, type, &rid, start, end, count,
1911 flags & ~RF_ACTIVE);
1914 pcib_add_window_resources(w, &res, 1);
1915 pcib_activate_window(sc, type);
1916 w->base = rman_get_start(res);
1917 w->limit = rman_get_end(res);
1921 /* Try to expand an existing window to the requested base and limit. */
1923 pcib_expand_window(struct pcib_softc *sc, struct pcib_window *w, int type,
1924 rman_res_t base, rman_res_t limit)
1926 struct resource *res;
1927 int error, i, force_64k_base;
1929 KASSERT(base <= w->base && limit >= w->limit,
1930 ("attempting to shrink window"));
1933 * XXX: pcib_grow_window() doesn't try to do this anyway and
1934 * the error handling for all the edge cases would be tedious.
1936 KASSERT(limit == w->limit || base == w->base,
1937 ("attempting to grow both ends of a window"));
1940 * Yet more special handling for requests to expand an I/O
1941 * window behind an ISA-enabled bridge. Since I/O windows
1942 * have to grow in 0x1000 increments and the end of the 0xffff
1943 * range is an alias, growing a window below 64k will always
1944 * result in allocating new resources and never adjusting an
1945 * existing resource.
1947 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE &&
1948 (limit <= 65535 || (base <= 65535 && base != w->base))) {
1949 KASSERT(limit == w->limit || limit <= 65535,
1950 ("attempting to grow both ends across 64k ISA alias"));
1952 if (base != w->base)
1953 error = pcib_alloc_nonisa_ranges(sc, base, w->base - 1);
1955 error = pcib_alloc_nonisa_ranges(sc, w->limit + 1,
1965 * Find the existing resource to adjust. Usually there is only one,
1966 * but for an ISA-enabled bridge we might be growing the I/O window
1967 * above 64k and need to find the existing resource that maps all
1968 * of the area above 64k.
1970 for (i = 0; i < w->count; i++) {
1971 if (rman_get_end(w->res[i]) == w->limit)
1974 KASSERT(i != w->count, ("did not find existing resource"));
1978 * Usually the resource we found should match the window's
1979 * existing range. The one exception is the ISA-enabled case
1980 * mentioned above in which case the resource should start at
1983 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE &&
1985 KASSERT(rman_get_start(res) == 65536,
1986 ("existing resource mismatch"));
1989 KASSERT(w->base == rman_get_start(res),
1990 ("existing resource mismatch"));
1994 error = bus_adjust_resource(sc->dev, type, res, force_64k_base ?
1995 rman_get_start(res) : base, limit);
1999 /* Add the newly allocated region to the resource manager. */
2000 if (w->base != base) {
2001 error = rman_manage_region(&w->rman, base, w->base - 1);
2004 error = rman_manage_region(&w->rman, w->limit + 1, limit);
2009 device_printf(sc->dev,
2010 "failed to expand %s resource manager\n", w->name);
2011 (void)bus_adjust_resource(sc->dev, type, res, force_64k_base ?
2012 rman_get_start(res) : w->base, w->limit);
2018 * Attempt to grow a window to make room for a given resource request.
2021 pcib_grow_window(struct pcib_softc *sc, struct pcib_window *w, int type,
2022 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
2024 rman_res_t align, start_free, end_free, front, back, wmask;
2028 * Clamp the desired resource range to the maximum address
2029 * this window supports. Reject impossible requests.
2031 * For I/O port requests behind a bridge with the ISA enable
2032 * bit set, force large allocations to start above 64k.
2036 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE && count > 0x100 &&
2039 if (end > w->rman.rm_end)
2040 end = w->rman.rm_end;
2041 if (start + count - 1 > end || start + count < start)
2043 wmask = ((rman_res_t)1 << w->step) - 1;
2046 * If there is no resource at all, just try to allocate enough
2047 * aligned space for this resource.
2049 if (w->res == NULL) {
2050 error = pcib_alloc_new_window(sc, w, type, start, end, count,
2054 device_printf(sc->dev,
2055 "failed to allocate initial %s window (%#jx-%#jx,%#jx)\n",
2056 w->name, start, end, count);
2060 device_printf(sc->dev,
2061 "allocated initial %s window of %#jx-%#jx\n",
2062 w->name, (uintmax_t)w->base, (uintmax_t)w->limit);
2067 * See if growing the window would help. Compute the minimum
2068 * amount of address space needed on both the front and back
2069 * ends of the existing window to satisfy the allocation.
2071 * For each end, build a candidate region adjusting for the
2072 * required alignment, etc. If there is a free region at the
2073 * edge of the window, grow from the inner edge of the free
2074 * region. Otherwise grow from the window boundary.
2076 * Growing an I/O window below 64k for a bridge with the ISA
2077 * enable bit doesn't require any special magic as the step
2078 * size of an I/O window (1k) always includes multiple
2079 * non-alias ranges when it is grown in either direction.
2081 * XXX: Special case: if w->res is completely empty and the
2082 * request size is larger than w->res, we should find the
2083 * optimal aligned buffer containing w->res and allocate that.
2086 device_printf(sc->dev,
2087 "attempting to grow %s window for (%#jx-%#jx,%#jx)\n",
2088 w->name, start, end, count);
2089 align = (rman_res_t)1 << RF_ALIGNMENT(flags);
2090 if (start < w->base) {
2091 if (rman_first_free_region(&w->rman, &start_free, &end_free) !=
2092 0 || start_free != w->base)
2097 /* Move end_free down until it is properly aligned. */
2098 end_free &= ~(align - 1);
2100 front = end_free - (count - 1);
2103 * The resource would now be allocated at (front,
2104 * end_free). Ensure that fits in the (start, end)
2105 * bounds. end_free is checked above. If 'front' is
2106 * ok, ensure it is properly aligned for this window.
2107 * Also check for underflow.
2109 if (front >= start && front <= end_free) {
2111 printf("\tfront candidate range: %#jx-%#jx\n",
2114 front = w->base - front;
2119 if (end > w->limit) {
2120 if (rman_last_free_region(&w->rman, &start_free, &end_free) !=
2121 0 || end_free != w->limit)
2122 start_free = w->limit + 1;
2123 if (start_free < start)
2126 /* Move start_free up until it is properly aligned. */
2127 start_free = roundup2(start_free, align);
2128 back = start_free + count - 1;
2131 * The resource would now be allocated at (start_free,
2132 * back). Ensure that fits in the (start, end)
2133 * bounds. start_free is checked above. If 'back' is
2134 * ok, ensure it is properly aligned for this window.
2135 * Also check for overflow.
2137 if (back <= end && start_free <= back) {
2139 printf("\tback candidate range: %#jx-%#jx\n",
2149 * Try to allocate the smallest needed region first.
2150 * If that fails, fall back to the other region.
2153 while (front != 0 || back != 0) {
2154 if (front != 0 && (front <= back || back == 0)) {
2155 error = pcib_expand_window(sc, w, type, w->base - front,
2161 error = pcib_expand_window(sc, w, type, w->base,
2172 device_printf(sc->dev, "grew %s window to %#jx-%#jx\n",
2173 w->name, (uintmax_t)w->base, (uintmax_t)w->limit);
2176 /* Write the new window. */
2177 KASSERT((w->base & wmask) == 0, ("start address is not aligned"));
2178 KASSERT((w->limit & wmask) == wmask, ("end address is not aligned"));
2179 pcib_write_windows(sc, w->mask);
2184 * We have to trap resource allocation requests and ensure that the bridge
2185 * is set up to, or capable of handling them.
2188 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
2189 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
2191 struct pcib_softc *sc;
2194 sc = device_get_softc(dev);
2197 * VGA resources are decoded iff the VGA enable bit is set in
2198 * the bridge control register. VGA resources do not fall into
2199 * the resource windows and are passed up to the parent.
2201 if ((type == SYS_RES_IOPORT && pci_is_vga_ioport_range(start, end)) ||
2202 (type == SYS_RES_MEMORY && pci_is_vga_memory_range(start, end))) {
2203 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE)
2204 return (bus_generic_alloc_resource(dev, child, type,
2205 rid, start, end, count, flags));
2213 return (pcib_alloc_subbus(&sc->bus, child, rid, start, end,
2216 case SYS_RES_IOPORT:
2217 if (pcib_is_isa_range(sc, start, end, count))
2219 r = pcib_suballoc_resource(sc, &sc->io, child, type, rid, start,
2221 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0)
2223 if (pcib_grow_window(sc, &sc->io, type, start, end, count,
2225 r = pcib_suballoc_resource(sc, &sc->io, child, type,
2226 rid, start, end, count, flags);
2228 case SYS_RES_MEMORY:
2230 * For prefetchable resources, prefer the prefetchable
2231 * memory window, but fall back to the regular memory
2232 * window if that fails. Try both windows before
2233 * attempting to grow a window in case the firmware
2234 * has used a range in the regular memory window to
2235 * map a prefetchable BAR.
2237 if (flags & RF_PREFETCHABLE) {
2238 r = pcib_suballoc_resource(sc, &sc->pmem, child, type,
2239 rid, start, end, count, flags);
2243 r = pcib_suballoc_resource(sc, &sc->mem, child, type, rid,
2244 start, end, count, flags);
2245 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0)
2247 if (flags & RF_PREFETCHABLE) {
2248 if (pcib_grow_window(sc, &sc->pmem, type, start, end,
2249 count, flags) == 0) {
2250 r = pcib_suballoc_resource(sc, &sc->pmem, child,
2251 type, rid, start, end, count, flags);
2256 if (pcib_grow_window(sc, &sc->mem, type, start, end, count,
2257 flags & ~RF_PREFETCHABLE) == 0)
2258 r = pcib_suballoc_resource(sc, &sc->mem, child, type,
2259 rid, start, end, count, flags);
2262 return (bus_generic_alloc_resource(dev, child, type, rid,
2263 start, end, count, flags));
2267 * If attempts to suballocate from the window fail but this is a
2268 * subtractive bridge, pass the request up the tree.
2270 if (sc->flags & PCIB_SUBTRACTIVE && r == NULL)
2271 return (bus_generic_alloc_resource(dev, child, type, rid,
2272 start, end, count, flags));
2277 pcib_adjust_resource(device_t bus, device_t child, int type, struct resource *r,
2278 rman_res_t start, rman_res_t end)
2280 struct pcib_softc *sc;
2282 sc = device_get_softc(bus);
2283 if (pcib_is_resource_managed(sc, type, r))
2284 return (rman_adjust_resource(r, start, end));
2285 return (bus_generic_adjust_resource(bus, child, type, r, start, end));
2289 pcib_release_resource(device_t dev, device_t child, int type, int rid,
2292 struct pcib_softc *sc;
2295 sc = device_get_softc(dev);
2296 if (pcib_is_resource_managed(sc, type, r)) {
2297 if (rman_get_flags(r) & RF_ACTIVE) {
2298 error = bus_deactivate_resource(child, type, rid, r);
2302 return (rman_release_resource(r));
2304 return (bus_generic_release_resource(dev, child, type, rid, r));
2308 * We have to trap resource allocation requests and ensure that the bridge
2309 * is set up to, or capable of handling them.
2312 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
2313 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
2315 struct pcib_softc *sc = device_get_softc(dev);
2316 const char *name, *suffix;
2320 * Fail the allocation for this range if it's not supported.
2322 name = device_get_nameunit(child);
2329 case SYS_RES_IOPORT:
2331 if (!pcib_is_io_open(sc))
2333 ok = (start >= sc->iobase && end <= sc->iolimit);
2336 * Make sure we allow access to VGA I/O addresses when the
2337 * bridge has the "VGA Enable" bit set.
2339 if (!ok && pci_is_vga_ioport_range(start, end))
2340 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
2342 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
2344 if (start < sc->iobase)
2346 if (end > sc->iolimit)
2355 * If we overlap with the subtractive range, then
2356 * pick the upper range to use.
2358 if (start < sc->iolimit && end > sc->iobase)
2359 start = sc->iolimit + 1;
2363 device_printf(dev, "ioport: end (%jx) < start (%jx)\n",
2370 device_printf(dev, "%s%srequested unsupported I/O "
2371 "range 0x%jx-0x%jx (decoding 0x%x-0x%x)\n",
2372 name, suffix, start, end, sc->iobase, sc->iolimit);
2377 "%s%srequested I/O range 0x%jx-0x%jx: in range\n",
2378 name, suffix, start, end);
2381 case SYS_RES_MEMORY:
2383 if (pcib_is_nonprefetch_open(sc))
2384 ok = ok || (start >= sc->membase && end <= sc->memlimit);
2385 if (pcib_is_prefetch_open(sc))
2386 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit);
2389 * Make sure we allow access to VGA memory addresses when the
2390 * bridge has the "VGA Enable" bit set.
2392 if (!ok && pci_is_vga_memory_range(start, end))
2393 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
2395 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
2398 if (flags & RF_PREFETCHABLE) {
2399 if (pcib_is_prefetch_open(sc)) {
2400 if (start < sc->pmembase)
2401 start = sc->pmembase;
2402 if (end > sc->pmemlimit)
2403 end = sc->pmemlimit;
2407 } else { /* non-prefetchable */
2408 if (pcib_is_nonprefetch_open(sc)) {
2409 if (start < sc->membase)
2410 start = sc->membase;
2411 if (end > sc->memlimit)
2419 ok = 1; /* subtractive bridge: always ok */
2421 if (pcib_is_nonprefetch_open(sc)) {
2422 if (start < sc->memlimit && end > sc->membase)
2423 start = sc->memlimit + 1;
2425 if (pcib_is_prefetch_open(sc)) {
2426 if (start < sc->pmemlimit && end > sc->pmembase)
2427 start = sc->pmemlimit + 1;
2432 device_printf(dev, "memory: end (%jx) < start (%jx)\n",
2438 if (!ok && bootverbose)
2440 "%s%srequested unsupported memory range %#jx-%#jx "
2441 "(decoding %#jx-%#jx, %#jx-%#jx)\n",
2442 name, suffix, start, end,
2443 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit,
2444 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit);
2448 device_printf(dev,"%s%srequested memory range "
2449 "0x%jx-0x%jx: good\n",
2450 name, suffix, start, end);
2457 * Bridge is OK decoding this resource, so pass it up.
2459 return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
2465 * If ARI is enabled on this downstream port, translate the function number
2466 * to the non-ARI slot/function. The downstream port will convert it back in
2467 * hardware. If ARI is not enabled slot and func are not modified.
2469 static __inline void
2470 pcib_xlate_ari(device_t pcib, int bus, int *slot, int *func)
2472 struct pcib_softc *sc;
2475 sc = device_get_softc(pcib);
2478 if (sc->flags & PCIB_ENABLE_ARI) {
2480 ("Non-zero slot number with ARI enabled!"));
2481 *slot = PCIE_ARI_SLOT(ari_func);
2482 *func = PCIE_ARI_FUNC(ari_func);
2488 pcib_enable_ari(struct pcib_softc *sc, uint32_t pcie_pos)
2492 ctl2 = pci_read_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, 4);
2493 ctl2 |= PCIEM_CTL2_ARI;
2494 pci_write_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, ctl2, 4);
2496 sc->flags |= PCIB_ENABLE_ARI;
2503 pcib_maxslots(device_t dev)
2505 return (PCI_SLOTMAX);
2509 pcib_ari_maxslots(device_t dev)
2511 struct pcib_softc *sc;
2513 sc = device_get_softc(dev);
2515 if (sc->flags & PCIB_ENABLE_ARI)
2516 return (PCIE_ARI_SLOTMAX);
2518 return (PCI_SLOTMAX);
2522 pcib_ari_maxfuncs(device_t dev)
2524 struct pcib_softc *sc;
2526 sc = device_get_softc(dev);
2528 if (sc->flags & PCIB_ENABLE_ARI)
2529 return (PCIE_ARI_FUNCMAX);
2531 return (PCI_FUNCMAX);
2535 pcib_ari_decode_rid(device_t pcib, uint16_t rid, int *bus, int *slot,
2538 struct pcib_softc *sc;
2540 sc = device_get_softc(pcib);
2542 *bus = PCI_RID2BUS(rid);
2543 if (sc->flags & PCIB_ENABLE_ARI) {
2544 *slot = PCIE_ARI_RID2SLOT(rid);
2545 *func = PCIE_ARI_RID2FUNC(rid);
2547 *slot = PCI_RID2SLOT(rid);
2548 *func = PCI_RID2FUNC(rid);
2553 * Since we are a child of a PCI bus, its parent must support the pcib interface.
2556 pcib_read_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, int width)
2559 struct pcib_softc *sc;
2561 sc = device_get_softc(dev);
2562 if (!pcib_present(sc)) {
2569 return (0xffffffff);
2573 pcib_xlate_ari(dev, b, &s, &f);
2574 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s,
2579 pcib_write_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, int width)
2582 struct pcib_softc *sc;
2584 sc = device_get_softc(dev);
2585 if (!pcib_present(sc))
2588 pcib_xlate_ari(dev, b, &s, &f);
2589 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f,
2594 * Route an interrupt across a PCI bridge.
2597 pcib_route_interrupt(device_t pcib, device_t dev, int pin)
2605 * The PCI standard defines a swizzle of the child-side device/intpin to
2606 * the parent-side intpin as follows.
2608 * device = device on child bus
2609 * child_intpin = intpin on child bus slot (0-3)
2610 * parent_intpin = intpin on parent bus slot (0-3)
2612 * parent_intpin = (device + child_intpin) % 4
2614 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4;
2617 * Our parent is a PCI bus. Its parent must export the pcib interface
2618 * which includes the ability to route interrupts.
2620 bus = device_get_parent(pcib);
2621 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1);
2622 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) {
2623 device_printf(pcib, "slot %d INT%c is routed to irq %d\n",
2624 pci_get_slot(dev), 'A' + pin - 1, intnum);
2629 /* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */
2631 pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs)
2633 struct pcib_softc *sc = device_get_softc(pcib);
2636 if (sc->flags & PCIB_DISABLE_MSI)
2638 bus = device_get_parent(pcib);
2639 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount,
2643 /* Pass request to release MSI/MSI-X messages up to the parent bridge. */
2645 pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs)
2649 bus = device_get_parent(pcib);
2650 return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs));
2653 /* Pass request to alloc an MSI-X message up to the parent bridge. */
2655 pcib_alloc_msix(device_t pcib, device_t dev, int *irq)
2657 struct pcib_softc *sc = device_get_softc(pcib);
2660 if (sc->flags & PCIB_DISABLE_MSIX)
2662 bus = device_get_parent(pcib);
2663 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq));
2666 /* Pass request to release an MSI-X message up to the parent bridge. */
2668 pcib_release_msix(device_t pcib, device_t dev, int irq)
2672 bus = device_get_parent(pcib);
2673 return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq));
2676 /* Pass request to map MSI/MSI-X message up to parent bridge. */
2678 pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
2684 bus = device_get_parent(pcib);
2685 error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data);
2689 pci_ht_map_msi(pcib, *addr);
2693 /* Pass request for device power state up to parent bridge. */
2695 pcib_power_for_sleep(device_t pcib, device_t dev, int *pstate)
2699 bus = device_get_parent(pcib);
2700 return (PCIB_POWER_FOR_SLEEP(bus, dev, pstate));
2704 pcib_ari_enabled(device_t pcib)
2706 struct pcib_softc *sc;
2708 sc = device_get_softc(pcib);
2710 return ((sc->flags & PCIB_ENABLE_ARI) != 0);
2714 pcib_ari_get_id(device_t pcib, device_t dev, enum pci_id_type type,
2717 struct pcib_softc *sc;
2719 uint8_t bus, slot, func;
2721 if (type != PCI_ID_RID) {
2722 bus_dev = device_get_parent(pcib);
2723 return (PCIB_GET_ID(device_get_parent(bus_dev), dev, type, id));
2726 sc = device_get_softc(pcib);
2728 if (sc->flags & PCIB_ENABLE_ARI) {
2729 bus = pci_get_bus(dev);
2730 func = pci_get_function(dev);
2732 *id = (PCI_ARI_RID(bus, func));
2734 bus = pci_get_bus(dev);
2735 slot = pci_get_slot(dev);
2736 func = pci_get_function(dev);
2738 *id = (PCI_RID(bus, slot, func));
2745 * Check that the downstream port (pcib) and the endpoint device (dev) both
2746 * support ARI. If so, enable it and return 0, otherwise return an error.
2749 pcib_try_enable_ari(device_t pcib, device_t dev)
2751 struct pcib_softc *sc;
2758 sc = device_get_softc(pcib);
2761 * ARI is controlled in a register in the PCIe capability structure.
2762 * If the downstream port does not have the PCIe capability structure
2763 * then it does not support ARI.
2765 error = pci_find_cap(pcib, PCIY_EXPRESS, &pcie_pos);
2769 /* Check that the PCIe port advertises ARI support. */
2770 cap2 = pci_read_config(pcib, pcie_pos + PCIER_DEVICE_CAP2, 4);
2771 if (!(cap2 & PCIEM_CAP2_ARI))
2775 * Check that the endpoint device advertises ARI support via the ARI
2776 * extended capability structure.
2778 error = pci_find_extcap(dev, PCIZ_ARI, &ari_cap_off);
2783 * Finally, check that the endpoint device supports the same version
2784 * of ARI that we do.
2786 ari_ver = pci_read_config(dev, ari_cap_off, 4);
2787 if (PCI_EXTCAP_VER(ari_ver) != PCIB_SUPPORTED_ARI_VER) {
2790 "Unsupported version of ARI (%d) detected\n",
2791 PCI_EXTCAP_VER(ari_ver));
2796 pcib_enable_ari(sc, pcie_pos);