2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000 BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
35 * PCI:PCI bridge support.
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
43 #include <machine/bus.h>
45 #include <sys/sysctl.h>
47 #include <machine/resource.h>
49 #include <dev/pci/pcivar.h>
50 #include <dev/pci/pcireg.h>
51 #include <dev/pci/pcib_private.h>
55 static int pcib_probe(device_t dev);
57 static device_method_t pcib_methods[] = {
58 /* Device interface */
59 DEVMETHOD(device_probe, pcib_probe),
60 DEVMETHOD(device_attach, pcib_attach),
61 DEVMETHOD(device_detach, bus_generic_detach),
62 DEVMETHOD(device_shutdown, bus_generic_shutdown),
63 DEVMETHOD(device_suspend, bus_generic_suspend),
64 DEVMETHOD(device_resume, bus_generic_resume),
67 DEVMETHOD(bus_print_child, bus_generic_print_child),
68 DEVMETHOD(bus_read_ivar, pcib_read_ivar),
69 DEVMETHOD(bus_write_ivar, pcib_write_ivar),
70 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
71 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
72 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
73 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
74 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
75 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
78 DEVMETHOD(pcib_maxslots, pcib_maxslots),
79 DEVMETHOD(pcib_read_config, pcib_read_config),
80 DEVMETHOD(pcib_write_config, pcib_write_config),
81 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
82 DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi),
83 DEVMETHOD(pcib_release_msi, pcib_release_msi),
84 DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix),
85 DEVMETHOD(pcib_release_msix, pcib_release_msix),
86 DEVMETHOD(pcib_map_msi, pcib_map_msi),
91 static devclass_t pcib_devclass;
93 DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc));
94 DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0);
97 * Is the prefetch window open (eg, can we allocate memory in it?)
100 pcib_is_prefetch_open(struct pcib_softc *sc)
102 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit);
106 * Is the nonprefetch window open (eg, can we allocate memory in it?)
109 pcib_is_nonprefetch_open(struct pcib_softc *sc)
111 return (sc->membase > 0 && sc->membase < sc->memlimit);
115 * Is the io window open (eg, can we allocate ports in it?)
118 pcib_is_io_open(struct pcib_softc *sc)
120 return (sc->iobase > 0 && sc->iobase < sc->iolimit);
124 * Generic device interface
127 pcib_probe(device_t dev)
129 if ((pci_get_class(dev) == PCIC_BRIDGE) &&
130 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) {
131 device_set_desc(dev, "PCI-PCI bridge");
138 pcib_attach_common(device_t dev)
140 struct pcib_softc *sc;
143 sc = device_get_softc(dev);
147 * Get current bridge configuration.
149 sc->command = pci_read_config(dev, PCIR_COMMAND, 1);
150 sc->domain = pci_get_domain(dev);
151 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1);
152 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1);
153 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2);
154 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
155 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1);
158 * Determine current I/O decode.
160 if (sc->command & PCIM_CMD_PORTEN) {
161 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1);
162 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
163 sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2),
164 pci_read_config(dev, PCIR_IOBASEL_1, 1));
166 sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1));
169 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1);
170 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
171 sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2),
172 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
174 sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1));
179 * Determine current memory decode.
181 if (sc->command & PCIM_CMD_MEMEN) {
182 sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2));
183 sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
184 sc->pmembase = PCI_PPBMEMBASE(pci_read_config(dev, PCIR_PMBASEH_1, 4),
185 pci_read_config(dev, PCIR_PMBASEL_1, 2));
186 sc->pmemlimit = PCI_PPBMEMLIMIT(pci_read_config(dev, PCIR_PMLIMITH_1, 4),
187 pci_read_config(dev, PCIR_PMLIMITL_1, 2));
193 switch (pci_get_devid(dev)) {
194 case 0x12258086: /* Intel 82454KX/GX (Orion) */
198 supbus = pci_read_config(dev, 0x41, 1);
199 if (supbus != 0xff) {
200 sc->secbus = supbus + 1;
201 sc->subbus = supbus + 1;
207 * The i82380FB mobile docking controller is a PCI-PCI bridge,
208 * and it is a subtractive bridge. However, the ProgIf is wrong
209 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't
210 * happen. There's also a Toshiba bridge that behaves this
213 case 0x124b8086: /* Intel 82380FB Mobile */
214 case 0x060513d7: /* Toshiba ???? */
215 sc->flags |= PCIB_SUBTRACTIVE;
218 /* Compaq R3000 BIOS sets wrong subordinate bus number. */
223 if ((cp = getenv("smbios.planar.maker")) == NULL)
225 if (strncmp(cp, "Compal", 6) != 0) {
230 if ((cp = getenv("smbios.planar.product")) == NULL)
232 if (strncmp(cp, "08A0", 4) != 0) {
237 if (sc->subbus < 0xa) {
238 pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1);
239 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1);
245 if (pci_msi_device_blacklisted(dev))
246 sc->flags |= PCIB_DISABLE_MSI;
249 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges,
250 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM,
251 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese.
252 * This means they act as if they were subtractively decoding
253 * bridges and pass all transactions. Mark them and real ProgIf 1
254 * parts as subtractive.
256 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 ||
257 pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_BRIDGE_PCI_SUBTRACTIVE)
258 sc->flags |= PCIB_SUBTRACTIVE;
261 device_printf(dev, " domain %d\n", sc->domain);
262 device_printf(dev, " secondary bus %d\n", sc->secbus);
263 device_printf(dev, " subordinate bus %d\n", sc->subbus);
264 device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit);
265 if (pcib_is_nonprefetch_open(sc))
266 device_printf(dev, " memory decode 0x%jx-0x%jx\n",
267 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit);
268 if (pcib_is_prefetch_open(sc))
269 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n",
270 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit);
272 device_printf(dev, " no prefetched decode\n");
273 if (sc->flags & PCIB_SUBTRACTIVE)
274 device_printf(dev, " Subtractively decoded bridge.\n");
278 * XXX If the secondary bus number is zero, we should assign a bus number
279 * since the BIOS hasn't, then initialise the bridge.
283 * XXX If the subordinate bus number is less than the secondary bus number,
284 * we should pick a better value. One sensible alternative would be to
285 * pick 255; the only tradeoff here is that configuration transactions
286 * would be more widely routed than absolutely necessary.
291 pcib_attach(device_t dev)
293 struct pcib_softc *sc;
296 pcib_attach_common(dev);
297 sc = device_get_softc(dev);
298 if (sc->secbus != 0) {
299 child = device_add_child(dev, "pci", sc->secbus);
301 return(bus_generic_attach(dev));
304 /* no secondary bus; we should have fixed this */
309 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
311 struct pcib_softc *sc = device_get_softc(dev);
314 case PCIB_IVAR_DOMAIN:
315 *result = sc->domain;
318 *result = sc->secbus;
325 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
327 struct pcib_softc *sc = device_get_softc(dev);
330 case PCIB_IVAR_DOMAIN:
340 * We have to trap resource allocation requests and ensure that the bridge
341 * is set up to, or capable of handling them.
344 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
345 u_long start, u_long end, u_long count, u_int flags)
347 struct pcib_softc *sc = device_get_softc(dev);
348 const char *name, *suffix;
352 * Fail the allocation for this range if it's not supported.
354 name = device_get_nameunit(child);
363 if (!pcib_is_io_open(sc))
365 ok = (start >= sc->iobase && end <= sc->iolimit);
368 * Make sure we allow access to VGA I/O addresses when the
369 * bridge has the "VGA Enable" bit set.
371 if (!ok && pci_is_vga_ioport_range(start, end))
372 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
374 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
376 if (start < sc->iobase)
378 if (end > sc->iolimit)
386 if (start < sc->iobase && end > sc->iolimit) {
393 device_printf(dev, "ioport: end (%lx) < start (%lx)\n",
400 device_printf(dev, "%s%srequested unsupported I/O "
401 "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n",
402 name, suffix, start, end, sc->iobase, sc->iolimit);
407 "%s%srequested I/O range 0x%lx-0x%lx: in range\n",
408 name, suffix, start, end);
413 if (pcib_is_nonprefetch_open(sc))
414 ok = ok || (start >= sc->membase && end <= sc->memlimit);
415 if (pcib_is_prefetch_open(sc))
416 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit);
419 * Make sure we allow access to VGA memory addresses when the
420 * bridge has the "VGA Enable" bit set.
422 if (!ok && pci_is_vga_memory_range(start, end))
423 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
425 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
428 if (flags & RF_PREFETCHABLE) {
429 if (pcib_is_prefetch_open(sc)) {
430 if (start < sc->pmembase)
431 start = sc->pmembase;
432 if (end > sc->pmemlimit)
437 } else { /* non-prefetchable */
438 if (pcib_is_nonprefetch_open(sc)) {
439 if (start < sc->membase)
441 if (end > sc->memlimit)
449 ok = 1; /* subtractive bridge: always ok */
451 if (pcib_is_nonprefetch_open(sc)) {
452 if (start < sc->membase && end > sc->memlimit) {
457 if (pcib_is_prefetch_open(sc)) {
458 if (start < sc->pmembase && end > sc->pmemlimit) {
459 start = sc->pmembase;
466 device_printf(dev, "memory: end (%lx) < start (%lx)\n",
472 if (!ok && bootverbose)
474 "%s%srequested unsupported memory range %#lx-%#lx "
475 "(decoding %#jx-%#jx, %#jx-%#jx)\n",
476 name, suffix, start, end,
477 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit,
478 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit);
482 device_printf(dev,"%s%srequested memory range "
483 "0x%lx-0x%lx: good\n",
484 name, suffix, start, end);
491 * Bridge is OK decoding this resource, so pass it up.
493 return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
501 pcib_maxslots(device_t dev)
507 * Since we are a child of a PCI bus, its parent must support the pcib interface.
510 pcib_read_config(device_t dev, int b, int s, int f, int reg, int width)
512 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width));
516 pcib_write_config(device_t dev, int b, int s, int f, int reg, uint32_t val, int width)
518 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width);
522 * Route an interrupt across a PCI bridge.
525 pcib_route_interrupt(device_t pcib, device_t dev, int pin)
533 * The PCI standard defines a swizzle of the child-side device/intpin to
534 * the parent-side intpin as follows.
536 * device = device on child bus
537 * child_intpin = intpin on child bus slot (0-3)
538 * parent_intpin = intpin on parent bus slot (0-3)
540 * parent_intpin = (device + child_intpin) % 4
542 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4;
545 * Our parent is a PCI bus. Its parent must export the pcib interface
546 * which includes the ability to route interrupts.
548 bus = device_get_parent(pcib);
549 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1);
550 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) {
551 device_printf(pcib, "slot %d INT%c is routed to irq %d\n",
552 pci_get_slot(dev), 'A' + pin - 1, intnum);
557 /* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */
559 pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs)
561 struct pcib_softc *sc = device_get_softc(pcib);
564 if (sc->flags & PCIB_DISABLE_MSI)
566 bus = device_get_parent(pcib);
567 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount,
571 /* Pass request to release MSI/MSI-X messages up to the parent bridge. */
573 pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs)
577 bus = device_get_parent(pcib);
578 return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs));
581 /* Pass request to alloc an MSI-X message up to the parent bridge. */
583 pcib_alloc_msix(device_t pcib, device_t dev, int *irq)
585 struct pcib_softc *sc = device_get_softc(pcib);
588 if (sc->flags & PCIB_DISABLE_MSI)
590 bus = device_get_parent(pcib);
591 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq));
594 /* Pass request to release an MSI-X message up to the parent bridge. */
596 pcib_release_msix(device_t pcib, device_t dev, int irq)
600 bus = device_get_parent(pcib);
601 return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq));
604 /* Pass request to map MSI/MSI-X message up to parent bridge. */
606 pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
611 bus = device_get_parent(pcib);
612 return (PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data));
616 * Try to read the bus number of a host-PCI bridge using appropriate config
620 host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func,
625 id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4);
626 if (id == 0xffffffff)
632 /* XXX This is a guess */
633 /* *busnum = read_config(bus, slot, func, 0x41, 1); */
637 /* Intel 82454KX/GX (Orion) */
638 *busnum = read_config(bus, slot, func, 0x4a, 1);
642 * For the 450nx chipset, there is a whole bundle of
643 * things pretending to be host bridges. The MIOC will
644 * be seen first and isn't really a pci bridge (the
645 * actual busses are attached to the PXB's). We need to
646 * read the registers of the MIOC to figure out the
647 * bus numbers for the PXB channels.
649 * Since the MIOC doesn't have a pci bus attached, we
650 * pretend it wasn't there.
656 /* Intel 82454NX PXB#0, Bus#A */
657 *busnum = read_config(bus, 0x10, func, 0xd0, 1);
660 /* Intel 82454NX PXB#0, Bus#B */
661 *busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1;
664 /* Intel 82454NX PXB#1, Bus#A */
665 *busnum = read_config(bus, 0x10, func, 0xd3, 1);
668 /* Intel 82454NX PXB#1, Bus#B */
669 *busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1;
674 /* ServerWorks -- vendor 0x1166 */
686 *busnum = read_config(bus, slot, func, 0x44, 1);
689 /* Compaq/HP -- vendor 0x0e11 */
691 *busnum = read_config(bus, slot, func, 0xc8, 1);
694 /* Don't know how to read bus number. */