2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000 BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
35 * PCI:PCI bridge support.
40 #include <sys/param.h>
42 #include <sys/kernel.h>
43 #include <sys/malloc.h>
44 #include <sys/module.h>
46 #include <sys/sysctl.h>
47 #include <sys/systm.h>
48 #include <sys/taskqueue.h>
50 #include <dev/pci/pcivar.h>
51 #include <dev/pci/pcireg.h>
52 #include <dev/pci/pci_private.h>
53 #include <dev/pci/pcib_private.h>
57 static int pcib_probe(device_t dev);
58 static int pcib_suspend(device_t dev);
59 static int pcib_resume(device_t dev);
60 static int pcib_power_for_sleep(device_t pcib, device_t dev,
62 static int pcib_ari_get_id(device_t pcib, device_t dev,
63 enum pci_id_type type, uintptr_t *id);
64 static uint32_t pcib_read_config(device_t dev, u_int b, u_int s,
65 u_int f, u_int reg, int width);
66 static void pcib_write_config(device_t dev, u_int b, u_int s,
67 u_int f, u_int reg, uint32_t val, int width);
68 static int pcib_ari_maxslots(device_t dev);
69 static int pcib_ari_maxfuncs(device_t dev);
70 static int pcib_try_enable_ari(device_t pcib, device_t dev);
71 static int pcib_ari_enabled(device_t pcib);
72 static void pcib_ari_decode_rid(device_t pcib, uint16_t rid,
73 int *bus, int *slot, int *func);
75 static void pcib_pcie_ab_timeout(void *arg);
76 static void pcib_pcie_cc_timeout(void *arg);
77 static void pcib_pcie_dll_timeout(void *arg);
79 static int pcib_request_feature(device_t pcib, device_t dev,
80 enum pci_feature feature);
82 static device_method_t pcib_methods[] = {
83 /* Device interface */
84 DEVMETHOD(device_probe, pcib_probe),
85 DEVMETHOD(device_attach, pcib_attach),
86 DEVMETHOD(device_detach, pcib_detach),
87 DEVMETHOD(device_shutdown, bus_generic_shutdown),
88 DEVMETHOD(device_suspend, pcib_suspend),
89 DEVMETHOD(device_resume, pcib_resume),
92 DEVMETHOD(bus_child_present, pcib_child_present),
93 DEVMETHOD(bus_read_ivar, pcib_read_ivar),
94 DEVMETHOD(bus_write_ivar, pcib_write_ivar),
95 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
97 DEVMETHOD(bus_adjust_resource, pcib_adjust_resource),
98 DEVMETHOD(bus_release_resource, pcib_release_resource),
100 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
101 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
103 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
104 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
105 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
106 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
109 DEVMETHOD(pcib_maxslots, pcib_ari_maxslots),
110 DEVMETHOD(pcib_maxfuncs, pcib_ari_maxfuncs),
111 DEVMETHOD(pcib_read_config, pcib_read_config),
112 DEVMETHOD(pcib_write_config, pcib_write_config),
113 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
114 DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi),
115 DEVMETHOD(pcib_release_msi, pcib_release_msi),
116 DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix),
117 DEVMETHOD(pcib_release_msix, pcib_release_msix),
118 DEVMETHOD(pcib_map_msi, pcib_map_msi),
119 DEVMETHOD(pcib_power_for_sleep, pcib_power_for_sleep),
120 DEVMETHOD(pcib_get_id, pcib_ari_get_id),
121 DEVMETHOD(pcib_try_enable_ari, pcib_try_enable_ari),
122 DEVMETHOD(pcib_ari_enabled, pcib_ari_enabled),
123 DEVMETHOD(pcib_decode_rid, pcib_ari_decode_rid),
124 DEVMETHOD(pcib_request_feature, pcib_request_feature),
129 static devclass_t pcib_devclass;
131 DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc));
132 DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, NULL, NULL);
134 #if defined(NEW_PCIB) || defined(PCI_HP)
135 SYSCTL_DECL(_hw_pci);
139 static int pci_clear_pcib;
140 SYSCTL_INT(_hw_pci, OID_AUTO, clear_pcib, CTLFLAG_RDTUN, &pci_clear_pcib, 0,
141 "Clear firmware-assigned resources for PCI-PCI bridge I/O windows.");
144 * Is a resource from a child device sub-allocated from one of our
148 pcib_is_resource_managed(struct pcib_softc *sc, int type, struct resource *r)
154 return (rman_is_region_manager(r, &sc->bus.rman));
157 return (rman_is_region_manager(r, &sc->io.rman));
159 /* Prefetchable resources may live in either memory rman. */
160 if (rman_get_flags(r) & RF_PREFETCHABLE &&
161 rman_is_region_manager(r, &sc->pmem.rman))
163 return (rman_is_region_manager(r, &sc->mem.rman));
169 pcib_is_window_open(struct pcib_window *pw)
172 return (pw->valid && pw->base < pw->limit);
176 * XXX: If RF_ACTIVE did not also imply allocating a bus space tag and
177 * handle for the resource, we could pass RF_ACTIVE up to the PCI bus
178 * when allocating the resource windows and rely on the PCI bus driver
182 pcib_activate_window(struct pcib_softc *sc, int type)
185 PCI_ENABLE_IO(device_get_parent(sc->dev), sc->dev, type);
189 pcib_write_windows(struct pcib_softc *sc, int mask)
195 if (sc->io.valid && mask & WIN_IO) {
196 val = pci_read_config(dev, PCIR_IOBASEL_1, 1);
197 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
198 pci_write_config(dev, PCIR_IOBASEH_1,
199 sc->io.base >> 16, 2);
200 pci_write_config(dev, PCIR_IOLIMITH_1,
201 sc->io.limit >> 16, 2);
203 pci_write_config(dev, PCIR_IOBASEL_1, sc->io.base >> 8, 1);
204 pci_write_config(dev, PCIR_IOLIMITL_1, sc->io.limit >> 8, 1);
207 if (mask & WIN_MEM) {
208 pci_write_config(dev, PCIR_MEMBASE_1, sc->mem.base >> 16, 2);
209 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->mem.limit >> 16, 2);
212 if (sc->pmem.valid && mask & WIN_PMEM) {
213 val = pci_read_config(dev, PCIR_PMBASEL_1, 2);
214 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) {
215 pci_write_config(dev, PCIR_PMBASEH_1,
216 sc->pmem.base >> 32, 4);
217 pci_write_config(dev, PCIR_PMLIMITH_1,
218 sc->pmem.limit >> 32, 4);
220 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmem.base >> 16, 2);
221 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmem.limit >> 16, 2);
226 * This is used to reject I/O port allocations that conflict with an
230 pcib_is_isa_range(struct pcib_softc *sc, rman_res_t start, rman_res_t end,
233 rman_res_t next_alias;
235 if (!(sc->bridgectl & PCIB_BCR_ISA_ENABLE))
238 /* Only check fixed ranges for overlap. */
239 if (start + count - 1 != end)
242 /* ISA aliases are only in the lower 64KB of I/O space. */
246 /* Check for overlap with 0x000 - 0x0ff as a special case. */
251 * If the start address is an alias, the range is an alias.
252 * Otherwise, compute the start of the next alias range and
253 * check if it is before the end of the candidate range.
255 if ((start & 0x300) != 0)
257 next_alias = (start & ~0x3fful) | 0x100;
258 if (next_alias <= end)
264 device_printf(sc->dev,
265 "I/O range %#jx-%#jx overlaps with an ISA alias\n", start,
271 pcib_add_window_resources(struct pcib_window *w, struct resource **res,
274 struct resource **newarray;
277 newarray = malloc(sizeof(struct resource *) * (w->count + count),
280 bcopy(w->res, newarray, sizeof(struct resource *) * w->count);
281 bcopy(res, newarray + w->count, sizeof(struct resource *) * count);
282 free(w->res, M_DEVBUF);
286 for (i = 0; i < count; i++) {
287 error = rman_manage_region(&w->rman, rman_get_start(res[i]),
288 rman_get_end(res[i]));
290 panic("Failed to add resource to rman");
294 typedef void (nonisa_callback)(rman_res_t start, rman_res_t end, void *arg);
297 pcib_walk_nonisa_ranges(rman_res_t start, rman_res_t end, nonisa_callback *cb,
303 * If start is within an ISA alias range, move up to the start
304 * of the next non-alias range. As a special case, addresses
305 * in the range 0x000 - 0x0ff should also be skipped since
306 * those are used for various system I/O devices in ISA
309 if (start <= 65535) {
310 if (start < 0x100 || (start & 0x300) != 0) {
316 /* ISA aliases are only in the lower 64KB of I/O space. */
317 while (start <= MIN(end, 65535)) {
318 next_end = MIN(start | 0xff, end);
319 cb(start, next_end, arg);
328 count_ranges(rman_res_t start, rman_res_t end, void *arg)
337 struct resource **res;
338 struct pcib_softc *sc;
343 alloc_ranges(rman_res_t start, rman_res_t end, void *arg)
345 struct alloc_state *as;
346 struct pcib_window *w;
356 device_printf(as->sc->dev,
357 "allocating non-ISA range %#jx-%#jx\n", start, end);
358 as->res[as->count] = bus_alloc_resource(as->sc->dev, SYS_RES_IOPORT,
359 &rid, start, end, end - start + 1, 0);
360 if (as->res[as->count] == NULL)
367 pcib_alloc_nonisa_ranges(struct pcib_softc *sc, rman_res_t start, rman_res_t end)
369 struct alloc_state as;
372 /* First, see how many ranges we need. */
374 pcib_walk_nonisa_ranges(start, end, count_ranges, &new_count);
376 /* Second, allocate the ranges. */
377 as.res = malloc(sizeof(struct resource *) * new_count, M_DEVBUF,
382 pcib_walk_nonisa_ranges(start, end, alloc_ranges, &as);
384 for (i = 0; i < as.count; i++)
385 bus_release_resource(sc->dev, SYS_RES_IOPORT,
386 sc->io.reg, as.res[i]);
387 free(as.res, M_DEVBUF);
390 KASSERT(as.count == new_count, ("%s: count mismatch", __func__));
392 /* Third, add the ranges to the window. */
393 pcib_add_window_resources(&sc->io, as.res, as.count);
394 free(as.res, M_DEVBUF);
399 pcib_alloc_window(struct pcib_softc *sc, struct pcib_window *w, int type,
400 int flags, pci_addr_t max_address)
402 struct resource *res;
406 if (max_address != (rman_res_t)max_address)
408 w->rman.rm_start = 0;
409 w->rman.rm_end = max_address;
410 w->rman.rm_type = RMAN_ARRAY;
411 snprintf(buf, sizeof(buf), "%s %s window",
412 device_get_nameunit(sc->dev), w->name);
413 w->rman.rm_descr = strdup(buf, M_DEVBUF);
414 error = rman_init(&w->rman);
416 panic("Failed to initialize %s %s rman",
417 device_get_nameunit(sc->dev), w->name);
419 if (!pcib_is_window_open(w))
422 if (w->base > max_address || w->limit > max_address) {
423 device_printf(sc->dev,
424 "initial %s window has too many bits, ignoring\n", w->name);
427 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE)
428 (void)pcib_alloc_nonisa_ranges(sc, w->base, w->limit);
431 res = bus_alloc_resource(sc->dev, type, &rid, w->base, w->limit,
432 w->limit - w->base + 1, flags);
434 pcib_add_window_resources(w, &res, 1);
436 if (w->res == NULL) {
437 device_printf(sc->dev,
438 "failed to allocate initial %s window: %#jx-%#jx\n",
439 w->name, (uintmax_t)w->base, (uintmax_t)w->limit);
440 w->base = max_address;
442 pcib_write_windows(sc, w->mask);
445 pcib_activate_window(sc, type);
449 * Initialize I/O windows.
452 pcib_probe_windows(struct pcib_softc *sc)
460 if (pci_clear_pcib) {
461 pcib_bridge_init(dev);
464 /* Determine if the I/O port window is implemented. */
465 val = pci_read_config(dev, PCIR_IOBASEL_1, 1);
468 * If 'val' is zero, then only 16-bits of I/O space
471 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1);
472 if (pci_read_config(dev, PCIR_IOBASEL_1, 1) != 0) {
474 pci_write_config(dev, PCIR_IOBASEL_1, 0, 1);
479 /* Read the existing I/O port window. */
481 sc->io.reg = PCIR_IOBASEL_1;
483 sc->io.mask = WIN_IO;
484 sc->io.name = "I/O port";
485 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
486 sc->io.base = PCI_PPBIOBASE(
487 pci_read_config(dev, PCIR_IOBASEH_1, 2), val);
488 sc->io.limit = PCI_PPBIOLIMIT(
489 pci_read_config(dev, PCIR_IOLIMITH_1, 2),
490 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
493 sc->io.base = PCI_PPBIOBASE(0, val);
494 sc->io.limit = PCI_PPBIOLIMIT(0,
495 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
498 pcib_alloc_window(sc, &sc->io, SYS_RES_IOPORT, 0, max);
501 /* Read the existing memory window. */
503 sc->mem.reg = PCIR_MEMBASE_1;
505 sc->mem.mask = WIN_MEM;
506 sc->mem.name = "memory";
507 sc->mem.base = PCI_PPBMEMBASE(0,
508 pci_read_config(dev, PCIR_MEMBASE_1, 2));
509 sc->mem.limit = PCI_PPBMEMLIMIT(0,
510 pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
511 pcib_alloc_window(sc, &sc->mem, SYS_RES_MEMORY, 0, 0xffffffff);
513 /* Determine if the prefetchable memory window is implemented. */
514 val = pci_read_config(dev, PCIR_PMBASEL_1, 2);
517 * If 'val' is zero, then only 32-bits of memory space
520 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2);
521 if (pci_read_config(dev, PCIR_PMBASEL_1, 2) != 0) {
523 pci_write_config(dev, PCIR_PMBASEL_1, 0, 2);
528 /* Read the existing prefetchable memory window. */
529 if (sc->pmem.valid) {
530 sc->pmem.reg = PCIR_PMBASEL_1;
532 sc->pmem.mask = WIN_PMEM;
533 sc->pmem.name = "prefetch";
534 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) {
535 sc->pmem.base = PCI_PPBMEMBASE(
536 pci_read_config(dev, PCIR_PMBASEH_1, 4), val);
537 sc->pmem.limit = PCI_PPBMEMLIMIT(
538 pci_read_config(dev, PCIR_PMLIMITH_1, 4),
539 pci_read_config(dev, PCIR_PMLIMITL_1, 2));
540 max = 0xffffffffffffffff;
542 sc->pmem.base = PCI_PPBMEMBASE(0, val);
543 sc->pmem.limit = PCI_PPBMEMLIMIT(0,
544 pci_read_config(dev, PCIR_PMLIMITL_1, 2));
547 pcib_alloc_window(sc, &sc->pmem, SYS_RES_MEMORY,
548 RF_PREFETCHABLE, max);
553 pcib_release_window(struct pcib_softc *sc, struct pcib_window *w, int type)
562 error = rman_fini(&w->rman);
564 device_printf(dev, "failed to release %s rman\n", w->name);
567 free(__DECONST(char *, w->rman.rm_descr), M_DEVBUF);
569 for (i = 0; i < w->count; i++) {
570 error = bus_free_resource(dev, type, w->res[i]);
573 "failed to release %s resource: %d\n", w->name,
576 free(w->res, M_DEVBUF);
580 pcib_free_windows(struct pcib_softc *sc)
583 pcib_release_window(sc, &sc->pmem, SYS_RES_MEMORY);
584 pcib_release_window(sc, &sc->mem, SYS_RES_MEMORY);
585 pcib_release_window(sc, &sc->io, SYS_RES_IOPORT);
590 * Allocate a suitable secondary bus for this bridge if needed and
591 * initialize the resource manager for the secondary bus range. Note
592 * that the minimum count is a desired value and this may allocate a
596 pcib_setup_secbus(device_t dev, struct pcib_secbus *bus, int min_count)
599 int error, rid, sec_reg;
601 switch (pci_read_config(dev, PCIR_HDRTYPE, 1) & PCIM_HDRTYPE) {
602 case PCIM_HDRTYPE_BRIDGE:
603 sec_reg = PCIR_SECBUS_1;
604 bus->sub_reg = PCIR_SUBBUS_1;
606 case PCIM_HDRTYPE_CARDBUS:
607 sec_reg = PCIR_SECBUS_2;
608 bus->sub_reg = PCIR_SUBBUS_2;
611 panic("not a PCI bridge");
613 bus->sec = pci_read_config(dev, sec_reg, 1);
614 bus->sub = pci_read_config(dev, bus->sub_reg, 1);
616 bus->rman.rm_start = 0;
617 bus->rman.rm_end = PCI_BUSMAX;
618 bus->rman.rm_type = RMAN_ARRAY;
619 snprintf(buf, sizeof(buf), "%s bus numbers", device_get_nameunit(dev));
620 bus->rman.rm_descr = strdup(buf, M_DEVBUF);
621 error = rman_init(&bus->rman);
623 panic("Failed to initialize %s bus number rman",
624 device_get_nameunit(dev));
627 * Allocate a bus range. This will return an existing bus range
628 * if one exists, or a new bus range if one does not.
631 bus->res = bus_alloc_resource_anywhere(dev, PCI_RES_BUS, &rid,
633 if (bus->res == NULL) {
635 * Fall back to just allocating a range of a single bus
638 bus->res = bus_alloc_resource_anywhere(dev, PCI_RES_BUS, &rid,
640 } else if (rman_get_size(bus->res) < min_count)
642 * Attempt to grow the existing range to satisfy the
643 * minimum desired count.
645 (void)bus_adjust_resource(dev, PCI_RES_BUS, bus->res,
646 rman_get_start(bus->res), rman_get_start(bus->res) +
650 * Add the initial resource to the rman.
652 if (bus->res != NULL) {
653 error = rman_manage_region(&bus->rman, rman_get_start(bus->res),
654 rman_get_end(bus->res));
656 panic("Failed to add resource to rman");
657 bus->sec = rman_get_start(bus->res);
658 bus->sub = rman_get_end(bus->res);
663 pcib_free_secbus(device_t dev, struct pcib_secbus *bus)
667 error = rman_fini(&bus->rman);
669 device_printf(dev, "failed to release bus number rman\n");
672 free(__DECONST(char *, bus->rman.rm_descr), M_DEVBUF);
674 error = bus_free_resource(dev, PCI_RES_BUS, bus->res);
677 "failed to release bus numbers resource: %d\n", error);
680 static struct resource *
681 pcib_suballoc_bus(struct pcib_secbus *bus, device_t child, int *rid,
682 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
684 struct resource *res;
686 res = rman_reserve_resource(&bus->rman, start, end, count, flags,
692 device_printf(bus->dev,
693 "allocated bus range (%ju-%ju) for rid %d of %s\n",
694 rman_get_start(res), rman_get_end(res), *rid,
695 pcib_child_name(child));
696 rman_set_rid(res, *rid);
701 * Attempt to grow the secondary bus range. This is much simpler than
702 * for I/O windows as the range can only be grown by increasing
706 pcib_grow_subbus(struct pcib_secbus *bus, rman_res_t new_end)
711 old_end = rman_get_end(bus->res);
712 KASSERT(new_end > old_end, ("attempt to shrink subbus"));
713 error = bus_adjust_resource(bus->dev, PCI_RES_BUS, bus->res,
714 rman_get_start(bus->res), new_end);
718 device_printf(bus->dev, "grew bus range to %ju-%ju\n",
719 rman_get_start(bus->res), rman_get_end(bus->res));
720 error = rman_manage_region(&bus->rman, old_end + 1,
721 rman_get_end(bus->res));
723 panic("Failed to add resource to rman");
724 bus->sub = rman_get_end(bus->res);
725 pci_write_config(bus->dev, bus->sub_reg, bus->sub, 1);
730 pcib_alloc_subbus(struct pcib_secbus *bus, device_t child, int *rid,
731 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
733 struct resource *res;
734 rman_res_t start_free, end_free, new_end;
737 * First, see if the request can be satisified by the existing
740 res = pcib_suballoc_bus(bus, child, rid, start, end, count, flags);
745 * Figure out a range to grow the bus range. First, find the
746 * first bus number after the last allocated bus in the rman and
747 * enforce that as a minimum starting point for the range.
749 if (rman_last_free_region(&bus->rman, &start_free, &end_free) != 0 ||
750 end_free != bus->sub)
751 start_free = bus->sub + 1;
752 if (start_free < start)
754 new_end = start_free + count - 1;
757 * See if this new range would satisfy the request if it
763 /* Finally, attempt to grow the existing resource. */
765 device_printf(bus->dev,
766 "attempting to grow bus range for %ju buses\n", count);
767 printf("\tback candidate range: %ju-%ju\n", start_free,
770 if (pcib_grow_subbus(bus, new_end) == 0)
771 return (pcib_suballoc_bus(bus, child, rid, start, end, count,
780 * Is the prefetch window open (eg, can we allocate memory in it?)
783 pcib_is_prefetch_open(struct pcib_softc *sc)
785 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit);
789 * Is the nonprefetch window open (eg, can we allocate memory in it?)
792 pcib_is_nonprefetch_open(struct pcib_softc *sc)
794 return (sc->membase > 0 && sc->membase < sc->memlimit);
798 * Is the io window open (eg, can we allocate ports in it?)
801 pcib_is_io_open(struct pcib_softc *sc)
803 return (sc->iobase > 0 && sc->iobase < sc->iolimit);
807 * Get current I/O decode.
810 pcib_get_io_decode(struct pcib_softc *sc)
817 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1);
818 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32)
819 sc->iobase = PCI_PPBIOBASE(
820 pci_read_config(dev, PCIR_IOBASEH_1, 2), iolow);
822 sc->iobase = PCI_PPBIOBASE(0, iolow);
824 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1);
825 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32)
826 sc->iolimit = PCI_PPBIOLIMIT(
827 pci_read_config(dev, PCIR_IOLIMITH_1, 2), iolow);
829 sc->iolimit = PCI_PPBIOLIMIT(0, iolow);
833 * Get current memory decode.
836 pcib_get_mem_decode(struct pcib_softc *sc)
843 sc->membase = PCI_PPBMEMBASE(0,
844 pci_read_config(dev, PCIR_MEMBASE_1, 2));
845 sc->memlimit = PCI_PPBMEMLIMIT(0,
846 pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
848 pmemlow = pci_read_config(dev, PCIR_PMBASEL_1, 2);
849 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64)
850 sc->pmembase = PCI_PPBMEMBASE(
851 pci_read_config(dev, PCIR_PMBASEH_1, 4), pmemlow);
853 sc->pmembase = PCI_PPBMEMBASE(0, pmemlow);
855 pmemlow = pci_read_config(dev, PCIR_PMLIMITL_1, 2);
856 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64)
857 sc->pmemlimit = PCI_PPBMEMLIMIT(
858 pci_read_config(dev, PCIR_PMLIMITH_1, 4), pmemlow);
860 sc->pmemlimit = PCI_PPBMEMLIMIT(0, pmemlow);
864 * Restore previous I/O decode.
867 pcib_set_io_decode(struct pcib_softc *sc)
874 iohi = sc->iobase >> 16;
876 pci_write_config(dev, PCIR_IOBASEH_1, iohi, 2);
877 pci_write_config(dev, PCIR_IOBASEL_1, sc->iobase >> 8, 1);
879 iohi = sc->iolimit >> 16;
881 pci_write_config(dev, PCIR_IOLIMITH_1, iohi, 2);
882 pci_write_config(dev, PCIR_IOLIMITL_1, sc->iolimit >> 8, 1);
886 * Restore previous memory decode.
889 pcib_set_mem_decode(struct pcib_softc *sc)
896 pci_write_config(dev, PCIR_MEMBASE_1, sc->membase >> 16, 2);
897 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->memlimit >> 16, 2);
899 pmemhi = sc->pmembase >> 32;
901 pci_write_config(dev, PCIR_PMBASEH_1, pmemhi, 4);
902 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmembase >> 16, 2);
904 pmemhi = sc->pmemlimit >> 32;
906 pci_write_config(dev, PCIR_PMLIMITH_1, pmemhi, 4);
907 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmemlimit >> 16, 2);
913 * PCI-express HotPlug support.
915 static int pci_enable_pcie_hp = 1;
916 SYSCTL_INT(_hw_pci, OID_AUTO, enable_pcie_hp, CTLFLAG_RDTUN,
917 &pci_enable_pcie_hp, 0,
918 "Enable support for native PCI-express HotPlug.");
921 pcib_probe_hotplug(struct pcib_softc *sc)
925 uint16_t link_sta, slot_sta;
927 if (!pci_enable_pcie_hp)
931 if (pci_find_cap(dev, PCIY_EXPRESS, NULL) != 0)
934 if (!(pcie_read_config(dev, PCIER_FLAGS, 2) & PCIEM_FLAGS_SLOT))
937 sc->pcie_slot_cap = pcie_read_config(dev, PCIER_SLOT_CAP, 4);
939 if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_HPC) == 0)
941 link_cap = pcie_read_config(dev, PCIER_LINK_CAP, 4);
942 if ((link_cap & PCIEM_LINK_CAP_DL_ACTIVE) == 0)
946 * Some devices report that they have an MRL when they actually
947 * do not. Since they always report that the MRL is open, child
948 * devices would be ignored. Try to detect these devices and
949 * ignore their claim of HotPlug support.
951 * If there is an open MRL but the Data Link Layer is active,
952 * the MRL is not real.
954 if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP) != 0) {
955 link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2);
956 slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2);
957 if ((slot_sta & PCIEM_SLOT_STA_MRLSS) != 0 &&
958 (link_sta & PCIEM_LINK_STA_DL_ACTIVE) != 0) {
964 * Now that we're sure we want to do hot plug, ask the
965 * firmware, if any, if that's OK.
967 if (pcib_request_feature(device_get_parent(device_get_parent(dev)), dev,
968 PCI_FEATURE_HP) != 0) {
970 device_printf(dev, "Unable to activate hot plug feature.\n");
974 sc->flags |= PCIB_HOTPLUG;
978 * Send a HotPlug command to the slot control register. If this slot
979 * uses command completion interrupts and a previous command is still
980 * in progress, then the command is dropped. Once the previous
981 * command completes or times out, pcib_pcie_hotplug_update() will be
982 * invoked to post a new command based on the slot's state at that
986 pcib_pcie_hotplug_command(struct pcib_softc *sc, uint16_t val, uint16_t mask)
993 if (sc->flags & PCIB_HOTPLUG_CMD_PENDING)
996 ctl = pcie_read_config(dev, PCIER_SLOT_CTL, 2);
997 new = (ctl & ~mask) | val;
1001 device_printf(dev, "HotPlug command: %04x -> %04x\n", ctl, new);
1002 pcie_write_config(dev, PCIER_SLOT_CTL, new, 2);
1003 if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS) &&
1004 (ctl & new) & PCIEM_SLOT_CTL_CCIE) {
1005 sc->flags |= PCIB_HOTPLUG_CMD_PENDING;
1007 callout_reset(&sc->pcie_cc_timer, hz,
1008 pcib_pcie_cc_timeout, sc);
1013 pcib_pcie_hotplug_command_completed(struct pcib_softc *sc)
1020 device_printf(dev, "Command Completed\n");
1021 if (!(sc->flags & PCIB_HOTPLUG_CMD_PENDING))
1023 callout_stop(&sc->pcie_cc_timer);
1024 sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING;
1029 * Returns true if a card is fully inserted from the user's
1030 * perspective. It may not yet be ready for access, but the driver
1031 * can now start enabling access if necessary.
1034 pcib_hotplug_inserted(struct pcib_softc *sc)
1037 /* Pretend the card isn't present if a detach is forced. */
1038 if (sc->flags & PCIB_DETACHING)
1041 /* Card must be present in the slot. */
1042 if ((sc->pcie_slot_sta & PCIEM_SLOT_STA_PDS) == 0)
1045 /* A power fault implicitly turns off power to the slot. */
1046 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_PFD)
1049 /* If the MRL is disengaged, the slot is powered off. */
1050 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP &&
1051 (sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSS) != 0)
1058 * Returns -1 if the card is fully inserted, powered, and ready for
1059 * access. Otherwise, returns 0.
1062 pcib_hotplug_present(struct pcib_softc *sc)
1065 /* Card must be inserted. */
1066 if (!pcib_hotplug_inserted(sc))
1070 * Require the Electromechanical Interlock to be engaged if
1073 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_EIP &&
1074 (sc->pcie_slot_sta & PCIEM_SLOT_STA_EIS) == 0)
1077 /* Require the Data Link Layer to be active. */
1078 if (!(sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE))
1085 pcib_pcie_hotplug_update(struct pcib_softc *sc, uint16_t val, uint16_t mask,
1088 bool card_inserted, ei_engaged;
1090 /* Clear DETACHING if Presence Detect has cleared. */
1091 if ((sc->pcie_slot_sta & (PCIEM_SLOT_STA_PDC | PCIEM_SLOT_STA_PDS)) ==
1093 sc->flags &= ~PCIB_DETACHING;
1095 card_inserted = pcib_hotplug_inserted(sc);
1097 /* Turn the power indicator on if a card is inserted. */
1098 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PIP) {
1099 mask |= PCIEM_SLOT_CTL_PIC;
1101 val |= PCIEM_SLOT_CTL_PI_ON;
1102 else if (sc->flags & PCIB_DETACH_PENDING)
1103 val |= PCIEM_SLOT_CTL_PI_BLINK;
1105 val |= PCIEM_SLOT_CTL_PI_OFF;
1108 /* Turn the power on via the Power Controller if a card is inserted. */
1109 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PCP) {
1110 mask |= PCIEM_SLOT_CTL_PCC;
1112 val |= PCIEM_SLOT_CTL_PC_ON;
1114 val |= PCIEM_SLOT_CTL_PC_OFF;
1118 * If a card is inserted, enable the Electromechanical
1119 * Interlock. If a card is not inserted (or we are in the
1120 * process of detaching), disable the Electromechanical
1123 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_EIP) {
1124 mask |= PCIEM_SLOT_CTL_EIC;
1125 ei_engaged = (sc->pcie_slot_sta & PCIEM_SLOT_STA_EIS) != 0;
1126 if (card_inserted != ei_engaged)
1127 val |= PCIEM_SLOT_CTL_EIC;
1131 * Start a timer to see if the Data Link Layer times out.
1132 * Note that we only start the timer if Presence Detect or MRL Sensor
1133 * changed on this interrupt. Stop any scheduled timer if
1134 * the Data Link Layer is active.
1136 if (card_inserted &&
1137 !(sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE) &&
1139 (PCIEM_SLOT_STA_MRLSC | PCIEM_SLOT_STA_PDC)) {
1141 device_printf(sc->dev,
1142 "Data Link Layer inactive\n");
1144 callout_reset(&sc->pcie_dll_timer, hz,
1145 pcib_pcie_dll_timeout, sc);
1146 } else if (sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE)
1147 callout_stop(&sc->pcie_dll_timer);
1149 pcib_pcie_hotplug_command(sc, val, mask);
1152 * During attach the child "pci" device is added synchronously;
1153 * otherwise, the task is scheduled to manage the child
1156 if (schedule_task &&
1157 (pcib_hotplug_present(sc) != 0) != (sc->child != NULL))
1158 taskqueue_enqueue(taskqueue_thread, &sc->pcie_hp_task);
1162 pcib_pcie_intr_hotplug(void *arg)
1164 struct pcib_softc *sc;
1169 sc->pcie_slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2);
1171 /* Clear the events just reported. */
1172 pcie_write_config(dev, PCIER_SLOT_STA, sc->pcie_slot_sta, 2);
1175 device_printf(dev, "HotPlug interrupt: %#x\n",
1178 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_ABP) {
1179 if (sc->flags & PCIB_DETACH_PENDING) {
1181 "Attention Button Pressed: Detach Cancelled\n");
1182 sc->flags &= ~PCIB_DETACH_PENDING;
1183 callout_stop(&sc->pcie_ab_timer);
1186 "Attention Button Pressed: Detaching in 5 seconds\n");
1187 sc->flags |= PCIB_DETACH_PENDING;
1188 callout_reset(&sc->pcie_ab_timer, 5 * hz,
1189 pcib_pcie_ab_timeout, sc);
1192 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_PFD)
1193 device_printf(dev, "Power Fault Detected\n");
1194 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSC)
1195 device_printf(dev, "MRL Sensor Changed to %s\n",
1196 sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSS ? "open" :
1198 if (bootverbose && sc->pcie_slot_sta & PCIEM_SLOT_STA_PDC)
1199 device_printf(dev, "Presence Detect Changed to %s\n",
1200 sc->pcie_slot_sta & PCIEM_SLOT_STA_PDS ? "card present" :
1202 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_CC)
1203 pcib_pcie_hotplug_command_completed(sc);
1204 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_DLLSC) {
1205 sc->pcie_link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2);
1208 "Data Link Layer State Changed to %s\n",
1209 sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE ?
1210 "active" : "inactive");
1213 pcib_pcie_hotplug_update(sc, 0, 0, true);
1217 pcib_pcie_hotplug_task(void *context, int pending)
1219 struct pcib_softc *sc;
1225 if (pcib_hotplug_present(sc) != 0) {
1226 if (sc->child == NULL) {
1227 sc->child = device_add_child(dev, "pci", -1);
1228 bus_generic_attach(dev);
1231 if (sc->child != NULL) {
1232 if (device_delete_child(dev, sc->child) == 0)
1240 pcib_pcie_ab_timeout(void *arg)
1242 struct pcib_softc *sc;
1247 mtx_assert(&Giant, MA_OWNED);
1248 if (sc->flags & PCIB_DETACH_PENDING) {
1249 sc->flags |= PCIB_DETACHING;
1250 sc->flags &= ~PCIB_DETACH_PENDING;
1251 pcib_pcie_hotplug_update(sc, 0, 0, true);
1256 pcib_pcie_cc_timeout(void *arg)
1258 struct pcib_softc *sc;
1264 mtx_assert(&Giant, MA_OWNED);
1265 sta = pcie_read_config(dev, PCIER_SLOT_STA, 2);
1266 if (!(sta & PCIEM_SLOT_STA_CC)) {
1268 "HotPlug Command Timed Out - forcing detach\n");
1269 sc->flags &= ~(PCIB_HOTPLUG_CMD_PENDING | PCIB_DETACH_PENDING);
1270 sc->flags |= PCIB_DETACHING;
1271 pcib_pcie_hotplug_update(sc, 0, 0, true);
1274 "Missed HotPlug interrupt waiting for Command Completion\n");
1275 pcib_pcie_intr_hotplug(sc);
1280 pcib_pcie_dll_timeout(void *arg)
1282 struct pcib_softc *sc;
1288 mtx_assert(&Giant, MA_OWNED);
1289 sta = pcie_read_config(dev, PCIER_LINK_STA, 2);
1290 if (!(sta & PCIEM_LINK_STA_DL_ACTIVE)) {
1292 "Timed out waiting for Data Link Layer Active\n");
1293 sc->flags |= PCIB_DETACHING;
1294 pcib_pcie_hotplug_update(sc, 0, 0, true);
1295 } else if (sta != sc->pcie_link_sta) {
1297 "Missed HotPlug interrupt waiting for DLL Active\n");
1298 pcib_pcie_intr_hotplug(sc);
1303 pcib_alloc_pcie_irq(struct pcib_softc *sc)
1306 int count, error, rid;
1312 * For simplicity, only use MSI-X if there is a single message.
1313 * To support a device with multiple messages we would have to
1314 * use remap intr if the MSI number is not 0.
1316 count = pci_msix_count(dev);
1318 error = pci_alloc_msix(dev, &count);
1323 if (rid < 0 && pci_msi_count(dev) > 0) {
1325 error = pci_alloc_msi(dev, &count);
1333 sc->pcie_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1335 if (sc->pcie_irq == NULL) {
1337 "Failed to allocate interrupt for PCI-e events\n");
1339 pci_release_msi(dev);
1343 error = bus_setup_intr(dev, sc->pcie_irq, INTR_TYPE_MISC,
1344 NULL, pcib_pcie_intr_hotplug, sc, &sc->pcie_ihand);
1346 device_printf(dev, "Failed to setup PCI-e interrupt handler\n");
1347 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->pcie_irq);
1349 pci_release_msi(dev);
1356 pcib_release_pcie_irq(struct pcib_softc *sc)
1362 error = bus_teardown_intr(dev, sc->pcie_irq, sc->pcie_ihand);
1365 error = bus_free_resource(dev, SYS_RES_IRQ, sc->pcie_irq);
1368 return (pci_release_msi(dev));
1372 pcib_setup_hotplug(struct pcib_softc *sc)
1378 callout_init(&sc->pcie_ab_timer, 0);
1379 callout_init(&sc->pcie_cc_timer, 0);
1380 callout_init(&sc->pcie_dll_timer, 0);
1381 TASK_INIT(&sc->pcie_hp_task, 0, pcib_pcie_hotplug_task, sc);
1384 if (pcib_alloc_pcie_irq(sc) != 0)
1387 sc->pcie_link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2);
1388 sc->pcie_slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2);
1390 /* Clear any events previously pending. */
1391 pcie_write_config(dev, PCIER_SLOT_STA, sc->pcie_slot_sta, 2);
1393 /* Enable HotPlug events. */
1394 mask = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE |
1395 PCIEM_SLOT_CTL_CCIE | PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_MRLSCE |
1396 PCIEM_SLOT_CTL_PFDE | PCIEM_SLOT_CTL_ABPE;
1397 val = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE | PCIEM_SLOT_CTL_PDCE;
1398 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_APB)
1399 val |= PCIEM_SLOT_CTL_ABPE;
1400 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PCP)
1401 val |= PCIEM_SLOT_CTL_PFDE;
1402 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP)
1403 val |= PCIEM_SLOT_CTL_MRLSCE;
1404 if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS))
1405 val |= PCIEM_SLOT_CTL_CCIE;
1407 /* Turn the attention indicator off. */
1408 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_AIP) {
1409 mask |= PCIEM_SLOT_CTL_AIC;
1410 val |= PCIEM_SLOT_CTL_AI_OFF;
1413 pcib_pcie_hotplug_update(sc, val, mask, false);
1417 pcib_detach_hotplug(struct pcib_softc *sc)
1422 /* Disable the card in the slot and force it to detach. */
1423 if (sc->flags & PCIB_DETACH_PENDING) {
1424 sc->flags &= ~PCIB_DETACH_PENDING;
1425 callout_stop(&sc->pcie_ab_timer);
1427 sc->flags |= PCIB_DETACHING;
1429 if (sc->flags & PCIB_HOTPLUG_CMD_PENDING) {
1430 callout_stop(&sc->pcie_cc_timer);
1431 tsleep(sc, 0, "hpcmd", hz);
1432 sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING;
1435 /* Disable HotPlug events. */
1436 mask = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE |
1437 PCIEM_SLOT_CTL_CCIE | PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_MRLSCE |
1438 PCIEM_SLOT_CTL_PFDE | PCIEM_SLOT_CTL_ABPE;
1441 /* Turn the attention indicator off. */
1442 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_AIP) {
1443 mask |= PCIEM_SLOT_CTL_AIC;
1444 val |= PCIEM_SLOT_CTL_AI_OFF;
1447 pcib_pcie_hotplug_update(sc, val, mask, false);
1449 error = pcib_release_pcie_irq(sc);
1452 taskqueue_drain(taskqueue_thread, &sc->pcie_hp_task);
1453 callout_drain(&sc->pcie_ab_timer);
1454 callout_drain(&sc->pcie_cc_timer);
1455 callout_drain(&sc->pcie_dll_timer);
1461 * Get current bridge configuration.
1464 pcib_cfg_save(struct pcib_softc *sc)
1472 command = pci_read_config(dev, PCIR_COMMAND, 2);
1473 if (command & PCIM_CMD_PORTEN)
1474 pcib_get_io_decode(sc);
1475 if (command & PCIM_CMD_MEMEN)
1476 pcib_get_mem_decode(sc);
1481 * Restore previous bridge configuration.
1484 pcib_cfg_restore(struct pcib_softc *sc)
1493 pcib_write_windows(sc, WIN_IO | WIN_MEM | WIN_PMEM);
1495 command = pci_read_config(dev, PCIR_COMMAND, 2);
1496 if (command & PCIM_CMD_PORTEN)
1497 pcib_set_io_decode(sc);
1498 if (command & PCIM_CMD_MEMEN)
1499 pcib_set_mem_decode(sc);
1504 * Generic device interface
1507 pcib_probe(device_t dev)
1509 if ((pci_get_class(dev) == PCIC_BRIDGE) &&
1510 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) {
1511 device_set_desc(dev, "PCI-PCI bridge");
1518 pcib_attach_common(device_t dev)
1520 struct pcib_softc *sc;
1521 struct sysctl_ctx_list *sctx;
1522 struct sysctl_oid *soid;
1525 sc = device_get_softc(dev);
1529 * Get current bridge configuration.
1531 sc->domain = pci_get_domain(dev);
1532 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS))
1533 sc->bus.sec = pci_read_config(dev, PCIR_SECBUS_1, 1);
1534 sc->bus.sub = pci_read_config(dev, PCIR_SUBBUS_1, 1);
1536 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
1540 * The primary bus register should always be the bus of the
1543 sc->pribus = pci_get_bus(dev);
1544 pci_write_config(dev, PCIR_PRIBUS_1, sc->pribus, 1);
1547 * Setup sysctl reporting nodes
1549 sctx = device_get_sysctl_ctx(dev);
1550 soid = device_get_sysctl_tree(dev);
1551 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain",
1552 CTLFLAG_RD, &sc->domain, 0, "Domain number");
1553 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus",
1554 CTLFLAG_RD, &sc->pribus, 0, "Primary bus number");
1555 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus",
1556 CTLFLAG_RD, &sc->bus.sec, 0, "Secondary bus number");
1557 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus",
1558 CTLFLAG_RD, &sc->bus.sub, 0, "Subordinate bus number");
1563 switch (pci_get_devid(dev)) {
1564 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS))
1565 case 0x12258086: /* Intel 82454KX/GX (Orion) */
1569 supbus = pci_read_config(dev, 0x41, 1);
1570 if (supbus != 0xff) {
1571 sc->bus.sec = supbus + 1;
1572 sc->bus.sub = supbus + 1;
1579 * The i82380FB mobile docking controller is a PCI-PCI bridge,
1580 * and it is a subtractive bridge. However, the ProgIf is wrong
1581 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't
1582 * happen. There are also Toshiba and Cavium ThunderX bridges
1583 * that behave this way.
1585 case 0xa002177d: /* Cavium ThunderX */
1586 case 0x124b8086: /* Intel 82380FB Mobile */
1587 case 0x060513d7: /* Toshiba ???? */
1588 sc->flags |= PCIB_SUBTRACTIVE;
1591 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS))
1592 /* Compaq R3000 BIOS sets wrong subordinate bus number. */
1597 if ((cp = kern_getenv("smbios.planar.maker")) == NULL)
1599 if (strncmp(cp, "Compal", 6) != 0) {
1604 if ((cp = kern_getenv("smbios.planar.product")) == NULL)
1606 if (strncmp(cp, "08A0", 4) != 0) {
1611 if (sc->bus.sub < 0xa) {
1612 pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1);
1613 sc->bus.sub = pci_read_config(dev, PCIR_SUBBUS_1, 1);
1620 if (pci_msi_device_blacklisted(dev))
1621 sc->flags |= PCIB_DISABLE_MSI;
1623 if (pci_msix_device_blacklisted(dev))
1624 sc->flags |= PCIB_DISABLE_MSIX;
1627 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges,
1628 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM,
1629 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese.
1630 * This means they act as if they were subtractively decoding
1631 * bridges and pass all transactions. Mark them and real ProgIf 1
1632 * parts as subtractive.
1634 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 ||
1635 pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_BRIDGE_PCI_SUBTRACTIVE)
1636 sc->flags |= PCIB_SUBTRACTIVE;
1639 pcib_probe_hotplug(sc);
1643 pcib_setup_secbus(dev, &sc->bus, 1);
1645 pcib_probe_windows(sc);
1648 if (sc->flags & PCIB_HOTPLUG)
1649 pcib_setup_hotplug(sc);
1652 device_printf(dev, " domain %d\n", sc->domain);
1653 device_printf(dev, " secondary bus %d\n", sc->bus.sec);
1654 device_printf(dev, " subordinate bus %d\n", sc->bus.sub);
1656 if (pcib_is_window_open(&sc->io))
1657 device_printf(dev, " I/O decode 0x%jx-0x%jx\n",
1658 (uintmax_t)sc->io.base, (uintmax_t)sc->io.limit);
1659 if (pcib_is_window_open(&sc->mem))
1660 device_printf(dev, " memory decode 0x%jx-0x%jx\n",
1661 (uintmax_t)sc->mem.base, (uintmax_t)sc->mem.limit);
1662 if (pcib_is_window_open(&sc->pmem))
1663 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n",
1664 (uintmax_t)sc->pmem.base, (uintmax_t)sc->pmem.limit);
1666 if (pcib_is_io_open(sc))
1667 device_printf(dev, " I/O decode 0x%x-0x%x\n",
1668 sc->iobase, sc->iolimit);
1669 if (pcib_is_nonprefetch_open(sc))
1670 device_printf(dev, " memory decode 0x%jx-0x%jx\n",
1671 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit);
1672 if (pcib_is_prefetch_open(sc))
1673 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n",
1674 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit);
1676 if (sc->bridgectl & (PCIB_BCR_ISA_ENABLE | PCIB_BCR_VGA_ENABLE) ||
1677 sc->flags & PCIB_SUBTRACTIVE) {
1678 device_printf(dev, " special decode ");
1680 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE) {
1684 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE) {
1685 printf("%sVGA", comma ? ", " : "");
1688 if (sc->flags & PCIB_SUBTRACTIVE)
1689 printf("%ssubtractive", comma ? ", " : "");
1695 * Always enable busmastering on bridges so that transactions
1696 * initiated on the secondary bus are passed through to the
1699 pci_enable_busmaster(dev);
1704 pcib_present(struct pcib_softc *sc)
1707 if (sc->flags & PCIB_HOTPLUG)
1708 return (pcib_hotplug_present(sc) != 0);
1714 pcib_attach_child(device_t dev)
1716 struct pcib_softc *sc;
1718 sc = device_get_softc(dev);
1719 if (sc->bus.sec == 0) {
1720 /* no secondary bus; we should have fixed this */
1725 if (!pcib_present(sc)) {
1726 /* An empty HotPlug slot, so don't add a PCI bus yet. */
1731 sc->child = device_add_child(dev, "pci", -1);
1732 return (bus_generic_attach(dev));
1736 pcib_attach(device_t dev)
1739 pcib_attach_common(dev);
1740 return (pcib_attach_child(dev));
1744 pcib_detach(device_t dev)
1746 #if defined(PCI_HP) || defined(NEW_PCIB)
1747 struct pcib_softc *sc;
1751 #if defined(PCI_HP) || defined(NEW_PCIB)
1752 sc = device_get_softc(dev);
1754 error = bus_generic_detach(dev);
1758 if (sc->flags & PCIB_HOTPLUG) {
1759 error = pcib_detach_hotplug(sc);
1764 error = device_delete_children(dev);
1768 pcib_free_windows(sc);
1770 pcib_free_secbus(dev, &sc->bus);
1777 pcib_suspend(device_t dev)
1780 pcib_cfg_save(device_get_softc(dev));
1781 return (bus_generic_suspend(dev));
1785 pcib_resume(device_t dev)
1788 pcib_cfg_restore(device_get_softc(dev));
1789 return (bus_generic_resume(dev));
1793 pcib_bridge_init(device_t dev)
1795 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1);
1796 pci_write_config(dev, PCIR_IOBASEH_1, 0xffff, 2);
1797 pci_write_config(dev, PCIR_IOLIMITL_1, 0, 1);
1798 pci_write_config(dev, PCIR_IOLIMITH_1, 0, 2);
1799 pci_write_config(dev, PCIR_MEMBASE_1, 0xffff, 2);
1800 pci_write_config(dev, PCIR_MEMLIMIT_1, 0, 2);
1801 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2);
1802 pci_write_config(dev, PCIR_PMBASEH_1, 0xffffffff, 4);
1803 pci_write_config(dev, PCIR_PMLIMITL_1, 0, 2);
1804 pci_write_config(dev, PCIR_PMLIMITH_1, 0, 4);
1808 pcib_child_present(device_t dev, device_t child)
1811 struct pcib_softc *sc = device_get_softc(dev);
1814 retval = bus_child_present(dev);
1815 if (retval != 0 && sc->flags & PCIB_HOTPLUG)
1816 retval = pcib_hotplug_present(sc);
1819 return (bus_child_present(dev));
1824 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1826 struct pcib_softc *sc = device_get_softc(dev);
1829 case PCIB_IVAR_DOMAIN:
1830 *result = sc->domain;
1833 *result = sc->bus.sec;
1840 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1844 case PCIB_IVAR_DOMAIN:
1854 * Attempt to allocate a resource from the existing resources assigned
1857 static struct resource *
1858 pcib_suballoc_resource(struct pcib_softc *sc, struct pcib_window *w,
1859 device_t child, int type, int *rid, rman_res_t start, rman_res_t end,
1860 rman_res_t count, u_int flags)
1862 struct resource *res;
1864 if (!pcib_is_window_open(w))
1867 res = rman_reserve_resource(&w->rman, start, end, count,
1868 flags & ~RF_ACTIVE, child);
1873 device_printf(sc->dev,
1874 "allocated %s range (%#jx-%#jx) for rid %x of %s\n",
1875 w->name, rman_get_start(res), rman_get_end(res), *rid,
1876 pcib_child_name(child));
1877 rman_set_rid(res, *rid);
1880 * If the resource should be active, pass that request up the
1881 * tree. This assumes the parent drivers can handle
1882 * activating sub-allocated resources.
1884 if (flags & RF_ACTIVE) {
1885 if (bus_activate_resource(child, type, *rid, res) != 0) {
1886 rman_release_resource(res);
1894 /* Allocate a fresh resource range for an unconfigured window. */
1896 pcib_alloc_new_window(struct pcib_softc *sc, struct pcib_window *w, int type,
1897 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
1899 struct resource *res;
1900 rman_res_t base, limit, wmask;
1904 * If this is an I/O window on a bridge with ISA enable set
1905 * and the start address is below 64k, then try to allocate an
1906 * initial window of 0x1000 bytes long starting at address
1907 * 0xf000 and walking down. Note that if the original request
1908 * was larger than the non-aliased range size of 0x100 our
1909 * caller would have raised the start address up to 64k
1912 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE &&
1914 for (base = 0xf000; (long)base >= 0; base -= 0x1000) {
1915 limit = base + 0xfff;
1918 * Skip ranges that wouldn't work for the
1919 * original request. Note that the actual
1920 * window that overlaps are the non-alias
1921 * ranges within [base, limit], so this isn't
1922 * quite a simple comparison.
1924 if (start + count > limit - 0x400)
1928 * The first open region for the window at
1931 if (end - count + 1 < 0x400)
1934 if (end - count + 1 < base)
1938 if (pcib_alloc_nonisa_ranges(sc, base, limit) == 0) {
1947 wmask = ((rman_res_t)1 << w->step) - 1;
1948 if (RF_ALIGNMENT(flags) < w->step) {
1949 flags &= ~RF_ALIGNMENT_MASK;
1950 flags |= RF_ALIGNMENT_LOG2(w->step);
1954 count = roundup2(count, (rman_res_t)1 << w->step);
1956 res = bus_alloc_resource(sc->dev, type, &rid, start, end, count,
1957 flags & ~RF_ACTIVE);
1960 pcib_add_window_resources(w, &res, 1);
1961 pcib_activate_window(sc, type);
1962 w->base = rman_get_start(res);
1963 w->limit = rman_get_end(res);
1967 /* Try to expand an existing window to the requested base and limit. */
1969 pcib_expand_window(struct pcib_softc *sc, struct pcib_window *w, int type,
1970 rman_res_t base, rman_res_t limit)
1972 struct resource *res;
1973 int error, i, force_64k_base;
1975 KASSERT(base <= w->base && limit >= w->limit,
1976 ("attempting to shrink window"));
1979 * XXX: pcib_grow_window() doesn't try to do this anyway and
1980 * the error handling for all the edge cases would be tedious.
1982 KASSERT(limit == w->limit || base == w->base,
1983 ("attempting to grow both ends of a window"));
1986 * Yet more special handling for requests to expand an I/O
1987 * window behind an ISA-enabled bridge. Since I/O windows
1988 * have to grow in 0x1000 increments and the end of the 0xffff
1989 * range is an alias, growing a window below 64k will always
1990 * result in allocating new resources and never adjusting an
1991 * existing resource.
1993 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE &&
1994 (limit <= 65535 || (base <= 65535 && base != w->base))) {
1995 KASSERT(limit == w->limit || limit <= 65535,
1996 ("attempting to grow both ends across 64k ISA alias"));
1998 if (base != w->base)
1999 error = pcib_alloc_nonisa_ranges(sc, base, w->base - 1);
2001 error = pcib_alloc_nonisa_ranges(sc, w->limit + 1,
2011 * Find the existing resource to adjust. Usually there is only one,
2012 * but for an ISA-enabled bridge we might be growing the I/O window
2013 * above 64k and need to find the existing resource that maps all
2014 * of the area above 64k.
2016 for (i = 0; i < w->count; i++) {
2017 if (rman_get_end(w->res[i]) == w->limit)
2020 KASSERT(i != w->count, ("did not find existing resource"));
2024 * Usually the resource we found should match the window's
2025 * existing range. The one exception is the ISA-enabled case
2026 * mentioned above in which case the resource should start at
2029 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE &&
2031 KASSERT(rman_get_start(res) == 65536,
2032 ("existing resource mismatch"));
2035 KASSERT(w->base == rman_get_start(res),
2036 ("existing resource mismatch"));
2040 error = bus_adjust_resource(sc->dev, type, res, force_64k_base ?
2041 rman_get_start(res) : base, limit);
2045 /* Add the newly allocated region to the resource manager. */
2046 if (w->base != base) {
2047 error = rman_manage_region(&w->rman, base, w->base - 1);
2050 error = rman_manage_region(&w->rman, w->limit + 1, limit);
2055 device_printf(sc->dev,
2056 "failed to expand %s resource manager\n", w->name);
2057 (void)bus_adjust_resource(sc->dev, type, res, force_64k_base ?
2058 rman_get_start(res) : w->base, w->limit);
2064 * Attempt to grow a window to make room for a given resource request.
2067 pcib_grow_window(struct pcib_softc *sc, struct pcib_window *w, int type,
2068 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
2070 rman_res_t align, start_free, end_free, front, back, wmask;
2074 * Clamp the desired resource range to the maximum address
2075 * this window supports. Reject impossible requests.
2077 * For I/O port requests behind a bridge with the ISA enable
2078 * bit set, force large allocations to start above 64k.
2082 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE && count > 0x100 &&
2085 if (end > w->rman.rm_end)
2086 end = w->rman.rm_end;
2087 if (start + count - 1 > end || start + count < start)
2089 wmask = ((rman_res_t)1 << w->step) - 1;
2092 * If there is no resource at all, just try to allocate enough
2093 * aligned space for this resource.
2095 if (w->res == NULL) {
2096 error = pcib_alloc_new_window(sc, w, type, start, end, count,
2100 device_printf(sc->dev,
2101 "failed to allocate initial %s window (%#jx-%#jx,%#jx)\n",
2102 w->name, start, end, count);
2106 device_printf(sc->dev,
2107 "allocated initial %s window of %#jx-%#jx\n",
2108 w->name, (uintmax_t)w->base, (uintmax_t)w->limit);
2113 * See if growing the window would help. Compute the minimum
2114 * amount of address space needed on both the front and back
2115 * ends of the existing window to satisfy the allocation.
2117 * For each end, build a candidate region adjusting for the
2118 * required alignment, etc. If there is a free region at the
2119 * edge of the window, grow from the inner edge of the free
2120 * region. Otherwise grow from the window boundary.
2122 * Growing an I/O window below 64k for a bridge with the ISA
2123 * enable bit doesn't require any special magic as the step
2124 * size of an I/O window (1k) always includes multiple
2125 * non-alias ranges when it is grown in either direction.
2127 * XXX: Special case: if w->res is completely empty and the
2128 * request size is larger than w->res, we should find the
2129 * optimal aligned buffer containing w->res and allocate that.
2132 device_printf(sc->dev,
2133 "attempting to grow %s window for (%#jx-%#jx,%#jx)\n",
2134 w->name, start, end, count);
2135 align = (rman_res_t)1 << RF_ALIGNMENT(flags);
2136 if (start < w->base) {
2137 if (rman_first_free_region(&w->rman, &start_free, &end_free) !=
2138 0 || start_free != w->base)
2143 /* Move end_free down until it is properly aligned. */
2144 end_free &= ~(align - 1);
2146 front = end_free - (count - 1);
2149 * The resource would now be allocated at (front,
2150 * end_free). Ensure that fits in the (start, end)
2151 * bounds. end_free is checked above. If 'front' is
2152 * ok, ensure it is properly aligned for this window.
2153 * Also check for underflow.
2155 if (front >= start && front <= end_free) {
2157 printf("\tfront candidate range: %#jx-%#jx\n",
2160 front = w->base - front;
2165 if (end > w->limit) {
2166 if (rman_last_free_region(&w->rman, &start_free, &end_free) !=
2167 0 || end_free != w->limit)
2168 start_free = w->limit + 1;
2169 if (start_free < start)
2172 /* Move start_free up until it is properly aligned. */
2173 start_free = roundup2(start_free, align);
2174 back = start_free + count - 1;
2177 * The resource would now be allocated at (start_free,
2178 * back). Ensure that fits in the (start, end)
2179 * bounds. start_free is checked above. If 'back' is
2180 * ok, ensure it is properly aligned for this window.
2181 * Also check for overflow.
2183 if (back <= end && start_free <= back) {
2185 printf("\tback candidate range: %#jx-%#jx\n",
2195 * Try to allocate the smallest needed region first.
2196 * If that fails, fall back to the other region.
2199 while (front != 0 || back != 0) {
2200 if (front != 0 && (front <= back || back == 0)) {
2201 error = pcib_expand_window(sc, w, type, w->base - front,
2207 error = pcib_expand_window(sc, w, type, w->base,
2218 device_printf(sc->dev, "grew %s window to %#jx-%#jx\n",
2219 w->name, (uintmax_t)w->base, (uintmax_t)w->limit);
2222 /* Write the new window. */
2223 KASSERT((w->base & wmask) == 0, ("start address is not aligned"));
2224 KASSERT((w->limit & wmask) == wmask, ("end address is not aligned"));
2225 pcib_write_windows(sc, w->mask);
2230 * We have to trap resource allocation requests and ensure that the bridge
2231 * is set up to, or capable of handling them.
2234 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
2235 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
2237 struct pcib_softc *sc;
2240 sc = device_get_softc(dev);
2243 * VGA resources are decoded iff the VGA enable bit is set in
2244 * the bridge control register. VGA resources do not fall into
2245 * the resource windows and are passed up to the parent.
2247 if ((type == SYS_RES_IOPORT && pci_is_vga_ioport_range(start, end)) ||
2248 (type == SYS_RES_MEMORY && pci_is_vga_memory_range(start, end))) {
2249 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE)
2250 return (bus_generic_alloc_resource(dev, child, type,
2251 rid, start, end, count, flags));
2259 return (pcib_alloc_subbus(&sc->bus, child, rid, start, end,
2262 case SYS_RES_IOPORT:
2263 if (pcib_is_isa_range(sc, start, end, count))
2265 r = pcib_suballoc_resource(sc, &sc->io, child, type, rid, start,
2267 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0)
2269 if (pcib_grow_window(sc, &sc->io, type, start, end, count,
2271 r = pcib_suballoc_resource(sc, &sc->io, child, type,
2272 rid, start, end, count, flags);
2274 case SYS_RES_MEMORY:
2276 * For prefetchable resources, prefer the prefetchable
2277 * memory window, but fall back to the regular memory
2278 * window if that fails. Try both windows before
2279 * attempting to grow a window in case the firmware
2280 * has used a range in the regular memory window to
2281 * map a prefetchable BAR.
2283 if (flags & RF_PREFETCHABLE) {
2284 r = pcib_suballoc_resource(sc, &sc->pmem, child, type,
2285 rid, start, end, count, flags);
2289 r = pcib_suballoc_resource(sc, &sc->mem, child, type, rid,
2290 start, end, count, flags);
2291 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0)
2293 if (flags & RF_PREFETCHABLE) {
2294 if (pcib_grow_window(sc, &sc->pmem, type, start, end,
2295 count, flags) == 0) {
2296 r = pcib_suballoc_resource(sc, &sc->pmem, child,
2297 type, rid, start, end, count, flags);
2302 if (pcib_grow_window(sc, &sc->mem, type, start, end, count,
2303 flags & ~RF_PREFETCHABLE) == 0)
2304 r = pcib_suballoc_resource(sc, &sc->mem, child, type,
2305 rid, start, end, count, flags);
2308 return (bus_generic_alloc_resource(dev, child, type, rid,
2309 start, end, count, flags));
2313 * If attempts to suballocate from the window fail but this is a
2314 * subtractive bridge, pass the request up the tree.
2316 if (sc->flags & PCIB_SUBTRACTIVE && r == NULL)
2317 return (bus_generic_alloc_resource(dev, child, type, rid,
2318 start, end, count, flags));
2323 pcib_adjust_resource(device_t bus, device_t child, int type, struct resource *r,
2324 rman_res_t start, rman_res_t end)
2326 struct pcib_softc *sc;
2328 sc = device_get_softc(bus);
2329 if (pcib_is_resource_managed(sc, type, r))
2330 return (rman_adjust_resource(r, start, end));
2331 return (bus_generic_adjust_resource(bus, child, type, r, start, end));
2335 pcib_release_resource(device_t dev, device_t child, int type, int rid,
2338 struct pcib_softc *sc;
2341 sc = device_get_softc(dev);
2342 if (pcib_is_resource_managed(sc, type, r)) {
2343 if (rman_get_flags(r) & RF_ACTIVE) {
2344 error = bus_deactivate_resource(child, type, rid, r);
2348 return (rman_release_resource(r));
2350 return (bus_generic_release_resource(dev, child, type, rid, r));
2354 * We have to trap resource allocation requests and ensure that the bridge
2355 * is set up to, or capable of handling them.
2358 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
2359 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
2361 struct pcib_softc *sc = device_get_softc(dev);
2362 const char *name, *suffix;
2366 * Fail the allocation for this range if it's not supported.
2368 name = device_get_nameunit(child);
2375 case SYS_RES_IOPORT:
2377 if (!pcib_is_io_open(sc))
2379 ok = (start >= sc->iobase && end <= sc->iolimit);
2382 * Make sure we allow access to VGA I/O addresses when the
2383 * bridge has the "VGA Enable" bit set.
2385 if (!ok && pci_is_vga_ioport_range(start, end))
2386 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
2388 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
2390 if (start < sc->iobase)
2392 if (end > sc->iolimit)
2401 * If we overlap with the subtractive range, then
2402 * pick the upper range to use.
2404 if (start < sc->iolimit && end > sc->iobase)
2405 start = sc->iolimit + 1;
2409 device_printf(dev, "ioport: end (%jx) < start (%jx)\n",
2416 device_printf(dev, "%s%srequested unsupported I/O "
2417 "range 0x%jx-0x%jx (decoding 0x%x-0x%x)\n",
2418 name, suffix, start, end, sc->iobase, sc->iolimit);
2423 "%s%srequested I/O range 0x%jx-0x%jx: in range\n",
2424 name, suffix, start, end);
2427 case SYS_RES_MEMORY:
2429 if (pcib_is_nonprefetch_open(sc))
2430 ok = ok || (start >= sc->membase && end <= sc->memlimit);
2431 if (pcib_is_prefetch_open(sc))
2432 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit);
2435 * Make sure we allow access to VGA memory addresses when the
2436 * bridge has the "VGA Enable" bit set.
2438 if (!ok && pci_is_vga_memory_range(start, end))
2439 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
2441 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
2444 if (flags & RF_PREFETCHABLE) {
2445 if (pcib_is_prefetch_open(sc)) {
2446 if (start < sc->pmembase)
2447 start = sc->pmembase;
2448 if (end > sc->pmemlimit)
2449 end = sc->pmemlimit;
2453 } else { /* non-prefetchable */
2454 if (pcib_is_nonprefetch_open(sc)) {
2455 if (start < sc->membase)
2456 start = sc->membase;
2457 if (end > sc->memlimit)
2465 ok = 1; /* subtractive bridge: always ok */
2467 if (pcib_is_nonprefetch_open(sc)) {
2468 if (start < sc->memlimit && end > sc->membase)
2469 start = sc->memlimit + 1;
2471 if (pcib_is_prefetch_open(sc)) {
2472 if (start < sc->pmemlimit && end > sc->pmembase)
2473 start = sc->pmemlimit + 1;
2478 device_printf(dev, "memory: end (%jx) < start (%jx)\n",
2484 if (!ok && bootverbose)
2486 "%s%srequested unsupported memory range %#jx-%#jx "
2487 "(decoding %#jx-%#jx, %#jx-%#jx)\n",
2488 name, suffix, start, end,
2489 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit,
2490 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit);
2494 device_printf(dev,"%s%srequested memory range "
2495 "0x%jx-0x%jx: good\n",
2496 name, suffix, start, end);
2503 * Bridge is OK decoding this resource, so pass it up.
2505 return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
2511 * If ARI is enabled on this downstream port, translate the function number
2512 * to the non-ARI slot/function. The downstream port will convert it back in
2513 * hardware. If ARI is not enabled slot and func are not modified.
2515 static __inline void
2516 pcib_xlate_ari(device_t pcib, int bus, int *slot, int *func)
2518 struct pcib_softc *sc;
2521 sc = device_get_softc(pcib);
2524 if (sc->flags & PCIB_ENABLE_ARI) {
2526 ("Non-zero slot number with ARI enabled!"));
2527 *slot = PCIE_ARI_SLOT(ari_func);
2528 *func = PCIE_ARI_FUNC(ari_func);
2534 pcib_enable_ari(struct pcib_softc *sc, uint32_t pcie_pos)
2538 ctl2 = pci_read_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, 4);
2539 ctl2 |= PCIEM_CTL2_ARI;
2540 pci_write_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, ctl2, 4);
2542 sc->flags |= PCIB_ENABLE_ARI;
2549 pcib_maxslots(device_t dev)
2551 return (PCI_SLOTMAX);
2555 pcib_ari_maxslots(device_t dev)
2557 struct pcib_softc *sc;
2559 sc = device_get_softc(dev);
2561 if (sc->flags & PCIB_ENABLE_ARI)
2562 return (PCIE_ARI_SLOTMAX);
2564 return (PCI_SLOTMAX);
2568 pcib_ari_maxfuncs(device_t dev)
2570 struct pcib_softc *sc;
2572 sc = device_get_softc(dev);
2574 if (sc->flags & PCIB_ENABLE_ARI)
2575 return (PCIE_ARI_FUNCMAX);
2577 return (PCI_FUNCMAX);
2581 pcib_ari_decode_rid(device_t pcib, uint16_t rid, int *bus, int *slot,
2584 struct pcib_softc *sc;
2586 sc = device_get_softc(pcib);
2588 *bus = PCI_RID2BUS(rid);
2589 if (sc->flags & PCIB_ENABLE_ARI) {
2590 *slot = PCIE_ARI_RID2SLOT(rid);
2591 *func = PCIE_ARI_RID2FUNC(rid);
2593 *slot = PCI_RID2SLOT(rid);
2594 *func = PCI_RID2FUNC(rid);
2599 * Since we are a child of a PCI bus, its parent must support the pcib interface.
2602 pcib_read_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, int width)
2605 struct pcib_softc *sc;
2607 sc = device_get_softc(dev);
2608 if (!pcib_present(sc)) {
2615 return (0xffffffff);
2619 pcib_xlate_ari(dev, b, &s, &f);
2620 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s,
2625 pcib_write_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, int width)
2628 struct pcib_softc *sc;
2630 sc = device_get_softc(dev);
2631 if (!pcib_present(sc))
2634 pcib_xlate_ari(dev, b, &s, &f);
2635 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f,
2640 * Route an interrupt across a PCI bridge.
2643 pcib_route_interrupt(device_t pcib, device_t dev, int pin)
2651 * The PCI standard defines a swizzle of the child-side device/intpin to
2652 * the parent-side intpin as follows.
2654 * device = device on child bus
2655 * child_intpin = intpin on child bus slot (0-3)
2656 * parent_intpin = intpin on parent bus slot (0-3)
2658 * parent_intpin = (device + child_intpin) % 4
2660 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4;
2663 * Our parent is a PCI bus. Its parent must export the pcib interface
2664 * which includes the ability to route interrupts.
2666 bus = device_get_parent(pcib);
2667 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1);
2668 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) {
2669 device_printf(pcib, "slot %d INT%c is routed to irq %d\n",
2670 pci_get_slot(dev), 'A' + pin - 1, intnum);
2675 /* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */
2677 pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs)
2679 struct pcib_softc *sc = device_get_softc(pcib);
2682 if (sc->flags & PCIB_DISABLE_MSI)
2684 bus = device_get_parent(pcib);
2685 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount,
2689 /* Pass request to release MSI/MSI-X messages up to the parent bridge. */
2691 pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs)
2695 bus = device_get_parent(pcib);
2696 return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs));
2699 /* Pass request to alloc an MSI-X message up to the parent bridge. */
2701 pcib_alloc_msix(device_t pcib, device_t dev, int *irq)
2703 struct pcib_softc *sc = device_get_softc(pcib);
2706 if (sc->flags & PCIB_DISABLE_MSIX)
2708 bus = device_get_parent(pcib);
2709 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq));
2712 /* Pass request to release an MSI-X message up to the parent bridge. */
2714 pcib_release_msix(device_t pcib, device_t dev, int irq)
2718 bus = device_get_parent(pcib);
2719 return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq));
2722 /* Pass request to map MSI/MSI-X message up to parent bridge. */
2724 pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
2730 bus = device_get_parent(pcib);
2731 error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data);
2735 pci_ht_map_msi(pcib, *addr);
2739 /* Pass request for device power state up to parent bridge. */
2741 pcib_power_for_sleep(device_t pcib, device_t dev, int *pstate)
2745 bus = device_get_parent(pcib);
2746 return (PCIB_POWER_FOR_SLEEP(bus, dev, pstate));
2750 pcib_ari_enabled(device_t pcib)
2752 struct pcib_softc *sc;
2754 sc = device_get_softc(pcib);
2756 return ((sc->flags & PCIB_ENABLE_ARI) != 0);
2760 pcib_ari_get_id(device_t pcib, device_t dev, enum pci_id_type type,
2763 struct pcib_softc *sc;
2765 uint8_t bus, slot, func;
2767 if (type != PCI_ID_RID) {
2768 bus_dev = device_get_parent(pcib);
2769 return (PCIB_GET_ID(device_get_parent(bus_dev), dev, type, id));
2772 sc = device_get_softc(pcib);
2774 if (sc->flags & PCIB_ENABLE_ARI) {
2775 bus = pci_get_bus(dev);
2776 func = pci_get_function(dev);
2778 *id = (PCI_ARI_RID(bus, func));
2780 bus = pci_get_bus(dev);
2781 slot = pci_get_slot(dev);
2782 func = pci_get_function(dev);
2784 *id = (PCI_RID(bus, slot, func));
2791 * Check that the downstream port (pcib) and the endpoint device (dev) both
2792 * support ARI. If so, enable it and return 0, otherwise return an error.
2795 pcib_try_enable_ari(device_t pcib, device_t dev)
2797 struct pcib_softc *sc;
2804 sc = device_get_softc(pcib);
2807 * ARI is controlled in a register in the PCIe capability structure.
2808 * If the downstream port does not have the PCIe capability structure
2809 * then it does not support ARI.
2811 error = pci_find_cap(pcib, PCIY_EXPRESS, &pcie_pos);
2815 /* Check that the PCIe port advertises ARI support. */
2816 cap2 = pci_read_config(pcib, pcie_pos + PCIER_DEVICE_CAP2, 4);
2817 if (!(cap2 & PCIEM_CAP2_ARI))
2821 * Check that the endpoint device advertises ARI support via the ARI
2822 * extended capability structure.
2824 error = pci_find_extcap(dev, PCIZ_ARI, &ari_cap_off);
2829 * Finally, check that the endpoint device supports the same version
2830 * of ARI that we do.
2832 ari_ver = pci_read_config(dev, ari_cap_off, 4);
2833 if (PCI_EXTCAP_VER(ari_ver) != PCIB_SUPPORTED_ARI_VER) {
2836 "Unsupported version of ARI (%d) detected\n",
2837 PCI_EXTCAP_VER(ari_ver));
2842 pcib_enable_ari(sc, pcie_pos);
2848 pcib_request_feature_allow(device_t pcib, device_t dev,
2849 enum pci_feature feature)
2852 * No host firmware we have to negotiate with, so we allow
2853 * every valid feature requested.
2856 case PCI_FEATURE_AER:
2857 case PCI_FEATURE_HP:
2867 * Pass the request to use this PCI feature up the tree. Either there's a
2868 * firmware like ACPI that's using this feature that will approve (or deny) the
2869 * request to take it over, or the platform has no such firmware, in which case
2870 * the request will be approved. If the request is approved, the OS is expected
2871 * to make use of the feature or render it harmless.
2874 pcib_request_feature(device_t pcib, device_t dev, enum pci_feature feature)
2879 * Our parent is necessarily a pci bus. Its parent will either be
2880 * another pci bridge (which passes it up) or a host bridge that can
2881 * approve or reject the request.
2883 bus = device_get_parent(pcib);
2884 return (PCIB_REQUEST_FEATURE(device_get_parent(bus), dev, feature));