2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
5 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
6 * Copyright (c) 2000 BSDi
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. The name of the author may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * PCI:PCI bridge support.
42 #include <sys/param.h>
44 #include <sys/kernel.h>
46 #include <sys/malloc.h>
47 #include <sys/module.h>
48 #include <sys/mutex.h>
49 #include <sys/pciio.h>
51 #include <sys/sysctl.h>
52 #include <sys/systm.h>
53 #include <sys/taskqueue.h>
55 #include <dev/pci/pcivar.h>
56 #include <dev/pci/pcireg.h>
57 #include <dev/pci/pci_private.h>
58 #include <dev/pci/pcib_private.h>
62 static int pcib_probe(device_t dev);
63 static int pcib_suspend(device_t dev);
64 static int pcib_resume(device_t dev);
65 static int pcib_power_for_sleep(device_t pcib, device_t dev,
67 static int pcib_ari_get_id(device_t pcib, device_t dev,
68 enum pci_id_type type, uintptr_t *id);
69 static uint32_t pcib_read_config(device_t dev, u_int b, u_int s,
70 u_int f, u_int reg, int width);
71 static void pcib_write_config(device_t dev, u_int b, u_int s,
72 u_int f, u_int reg, uint32_t val, int width);
73 static int pcib_ari_maxslots(device_t dev);
74 static int pcib_ari_maxfuncs(device_t dev);
75 static int pcib_try_enable_ari(device_t pcib, device_t dev);
76 static int pcib_ari_enabled(device_t pcib);
77 static void pcib_ari_decode_rid(device_t pcib, uint16_t rid,
78 int *bus, int *slot, int *func);
80 static void pcib_pcie_ab_timeout(void *arg);
81 static void pcib_pcie_cc_timeout(void *arg);
82 static void pcib_pcie_dll_timeout(void *arg);
84 static int pcib_request_feature_default(device_t pcib, device_t dev,
85 enum pci_feature feature);
86 static int pcib_reset_child(device_t dev, device_t child, int flags);
88 static device_method_t pcib_methods[] = {
89 /* Device interface */
90 DEVMETHOD(device_probe, pcib_probe),
91 DEVMETHOD(device_attach, pcib_attach),
92 DEVMETHOD(device_detach, pcib_detach),
93 DEVMETHOD(device_shutdown, bus_generic_shutdown),
94 DEVMETHOD(device_suspend, pcib_suspend),
95 DEVMETHOD(device_resume, pcib_resume),
98 DEVMETHOD(bus_child_present, pcib_child_present),
99 DEVMETHOD(bus_read_ivar, pcib_read_ivar),
100 DEVMETHOD(bus_write_ivar, pcib_write_ivar),
101 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
103 DEVMETHOD(bus_adjust_resource, pcib_adjust_resource),
104 DEVMETHOD(bus_release_resource, pcib_release_resource),
106 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
107 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
109 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
110 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
111 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
112 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
113 DEVMETHOD(bus_reset_child, pcib_reset_child),
116 DEVMETHOD(pcib_maxslots, pcib_ari_maxslots),
117 DEVMETHOD(pcib_maxfuncs, pcib_ari_maxfuncs),
118 DEVMETHOD(pcib_read_config, pcib_read_config),
119 DEVMETHOD(pcib_write_config, pcib_write_config),
120 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
121 DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi),
122 DEVMETHOD(pcib_release_msi, pcib_release_msi),
123 DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix),
124 DEVMETHOD(pcib_release_msix, pcib_release_msix),
125 DEVMETHOD(pcib_map_msi, pcib_map_msi),
126 DEVMETHOD(pcib_power_for_sleep, pcib_power_for_sleep),
127 DEVMETHOD(pcib_get_id, pcib_ari_get_id),
128 DEVMETHOD(pcib_try_enable_ari, pcib_try_enable_ari),
129 DEVMETHOD(pcib_ari_enabled, pcib_ari_enabled),
130 DEVMETHOD(pcib_decode_rid, pcib_ari_decode_rid),
131 DEVMETHOD(pcib_request_feature, pcib_request_feature_default),
136 static devclass_t pcib_devclass;
138 DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc));
139 EARLY_DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, NULL, NULL,
142 #if defined(NEW_PCIB) || defined(PCI_HP)
143 SYSCTL_DECL(_hw_pci);
147 static int pci_clear_pcib;
148 SYSCTL_INT(_hw_pci, OID_AUTO, clear_pcib, CTLFLAG_RDTUN, &pci_clear_pcib, 0,
149 "Clear firmware-assigned resources for PCI-PCI bridge I/O windows.");
152 * Is a resource from a child device sub-allocated from one of our
156 pcib_is_resource_managed(struct pcib_softc *sc, int type, struct resource *r)
162 return (rman_is_region_manager(r, &sc->bus.rman));
165 return (rman_is_region_manager(r, &sc->io.rman));
167 /* Prefetchable resources may live in either memory rman. */
168 if (rman_get_flags(r) & RF_PREFETCHABLE &&
169 rman_is_region_manager(r, &sc->pmem.rman))
171 return (rman_is_region_manager(r, &sc->mem.rman));
177 pcib_is_window_open(struct pcib_window *pw)
180 return (pw->valid && pw->base < pw->limit);
184 * XXX: If RF_ACTIVE did not also imply allocating a bus space tag and
185 * handle for the resource, we could pass RF_ACTIVE up to the PCI bus
186 * when allocating the resource windows and rely on the PCI bus driver
190 pcib_activate_window(struct pcib_softc *sc, int type)
193 PCI_ENABLE_IO(device_get_parent(sc->dev), sc->dev, type);
197 pcib_write_windows(struct pcib_softc *sc, int mask)
203 if (sc->io.valid && mask & WIN_IO) {
204 val = pci_read_config(dev, PCIR_IOBASEL_1, 1);
205 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
206 pci_write_config(dev, PCIR_IOBASEH_1,
207 sc->io.base >> 16, 2);
208 pci_write_config(dev, PCIR_IOLIMITH_1,
209 sc->io.limit >> 16, 2);
211 pci_write_config(dev, PCIR_IOBASEL_1, sc->io.base >> 8, 1);
212 pci_write_config(dev, PCIR_IOLIMITL_1, sc->io.limit >> 8, 1);
215 if (mask & WIN_MEM) {
216 pci_write_config(dev, PCIR_MEMBASE_1, sc->mem.base >> 16, 2);
217 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->mem.limit >> 16, 2);
220 if (sc->pmem.valid && mask & WIN_PMEM) {
221 val = pci_read_config(dev, PCIR_PMBASEL_1, 2);
222 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) {
223 pci_write_config(dev, PCIR_PMBASEH_1,
224 sc->pmem.base >> 32, 4);
225 pci_write_config(dev, PCIR_PMLIMITH_1,
226 sc->pmem.limit >> 32, 4);
228 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmem.base >> 16, 2);
229 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmem.limit >> 16, 2);
234 * This is used to reject I/O port allocations that conflict with an
238 pcib_is_isa_range(struct pcib_softc *sc, rman_res_t start, rman_res_t end,
241 rman_res_t next_alias;
243 if (!(sc->bridgectl & PCIB_BCR_ISA_ENABLE))
246 /* Only check fixed ranges for overlap. */
247 if (start + count - 1 != end)
250 /* ISA aliases are only in the lower 64KB of I/O space. */
254 /* Check for overlap with 0x000 - 0x0ff as a special case. */
259 * If the start address is an alias, the range is an alias.
260 * Otherwise, compute the start of the next alias range and
261 * check if it is before the end of the candidate range.
263 if ((start & 0x300) != 0)
265 next_alias = (start & ~0x3fful) | 0x100;
266 if (next_alias <= end)
272 device_printf(sc->dev,
273 "I/O range %#jx-%#jx overlaps with an ISA alias\n", start,
279 pcib_add_window_resources(struct pcib_window *w, struct resource **res,
282 struct resource **newarray;
285 newarray = malloc(sizeof(struct resource *) * (w->count + count),
288 bcopy(w->res, newarray, sizeof(struct resource *) * w->count);
289 bcopy(res, newarray + w->count, sizeof(struct resource *) * count);
290 free(w->res, M_DEVBUF);
294 for (i = 0; i < count; i++) {
295 error = rman_manage_region(&w->rman, rman_get_start(res[i]),
296 rman_get_end(res[i]));
298 panic("Failed to add resource to rman");
302 typedef void (nonisa_callback)(rman_res_t start, rman_res_t end, void *arg);
305 pcib_walk_nonisa_ranges(rman_res_t start, rman_res_t end, nonisa_callback *cb,
311 * If start is within an ISA alias range, move up to the start
312 * of the next non-alias range. As a special case, addresses
313 * in the range 0x000 - 0x0ff should also be skipped since
314 * those are used for various system I/O devices in ISA
317 if (start <= 65535) {
318 if (start < 0x100 || (start & 0x300) != 0) {
324 /* ISA aliases are only in the lower 64KB of I/O space. */
325 while (start <= MIN(end, 65535)) {
326 next_end = MIN(start | 0xff, end);
327 cb(start, next_end, arg);
336 count_ranges(rman_res_t start, rman_res_t end, void *arg)
345 struct resource **res;
346 struct pcib_softc *sc;
351 alloc_ranges(rman_res_t start, rman_res_t end, void *arg)
353 struct alloc_state *as;
354 struct pcib_window *w;
364 device_printf(as->sc->dev,
365 "allocating non-ISA range %#jx-%#jx\n", start, end);
366 as->res[as->count] = bus_alloc_resource(as->sc->dev, SYS_RES_IOPORT,
367 &rid, start, end, end - start + 1, 0);
368 if (as->res[as->count] == NULL)
375 pcib_alloc_nonisa_ranges(struct pcib_softc *sc, rman_res_t start, rman_res_t end)
377 struct alloc_state as;
380 /* First, see how many ranges we need. */
382 pcib_walk_nonisa_ranges(start, end, count_ranges, &new_count);
384 /* Second, allocate the ranges. */
385 as.res = malloc(sizeof(struct resource *) * new_count, M_DEVBUF,
390 pcib_walk_nonisa_ranges(start, end, alloc_ranges, &as);
392 for (i = 0; i < as.count; i++)
393 bus_release_resource(sc->dev, SYS_RES_IOPORT,
394 sc->io.reg, as.res[i]);
395 free(as.res, M_DEVBUF);
398 KASSERT(as.count == new_count, ("%s: count mismatch", __func__));
400 /* Third, add the ranges to the window. */
401 pcib_add_window_resources(&sc->io, as.res, as.count);
402 free(as.res, M_DEVBUF);
407 pcib_alloc_window(struct pcib_softc *sc, struct pcib_window *w, int type,
408 int flags, pci_addr_t max_address)
410 struct resource *res;
414 if (max_address != (rman_res_t)max_address)
416 w->rman.rm_start = 0;
417 w->rman.rm_end = max_address;
418 w->rman.rm_type = RMAN_ARRAY;
419 snprintf(buf, sizeof(buf), "%s %s window",
420 device_get_nameunit(sc->dev), w->name);
421 w->rman.rm_descr = strdup(buf, M_DEVBUF);
422 error = rman_init(&w->rman);
424 panic("Failed to initialize %s %s rman",
425 device_get_nameunit(sc->dev), w->name);
427 if (!pcib_is_window_open(w))
430 if (w->base > max_address || w->limit > max_address) {
431 device_printf(sc->dev,
432 "initial %s window has too many bits, ignoring\n", w->name);
435 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE)
436 (void)pcib_alloc_nonisa_ranges(sc, w->base, w->limit);
439 res = bus_alloc_resource(sc->dev, type, &rid, w->base, w->limit,
440 w->limit - w->base + 1, flags);
442 pcib_add_window_resources(w, &res, 1);
444 if (w->res == NULL) {
445 device_printf(sc->dev,
446 "failed to allocate initial %s window: %#jx-%#jx\n",
447 w->name, (uintmax_t)w->base, (uintmax_t)w->limit);
448 w->base = max_address;
450 pcib_write_windows(sc, w->mask);
453 pcib_activate_window(sc, type);
457 * Initialize I/O windows.
460 pcib_probe_windows(struct pcib_softc *sc)
468 if (pci_clear_pcib) {
469 pcib_bridge_init(dev);
472 /* Determine if the I/O port window is implemented. */
473 val = pci_read_config(dev, PCIR_IOBASEL_1, 1);
476 * If 'val' is zero, then only 16-bits of I/O space
479 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1);
480 if (pci_read_config(dev, PCIR_IOBASEL_1, 1) != 0) {
482 pci_write_config(dev, PCIR_IOBASEL_1, 0, 1);
487 /* Read the existing I/O port window. */
489 sc->io.reg = PCIR_IOBASEL_1;
491 sc->io.mask = WIN_IO;
492 sc->io.name = "I/O port";
493 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
494 sc->io.base = PCI_PPBIOBASE(
495 pci_read_config(dev, PCIR_IOBASEH_1, 2), val);
496 sc->io.limit = PCI_PPBIOLIMIT(
497 pci_read_config(dev, PCIR_IOLIMITH_1, 2),
498 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
501 sc->io.base = PCI_PPBIOBASE(0, val);
502 sc->io.limit = PCI_PPBIOLIMIT(0,
503 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
506 pcib_alloc_window(sc, &sc->io, SYS_RES_IOPORT, 0, max);
509 /* Read the existing memory window. */
511 sc->mem.reg = PCIR_MEMBASE_1;
513 sc->mem.mask = WIN_MEM;
514 sc->mem.name = "memory";
515 sc->mem.base = PCI_PPBMEMBASE(0,
516 pci_read_config(dev, PCIR_MEMBASE_1, 2));
517 sc->mem.limit = PCI_PPBMEMLIMIT(0,
518 pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
519 pcib_alloc_window(sc, &sc->mem, SYS_RES_MEMORY, 0, 0xffffffff);
521 /* Determine if the prefetchable memory window is implemented. */
522 val = pci_read_config(dev, PCIR_PMBASEL_1, 2);
525 * If 'val' is zero, then only 32-bits of memory space
528 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2);
529 if (pci_read_config(dev, PCIR_PMBASEL_1, 2) != 0) {
531 pci_write_config(dev, PCIR_PMBASEL_1, 0, 2);
536 /* Read the existing prefetchable memory window. */
537 if (sc->pmem.valid) {
538 sc->pmem.reg = PCIR_PMBASEL_1;
540 sc->pmem.mask = WIN_PMEM;
541 sc->pmem.name = "prefetch";
542 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) {
543 sc->pmem.base = PCI_PPBMEMBASE(
544 pci_read_config(dev, PCIR_PMBASEH_1, 4), val);
545 sc->pmem.limit = PCI_PPBMEMLIMIT(
546 pci_read_config(dev, PCIR_PMLIMITH_1, 4),
547 pci_read_config(dev, PCIR_PMLIMITL_1, 2));
548 max = 0xffffffffffffffff;
550 sc->pmem.base = PCI_PPBMEMBASE(0, val);
551 sc->pmem.limit = PCI_PPBMEMLIMIT(0,
552 pci_read_config(dev, PCIR_PMLIMITL_1, 2));
555 pcib_alloc_window(sc, &sc->pmem, SYS_RES_MEMORY,
556 RF_PREFETCHABLE, max);
561 pcib_release_window(struct pcib_softc *sc, struct pcib_window *w, int type)
570 error = rman_fini(&w->rman);
572 device_printf(dev, "failed to release %s rman\n", w->name);
575 free(__DECONST(char *, w->rman.rm_descr), M_DEVBUF);
577 for (i = 0; i < w->count; i++) {
578 error = bus_free_resource(dev, type, w->res[i]);
581 "failed to release %s resource: %d\n", w->name,
584 free(w->res, M_DEVBUF);
588 pcib_free_windows(struct pcib_softc *sc)
591 pcib_release_window(sc, &sc->pmem, SYS_RES_MEMORY);
592 pcib_release_window(sc, &sc->mem, SYS_RES_MEMORY);
593 pcib_release_window(sc, &sc->io, SYS_RES_IOPORT);
598 * Allocate a suitable secondary bus for this bridge if needed and
599 * initialize the resource manager for the secondary bus range. Note
600 * that the minimum count is a desired value and this may allocate a
604 pcib_setup_secbus(device_t dev, struct pcib_secbus *bus, int min_count)
607 int error, rid, sec_reg;
609 switch (pci_read_config(dev, PCIR_HDRTYPE, 1) & PCIM_HDRTYPE) {
610 case PCIM_HDRTYPE_BRIDGE:
611 sec_reg = PCIR_SECBUS_1;
612 bus->sub_reg = PCIR_SUBBUS_1;
614 case PCIM_HDRTYPE_CARDBUS:
615 sec_reg = PCIR_SECBUS_2;
616 bus->sub_reg = PCIR_SUBBUS_2;
619 panic("not a PCI bridge");
621 bus->sec = pci_read_config(dev, sec_reg, 1);
622 bus->sub = pci_read_config(dev, bus->sub_reg, 1);
624 bus->rman.rm_start = 0;
625 bus->rman.rm_end = PCI_BUSMAX;
626 bus->rman.rm_type = RMAN_ARRAY;
627 snprintf(buf, sizeof(buf), "%s bus numbers", device_get_nameunit(dev));
628 bus->rman.rm_descr = strdup(buf, M_DEVBUF);
629 error = rman_init(&bus->rman);
631 panic("Failed to initialize %s bus number rman",
632 device_get_nameunit(dev));
635 * Allocate a bus range. This will return an existing bus range
636 * if one exists, or a new bus range if one does not.
639 bus->res = bus_alloc_resource_anywhere(dev, PCI_RES_BUS, &rid,
641 if (bus->res == NULL) {
643 * Fall back to just allocating a range of a single bus
646 bus->res = bus_alloc_resource_anywhere(dev, PCI_RES_BUS, &rid,
648 } else if (rman_get_size(bus->res) < min_count)
650 * Attempt to grow the existing range to satisfy the
651 * minimum desired count.
653 (void)bus_adjust_resource(dev, PCI_RES_BUS, bus->res,
654 rman_get_start(bus->res), rman_get_start(bus->res) +
658 * Add the initial resource to the rman.
660 if (bus->res != NULL) {
661 error = rman_manage_region(&bus->rman, rman_get_start(bus->res),
662 rman_get_end(bus->res));
664 panic("Failed to add resource to rman");
665 bus->sec = rman_get_start(bus->res);
666 bus->sub = rman_get_end(bus->res);
671 pcib_free_secbus(device_t dev, struct pcib_secbus *bus)
675 error = rman_fini(&bus->rman);
677 device_printf(dev, "failed to release bus number rman\n");
680 free(__DECONST(char *, bus->rman.rm_descr), M_DEVBUF);
682 error = bus_free_resource(dev, PCI_RES_BUS, bus->res);
685 "failed to release bus numbers resource: %d\n", error);
688 static struct resource *
689 pcib_suballoc_bus(struct pcib_secbus *bus, device_t child, int *rid,
690 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
692 struct resource *res;
694 res = rman_reserve_resource(&bus->rman, start, end, count, flags,
700 device_printf(bus->dev,
701 "allocated bus range (%ju-%ju) for rid %d of %s\n",
702 rman_get_start(res), rman_get_end(res), *rid,
703 pcib_child_name(child));
704 rman_set_rid(res, *rid);
709 * Attempt to grow the secondary bus range. This is much simpler than
710 * for I/O windows as the range can only be grown by increasing
714 pcib_grow_subbus(struct pcib_secbus *bus, rman_res_t new_end)
719 old_end = rman_get_end(bus->res);
720 KASSERT(new_end > old_end, ("attempt to shrink subbus"));
721 error = bus_adjust_resource(bus->dev, PCI_RES_BUS, bus->res,
722 rman_get_start(bus->res), new_end);
726 device_printf(bus->dev, "grew bus range to %ju-%ju\n",
727 rman_get_start(bus->res), rman_get_end(bus->res));
728 error = rman_manage_region(&bus->rman, old_end + 1,
729 rman_get_end(bus->res));
731 panic("Failed to add resource to rman");
732 bus->sub = rman_get_end(bus->res);
733 pci_write_config(bus->dev, bus->sub_reg, bus->sub, 1);
738 pcib_alloc_subbus(struct pcib_secbus *bus, device_t child, int *rid,
739 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
741 struct resource *res;
742 rman_res_t start_free, end_free, new_end;
745 * First, see if the request can be satisified by the existing
748 res = pcib_suballoc_bus(bus, child, rid, start, end, count, flags);
753 * Figure out a range to grow the bus range. First, find the
754 * first bus number after the last allocated bus in the rman and
755 * enforce that as a minimum starting point for the range.
757 if (rman_last_free_region(&bus->rman, &start_free, &end_free) != 0 ||
758 end_free != bus->sub)
759 start_free = bus->sub + 1;
760 if (start_free < start)
762 new_end = start_free + count - 1;
765 * See if this new range would satisfy the request if it
771 /* Finally, attempt to grow the existing resource. */
773 device_printf(bus->dev,
774 "attempting to grow bus range for %ju buses\n", count);
775 printf("\tback candidate range: %ju-%ju\n", start_free,
778 if (pcib_grow_subbus(bus, new_end) == 0)
779 return (pcib_suballoc_bus(bus, child, rid, start, end, count,
788 * Is the prefetch window open (eg, can we allocate memory in it?)
791 pcib_is_prefetch_open(struct pcib_softc *sc)
793 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit);
797 * Is the nonprefetch window open (eg, can we allocate memory in it?)
800 pcib_is_nonprefetch_open(struct pcib_softc *sc)
802 return (sc->membase > 0 && sc->membase < sc->memlimit);
806 * Is the io window open (eg, can we allocate ports in it?)
809 pcib_is_io_open(struct pcib_softc *sc)
811 return (sc->iobase > 0 && sc->iobase < sc->iolimit);
815 * Get current I/O decode.
818 pcib_get_io_decode(struct pcib_softc *sc)
825 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1);
826 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32)
827 sc->iobase = PCI_PPBIOBASE(
828 pci_read_config(dev, PCIR_IOBASEH_1, 2), iolow);
830 sc->iobase = PCI_PPBIOBASE(0, iolow);
832 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1);
833 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32)
834 sc->iolimit = PCI_PPBIOLIMIT(
835 pci_read_config(dev, PCIR_IOLIMITH_1, 2), iolow);
837 sc->iolimit = PCI_PPBIOLIMIT(0, iolow);
841 * Get current memory decode.
844 pcib_get_mem_decode(struct pcib_softc *sc)
851 sc->membase = PCI_PPBMEMBASE(0,
852 pci_read_config(dev, PCIR_MEMBASE_1, 2));
853 sc->memlimit = PCI_PPBMEMLIMIT(0,
854 pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
856 pmemlow = pci_read_config(dev, PCIR_PMBASEL_1, 2);
857 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64)
858 sc->pmembase = PCI_PPBMEMBASE(
859 pci_read_config(dev, PCIR_PMBASEH_1, 4), pmemlow);
861 sc->pmembase = PCI_PPBMEMBASE(0, pmemlow);
863 pmemlow = pci_read_config(dev, PCIR_PMLIMITL_1, 2);
864 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64)
865 sc->pmemlimit = PCI_PPBMEMLIMIT(
866 pci_read_config(dev, PCIR_PMLIMITH_1, 4), pmemlow);
868 sc->pmemlimit = PCI_PPBMEMLIMIT(0, pmemlow);
872 * Restore previous I/O decode.
875 pcib_set_io_decode(struct pcib_softc *sc)
882 iohi = sc->iobase >> 16;
884 pci_write_config(dev, PCIR_IOBASEH_1, iohi, 2);
885 pci_write_config(dev, PCIR_IOBASEL_1, sc->iobase >> 8, 1);
887 iohi = sc->iolimit >> 16;
889 pci_write_config(dev, PCIR_IOLIMITH_1, iohi, 2);
890 pci_write_config(dev, PCIR_IOLIMITL_1, sc->iolimit >> 8, 1);
894 * Restore previous memory decode.
897 pcib_set_mem_decode(struct pcib_softc *sc)
904 pci_write_config(dev, PCIR_MEMBASE_1, sc->membase >> 16, 2);
905 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->memlimit >> 16, 2);
907 pmemhi = sc->pmembase >> 32;
909 pci_write_config(dev, PCIR_PMBASEH_1, pmemhi, 4);
910 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmembase >> 16, 2);
912 pmemhi = sc->pmemlimit >> 32;
914 pci_write_config(dev, PCIR_PMLIMITH_1, pmemhi, 4);
915 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmemlimit >> 16, 2);
921 * PCI-express HotPlug support.
923 static int pci_enable_pcie_hp = 1;
924 SYSCTL_INT(_hw_pci, OID_AUTO, enable_pcie_hp, CTLFLAG_RDTUN,
925 &pci_enable_pcie_hp, 0,
926 "Enable support for native PCI-express HotPlug.");
929 pcib_probe_hotplug(struct pcib_softc *sc)
933 uint16_t link_sta, slot_sta;
935 if (!pci_enable_pcie_hp)
939 if (pci_find_cap(dev, PCIY_EXPRESS, NULL) != 0)
942 if (!(pcie_read_config(dev, PCIER_FLAGS, 2) & PCIEM_FLAGS_SLOT))
945 sc->pcie_slot_cap = pcie_read_config(dev, PCIER_SLOT_CAP, 4);
947 if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_HPC) == 0)
949 link_cap = pcie_read_config(dev, PCIER_LINK_CAP, 4);
950 if ((link_cap & PCIEM_LINK_CAP_DL_ACTIVE) == 0)
954 * Some devices report that they have an MRL when they actually
955 * do not. Since they always report that the MRL is open, child
956 * devices would be ignored. Try to detect these devices and
957 * ignore their claim of HotPlug support.
959 * If there is an open MRL but the Data Link Layer is active,
960 * the MRL is not real.
962 if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP) != 0) {
963 link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2);
964 slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2);
965 if ((slot_sta & PCIEM_SLOT_STA_MRLSS) != 0 &&
966 (link_sta & PCIEM_LINK_STA_DL_ACTIVE) != 0) {
972 * Now that we're sure we want to do hot plug, ask the
973 * firmware, if any, if that's OK.
975 if (pcib_request_feature(dev, PCI_FEATURE_HP) != 0) {
977 device_printf(dev, "Unable to activate hot plug feature.\n");
981 sc->flags |= PCIB_HOTPLUG;
985 * Send a HotPlug command to the slot control register. If this slot
986 * uses command completion interrupts and a previous command is still
987 * in progress, then the command is dropped. Once the previous
988 * command completes or times out, pcib_pcie_hotplug_update() will be
989 * invoked to post a new command based on the slot's state at that
993 pcib_pcie_hotplug_command(struct pcib_softc *sc, uint16_t val, uint16_t mask)
1000 if (sc->flags & PCIB_HOTPLUG_CMD_PENDING)
1003 ctl = pcie_read_config(dev, PCIER_SLOT_CTL, 2);
1004 new = (ctl & ~mask) | val;
1008 device_printf(dev, "HotPlug command: %04x -> %04x\n", ctl, new);
1009 pcie_write_config(dev, PCIER_SLOT_CTL, new, 2);
1010 if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS) &&
1011 (ctl & new) & PCIEM_SLOT_CTL_CCIE) {
1012 sc->flags |= PCIB_HOTPLUG_CMD_PENDING;
1014 callout_reset(&sc->pcie_cc_timer, hz,
1015 pcib_pcie_cc_timeout, sc);
1020 pcib_pcie_hotplug_command_completed(struct pcib_softc *sc)
1027 device_printf(dev, "Command Completed\n");
1028 if (!(sc->flags & PCIB_HOTPLUG_CMD_PENDING))
1030 callout_stop(&sc->pcie_cc_timer);
1031 sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING;
1036 * Returns true if a card is fully inserted from the user's
1037 * perspective. It may not yet be ready for access, but the driver
1038 * can now start enabling access if necessary.
1041 pcib_hotplug_inserted(struct pcib_softc *sc)
1044 /* Pretend the card isn't present if a detach is forced. */
1045 if (sc->flags & PCIB_DETACHING)
1048 /* Card must be present in the slot. */
1049 if ((sc->pcie_slot_sta & PCIEM_SLOT_STA_PDS) == 0)
1052 /* A power fault implicitly turns off power to the slot. */
1053 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_PFD)
1056 /* If the MRL is disengaged, the slot is powered off. */
1057 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP &&
1058 (sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSS) != 0)
1065 * Returns -1 if the card is fully inserted, powered, and ready for
1066 * access. Otherwise, returns 0.
1069 pcib_hotplug_present(struct pcib_softc *sc)
1072 /* Card must be inserted. */
1073 if (!pcib_hotplug_inserted(sc))
1076 /* Require the Data Link Layer to be active. */
1077 if (!(sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE))
1084 pcib_pcie_hotplug_update(struct pcib_softc *sc, uint16_t val, uint16_t mask,
1087 bool card_inserted, ei_engaged;
1089 /* Clear DETACHING if Presence Detect has cleared. */
1090 if ((sc->pcie_slot_sta & (PCIEM_SLOT_STA_PDC | PCIEM_SLOT_STA_PDS)) ==
1092 sc->flags &= ~PCIB_DETACHING;
1094 card_inserted = pcib_hotplug_inserted(sc);
1096 /* Turn the power indicator on if a card is inserted. */
1097 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PIP) {
1098 mask |= PCIEM_SLOT_CTL_PIC;
1100 val |= PCIEM_SLOT_CTL_PI_ON;
1101 else if (sc->flags & PCIB_DETACH_PENDING)
1102 val |= PCIEM_SLOT_CTL_PI_BLINK;
1104 val |= PCIEM_SLOT_CTL_PI_OFF;
1107 /* Turn the power on via the Power Controller if a card is inserted. */
1108 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PCP) {
1109 mask |= PCIEM_SLOT_CTL_PCC;
1111 val |= PCIEM_SLOT_CTL_PC_ON;
1113 val |= PCIEM_SLOT_CTL_PC_OFF;
1117 * If a card is inserted, enable the Electromechanical
1118 * Interlock. If a card is not inserted (or we are in the
1119 * process of detaching), disable the Electromechanical
1122 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_EIP) {
1123 mask |= PCIEM_SLOT_CTL_EIC;
1124 ei_engaged = (sc->pcie_slot_sta & PCIEM_SLOT_STA_EIS) != 0;
1125 if (card_inserted != ei_engaged)
1126 val |= PCIEM_SLOT_CTL_EIC;
1130 * Start a timer to see if the Data Link Layer times out.
1131 * Note that we only start the timer if Presence Detect or MRL Sensor
1132 * changed on this interrupt. Stop any scheduled timer if
1133 * the Data Link Layer is active.
1135 if (card_inserted &&
1136 !(sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE) &&
1138 (PCIEM_SLOT_STA_MRLSC | PCIEM_SLOT_STA_PDC)) {
1140 device_printf(sc->dev,
1141 "Data Link Layer inactive\n");
1143 callout_reset(&sc->pcie_dll_timer, hz,
1144 pcib_pcie_dll_timeout, sc);
1145 } else if (sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE)
1146 callout_stop(&sc->pcie_dll_timer);
1148 pcib_pcie_hotplug_command(sc, val, mask);
1151 * During attach the child "pci" device is added synchronously;
1152 * otherwise, the task is scheduled to manage the child
1155 if (schedule_task &&
1156 (pcib_hotplug_present(sc) != 0) != (sc->child != NULL))
1157 taskqueue_enqueue(taskqueue_thread, &sc->pcie_hp_task);
1161 pcib_pcie_intr_hotplug(void *arg)
1163 struct pcib_softc *sc;
1165 uint16_t old_slot_sta;
1170 old_slot_sta = sc->pcie_slot_sta;
1171 sc->pcie_slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2);
1173 /* Clear the events just reported. */
1174 pcie_write_config(dev, PCIER_SLOT_STA, sc->pcie_slot_sta, 2);
1177 device_printf(dev, "HotPlug interrupt: %#x\n",
1180 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_ABP) {
1181 if (sc->flags & PCIB_DETACH_PENDING) {
1183 "Attention Button Pressed: Detach Cancelled\n");
1184 sc->flags &= ~PCIB_DETACH_PENDING;
1185 callout_stop(&sc->pcie_ab_timer);
1186 } else if (old_slot_sta & PCIEM_SLOT_STA_PDS) {
1187 /* Only initiate detach sequence if device present. */
1189 "Attention Button Pressed: Detaching in 5 seconds\n");
1190 sc->flags |= PCIB_DETACH_PENDING;
1191 callout_reset(&sc->pcie_ab_timer, 5 * hz,
1192 pcib_pcie_ab_timeout, sc);
1195 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_PFD)
1196 device_printf(dev, "Power Fault Detected\n");
1197 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSC)
1198 device_printf(dev, "MRL Sensor Changed to %s\n",
1199 sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSS ? "open" :
1201 if (bootverbose && sc->pcie_slot_sta & PCIEM_SLOT_STA_PDC)
1202 device_printf(dev, "Presence Detect Changed to %s\n",
1203 sc->pcie_slot_sta & PCIEM_SLOT_STA_PDS ? "card present" :
1205 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_CC)
1206 pcib_pcie_hotplug_command_completed(sc);
1207 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_DLLSC) {
1208 sc->pcie_link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2);
1211 "Data Link Layer State Changed to %s\n",
1212 sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE ?
1213 "active" : "inactive");
1216 pcib_pcie_hotplug_update(sc, 0, 0, true);
1221 pcib_pcie_hotplug_task(void *context, int pending)
1223 struct pcib_softc *sc;
1229 if (pcib_hotplug_present(sc) != 0) {
1230 if (sc->child == NULL) {
1231 sc->child = device_add_child(dev, "pci", -1);
1232 bus_generic_attach(dev);
1235 if (sc->child != NULL) {
1236 if (device_delete_child(dev, sc->child) == 0)
1244 pcib_pcie_ab_timeout(void *arg)
1246 struct pcib_softc *sc;
1249 PCIB_HP_LOCK_ASSERT(sc);
1250 if (sc->flags & PCIB_DETACH_PENDING) {
1251 sc->flags |= PCIB_DETACHING;
1252 sc->flags &= ~PCIB_DETACH_PENDING;
1253 pcib_pcie_hotplug_update(sc, 0, 0, true);
1258 pcib_pcie_cc_timeout(void *arg)
1260 struct pcib_softc *sc;
1266 PCIB_HP_LOCK_ASSERT(sc);
1267 sta = pcie_read_config(dev, PCIER_SLOT_STA, 2);
1268 if (!(sta & PCIEM_SLOT_STA_CC)) {
1269 device_printf(dev, "HotPlug Command Timed Out\n");
1270 sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING;
1273 "Missed HotPlug interrupt waiting for Command Completion\n");
1274 pcib_pcie_intr_hotplug(sc);
1279 pcib_pcie_dll_timeout(void *arg)
1281 struct pcib_softc *sc;
1287 PCIB_HP_LOCK_ASSERT(sc);
1288 sta = pcie_read_config(dev, PCIER_LINK_STA, 2);
1289 if (!(sta & PCIEM_LINK_STA_DL_ACTIVE)) {
1291 "Timed out waiting for Data Link Layer Active\n");
1292 sc->flags |= PCIB_DETACHING;
1293 pcib_pcie_hotplug_update(sc, 0, 0, true);
1294 } else if (sta != sc->pcie_link_sta) {
1296 "Missed HotPlug interrupt waiting for DLL Active\n");
1297 pcib_pcie_intr_hotplug(sc);
1302 pcib_alloc_pcie_irq(struct pcib_softc *sc)
1305 int count, error, rid;
1311 * For simplicity, only use MSI-X if there is a single message.
1312 * To support a device with multiple messages we would have to
1313 * use remap intr if the MSI number is not 0.
1315 count = pci_msix_count(dev);
1317 error = pci_alloc_msix(dev, &count);
1322 if (rid < 0 && pci_msi_count(dev) > 0) {
1324 error = pci_alloc_msi(dev, &count);
1332 sc->pcie_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1333 RF_ACTIVE | RF_SHAREABLE);
1334 if (sc->pcie_irq == NULL) {
1336 "Failed to allocate interrupt for PCI-e events\n");
1338 pci_release_msi(dev);
1342 error = bus_setup_intr(dev, sc->pcie_irq, INTR_TYPE_MISC|INTR_MPSAFE,
1343 NULL, pcib_pcie_intr_hotplug, sc, &sc->pcie_ihand);
1345 device_printf(dev, "Failed to setup PCI-e interrupt handler\n");
1346 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->pcie_irq);
1348 pci_release_msi(dev);
1355 pcib_release_pcie_irq(struct pcib_softc *sc)
1361 error = bus_teardown_intr(dev, sc->pcie_irq, sc->pcie_ihand);
1364 error = bus_free_resource(dev, SYS_RES_IRQ, sc->pcie_irq);
1367 return (pci_release_msi(dev));
1371 pcib_setup_hotplug(struct pcib_softc *sc)
1377 callout_init(&sc->pcie_ab_timer, 0);
1378 callout_init(&sc->pcie_cc_timer, 0);
1379 callout_init(&sc->pcie_dll_timer, 0);
1380 TASK_INIT(&sc->pcie_hp_task, 0, pcib_pcie_hotplug_task, sc);
1381 sc->pcie_hp_lock = &Giant;
1384 if (pcib_alloc_pcie_irq(sc) != 0)
1387 sc->pcie_link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2);
1388 sc->pcie_slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2);
1390 /* Clear any events previously pending. */
1391 pcie_write_config(dev, PCIER_SLOT_STA, sc->pcie_slot_sta, 2);
1393 /* Enable HotPlug events. */
1394 mask = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE |
1395 PCIEM_SLOT_CTL_CCIE | PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_MRLSCE |
1396 PCIEM_SLOT_CTL_PFDE | PCIEM_SLOT_CTL_ABPE;
1397 val = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE | PCIEM_SLOT_CTL_PDCE;
1398 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_APB)
1399 val |= PCIEM_SLOT_CTL_ABPE;
1400 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PCP)
1401 val |= PCIEM_SLOT_CTL_PFDE;
1402 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP)
1403 val |= PCIEM_SLOT_CTL_MRLSCE;
1404 if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS))
1405 val |= PCIEM_SLOT_CTL_CCIE;
1407 /* Turn the attention indicator off. */
1408 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_AIP) {
1409 mask |= PCIEM_SLOT_CTL_AIC;
1410 val |= PCIEM_SLOT_CTL_AI_OFF;
1413 pcib_pcie_hotplug_update(sc, val, mask, false);
1417 pcib_detach_hotplug(struct pcib_softc *sc)
1422 /* Disable the card in the slot and force it to detach. */
1423 if (sc->flags & PCIB_DETACH_PENDING) {
1424 sc->flags &= ~PCIB_DETACH_PENDING;
1425 callout_stop(&sc->pcie_ab_timer);
1427 sc->flags |= PCIB_DETACHING;
1429 if (sc->flags & PCIB_HOTPLUG_CMD_PENDING) {
1430 callout_stop(&sc->pcie_cc_timer);
1431 tsleep(sc, 0, "hpcmd", hz);
1432 sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING;
1435 /* Disable HotPlug events. */
1436 mask = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE |
1437 PCIEM_SLOT_CTL_CCIE | PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_MRLSCE |
1438 PCIEM_SLOT_CTL_PFDE | PCIEM_SLOT_CTL_ABPE;
1441 /* Turn the attention indicator off. */
1442 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_AIP) {
1443 mask |= PCIEM_SLOT_CTL_AIC;
1444 val |= PCIEM_SLOT_CTL_AI_OFF;
1447 pcib_pcie_hotplug_update(sc, val, mask, false);
1449 error = pcib_release_pcie_irq(sc);
1452 taskqueue_drain(taskqueue_thread, &sc->pcie_hp_task);
1453 callout_drain(&sc->pcie_ab_timer);
1454 callout_drain(&sc->pcie_cc_timer);
1455 callout_drain(&sc->pcie_dll_timer);
1461 * Get current bridge configuration.
1464 pcib_cfg_save(struct pcib_softc *sc)
1472 command = pci_read_config(dev, PCIR_COMMAND, 2);
1473 if (command & PCIM_CMD_PORTEN)
1474 pcib_get_io_decode(sc);
1475 if (command & PCIM_CMD_MEMEN)
1476 pcib_get_mem_decode(sc);
1481 * Restore previous bridge configuration.
1484 pcib_cfg_restore(struct pcib_softc *sc)
1491 pcib_write_windows(sc, WIN_IO | WIN_MEM | WIN_PMEM);
1493 command = pci_read_config(sc->dev, PCIR_COMMAND, 2);
1494 if (command & PCIM_CMD_PORTEN)
1495 pcib_set_io_decode(sc);
1496 if (command & PCIM_CMD_MEMEN)
1497 pcib_set_mem_decode(sc);
1502 * Generic device interface
1505 pcib_probe(device_t dev)
1507 if ((pci_get_class(dev) == PCIC_BRIDGE) &&
1508 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) {
1509 device_set_desc(dev, "PCI-PCI bridge");
1516 pcib_attach_common(device_t dev)
1518 struct pcib_softc *sc;
1519 struct sysctl_ctx_list *sctx;
1520 struct sysctl_oid *soid;
1523 sc = device_get_softc(dev);
1527 * Get current bridge configuration.
1529 sc->domain = pci_get_domain(dev);
1530 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS))
1531 sc->bus.sec = pci_read_config(dev, PCIR_SECBUS_1, 1);
1532 sc->bus.sub = pci_read_config(dev, PCIR_SUBBUS_1, 1);
1534 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
1538 * The primary bus register should always be the bus of the
1541 sc->pribus = pci_get_bus(dev);
1542 pci_write_config(dev, PCIR_PRIBUS_1, sc->pribus, 1);
1545 * Setup sysctl reporting nodes
1547 sctx = device_get_sysctl_ctx(dev);
1548 soid = device_get_sysctl_tree(dev);
1549 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain",
1550 CTLFLAG_RD, &sc->domain, 0, "Domain number");
1551 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus",
1552 CTLFLAG_RD, &sc->pribus, 0, "Primary bus number");
1553 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus",
1554 CTLFLAG_RD, &sc->bus.sec, 0, "Secondary bus number");
1555 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus",
1556 CTLFLAG_RD, &sc->bus.sub, 0, "Subordinate bus number");
1561 switch (pci_get_devid(dev)) {
1562 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS))
1563 case 0x12258086: /* Intel 82454KX/GX (Orion) */
1567 supbus = pci_read_config(dev, 0x41, 1);
1568 if (supbus != 0xff) {
1569 sc->bus.sec = supbus + 1;
1570 sc->bus.sub = supbus + 1;
1577 * The i82380FB mobile docking controller is a PCI-PCI bridge,
1578 * and it is a subtractive bridge. However, the ProgIf is wrong
1579 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't
1580 * happen. There are also Toshiba and Cavium ThunderX bridges
1581 * that behave this way.
1583 case 0xa002177d: /* Cavium ThunderX */
1584 case 0x124b8086: /* Intel 82380FB Mobile */
1585 case 0x060513d7: /* Toshiba ???? */
1586 sc->flags |= PCIB_SUBTRACTIVE;
1589 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS))
1590 /* Compaq R3000 BIOS sets wrong subordinate bus number. */
1595 if ((cp = kern_getenv("smbios.planar.maker")) == NULL)
1597 if (strncmp(cp, "Compal", 6) != 0) {
1602 if ((cp = kern_getenv("smbios.planar.product")) == NULL)
1604 if (strncmp(cp, "08A0", 4) != 0) {
1609 if (sc->bus.sub < 0xa) {
1610 pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1);
1611 sc->bus.sub = pci_read_config(dev, PCIR_SUBBUS_1, 1);
1618 if (pci_msi_device_blacklisted(dev))
1619 sc->flags |= PCIB_DISABLE_MSI;
1621 if (pci_msix_device_blacklisted(dev))
1622 sc->flags |= PCIB_DISABLE_MSIX;
1625 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges,
1626 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM,
1627 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese.
1628 * This means they act as if they were subtractively decoding
1629 * bridges and pass all transactions. Mark them and real ProgIf 1
1630 * parts as subtractive.
1632 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 ||
1633 pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_BRIDGE_PCI_SUBTRACTIVE)
1634 sc->flags |= PCIB_SUBTRACTIVE;
1637 pcib_probe_hotplug(sc);
1641 pcib_setup_secbus(dev, &sc->bus, 1);
1643 pcib_probe_windows(sc);
1646 if (sc->flags & PCIB_HOTPLUG)
1647 pcib_setup_hotplug(sc);
1650 device_printf(dev, " domain %d\n", sc->domain);
1651 device_printf(dev, " secondary bus %d\n", sc->bus.sec);
1652 device_printf(dev, " subordinate bus %d\n", sc->bus.sub);
1654 if (pcib_is_window_open(&sc->io))
1655 device_printf(dev, " I/O decode 0x%jx-0x%jx\n",
1656 (uintmax_t)sc->io.base, (uintmax_t)sc->io.limit);
1657 if (pcib_is_window_open(&sc->mem))
1658 device_printf(dev, " memory decode 0x%jx-0x%jx\n",
1659 (uintmax_t)sc->mem.base, (uintmax_t)sc->mem.limit);
1660 if (pcib_is_window_open(&sc->pmem))
1661 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n",
1662 (uintmax_t)sc->pmem.base, (uintmax_t)sc->pmem.limit);
1664 if (pcib_is_io_open(sc))
1665 device_printf(dev, " I/O decode 0x%x-0x%x\n",
1666 sc->iobase, sc->iolimit);
1667 if (pcib_is_nonprefetch_open(sc))
1668 device_printf(dev, " memory decode 0x%jx-0x%jx\n",
1669 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit);
1670 if (pcib_is_prefetch_open(sc))
1671 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n",
1672 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit);
1674 if (sc->bridgectl & (PCIB_BCR_ISA_ENABLE | PCIB_BCR_VGA_ENABLE) ||
1675 sc->flags & PCIB_SUBTRACTIVE) {
1676 device_printf(dev, " special decode ");
1678 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE) {
1682 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE) {
1683 printf("%sVGA", comma ? ", " : "");
1686 if (sc->flags & PCIB_SUBTRACTIVE)
1687 printf("%ssubtractive", comma ? ", " : "");
1693 * Always enable busmastering on bridges so that transactions
1694 * initiated on the secondary bus are passed through to the
1697 pci_enable_busmaster(dev);
1702 pcib_present(struct pcib_softc *sc)
1705 if (sc->flags & PCIB_HOTPLUG)
1706 return (pcib_hotplug_present(sc) != 0);
1712 pcib_attach_child(device_t dev)
1714 struct pcib_softc *sc;
1716 sc = device_get_softc(dev);
1717 if (sc->bus.sec == 0) {
1718 /* no secondary bus; we should have fixed this */
1723 if (!pcib_present(sc)) {
1724 /* An empty HotPlug slot, so don't add a PCI bus yet. */
1729 sc->child = device_add_child(dev, "pci", -1);
1730 return (bus_generic_attach(dev));
1734 pcib_attach(device_t dev)
1737 pcib_attach_common(dev);
1738 return (pcib_attach_child(dev));
1742 pcib_detach(device_t dev)
1744 #if defined(PCI_HP) || defined(NEW_PCIB)
1745 struct pcib_softc *sc;
1749 #if defined(PCI_HP) || defined(NEW_PCIB)
1750 sc = device_get_softc(dev);
1752 error = bus_generic_detach(dev);
1756 if (sc->flags & PCIB_HOTPLUG) {
1757 error = pcib_detach_hotplug(sc);
1762 error = device_delete_children(dev);
1766 pcib_free_windows(sc);
1768 pcib_free_secbus(dev, &sc->bus);
1775 pcib_suspend(device_t dev)
1778 pcib_cfg_save(device_get_softc(dev));
1779 return (bus_generic_suspend(dev));
1783 pcib_resume(device_t dev)
1786 pcib_cfg_restore(device_get_softc(dev));
1789 * Restore the Command register only after restoring the windows.
1790 * The bridge should not be claiming random windows.
1792 pci_write_config(dev, PCIR_COMMAND, pci_get_cmdreg(dev), 2);
1793 return (bus_generic_resume(dev));
1797 pcib_bridge_init(device_t dev)
1799 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1);
1800 pci_write_config(dev, PCIR_IOBASEH_1, 0xffff, 2);
1801 pci_write_config(dev, PCIR_IOLIMITL_1, 0, 1);
1802 pci_write_config(dev, PCIR_IOLIMITH_1, 0, 2);
1803 pci_write_config(dev, PCIR_MEMBASE_1, 0xffff, 2);
1804 pci_write_config(dev, PCIR_MEMLIMIT_1, 0, 2);
1805 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2);
1806 pci_write_config(dev, PCIR_PMBASEH_1, 0xffffffff, 4);
1807 pci_write_config(dev, PCIR_PMLIMITL_1, 0, 2);
1808 pci_write_config(dev, PCIR_PMLIMITH_1, 0, 4);
1812 pcib_child_present(device_t dev, device_t child)
1815 struct pcib_softc *sc = device_get_softc(dev);
1818 retval = bus_child_present(dev);
1819 if (retval != 0 && sc->flags & PCIB_HOTPLUG)
1820 retval = pcib_hotplug_present(sc);
1823 return (bus_child_present(dev));
1828 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1830 struct pcib_softc *sc = device_get_softc(dev);
1833 case PCIB_IVAR_DOMAIN:
1834 *result = sc->domain;
1837 *result = sc->bus.sec;
1844 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1848 case PCIB_IVAR_DOMAIN:
1858 * Attempt to allocate a resource from the existing resources assigned
1861 static struct resource *
1862 pcib_suballoc_resource(struct pcib_softc *sc, struct pcib_window *w,
1863 device_t child, int type, int *rid, rman_res_t start, rman_res_t end,
1864 rman_res_t count, u_int flags)
1866 struct resource *res;
1868 if (!pcib_is_window_open(w))
1871 res = rman_reserve_resource(&w->rman, start, end, count,
1872 flags & ~RF_ACTIVE, child);
1877 device_printf(sc->dev,
1878 "allocated %s range (%#jx-%#jx) for rid %x of %s\n",
1879 w->name, rman_get_start(res), rman_get_end(res), *rid,
1880 pcib_child_name(child));
1881 rman_set_rid(res, *rid);
1884 * If the resource should be active, pass that request up the
1885 * tree. This assumes the parent drivers can handle
1886 * activating sub-allocated resources.
1888 if (flags & RF_ACTIVE) {
1889 if (bus_activate_resource(child, type, *rid, res) != 0) {
1890 rman_release_resource(res);
1898 /* Allocate a fresh resource range for an unconfigured window. */
1900 pcib_alloc_new_window(struct pcib_softc *sc, struct pcib_window *w, int type,
1901 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
1903 struct resource *res;
1904 rman_res_t base, limit, wmask;
1908 * If this is an I/O window on a bridge with ISA enable set
1909 * and the start address is below 64k, then try to allocate an
1910 * initial window of 0x1000 bytes long starting at address
1911 * 0xf000 and walking down. Note that if the original request
1912 * was larger than the non-aliased range size of 0x100 our
1913 * caller would have raised the start address up to 64k
1916 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE &&
1918 for (base = 0xf000; (long)base >= 0; base -= 0x1000) {
1919 limit = base + 0xfff;
1922 * Skip ranges that wouldn't work for the
1923 * original request. Note that the actual
1924 * window that overlaps are the non-alias
1925 * ranges within [base, limit], so this isn't
1926 * quite a simple comparison.
1928 if (start + count > limit - 0x400)
1932 * The first open region for the window at
1935 if (end - count + 1 < 0x400)
1938 if (end - count + 1 < base)
1942 if (pcib_alloc_nonisa_ranges(sc, base, limit) == 0) {
1951 wmask = ((rman_res_t)1 << w->step) - 1;
1952 if (RF_ALIGNMENT(flags) < w->step) {
1953 flags &= ~RF_ALIGNMENT_MASK;
1954 flags |= RF_ALIGNMENT_LOG2(w->step);
1958 count = roundup2(count, (rman_res_t)1 << w->step);
1960 res = bus_alloc_resource(sc->dev, type, &rid, start, end, count,
1961 flags & ~RF_ACTIVE);
1964 pcib_add_window_resources(w, &res, 1);
1965 pcib_activate_window(sc, type);
1966 w->base = rman_get_start(res);
1967 w->limit = rman_get_end(res);
1971 /* Try to expand an existing window to the requested base and limit. */
1973 pcib_expand_window(struct pcib_softc *sc, struct pcib_window *w, int type,
1974 rman_res_t base, rman_res_t limit)
1976 struct resource *res;
1977 int error, i, force_64k_base;
1979 KASSERT(base <= w->base && limit >= w->limit,
1980 ("attempting to shrink window"));
1983 * XXX: pcib_grow_window() doesn't try to do this anyway and
1984 * the error handling for all the edge cases would be tedious.
1986 KASSERT(limit == w->limit || base == w->base,
1987 ("attempting to grow both ends of a window"));
1990 * Yet more special handling for requests to expand an I/O
1991 * window behind an ISA-enabled bridge. Since I/O windows
1992 * have to grow in 0x1000 increments and the end of the 0xffff
1993 * range is an alias, growing a window below 64k will always
1994 * result in allocating new resources and never adjusting an
1995 * existing resource.
1997 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE &&
1998 (limit <= 65535 || (base <= 65535 && base != w->base))) {
1999 KASSERT(limit == w->limit || limit <= 65535,
2000 ("attempting to grow both ends across 64k ISA alias"));
2002 if (base != w->base)
2003 error = pcib_alloc_nonisa_ranges(sc, base, w->base - 1);
2005 error = pcib_alloc_nonisa_ranges(sc, w->limit + 1,
2015 * Find the existing resource to adjust. Usually there is only one,
2016 * but for an ISA-enabled bridge we might be growing the I/O window
2017 * above 64k and need to find the existing resource that maps all
2018 * of the area above 64k.
2020 for (i = 0; i < w->count; i++) {
2021 if (rman_get_end(w->res[i]) == w->limit)
2024 KASSERT(i != w->count, ("did not find existing resource"));
2028 * Usually the resource we found should match the window's
2029 * existing range. The one exception is the ISA-enabled case
2030 * mentioned above in which case the resource should start at
2033 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE &&
2035 KASSERT(rman_get_start(res) == 65536,
2036 ("existing resource mismatch"));
2039 KASSERT(w->base == rman_get_start(res),
2040 ("existing resource mismatch"));
2044 error = bus_adjust_resource(sc->dev, type, res, force_64k_base ?
2045 rman_get_start(res) : base, limit);
2049 /* Add the newly allocated region to the resource manager. */
2050 if (w->base != base) {
2051 error = rman_manage_region(&w->rman, base, w->base - 1);
2054 error = rman_manage_region(&w->rman, w->limit + 1, limit);
2059 device_printf(sc->dev,
2060 "failed to expand %s resource manager\n", w->name);
2061 (void)bus_adjust_resource(sc->dev, type, res, force_64k_base ?
2062 rman_get_start(res) : w->base, w->limit);
2068 * Attempt to grow a window to make room for a given resource request.
2071 pcib_grow_window(struct pcib_softc *sc, struct pcib_window *w, int type,
2072 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
2074 rman_res_t align, start_free, end_free, front, back, wmask;
2078 * Clamp the desired resource range to the maximum address
2079 * this window supports. Reject impossible requests.
2081 * For I/O port requests behind a bridge with the ISA enable
2082 * bit set, force large allocations to start above 64k.
2086 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE && count > 0x100 &&
2089 if (end > w->rman.rm_end)
2090 end = w->rman.rm_end;
2091 if (start + count - 1 > end || start + count < start)
2093 wmask = ((rman_res_t)1 << w->step) - 1;
2096 * If there is no resource at all, just try to allocate enough
2097 * aligned space for this resource.
2099 if (w->res == NULL) {
2100 error = pcib_alloc_new_window(sc, w, type, start, end, count,
2104 device_printf(sc->dev,
2105 "failed to allocate initial %s window (%#jx-%#jx,%#jx)\n",
2106 w->name, start, end, count);
2110 device_printf(sc->dev,
2111 "allocated initial %s window of %#jx-%#jx\n",
2112 w->name, (uintmax_t)w->base, (uintmax_t)w->limit);
2117 * See if growing the window would help. Compute the minimum
2118 * amount of address space needed on both the front and back
2119 * ends of the existing window to satisfy the allocation.
2121 * For each end, build a candidate region adjusting for the
2122 * required alignment, etc. If there is a free region at the
2123 * edge of the window, grow from the inner edge of the free
2124 * region. Otherwise grow from the window boundary.
2126 * Growing an I/O window below 64k for a bridge with the ISA
2127 * enable bit doesn't require any special magic as the step
2128 * size of an I/O window (1k) always includes multiple
2129 * non-alias ranges when it is grown in either direction.
2131 * XXX: Special case: if w->res is completely empty and the
2132 * request size is larger than w->res, we should find the
2133 * optimal aligned buffer containing w->res and allocate that.
2136 device_printf(sc->dev,
2137 "attempting to grow %s window for (%#jx-%#jx,%#jx)\n",
2138 w->name, start, end, count);
2139 align = (rman_res_t)1 << RF_ALIGNMENT(flags);
2140 if (start < w->base) {
2141 if (rman_first_free_region(&w->rman, &start_free, &end_free) !=
2142 0 || start_free != w->base)
2147 /* Move end_free down until it is properly aligned. */
2148 end_free &= ~(align - 1);
2150 front = end_free - (count - 1);
2153 * The resource would now be allocated at (front,
2154 * end_free). Ensure that fits in the (start, end)
2155 * bounds. end_free is checked above. If 'front' is
2156 * ok, ensure it is properly aligned for this window.
2157 * Also check for underflow.
2159 if (front >= start && front <= end_free) {
2161 printf("\tfront candidate range: %#jx-%#jx\n",
2164 front = w->base - front;
2169 if (end > w->limit) {
2170 if (rman_last_free_region(&w->rman, &start_free, &end_free) !=
2171 0 || end_free != w->limit)
2172 start_free = w->limit + 1;
2173 if (start_free < start)
2176 /* Move start_free up until it is properly aligned. */
2177 start_free = roundup2(start_free, align);
2178 back = start_free + count - 1;
2181 * The resource would now be allocated at (start_free,
2182 * back). Ensure that fits in the (start, end)
2183 * bounds. start_free is checked above. If 'back' is
2184 * ok, ensure it is properly aligned for this window.
2185 * Also check for overflow.
2187 if (back <= end && start_free <= back) {
2189 printf("\tback candidate range: %#jx-%#jx\n",
2199 * Try to allocate the smallest needed region first.
2200 * If that fails, fall back to the other region.
2203 while (front != 0 || back != 0) {
2204 if (front != 0 && (front <= back || back == 0)) {
2205 error = pcib_expand_window(sc, w, type, w->base - front,
2211 error = pcib_expand_window(sc, w, type, w->base,
2222 device_printf(sc->dev, "grew %s window to %#jx-%#jx\n",
2223 w->name, (uintmax_t)w->base, (uintmax_t)w->limit);
2226 /* Write the new window. */
2227 KASSERT((w->base & wmask) == 0, ("start address is not aligned"));
2228 KASSERT((w->limit & wmask) == wmask, ("end address is not aligned"));
2229 pcib_write_windows(sc, w->mask);
2234 * We have to trap resource allocation requests and ensure that the bridge
2235 * is set up to, or capable of handling them.
2238 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
2239 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
2241 struct pcib_softc *sc;
2244 sc = device_get_softc(dev);
2247 * VGA resources are decoded iff the VGA enable bit is set in
2248 * the bridge control register. VGA resources do not fall into
2249 * the resource windows and are passed up to the parent.
2251 if ((type == SYS_RES_IOPORT && pci_is_vga_ioport_range(start, end)) ||
2252 (type == SYS_RES_MEMORY && pci_is_vga_memory_range(start, end))) {
2253 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE)
2254 return (bus_generic_alloc_resource(dev, child, type,
2255 rid, start, end, count, flags));
2263 return (pcib_alloc_subbus(&sc->bus, child, rid, start, end,
2266 case SYS_RES_IOPORT:
2267 if (pcib_is_isa_range(sc, start, end, count))
2269 r = pcib_suballoc_resource(sc, &sc->io, child, type, rid, start,
2271 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0)
2273 if (pcib_grow_window(sc, &sc->io, type, start, end, count,
2275 r = pcib_suballoc_resource(sc, &sc->io, child, type,
2276 rid, start, end, count, flags);
2278 case SYS_RES_MEMORY:
2280 * For prefetchable resources, prefer the prefetchable
2281 * memory window, but fall back to the regular memory
2282 * window if that fails. Try both windows before
2283 * attempting to grow a window in case the firmware
2284 * has used a range in the regular memory window to
2285 * map a prefetchable BAR.
2287 if (flags & RF_PREFETCHABLE) {
2288 r = pcib_suballoc_resource(sc, &sc->pmem, child, type,
2289 rid, start, end, count, flags);
2293 r = pcib_suballoc_resource(sc, &sc->mem, child, type, rid,
2294 start, end, count, flags);
2295 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0)
2297 if (flags & RF_PREFETCHABLE) {
2298 if (pcib_grow_window(sc, &sc->pmem, type, start, end,
2299 count, flags) == 0) {
2300 r = pcib_suballoc_resource(sc, &sc->pmem, child,
2301 type, rid, start, end, count, flags);
2306 if (pcib_grow_window(sc, &sc->mem, type, start, end, count,
2307 flags & ~RF_PREFETCHABLE) == 0)
2308 r = pcib_suballoc_resource(sc, &sc->mem, child, type,
2309 rid, start, end, count, flags);
2312 return (bus_generic_alloc_resource(dev, child, type, rid,
2313 start, end, count, flags));
2317 * If attempts to suballocate from the window fail but this is a
2318 * subtractive bridge, pass the request up the tree.
2320 if (sc->flags & PCIB_SUBTRACTIVE && r == NULL)
2321 return (bus_generic_alloc_resource(dev, child, type, rid,
2322 start, end, count, flags));
2327 pcib_adjust_resource(device_t bus, device_t child, int type, struct resource *r,
2328 rman_res_t start, rman_res_t end)
2330 struct pcib_softc *sc;
2332 sc = device_get_softc(bus);
2333 if (pcib_is_resource_managed(sc, type, r))
2334 return (rman_adjust_resource(r, start, end));
2335 return (bus_generic_adjust_resource(bus, child, type, r, start, end));
2339 pcib_release_resource(device_t dev, device_t child, int type, int rid,
2342 struct pcib_softc *sc;
2345 sc = device_get_softc(dev);
2346 if (pcib_is_resource_managed(sc, type, r)) {
2347 if (rman_get_flags(r) & RF_ACTIVE) {
2348 error = bus_deactivate_resource(child, type, rid, r);
2352 return (rman_release_resource(r));
2354 return (bus_generic_release_resource(dev, child, type, rid, r));
2358 * We have to trap resource allocation requests and ensure that the bridge
2359 * is set up to, or capable of handling them.
2362 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
2363 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
2365 struct pcib_softc *sc = device_get_softc(dev);
2366 const char *name, *suffix;
2370 * Fail the allocation for this range if it's not supported.
2372 name = device_get_nameunit(child);
2379 case SYS_RES_IOPORT:
2381 if (!pcib_is_io_open(sc))
2383 ok = (start >= sc->iobase && end <= sc->iolimit);
2386 * Make sure we allow access to VGA I/O addresses when the
2387 * bridge has the "VGA Enable" bit set.
2389 if (!ok && pci_is_vga_ioport_range(start, end))
2390 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
2392 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
2394 if (start < sc->iobase)
2396 if (end > sc->iolimit)
2405 * If we overlap with the subtractive range, then
2406 * pick the upper range to use.
2408 if (start < sc->iolimit && end > sc->iobase)
2409 start = sc->iolimit + 1;
2413 device_printf(dev, "ioport: end (%jx) < start (%jx)\n",
2420 device_printf(dev, "%s%srequested unsupported I/O "
2421 "range 0x%jx-0x%jx (decoding 0x%x-0x%x)\n",
2422 name, suffix, start, end, sc->iobase, sc->iolimit);
2427 "%s%srequested I/O range 0x%jx-0x%jx: in range\n",
2428 name, suffix, start, end);
2431 case SYS_RES_MEMORY:
2433 if (pcib_is_nonprefetch_open(sc))
2434 ok = ok || (start >= sc->membase && end <= sc->memlimit);
2435 if (pcib_is_prefetch_open(sc))
2436 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit);
2439 * Make sure we allow access to VGA memory addresses when the
2440 * bridge has the "VGA Enable" bit set.
2442 if (!ok && pci_is_vga_memory_range(start, end))
2443 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
2445 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
2448 if (flags & RF_PREFETCHABLE) {
2449 if (pcib_is_prefetch_open(sc)) {
2450 if (start < sc->pmembase)
2451 start = sc->pmembase;
2452 if (end > sc->pmemlimit)
2453 end = sc->pmemlimit;
2457 } else { /* non-prefetchable */
2458 if (pcib_is_nonprefetch_open(sc)) {
2459 if (start < sc->membase)
2460 start = sc->membase;
2461 if (end > sc->memlimit)
2469 ok = 1; /* subtractive bridge: always ok */
2471 if (pcib_is_nonprefetch_open(sc)) {
2472 if (start < sc->memlimit && end > sc->membase)
2473 start = sc->memlimit + 1;
2475 if (pcib_is_prefetch_open(sc)) {
2476 if (start < sc->pmemlimit && end > sc->pmembase)
2477 start = sc->pmemlimit + 1;
2482 device_printf(dev, "memory: end (%jx) < start (%jx)\n",
2488 if (!ok && bootverbose)
2490 "%s%srequested unsupported memory range %#jx-%#jx "
2491 "(decoding %#jx-%#jx, %#jx-%#jx)\n",
2492 name, suffix, start, end,
2493 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit,
2494 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit);
2498 device_printf(dev,"%s%srequested memory range "
2499 "0x%jx-0x%jx: good\n",
2500 name, suffix, start, end);
2507 * Bridge is OK decoding this resource, so pass it up.
2509 return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
2515 * If ARI is enabled on this downstream port, translate the function number
2516 * to the non-ARI slot/function. The downstream port will convert it back in
2517 * hardware. If ARI is not enabled slot and func are not modified.
2519 static __inline void
2520 pcib_xlate_ari(device_t pcib, int bus, int *slot, int *func)
2522 struct pcib_softc *sc;
2525 sc = device_get_softc(pcib);
2528 if (sc->flags & PCIB_ENABLE_ARI) {
2530 ("Non-zero slot number with ARI enabled!"));
2531 *slot = PCIE_ARI_SLOT(ari_func);
2532 *func = PCIE_ARI_FUNC(ari_func);
2538 pcib_enable_ari(struct pcib_softc *sc, uint32_t pcie_pos)
2542 ctl2 = pci_read_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, 4);
2543 ctl2 |= PCIEM_CTL2_ARI;
2544 pci_write_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, ctl2, 4);
2546 sc->flags |= PCIB_ENABLE_ARI;
2553 pcib_maxslots(device_t dev)
2555 #if !defined(__amd64__) && !defined(__i386__)
2560 * If this is a PCIe rootport or downstream switch port, there's only
2561 * one slot permitted.
2563 if (pci_find_cap(dev, PCIY_EXPRESS, &pcie_pos) == 0) {
2564 val = pci_read_config(dev, pcie_pos + PCIER_FLAGS, 2);
2565 val &= PCIEM_FLAGS_TYPE;
2566 if (val == PCIEM_TYPE_ROOT_PORT ||
2567 val == PCIEM_TYPE_DOWNSTREAM_PORT)
2571 return (PCI_SLOTMAX);
2575 pcib_ari_maxslots(device_t dev)
2577 struct pcib_softc *sc;
2579 sc = device_get_softc(dev);
2581 if (sc->flags & PCIB_ENABLE_ARI)
2582 return (PCIE_ARI_SLOTMAX);
2584 return (pcib_maxslots(dev));
2588 pcib_ari_maxfuncs(device_t dev)
2590 struct pcib_softc *sc;
2592 sc = device_get_softc(dev);
2594 if (sc->flags & PCIB_ENABLE_ARI)
2595 return (PCIE_ARI_FUNCMAX);
2597 return (PCI_FUNCMAX);
2601 pcib_ari_decode_rid(device_t pcib, uint16_t rid, int *bus, int *slot,
2604 struct pcib_softc *sc;
2606 sc = device_get_softc(pcib);
2608 *bus = PCI_RID2BUS(rid);
2609 if (sc->flags & PCIB_ENABLE_ARI) {
2610 *slot = PCIE_ARI_RID2SLOT(rid);
2611 *func = PCIE_ARI_RID2FUNC(rid);
2613 *slot = PCI_RID2SLOT(rid);
2614 *func = PCI_RID2FUNC(rid);
2619 * Since we are a child of a PCI bus, its parent must support the pcib interface.
2622 pcib_read_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, int width)
2625 struct pcib_softc *sc;
2627 sc = device_get_softc(dev);
2628 if (!pcib_present(sc)) {
2635 return (0xffffffff);
2639 pcib_xlate_ari(dev, b, &s, &f);
2640 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s,
2645 pcib_write_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, int width)
2648 struct pcib_softc *sc;
2650 sc = device_get_softc(dev);
2651 if (!pcib_present(sc))
2654 pcib_xlate_ari(dev, b, &s, &f);
2655 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f,
2660 * Route an interrupt across a PCI bridge.
2663 pcib_route_interrupt(device_t pcib, device_t dev, int pin)
2671 * The PCI standard defines a swizzle of the child-side device/intpin to
2672 * the parent-side intpin as follows.
2674 * device = device on child bus
2675 * child_intpin = intpin on child bus slot (0-3)
2676 * parent_intpin = intpin on parent bus slot (0-3)
2678 * parent_intpin = (device + child_intpin) % 4
2680 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4;
2683 * Our parent is a PCI bus. Its parent must export the pcib interface
2684 * which includes the ability to route interrupts.
2686 bus = device_get_parent(pcib);
2687 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1);
2688 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) {
2689 device_printf(pcib, "slot %d INT%c is routed to irq %d\n",
2690 pci_get_slot(dev), 'A' + pin - 1, intnum);
2695 /* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */
2697 pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs)
2699 struct pcib_softc *sc = device_get_softc(pcib);
2702 if (sc->flags & PCIB_DISABLE_MSI)
2704 bus = device_get_parent(pcib);
2705 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount,
2709 /* Pass request to release MSI/MSI-X messages up to the parent bridge. */
2711 pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs)
2715 bus = device_get_parent(pcib);
2716 return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs));
2719 /* Pass request to alloc an MSI-X message up to the parent bridge. */
2721 pcib_alloc_msix(device_t pcib, device_t dev, int *irq)
2723 struct pcib_softc *sc = device_get_softc(pcib);
2726 if (sc->flags & PCIB_DISABLE_MSIX)
2728 bus = device_get_parent(pcib);
2729 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq));
2732 /* Pass request to release an MSI-X message up to the parent bridge. */
2734 pcib_release_msix(device_t pcib, device_t dev, int irq)
2738 bus = device_get_parent(pcib);
2739 return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq));
2742 /* Pass request to map MSI/MSI-X message up to parent bridge. */
2744 pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
2750 bus = device_get_parent(pcib);
2751 error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data);
2755 pci_ht_map_msi(pcib, *addr);
2759 /* Pass request for device power state up to parent bridge. */
2761 pcib_power_for_sleep(device_t pcib, device_t dev, int *pstate)
2765 bus = device_get_parent(pcib);
2766 return (PCIB_POWER_FOR_SLEEP(bus, dev, pstate));
2770 pcib_ari_enabled(device_t pcib)
2772 struct pcib_softc *sc;
2774 sc = device_get_softc(pcib);
2776 return ((sc->flags & PCIB_ENABLE_ARI) != 0);
2780 pcib_ari_get_id(device_t pcib, device_t dev, enum pci_id_type type,
2783 struct pcib_softc *sc;
2785 uint8_t bus, slot, func;
2787 if (type != PCI_ID_RID) {
2788 bus_dev = device_get_parent(pcib);
2789 return (PCIB_GET_ID(device_get_parent(bus_dev), dev, type, id));
2792 sc = device_get_softc(pcib);
2794 if (sc->flags & PCIB_ENABLE_ARI) {
2795 bus = pci_get_bus(dev);
2796 func = pci_get_function(dev);
2798 *id = (PCI_ARI_RID(bus, func));
2800 bus = pci_get_bus(dev);
2801 slot = pci_get_slot(dev);
2802 func = pci_get_function(dev);
2804 *id = (PCI_RID(bus, slot, func));
2811 * Check that the downstream port (pcib) and the endpoint device (dev) both
2812 * support ARI. If so, enable it and return 0, otherwise return an error.
2815 pcib_try_enable_ari(device_t pcib, device_t dev)
2817 struct pcib_softc *sc;
2824 sc = device_get_softc(pcib);
2827 * ARI is controlled in a register in the PCIe capability structure.
2828 * If the downstream port does not have the PCIe capability structure
2829 * then it does not support ARI.
2831 error = pci_find_cap(pcib, PCIY_EXPRESS, &pcie_pos);
2835 /* Check that the PCIe port advertises ARI support. */
2836 cap2 = pci_read_config(pcib, pcie_pos + PCIER_DEVICE_CAP2, 4);
2837 if (!(cap2 & PCIEM_CAP2_ARI))
2841 * Check that the endpoint device advertises ARI support via the ARI
2842 * extended capability structure.
2844 error = pci_find_extcap(dev, PCIZ_ARI, &ari_cap_off);
2849 * Finally, check that the endpoint device supports the same version
2850 * of ARI that we do.
2852 ari_ver = pci_read_config(dev, ari_cap_off, 4);
2853 if (PCI_EXTCAP_VER(ari_ver) != PCIB_SUPPORTED_ARI_VER) {
2856 "Unsupported version of ARI (%d) detected\n",
2857 PCI_EXTCAP_VER(ari_ver));
2862 pcib_enable_ari(sc, pcie_pos);
2868 pcib_request_feature_allow(device_t pcib, device_t dev,
2869 enum pci_feature feature)
2872 * No host firmware we have to negotiate with, so we allow
2873 * every valid feature requested.
2876 case PCI_FEATURE_AER:
2877 case PCI_FEATURE_HP:
2887 pcib_request_feature(device_t dev, enum pci_feature feature)
2891 * Invoke PCIB_REQUEST_FEATURE of this bridge first in case
2892 * the firmware overrides the method of PCI-PCI bridges.
2894 return (PCIB_REQUEST_FEATURE(dev, dev, feature));
2898 * Pass the request to use this PCI feature up the tree. Either there's a
2899 * firmware like ACPI that's using this feature that will approve (or deny) the
2900 * request to take it over, or the platform has no such firmware, in which case
2901 * the request will be approved. If the request is approved, the OS is expected
2902 * to make use of the feature or render it harmless.
2905 pcib_request_feature_default(device_t pcib, device_t dev,
2906 enum pci_feature feature)
2911 * Our parent is necessarily a pci bus. Its parent will either be
2912 * another pci bridge (which passes it up) or a host bridge that can
2913 * approve or reject the request.
2915 bus = device_get_parent(pcib);
2916 return (PCIB_REQUEST_FEATURE(device_get_parent(bus), dev, feature));
2920 pcib_reset_child(device_t dev, device_t child, int flags)
2922 struct pci_devinfo *pdinfo;
2926 if (dev == NULL || device_get_parent(child) != dev)
2929 if (device_get_devclass(child) != devclass_find("pci"))
2931 pdinfo = device_get_ivars(dev);
2932 if (pdinfo->cfg.pcie.pcie_location != 0 &&
2933 (pdinfo->cfg.pcie.pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT ||
2934 pdinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT)) {
2935 error = bus_helper_reset_prepare(child, flags);
2937 error = pcie_link_reset(dev,
2938 pdinfo->cfg.pcie.pcie_location);
2939 /* XXXKIB call _post even if error != 0 ? */
2940 bus_helper_reset_post(child, flags);