2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000 BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * PCI:PCI bridge support.
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/kernel.h>
42 #include <machine/resource.h>
44 #include <pci/pcivar.h>
45 #include <pci/pcireg.h>
51 * Bridge-specific data.
56 u_int16_t command; /* command register */
57 u_int8_t secbus; /* secondary bus number */
58 u_int8_t subbus; /* subordinate bus number */
59 pci_addr_t pmembase; /* base address of prefetchable memory */
60 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */
61 pci_addr_t membase; /* base address of memory window */
62 pci_addr_t memlimit; /* topmost address of memory window */
63 u_int32_t iobase; /* base address of port window */
64 u_int32_t iolimit; /* topmost address of port window */
65 u_int16_t secstat; /* secondary bus status register */
66 u_int16_t bridgectl; /* bridge control register */
67 u_int8_t seclat; /* secondary bus latency timer */
70 static int pcib_probe(device_t dev);
71 static int pcib_attach(device_t dev);
72 static int pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result);
73 static int pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value);
74 static struct resource *pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
75 u_long start, u_long end, u_long count, u_int flags);
76 static int pcib_maxslots(device_t dev);
77 static u_int32_t pcib_read_config(device_t dev, int b, int s, int f, int reg, int width);
78 static void pcib_write_config(device_t dev, int b, int s, int f, int reg, u_int32_t val, int width);
79 static int pcib_route_interrupt(device_t pcib, device_t dev, int pin);
81 static device_method_t pcib_methods[] = {
82 /* Device interface */
83 DEVMETHOD(device_probe, pcib_probe),
84 DEVMETHOD(device_attach, pcib_attach),
85 DEVMETHOD(device_shutdown, bus_generic_shutdown),
86 DEVMETHOD(device_suspend, bus_generic_suspend),
87 DEVMETHOD(device_resume, bus_generic_resume),
90 DEVMETHOD(bus_print_child, bus_generic_print_child),
91 DEVMETHOD(bus_read_ivar, pcib_read_ivar),
92 DEVMETHOD(bus_write_ivar, pcib_write_ivar),
93 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
94 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
95 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
96 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
97 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
98 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
101 DEVMETHOD(pcib_maxslots, pcib_maxslots),
102 DEVMETHOD(pcib_read_config, pcib_read_config),
103 DEVMETHOD(pcib_write_config, pcib_write_config),
104 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
109 static driver_t pcib_driver = {
112 sizeof(struct pcib_softc),
115 static devclass_t pcib_devclass;
117 DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0);
120 * Generic device interface
123 pcib_probe(device_t dev)
125 if ((pci_get_class(dev) == PCIC_BRIDGE) &&
126 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) {
127 device_set_desc(dev, "PCI-PCI bridge");
134 pcib_attach(device_t dev)
136 struct pcib_softc *sc;
140 sc = device_get_softc(dev);
144 * Get current bridge configuration.
146 sc->command = pci_read_config(dev, PCIR_COMMAND, 1);
147 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1);
148 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1);
149 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2);
150 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
151 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1);
154 * Determine current I/O decode.
156 if (sc->command & PCIM_CMD_PORTEN) {
157 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1);
158 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
159 sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2),
160 pci_read_config(dev, PCIR_IOBASEL_1, 1));
162 sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1));
165 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1);
166 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
167 sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2),
168 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
170 sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1));
175 * Determine current memory decode.
177 if (sc->command & PCIM_CMD_MEMEN) {
178 sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2));
179 sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
180 sc->pmembase = PCI_PPBMEMBASE((pci_addr_t)pci_read_config(dev, PCIR_PMBASEH_1, 4),
181 pci_read_config(dev, PCIR_PMBASEL_1, 2));
182 sc->pmemlimit = PCI_PPBMEMLIMIT((pci_addr_t)pci_read_config(dev, PCIR_PMLIMITH_1, 4),
183 pci_read_config(dev, PCIR_PMLIMITL_1, 2));
189 switch (pci_get_devid(dev)) {
190 case 0x12258086: /* Intel 82454KX/GX (Orion) */
194 supbus = pci_read_config(dev, 0x41, 1);
195 if (supbus != 0xff) {
196 sc->secbus = supbus + 1;
197 sc->subbus = supbus + 1;
204 device_printf(dev, " secondary bus %d\n", sc->secbus);
205 device_printf(dev, " subordinate bus %d\n", sc->subbus);
206 device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit);
207 device_printf(dev, " memory decode 0x%x-0x%x\n", sc->membase, sc->memlimit);
208 device_printf(dev, " prefetched decode 0x%x-0x%x\n", sc->pmembase, sc->pmemlimit);
212 * XXX If the secondary bus number is zero, we should assign a bus number
213 * since the BIOS hasn't, then initialise the bridge.
217 * XXX If the subordinate bus number is less than the secondary bus number,
218 * we should pick a better value. One sensible alternative would be to
219 * pick 255; the only tradeoff here is that configuration transactions
220 * would be more widely routed than absolutely necessary.
223 if (sc->secbus != 0) {
224 child = device_add_child(dev, "pci", -1);
226 return(bus_generic_attach(dev));
229 /* no secondary bus; we should have fixed this */
234 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
236 struct pcib_softc *sc = device_get_softc(dev);
240 *result = sc->secbus;
247 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
249 struct pcib_softc *sc = device_get_softc(dev);
260 * Is this a decoded ISA I/O port address? Note, we need to do the mask that
261 * we do below because of the ISA alias addresses. I'm not 100% sure that
265 pcib_is_isa_io(u_long start)
267 if ((start & 0xfffUL) > 0x3ffUL || start == 0)
273 * Is this a decoded ISA memory address?
276 pcib_is_isa_mem(u_long start)
278 if (start > 0xfffffUL || start == 0)
284 * We have to trap resource allocation requests and ensure that the bridge
285 * is set up to, or capable of handling them.
287 static struct resource *
288 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
289 u_long start, u_long end, u_long count, u_int flags)
291 struct pcib_softc *sc = device_get_softc(dev);
294 * If this is a "default" allocation against this rid, we can't work
295 * out where it's coming from (we should actually never see these) so we
298 if ((start == 0) && (end == ~0)) {
299 device_printf(dev, "can't decode default resource id %d for %s%d, bypassing\n",
300 *rid, device_get_name(child), device_get_unit(child));
303 * Fail the allocation for this range if it's not supported.
305 * XXX we should probably just fix up the bridge decode and soldier on.
309 if (!pcib_is_isa_io(start)) {
310 #ifndef PCI_ALLOW_UNSUPPORTED_IO_RANGE
311 if (start < sc->iobase)
313 if (end > sc->iolimit)
318 if (start < sc->iobase)
319 printf("start (%lx) < sc->iobase (%x)\n", start, sc->iobase);
320 if (end > sc->iolimit)
321 printf("end (%lx) > sc->iolimit (%x)\n", end, sc->iolimit);
323 printf("end (%lx) < start (%lx)\n", end, start);
326 if (!pcib_is_isa_io(start) &&
327 ((start < sc->iobase) || (end > sc->iolimit))) {
328 device_printf(dev, "device %s%d requested unsupported I/O range 0x%lx-0x%lx"
329 " (decoding 0x%x-0x%x)\n",
330 device_get_name(child), device_get_unit(child), start, end,
331 sc->iobase, sc->iolimit);
335 device_printf(sc->dev, "device %s%d requested decoded I/O range 0x%lx-0x%lx\n",
336 device_get_name(child), device_get_unit(child), start, end);
340 * XXX will have to decide whether the device making the request is asking
341 * for prefetchable memory or not. If it's coming from another bridge
342 * down the line, do we assume not, or ask the bridge to pass in another
343 * flag as the request bubbles up?
346 if (!pcib_is_isa_mem(start)) {
347 #ifndef PCI_ALLOW_UNSUPPORTED_IO_RANGE
348 if (start < sc->membase && end >= sc->membase)
350 if (end > sc->memlimit)
355 if (start < sc->membase && end > sc->membase)
356 printf("start (%lx) < sc->membase (%x)\n", start, sc->membase);
357 if (end > sc->memlimit)
358 printf("end (%lx) > sc->memlimit (%x)\n", end, sc->memlimit);
360 printf("end (%lx) < start (%lx)\n", end, start);
363 if (!pcib_is_isa_mem(start) &&
364 (((start < sc->membase) || (end > sc->memlimit)) &&
365 ((start < sc->pmembase) || (end > sc->pmemlimit)))) {
368 "device %s%d requested unsupported memory range "
369 "0x%lx-0x%lx (decoding 0x%x-0x%x, 0x%x-0x%x)\n",
370 device_get_name(child), device_get_unit(child), start,
371 end, sc->membase, sc->memlimit, sc->pmembase,
373 #ifndef PCI_ALLOW_UNSUPPORTED_IO_RANGE
378 device_printf(sc->dev, "device %s%d requested decoded memory range 0x%lx-0x%lx\n",
379 device_get_name(child), device_get_unit(child), start, end);
388 * Bridge is OK decoding this resource, so pass it up.
390 return(bus_generic_alloc_resource(dev, child, type, rid, start, end, count, flags));
397 pcib_maxslots(device_t dev)
403 * Since we are a child of a PCI bus, its parent must support the pcib interface.
406 pcib_read_config(device_t dev, int b, int s, int f, int reg, int width)
408 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width));
412 pcib_write_config(device_t dev, int b, int s, int f, int reg, u_int32_t val, int width)
414 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width);
418 * Route an interrupt across a PCI bridge.
421 pcib_route_interrupt(device_t pcib, device_t dev, int pin)
429 * The PCI standard defines a swizzle of the child-side device/intpin to
430 * the parent-side intpin as follows.
432 * device = device on child bus
433 * child_intpin = intpin on child bus slot (0-3)
434 * parent_intpin = intpin on parent bus slot (0-3)
436 * parent_intpin = (device + child_intpin) % 4
438 parent_intpin = (pci_get_slot(pcib) + (pin - 1)) % 4;
441 * Our parent is a PCI bus. Its parent must export the pcib interface
442 * which includes the ability to route interrupts.
444 bus = device_get_parent(pcib);
445 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1);
446 if (PCI_INTERRUPT_VALID(intnum)) {
447 device_printf(pcib, "routed slot %d INT%c to irq %d\n", pci_get_slot(dev),
448 'A' + pin - 1, intnum);