2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
5 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
6 * Copyright (c) 2000 BSDi
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. The name of the author may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 #ifndef __PCIB_PRIVATE_H__
36 #define __PCIB_PRIVATE_H__
38 #include <sys/taskqueue.h>
42 * Data structure and routines that Host to PCI bridge drivers can use
43 * to restrict allocations for child devices to ranges decoded by the
46 struct pcib_host_resources {
48 struct resource_list hr_rl;
51 int pcib_host_res_init(device_t pcib,
52 struct pcib_host_resources *hr);
53 int pcib_host_res_free(device_t pcib,
54 struct pcib_host_resources *hr);
55 int pcib_host_res_decodes(struct pcib_host_resources *hr, int type,
56 rman_res_t start, rman_res_t end, u_int flags);
57 struct resource *pcib_host_res_alloc(struct pcib_host_resources *hr,
58 device_t dev, int type, int *rid, rman_res_t start,
59 rman_res_t end, rman_res_t count, u_int flags);
60 int pcib_host_res_adjust(struct pcib_host_resources *hr,
61 device_t dev, int type, struct resource *r, rman_res_t start,
66 * Export portions of generic PCI:PCI bridge support so that it can be
69 DECLARE_CLASS(pcib_driver);
77 pci_addr_t base; /* base address */
78 pci_addr_t limit; /* topmost address */
80 struct resource **res;
81 int count; /* size of 'res' array */
82 int reg; /* resource id from parent */
84 int mask; /* WIN_* bitmask of this window */
85 int step; /* log_2 of window granularity */
93 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
103 * Bridge-specific data.
109 uint32_t flags; /* flags */
110 #define PCIB_SUBTRACTIVE 0x1
111 #define PCIB_DISABLE_MSI 0x2
112 #define PCIB_DISABLE_MSIX 0x4
113 #define PCIB_ENABLE_ARI 0x8
114 #define PCIB_HOTPLUG 0x10
115 #define PCIB_HOTPLUG_CMD_PENDING 0x20
116 #define PCIB_DETACH_PENDING 0x40
117 #define PCIB_DETACHING 0x80
118 u_int domain; /* domain number */
119 u_int pribus; /* primary bus number */
120 struct pcib_secbus bus; /* secondary bus numbers */
122 struct pcib_window io; /* I/O port window */
123 struct pcib_window mem; /* memory window */
124 struct pcib_window pmem; /* prefetchable memory window */
126 pci_addr_t pmembase; /* base address of prefetchable memory */
127 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */
128 pci_addr_t membase; /* base address of memory window */
129 pci_addr_t memlimit; /* topmost address of memory window */
130 uint32_t iobase; /* base address of port window */
131 uint32_t iolimit; /* topmost address of port window */
133 uint16_t bridgectl; /* bridge control register */
134 uint16_t pcie_link_sta;
135 uint16_t pcie_slot_sta;
136 uint32_t pcie_slot_cap;
137 struct resource *pcie_irq;
139 struct task pcie_hp_task;
140 struct timeout_task pcie_ab_task;
141 struct timeout_task pcie_cc_task;
142 struct timeout_task pcie_dll_task;
143 struct mtx *pcie_hp_lock;
146 #define PCIB_HP_LOCK(sc) mtx_lock((sc)->pcie_hp_lock)
147 #define PCIB_HP_UNLOCK(sc) mtx_unlock((sc)->pcie_hp_lock)
148 #define PCIB_HP_LOCK_ASSERT(sc) mtx_assert((sc)->pcie_hp_lock, MA_OWNED)
150 #define PCIB_SUPPORTED_ARI_VER 1
152 typedef uint32_t pci_read_config_fn(int b, int s, int f, int reg, int width);
154 int host_pcib_get_busno(pci_read_config_fn read_config, int bus,
155 int slot, int func, uint8_t *busnum);
156 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
157 struct resource *pci_domain_alloc_bus(int domain, device_t dev, int *rid,
158 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags);
159 int pci_domain_adjust_bus(int domain, device_t dev,
160 struct resource *r, rman_res_t start, rman_res_t end);
161 int pci_domain_release_bus(int domain, device_t dev, int rid,
163 struct resource *pcib_alloc_subbus(struct pcib_secbus *bus, device_t child,
164 int *rid, rman_res_t start, rman_res_t end, rman_res_t count,
166 void pcib_free_secbus(device_t dev, struct pcib_secbus *bus);
167 void pcib_setup_secbus(device_t dev, struct pcib_secbus *bus,
170 int pcib_attach(device_t dev);
171 int pcib_attach_child(device_t dev);
172 void pcib_attach_common(device_t dev);
173 void pcib_bridge_init(device_t dev);
175 const char *pcib_child_name(device_t child);
177 int pcib_child_present(device_t dev, device_t child);
178 int pcib_detach(device_t dev);
179 int pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result);
180 int pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value);
181 struct resource *pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
182 rman_res_t start, rman_res_t end,
183 rman_res_t count, u_int flags);
185 int pcib_adjust_resource(device_t bus, device_t child, int type,
186 struct resource *r, rman_res_t start, rman_res_t end);
187 int pcib_release_resource(device_t dev, device_t child, int type, int rid,
190 int pcib_maxslots(device_t dev);
191 int pcib_maxfuncs(device_t dev);
192 int pcib_route_interrupt(device_t pcib, device_t dev, int pin);
193 int pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs);
194 int pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs);
195 int pcib_alloc_msix(device_t pcib, device_t dev, int *irq);
196 int pcib_release_msix(device_t pcib, device_t dev, int irq);
197 int pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, uint32_t *data);
198 int pcib_get_id(device_t pcib, device_t dev, enum pci_id_type type,
200 void pcib_decode_rid(device_t pcib, uint16_t rid, int *bus,
201 int *slot, int *func);
202 int pcib_request_feature(device_t dev, enum pci_feature feature);
203 int pcib_request_feature_allow(device_t pcib, device_t dev, enum pci_feature feature);