2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000 BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #ifndef __PCIB_PRIVATE_H__
34 #define __PCIB_PRIVATE_H__
38 * Data structure and routines that Host to PCI bridge drivers can use
39 * to restrict allocations for child devices to ranges decoded by the
42 struct pcib_host_resources {
44 struct resource_list hr_rl;
47 int pcib_host_res_init(device_t pcib,
48 struct pcib_host_resources *hr);
49 int pcib_host_res_free(device_t pcib,
50 struct pcib_host_resources *hr);
51 int pcib_host_res_decodes(struct pcib_host_resources *hr, int type,
52 u_long start, u_long end, u_int flags);
53 struct resource *pcib_host_res_alloc(struct pcib_host_resources *hr,
54 device_t dev, int type, int *rid, u_long start, u_long end,
55 u_long count, u_int flags);
56 int pcib_host_res_adjust(struct pcib_host_resources *hr,
57 device_t dev, int type, struct resource *r, u_long start,
62 * Export portions of generic PCI:PCI bridge support so that it can be
65 DECLARE_CLASS(pcib_driver);
73 pci_addr_t base; /* base address */
74 pci_addr_t limit; /* topmost address */
76 struct resource **res;
77 int count; /* size of 'res' array */
78 int reg; /* resource id from parent */
80 int mask; /* WIN_* bitmask of this window */
81 int step; /* log_2 of window granularity */
89 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
99 * Bridge-specific data.
104 uint32_t flags; /* flags */
105 #define PCIB_SUBTRACTIVE 0x1
106 #define PCIB_DISABLE_MSI 0x2
107 #define PCIB_DISABLE_MSIX 0x4
108 uint16_t command; /* command register */
109 u_int domain; /* domain number */
110 u_int pribus; /* primary bus number */
111 struct pcib_secbus bus; /* secondary bus numbers */
113 struct pcib_window io; /* I/O port window */
114 struct pcib_window mem; /* memory window */
115 struct pcib_window pmem; /* prefetchable memory window */
117 pci_addr_t pmembase; /* base address of prefetchable memory */
118 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */
119 pci_addr_t membase; /* base address of memory window */
120 pci_addr_t memlimit; /* topmost address of memory window */
121 uint32_t iobase; /* base address of port window */
122 uint32_t iolimit; /* topmost address of port window */
124 uint16_t secstat; /* secondary bus status register */
125 uint16_t bridgectl; /* bridge control register */
126 uint8_t seclat; /* secondary bus latency timer */
129 typedef uint32_t pci_read_config_fn(int b, int s, int f, int reg, int width);
131 int host_pcib_get_busno(pci_read_config_fn read_config, int bus,
132 int slot, int func, uint8_t *busnum);
133 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
134 struct resource *pci_domain_alloc_bus(int domain, device_t dev, int *rid,
135 u_long start, u_long end, u_long count, u_int flags);
136 int pci_domain_adjust_bus(int domain, device_t dev,
137 struct resource *r, u_long start, u_long end);
138 int pci_domain_release_bus(int domain, device_t dev, int rid,
140 struct resource *pcib_alloc_subbus(struct pcib_secbus *bus, device_t child,
141 int *rid, u_long start, u_long end, u_long count,
143 void pcib_setup_secbus(device_t dev, struct pcib_secbus *bus,
146 int pcib_attach(device_t dev);
147 void pcib_attach_common(device_t dev);
149 const char *pcib_child_name(device_t child);
151 int pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result);
152 int pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value);
153 struct resource *pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
154 u_long start, u_long end, u_long count, u_int flags);
156 int pcib_adjust_resource(device_t bus, device_t child, int type,
157 struct resource *r, u_long start, u_long end);
158 int pcib_release_resource(device_t dev, device_t child, int type, int rid,
161 int pcib_maxslots(device_t dev);
162 uint32_t pcib_read_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, int width);
163 void pcib_write_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, int width);
164 int pcib_route_interrupt(device_t pcib, device_t dev, int pin);
165 int pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs);
166 int pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs);
167 int pcib_alloc_msix(device_t pcib, device_t dev, int *irq);
168 int pcib_release_msix(device_t pcib, device_t dev, int irq);
169 int pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, uint32_t *data);