2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 * PCIM_xxx: mask to locate subfield in register
32 * PCIR_xxx: config register offset
33 * PCIC_xxx: device class
34 * PCIS_xxx: device subclass
35 * PCIP_xxx: device programming interface
36 * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices)
38 * PCIY_xxx: capability identification number
41 /* some PCI bus constants */
43 #define PCI_BUSMAX 255
44 #define PCI_SLOTMAX 31
46 #define PCI_REGMAX 255
47 #define PCI_MAXHDRTYPE 2
49 /* PCI config header registers for all devices */
51 #define PCIR_DEVVENDOR 0x00
52 #define PCIR_VENDOR 0x00
53 #define PCIR_DEVICE 0x02
54 #define PCIR_COMMAND 0x04
55 #define PCIM_CMD_PORTEN 0x0001
56 #define PCIM_CMD_MEMEN 0x0002
57 #define PCIM_CMD_BUSMASTEREN 0x0004
58 #define PCIM_CMD_SPECIALEN 0x0008
59 #define PCIM_CMD_MWRICEN 0x0010
60 #define PCIM_CMD_PERRESPEN 0x0040
61 #define PCIM_CMD_SERRESPEN 0x0100
62 #define PCIM_CMD_BACKTOBACK 0x0200
63 #define PCIR_STATUS 0x06
64 #define PCIM_STATUS_CAPPRESENT 0x0010
65 #define PCIM_STATUS_66CAPABLE 0x0020
66 #define PCIM_STATUS_BACKTOBACK 0x0080
67 #define PCIM_STATUS_PERRREPORT 0x0100
68 #define PCIM_STATUS_SEL_FAST 0x0000
69 #define PCIM_STATUS_SEL_MEDIMUM 0x0200
70 #define PCIM_STATUS_SEL_SLOW 0x0400
71 #define PCIM_STATUS_SEL_MASK 0x0600
72 #define PCIM_STATUS_STABORT 0x0800
73 #define PCIM_STATUS_RTABORT 0x1000
74 #define PCIM_STATUS_RMABORT 0x2000
75 #define PCIM_STATUS_SERR 0x4000
76 #define PCIM_STATUS_PERR 0x8000
77 #define PCIR_REVID 0x08
78 #define PCIR_PROGIF 0x09
79 #define PCIR_SUBCLASS 0x0a
80 #define PCIR_CLASS 0x0b
81 #define PCIR_CACHELNSZ 0x0c
82 #define PCIR_LATTIMER 0x0d
83 #define PCIR_HDRTYPE 0x0e
84 #define PCIM_HDRTYPE 0x7f
85 #define PCIM_HDRTYPE_NORMAL 0x00
86 #define PCIM_HDRTYPE_BRIDGE 0x01
87 #define PCIM_HDRTYPE_CARDBUS 0x02
88 #define PCIM_MFDEV 0x80
89 #define PCIR_BIST 0x0f
91 /* Capability Register Offsets */
94 #define PCICAP_NEXTPTR 0x1
96 /* Capability Identification Numbers */
98 #define PCIY_PMG 0x01 /* PCI Power Management */
99 #define PCIY_AGP 0x02 /* AGP */
100 #define PCIY_VPD 0x03 /* Vital Product Data */
101 #define PCIY_SLOTID 0x04 /* Slot Identification */
102 #define PCIY_MSI 0x05 /* Message Signaled Interrupts */
103 #define PCIY_CHSWP 0x06 /* CompactPCI Hot Swap */
104 #define PCIY_PCIX 0x07 /* PCI-X */
105 #define PCIY_HT 0x08 /* HyperTransport */
106 #define PCIY_VENDOR 0x09 /* Vendor Unique */
107 #define PCIY_DEBUG 0x0a /* Debug port */
108 #define PCIY_CRES 0x0b /* CompactPCI central resource control */
109 #define PCIY_HOTPLUG 0x0c /* PCI Hot-Plug */
110 #define PCIY_SUBVENDOR 0x0d /* PCI-PCI bridge subvendor ID */
111 #define PCIY_AGP8X 0x0e /* AGP 8x */
112 #define PCIY_SECDEV 0x0f /* Secure Device */
113 #define PCIY_EXPRESS 0x10 /* PCI Express */
114 #define PCIY_MSIX 0x11 /* MSI-X */
116 /* config registers for header type 0 devices */
118 #define PCIR_BARS 0x10
119 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4)
120 #define PCI_MAX_BAR_0 5 /* Number of standard bars */
121 #define PCI_RID2BAR(rid) (((rid) - PCIR_BARS) / 4)
122 #define PCI_BAR_IO(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_IO_SPACE)
123 #define PCI_BAR_MEM(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_MEM_SPACE)
124 #define PCIM_BAR_SPACE 0x00000001
125 #define PCIM_BAR_MEM_SPACE 0
126 #define PCIM_BAR_IO_SPACE 1
127 #define PCIM_BAR_MEM_TYPE 0x00000006
128 #define PCIM_BAR_MEM_32 0
129 #define PCIM_BAR_MEM_1MB 2 /* Locate below 1MB in PCI <= 2.1 */
130 #define PCIM_BAR_MEM_64 4
131 #define PCIM_BAR_MEM_PREFETCH 0x00000008
132 #define PCIM_BAR_MEM_BASE 0xfffffff0
133 #define PCIM_BAR_IO_RESERVED 0x00000002
134 #define PCIM_BAR_IO_BASE 0xfffffffc
135 #define PCIR_CIS 0x28
136 #define PCIM_CIS_ASI_MASK 0x7
137 #define PCIM_CIS_ASI_CONFIG 0
138 #define PCIM_CIS_ASI_BAR0 1
139 #define PCIM_CIS_ASI_BAR1 2
140 #define PCIM_CIS_ASI_BAR2 3
141 #define PCIM_CIS_ASI_BAR3 4
142 #define PCIM_CIS_ASI_BAR4 5
143 #define PCIM_CIS_ASI_BAR5 6
144 #define PCIM_CIS_ASI_ROM 7
145 #define PCIM_CIS_ADDR_MASK 0x0ffffff8
146 #define PCIM_CIS_ROM_MASK 0xf0000000
147 #define PCIM_CIS_CONFIG_MASK 0xff
148 #define PCIR_SUBVEND_0 0x2c
149 #define PCIR_SUBDEV_0 0x2e
150 #define PCIR_BIOS 0x30
151 #define PCIM_BIOS_ENABLE 0x01
152 #define PCIM_BIOS_ADDR_MASK 0xfffff800
153 #define PCIR_CAP_PTR 0x34
154 #define PCIR_INTLINE 0x3c
155 #define PCIR_INTPIN 0x3d
156 #define PCIR_MINGNT 0x3e
157 #define PCIR_MAXLAT 0x3f
159 /* config registers for header type 1 (PCI-to-PCI bridge) devices */
161 #define PCIR_SECSTAT_1 0x1e
163 #define PCIR_PRIBUS_1 0x18
164 #define PCIR_SECBUS_1 0x19
165 #define PCIR_SUBBUS_1 0x1a
166 #define PCIR_SECLAT_1 0x1b
168 #define PCIR_IOBASEL_1 0x1c
169 #define PCIR_IOLIMITL_1 0x1d
170 #define PCIR_IOBASEH_1 0x30
171 #define PCIR_IOLIMITH_1 0x32
172 #define PCIM_BRIO_16 0x0
173 #define PCIM_BRIO_32 0x1
174 #define PCIM_BRIO_MASK 0xf
176 #define PCIR_MEMBASE_1 0x20
177 #define PCIR_MEMLIMIT_1 0x22
179 #define PCIR_PMBASEL_1 0x24
180 #define PCIR_PMLIMITL_1 0x26
181 #define PCIR_PMBASEH_1 0x28
182 #define PCIR_PMLIMITH_1 0x2c
183 #define PCIM_BRPM_32 0x0
184 #define PCIM_BRPM_64 0x1
185 #define PCIM_BRPM_MASK 0xf
187 #define PCIR_BRIDGECTL_1 0x3e
189 /* config registers for header type 2 (CardBus) devices */
191 #define PCIR_CAP_PTR_2 0x14
192 #define PCIR_SECSTAT_2 0x16
194 #define PCIR_PRIBUS_2 0x18
195 #define PCIR_SECBUS_2 0x19
196 #define PCIR_SUBBUS_2 0x1a
197 #define PCIR_SECLAT_2 0x1b
199 #define PCIR_MEMBASE0_2 0x1c
200 #define PCIR_MEMLIMIT0_2 0x20
201 #define PCIR_MEMBASE1_2 0x24
202 #define PCIR_MEMLIMIT1_2 0x28
203 #define PCIR_IOBASE0_2 0x2c
204 #define PCIR_IOLIMIT0_2 0x30
205 #define PCIR_IOBASE1_2 0x34
206 #define PCIR_IOLIMIT1_2 0x38
208 #define PCIR_BRIDGECTL_2 0x3e
210 #define PCIR_SUBVEND_2 0x40
211 #define PCIR_SUBDEV_2 0x42
213 #define PCIR_PCCARDIF_2 0x44
215 /* PCI device class, subclass and programming interface definitions */
217 #define PCIC_OLD 0x00
218 #define PCIS_OLD_NONVGA 0x00
219 #define PCIS_OLD_VGA 0x01
221 #define PCIC_STORAGE 0x01
222 #define PCIS_STORAGE_SCSI 0x00
223 #define PCIS_STORAGE_IDE 0x01
224 #define PCIP_STORAGE_IDE_MODEPRIM 0x01
225 #define PCIP_STORAGE_IDE_PROGINDPRIM 0x02
226 #define PCIP_STORAGE_IDE_MODESEC 0x04
227 #define PCIP_STORAGE_IDE_PROGINDSEC 0x08
228 #define PCIP_STORAGE_IDE_MASTERDEV 0x80
229 #define PCIS_STORAGE_FLOPPY 0x02
230 #define PCIS_STORAGE_IPI 0x03
231 #define PCIS_STORAGE_RAID 0x04
232 #define PCIS_STORAGE_ATA_ADMA 0x05
233 #define PCIS_STORAGE_SATA 0x06
234 #define PCIP_STORAGE_SATA_AHCI_1_0 0x01
235 #define PCIS_STORAGE_SAS 0x07
236 #define PCIS_STORAGE_OTHER 0x80
238 #define PCIC_NETWORK 0x02
239 #define PCIS_NETWORK_ETHERNET 0x00
240 #define PCIS_NETWORK_TOKENRING 0x01
241 #define PCIS_NETWORK_FDDI 0x02
242 #define PCIS_NETWORK_ATM 0x03
243 #define PCIS_NETWORK_ISDN 0x04
244 #define PCIS_NETWORK_WORLDFIP 0x05
245 #define PCIS_NETWORK_PICMG 0x06
246 #define PCIS_NETWORK_OTHER 0x80
248 #define PCIC_DISPLAY 0x03
249 #define PCIS_DISPLAY_VGA 0x00
250 #define PCIS_DISPLAY_XGA 0x01
251 #define PCIS_DISPLAY_3D 0x02
252 #define PCIS_DISPLAY_OTHER 0x80
254 #define PCIC_MULTIMEDIA 0x04
255 #define PCIS_MULTIMEDIA_VIDEO 0x00
256 #define PCIS_MULTIMEDIA_AUDIO 0x01
257 #define PCIS_MULTIMEDIA_TELE 0x02
258 #define PCIS_MULTIMEDIA_OTHER 0x80
260 #define PCIC_MEMORY 0x05
261 #define PCIS_MEMORY_RAM 0x00
262 #define PCIS_MEMORY_FLASH 0x01
263 #define PCIS_MEMORY_OTHER 0x80
265 #define PCIC_BRIDGE 0x06
266 #define PCIS_BRIDGE_HOST 0x00
267 #define PCIS_BRIDGE_ISA 0x01
268 #define PCIS_BRIDGE_EISA 0x02
269 #define PCIS_BRIDGE_MCA 0x03
270 #define PCIS_BRIDGE_PCI 0x04
271 #define PCIP_BRIDGE_PCI_SUBTRACTIVE 0x01
272 #define PCIS_BRIDGE_PCMCIA 0x05
273 #define PCIS_BRIDGE_NUBUS 0x06
274 #define PCIS_BRIDGE_CARDBUS 0x07
275 #define PCIS_BRIDGE_RACEWAY 0x08
276 #define PCIS_BRIDGE_PCI_TRANSPARENT 0x09
277 #define PCIS_BRIDGE_INFINIBAND 0x0a
278 #define PCIS_BRIDGE_OTHER 0x80
280 #define PCIC_SIMPLECOMM 0x07
281 #define PCIS_SIMPLECOMM_UART 0x00
282 #define PCIP_SIMPLECOMM_UART_8250 0x00
283 #define PCIP_SIMPLECOMM_UART_16450A 0x01
284 #define PCIP_SIMPLECOMM_UART_16550A 0x02
285 #define PCIP_SIMPLECOMM_UART_16650A 0x03
286 #define PCIP_SIMPLECOMM_UART_16750A 0x04
287 #define PCIP_SIMPLECOMM_UART_16850A 0x05
288 #define PCIP_SIMPLECOMM_UART_16950A 0x06
289 #define PCIS_SIMPLECOMM_PAR 0x01
290 #define PCIS_SIMPLECOMM_MULSER 0x02
291 #define PCIS_SIMPLECOMM_MODEM 0x03
292 #define PCIS_SIMPLECOMM_GPIB 0x04
293 #define PCIS_SIMPLECOMM_SMART_CARD 0x05
294 #define PCIS_SIMPLECOMM_OTHER 0x80
296 #define PCIC_BASEPERIPH 0x08
297 #define PCIS_BASEPERIPH_PIC 0x00
298 #define PCIP_BASEPERIPH_PIC_8259A 0x00
299 #define PCIP_BASEPERIPH_PIC_ISA 0x01
300 #define PCIP_BASEPERIPH_PIC_EISA 0x02
301 #define PCIP_BASEPERIPH_PIC_IO_APIC 0x10
302 #define PCIP_BASEPERIPH_PIC_IOX_APIC 0x20
303 #define PCIS_BASEPERIPH_DMA 0x01
304 #define PCIS_BASEPERIPH_TIMER 0x02
305 #define PCIS_BASEPERIPH_RTC 0x03
306 #define PCIS_BASEPERIPH_PCIHOT 0x04
307 #define PCIS_BASEPERIPH_SDHC 0x05
308 #define PCIS_BASEPERIPH_OTHER 0x80
310 #define PCIC_INPUTDEV 0x09
311 #define PCIS_INPUTDEV_KEYBOARD 0x00
312 #define PCIS_INPUTDEV_DIGITIZER 0x01
313 #define PCIS_INPUTDEV_MOUSE 0x02
314 #define PCIS_INPUTDEV_SCANNER 0x03
315 #define PCIS_INPUTDEV_GAMEPORT 0x04
316 #define PCIS_INPUTDEV_OTHER 0x80
318 #define PCIC_DOCKING 0x0a
319 #define PCIS_DOCKING_GENERIC 0x00
320 #define PCIS_DOCKING_OTHER 0x80
322 #define PCIC_PROCESSOR 0x0b
323 #define PCIS_PROCESSOR_386 0x00
324 #define PCIS_PROCESSOR_486 0x01
325 #define PCIS_PROCESSOR_PENTIUM 0x02
326 #define PCIS_PROCESSOR_ALPHA 0x10
327 #define PCIS_PROCESSOR_POWERPC 0x20
328 #define PCIS_PROCESSOR_MIPS 0x30
329 #define PCIS_PROCESSOR_COPROC 0x40
331 #define PCIC_SERIALBUS 0x0c
332 #define PCIS_SERIALBUS_FW 0x00
333 #define PCIS_SERIALBUS_ACCESS 0x01
334 #define PCIS_SERIALBUS_SSA 0x02
335 #define PCIS_SERIALBUS_USB 0x03
336 #define PCIP_SERIALBUS_USB_UHCI 0x00
337 #define PCIP_SERIALBUS_USB_OHCI 0x10
338 #define PCIP_SERIALBUS_USB_EHCI 0x20
339 #define PCIP_SERIALBUS_USB_DEVICE 0xfe
340 #define PCIS_SERIALBUS_FC 0x04
341 #define PCIS_SERIALBUS_SMBUS 0x05
342 #define PCIS_SERIALBUS_INFINIBAND 0x06
343 #define PCIS_SERIALBUS_IPMI 0x07
344 #define PCIP_SERIALBUS_IPMI_SMIC 0x00
345 #define PCIP_SERIALBUS_IPMI_KCS 0x01
346 #define PCIP_SERIALBUS_IPMI_BT 0x02
347 #define PCIS_SERIALBUS_SERCOS 0x08
348 #define PCIS_SERIALBUS_CANBUS 0x09
350 #define PCIC_WIRELESS 0x0d
351 #define PCIS_WIRELESS_IRDA 0x00
352 #define PCIS_WIRELESS_IR 0x01
353 #define PCIS_WIRELESS_RF 0x10
354 #define PCIS_WIRELESS_BLUETOOTH 0x11
355 #define PCIS_WIRELESS_BROADBAND 0x12
356 #define PCIS_WIRELESS_80211A 0x20
357 #define PCIS_WIRELESS_80211B 0x21
358 #define PCIS_WIRELESS_OTHER 0x80
360 #define PCIC_INTELLIIO 0x0e
361 #define PCIS_INTELLIIO_I2O 0x00
363 #define PCIC_SATCOM 0x0f
364 #define PCIS_SATCOM_TV 0x01
365 #define PCIS_SATCOM_AUDIO 0x02
366 #define PCIS_SATCOM_VOICE 0x03
367 #define PCIS_SATCOM_DATA 0x04
369 #define PCIC_CRYPTO 0x10
370 #define PCIS_CRYPTO_NETCOMP 0x00
371 #define PCIS_CRYPTO_ENTERTAIN 0x10
372 #define PCIS_CRYPTO_OTHER 0x80
374 #define PCIC_DASP 0x11
375 #define PCIS_DASP_DPIO 0x00
376 #define PCIS_DASP_PERFCNTRS 0x01
377 #define PCIS_DASP_COMM_SYNC 0x10
378 #define PCIS_DASP_MGMT_CARD 0x20
379 #define PCIS_DASP_OTHER 0x80
381 #define PCIC_OTHER 0xff
383 /* Bridge Control Values. */
384 #define PCIB_BCR_PERR_ENABLE 0x0001
385 #define PCIB_BCR_SERR_ENABLE 0x0002
386 #define PCIB_BCR_ISA_ENABLE 0x0004
387 #define PCIB_BCR_VGA_ENABLE 0x0008
388 #define PCIB_BCR_MASTER_ABORT_MODE 0x0020
389 #define PCIB_BCR_SECBUS_RESET 0x0040
390 #define PCIB_BCR_SECBUS_BACKTOBACK 0x0080
391 #define PCIB_BCR_PRI_DISCARD_TIMEOUT 0x0100
392 #define PCIB_BCR_SEC_DISCARD_TIMEOUT 0x0200
393 #define PCIB_BCR_DISCARD_TIMER_STATUS 0x0400
394 #define PCIB_BCR_DISCARD_TIMER_SERREN 0x0800
396 /* PCI power manangement */
397 #define PCIR_POWER_CAP 0x2
398 #define PCIM_PCAP_SPEC 0x0007
399 #define PCIM_PCAP_PMEREQCLK 0x0008
400 #define PCIM_PCAP_PMEREQPWR 0x0010
401 #define PCIM_PCAP_DEVSPECINIT 0x0020
402 #define PCIM_PCAP_DYNCLOCK 0x0040
403 #define PCIM_PCAP_SECCLOCK 0x00c0
404 #define PCIM_PCAP_CLOCKMASK 0x00c0
405 #define PCIM_PCAP_REQFULLCLOCK 0x0100
406 #define PCIM_PCAP_D1SUPP 0x0200
407 #define PCIM_PCAP_D2SUPP 0x0400
408 #define PCIM_PCAP_D0PME 0x0800
409 #define PCIM_PCAP_D1PME 0x1000
410 #define PCIM_PCAP_D2PME 0x2000
411 #define PCIM_PCAP_D3PME_HOT 0x4000
412 #define PCIM_PCAP_D3PME_COLD 0x8000
414 #define PCIR_POWER_STATUS 0x4
415 #define PCIM_PSTAT_D0 0x0000
416 #define PCIM_PSTAT_D1 0x0001
417 #define PCIM_PSTAT_D2 0x0002
418 #define PCIM_PSTAT_D3 0x0003
419 #define PCIM_PSTAT_DMASK 0x0003
420 #define PCIM_PSTAT_REPENABLE 0x0010
421 #define PCIM_PSTAT_PMEENABLE 0x0100
422 #define PCIM_PSTAT_D0POWER 0x0000
423 #define PCIM_PSTAT_D1POWER 0x0200
424 #define PCIM_PSTAT_D2POWER 0x0400
425 #define PCIM_PSTAT_D3POWER 0x0600
426 #define PCIM_PSTAT_D0HEAT 0x0800
427 #define PCIM_PSTAT_D1HEAT 0x1000
428 #define PCIM_PSTAT_D2HEAT 0x1200
429 #define PCIM_PSTAT_D3HEAT 0x1400
430 #define PCIM_PSTAT_DATAUNKN 0x0000
431 #define PCIM_PSTAT_DATADIV10 0x2000
432 #define PCIM_PSTAT_DATADIV100 0x4000
433 #define PCIM_PSTAT_DATADIV1000 0x6000
434 #define PCIM_PSTAT_DATADIVMASK 0x6000
435 #define PCIM_PSTAT_PME 0x8000
437 #define PCIR_POWER_PMCSR 0x6
438 #define PCIM_PMCSR_DCLOCK 0x10
439 #define PCIM_PMCSR_B2SUPP 0x20
440 #define PCIM_BMCSR_B3SUPP 0x40
441 #define PCIM_BMCSR_BPCE 0x80
443 #define PCIR_POWER_DATA 0x7
445 /* VPD capability registers */
446 #define PCIR_VPD_ADDR 0x2
447 #define PCIR_VPD_DATA 0x4
449 /* PCI Message Signalled Interrupts (MSI) */
450 #define PCIR_MSI_CTRL 0x2
451 #define PCIM_MSICTRL_VECTOR 0x0100
452 #define PCIM_MSICTRL_64BIT 0x0080
453 #define PCIM_MSICTRL_MME_MASK 0x0070
454 #define PCIM_MSICTRL_MME_1 0x0000
455 #define PCIM_MSICTRL_MME_2 0x0010
456 #define PCIM_MSICTRL_MME_4 0x0020
457 #define PCIM_MSICTRL_MME_8 0x0030
458 #define PCIM_MSICTRL_MME_16 0x0040
459 #define PCIM_MSICTRL_MME_32 0x0050
460 #define PCIM_MSICTRL_MMC_MASK 0x000E
461 #define PCIM_MSICTRL_MMC_1 0x0000
462 #define PCIM_MSICTRL_MMC_2 0x0002
463 #define PCIM_MSICTRL_MMC_4 0x0004
464 #define PCIM_MSICTRL_MMC_8 0x0006
465 #define PCIM_MSICTRL_MMC_16 0x0008
466 #define PCIM_MSICTRL_MMC_32 0x000A
467 #define PCIM_MSICTRL_MSI_ENABLE 0x0001
468 #define PCIR_MSI_ADDR 0x4
469 #define PCIR_MSI_ADDR_HIGH 0x8
470 #define PCIR_MSI_DATA 0x8
471 #define PCIR_MSI_DATA_64BIT 0xc
472 #define PCIR_MSI_MASK 0x10
473 #define PCIR_MSI_PENDING 0x14
475 /* PCI-X definitions */
477 /* For header type 0 devices */
478 #define PCIXR_COMMAND 0x2
479 #define PCIXM_COMMAND_DPERR_E 0x0001 /* Data Parity Error Recovery */
480 #define PCIXM_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */
481 #define PCIXM_COMMAND_MAX_READ 0x000c /* Maximum Burst Read Count */
482 #define PCIXM_COMMAND_MAX_READ_512 0x0000
483 #define PCIXM_COMMAND_MAX_READ_1024 0x0004
484 #define PCIXM_COMMAND_MAX_READ_2048 0x0008
485 #define PCIXM_COMMAND_MAX_READ_4096 0x000c
486 #define PCIXM_COMMAND_MAX_SPLITS 0x0070 /* Maximum Split Transactions */
487 #define PCIXM_COMMAND_MAX_SPLITS_1 0x0000
488 #define PCIXM_COMMAND_MAX_SPLITS_2 0x0010
489 #define PCIXM_COMMAND_MAX_SPLITS_3 0x0020
490 #define PCIXM_COMMAND_MAX_SPLITS_4 0x0030
491 #define PCIXM_COMMAND_MAX_SPLITS_8 0x0040
492 #define PCIXM_COMMAND_MAX_SPLITS_12 0x0050
493 #define PCIXM_COMMAND_MAX_SPLITS_16 0x0060
494 #define PCIXM_COMMAND_MAX_SPLITS_32 0x0070
495 #define PCIXM_COMMAND_VERSION 0x3000
496 #define PCIXR_STATUS 0x4
497 #define PCIXM_STATUS_DEVFN 0x000000FF
498 #define PCIXM_STATUS_BUS 0x0000FF00
499 #define PCIXM_STATUS_64BIT 0x00010000
500 #define PCIXM_STATUS_133CAP 0x00020000
501 #define PCIXM_STATUS_SC_DISCARDED 0x00040000
502 #define PCIXM_STATUS_UNEXP_SC 0x00080000
503 #define PCIXM_STATUS_COMPLEX_DEV 0x00100000
504 #define PCIXM_STATUS_MAX_READ 0x00600000
505 #define PCIXM_STATUS_MAX_READ_512 0x00000000
506 #define PCIXM_STATUS_MAX_READ_1024 0x00200000
507 #define PCIXM_STATUS_MAX_READ_2048 0x00400000
508 #define PCIXM_STATUS_MAX_READ_4096 0x00600000
509 #define PCIXM_STATUS_MAX_SPLITS 0x03800000
510 #define PCIXM_STATUS_MAX_SPLITS_1 0x00000000
511 #define PCIXM_STATUS_MAX_SPLITS_2 0x00800000
512 #define PCIXM_STATUS_MAX_SPLITS_3 0x01000000
513 #define PCIXM_STATUS_MAX_SPLITS_4 0x01800000
514 #define PCIXM_STATUS_MAX_SPLITS_8 0x02000000
515 #define PCIXM_STATUS_MAX_SPLITS_12 0x02800000
516 #define PCIXM_STATUS_MAX_SPLITS_16 0x03000000
517 #define PCIXM_STATUS_MAX_SPLITS_32 0x03800000
518 #define PCIXM_STATUS_MAX_CUM_READ 0x1C000000
519 #define PCIXM_STATUS_RCVD_SC_ERR 0x20000000
520 #define PCIXM_STATUS_266CAP 0x40000000
521 #define PCIXM_STATUS_533CAP 0x80000000
523 /* For header type 1 devices (PCI-X bridges) */
524 #define PCIXR_SEC_STATUS 0x2
525 #define PCIXM_SEC_STATUS_64BIT 0x0001
526 #define PCIXM_SEC_STATUS_133CAP 0x0002
527 #define PCIXM_SEC_STATUS_SC_DISC 0x0004
528 #define PCIXM_SEC_STATUS_UNEXP_SC 0x0008
529 #define PCIXM_SEC_STATUS_SC_OVERRUN 0x0010
530 #define PCIXM_SEC_STATUS_SR_DELAYED 0x0020
531 #define PCIXM_SEC_STATUS_BUS_MODE 0x03c0
532 #define PCIXM_SEC_STATUS_VERSION 0x3000
533 #define PCIXM_SEC_STATUS_266CAP 0x4000
534 #define PCIXM_SEC_STATUS_533CAP 0x8000
535 #define PCIXR_BRIDGE_STATUS 0x4
536 #define PCIXM_BRIDGE_STATUS_DEVFN 0x000000FF
537 #define PCIXM_BRIDGE_STATUS_BUS 0x0000FF00
538 #define PCIXM_BRIDGE_STATUS_64BIT 0x00010000
539 #define PCIXM_BRIDGE_STATUS_133CAP 0x00020000
540 #define PCIXM_BRIDGE_STATUS_SC_DISCARDED 0x00040000
541 #define PCIXM_BRIDGE_STATUS_UNEXP_SC 0x00080000
542 #define PCIXM_BRIDGE_STATUS_SC_OVERRUN 0x00100000
543 #define PCIXM_BRIDGE_STATUS_SR_DELAYED 0x00200000
544 #define PCIXM_BRIDGE_STATUS_DEVID_MSGCAP 0x20000000
545 #define PCIXM_BRIDGE_STATUS_266CAP 0x40000000
546 #define PCIXM_BRIDGE_STATUS_533CAP 0x80000000
548 /* HT (HyperTransport) Capability definitions */
549 #define PCIR_HT_COMMAND 0x2
550 #define PCIM_HTCMD_CAP_MASK 0xf800 /* Capability type. */
551 #define PCIM_HTCAP_SLAVE 0x0000 /* 000xx */
552 #define PCIM_HTCAP_HOST 0x2000 /* 001xx */
553 #define PCIM_HTCAP_SWITCH 0x4000 /* 01000 */
554 #define PCIM_HTCAP_INTERRUPT 0x8000 /* 10000 */
555 #define PCIM_HTCAP_REVISION_ID 0x8800 /* 10001 */
556 #define PCIM_HTCAP_UNITID_CLUMPING 0x9000 /* 10010 */
557 #define PCIM_HTCAP_EXT_CONFIG_SPACE 0x9800 /* 10011 */
558 #define PCIM_HTCAP_ADDRESS_MAPPING 0xa000 /* 10100 */
559 #define PCIM_HTCAP_MSI_MAPPING 0xa800 /* 10101 */
560 #define PCIM_HTCAP_DIRECT_ROUTE 0xb000 /* 10110 */
561 #define PCIM_HTCAP_VCSET 0xb800 /* 10111 */
562 #define PCIM_HTCAP_RETRY_MODE 0xc000 /* 11000 */
563 #define PCIM_HTCAP_X86_ENCODING 0xc800 /* 11001 */
565 /* HT MSI Mapping Capability definitions. */
566 #define PCIM_HTCMD_MSI_ENABLE 0x0001
567 #define PCIM_HTCMD_MSI_FIXED 0x0002
568 #define PCIR_HTMSI_ADDRESS_LO 0x4
569 #define PCIR_HTMSI_ADDRESS_HI 0x8
571 /* PCI Vendor capability definitions */
572 #define PCIR_VENDOR_LENGTH 0x2
573 #define PCIR_VENDOR_DATA 0x3
575 /* PCI EHCI Debug Port definitions */
576 #define PCIR_DEBUG_PORT 0x2
577 #define PCIM_DEBUG_PORT_OFFSET 0x1FFF
578 #define PCIM_DEBUG_PORT_BAR 0xe000
580 /* PCI-PCI Bridge Subvendor definitions */
581 #define PCIR_SUBVENDCAP_ID 0x4
583 /* PCI Express definitions */
584 #define PCIR_EXPRESS_FLAGS 0x2
585 #define PCIM_EXP_FLAGS_VERSION 0x000F
586 #define PCIM_EXP_FLAGS_TYPE 0x00F0
587 #define PCIM_EXP_TYPE_ENDPOINT 0x0000
588 #define PCIM_EXP_TYPE_LEGACY_ENDPOINT 0x0010
589 #define PCIM_EXP_TYPE_ROOT_PORT 0x0040
590 #define PCIM_EXP_TYPE_UPSTREAM_PORT 0x0050
591 #define PCIM_EXP_TYPE_DOWNSTREAM_PORT 0x0060
592 #define PCIM_EXP_TYPE_PCI_BRIDGE 0x0070
593 #define PCIM_EXP_FLAGS_SLOT 0x0100
594 #define PCIM_EXP_FLAGS_IRQ 0x3e00
596 /* MSI-X definitions */
597 #define PCIR_MSIX_CTRL 0x2
598 #define PCIM_MSIXCTRL_MSIX_ENABLE 0x8000
599 #define PCIM_MSIXCTRL_FUNCTION_MASK 0x4000
600 #define PCIM_MSIXCTRL_TABLE_SIZE 0x07FF
601 #define PCIR_MSIX_TABLE 0x4
602 #define PCIR_MSIX_PBA 0x8
603 #define PCIM_MSIX_BIR_MASK 0x7
604 #define PCIM_MSIX_BIR_BAR_10 0
605 #define PCIM_MSIX_BIR_BAR_14 1
606 #define PCIM_MSIX_BIR_BAR_18 2
607 #define PCIM_MSIX_BIR_BAR_1C 3
608 #define PCIM_MSIX_BIR_BAR_20 4
609 #define PCIM_MSIX_BIR_BAR_24 5
610 #define PCIM_MSIX_VCTRL_MASK 0x1